Validator for scrip

Abstract

A piece of scrip is engraved or printed with groups of patterns which can be sensed by a validator for scrip and one of those groups of patterns will define a code which will permit that piece of scrip to be accepted only by a scrip validator or by scrip validators which have that same code stored therein. Two additional groups of patterns define codes which can cause that scrip validator or those scrip validators to automatically respond to the codes stored therein to actuate price-determining relays within a vending machine. Each pattern is formed by a number of spaced parallel lines, and the various patterns on a piece of scrip can be given different identities merely by changing the spacing between the trailing edges of those spaced parallel lines. The patterns in each group of patterns will be sensed in a prescribed sequence, and the sequentially sensed patterns in any of those groups of patterns can be given various identities. As a result, the scrip validator of the present invention can accept a piece of scrip which has a given number of patterns of specifically different identities and yet reject a piece of scrip which has those same patterns arranged in a different sequence. In this way, the present invention makes it possible to use permutations, rather than mere combinations, of potentially usable pattern identities, and thus makes it possible to use just fifteen specifically different pattern identities to make thirty-two thousand seven hundred and sixty different pieces of scrip. The scrip validator of the present invention stores the codes, which correspond to the codes defined by the patterns on the piece of scrip, in serially shifted shift registers; and, as each pattern on the piece of scrip is sensed by the scrip validator, the data within the shift registers is serially shifted a plurality of times. The identity of any given pattern can be determined by three signals; and, by utilizing serially shifted shift registers which have seven or more stages, the present invention enables each shift register to store the pattern-identifying data for at least two patterns. In addition, the serial shifting of the shift registers permits the pattern-identifying data for the various patterns to be presented in fixed sequences. Moreover, by merely changing some of the connections to the input terminals of the shift registers, it is possible to change the codes stored within those shift registers. The frequency which identifies each pattern is sensed by the combination of a digital filter and a counter; and such a combination provides a strict test of the identification of each pattern because it requires the frequency which corresponds to the spacing of the trailing edges of the lines of that pattern to match the frequency of the digital filter, and it also requires that pattern to have a minimum number of lines which have that same spacing.

Claims

What we claim is:

1. A validator which comprises sensing means that senses a plurality of patterns on a document in a predetermined sequence to effect the developing of sensed data, recognition means responsive to the developing of said sensed data to provide a plurality of logic level signals, a preprogrammed memory which is an electronic memory and thus has no moving parts and which contains pre-programmed data hard-wired therein, said hard-wired pre-programmed data corresponding to said plurality of patterns on said document, said pre-programmed memory holding said pre-programmed data as a plurality of discrete groupings of pre-programmed data in the form of predetermined logic level signals, one of said groupings of pre-programmed data corresponding to the logic level signals which said recognition means develops when said sensing means senses a predetermined one of said plurality of patterns on said document, another of said groupings of pre-programmed data corresponding to the logic level signals which said recognition means develops when said sensing means senses a predetermined succeeding one of said plurality of patterns on said document, said one and said other groupings of said pre-programmed data being stored within said pre-programmed memory in a manner which permits said one and said other groupings of said pre-programmed data to be read in the same sequence in which said predetermined one and said predetermined succeeding one of said patterns on said document are sensed by said sensing means, a comparing means that can compare said logic level signals which said recognition means develops when said sensing means senses said predetermined one and said predetermined succeeding one of said plurality of patterns on said document directly with said predetermined logic level signals while said predetermined logic level signals are stored within said pre-programmed memory, further means to effect sequential comparing by said comparing means of said logic level signals, developed by said recognition means during the sensing of said predetermined one and of said predetermined succeeding one of said patterns by said sensing means, with said predetermined logic level signals which constitute said pre-programmed data within said pre-programmed memory, and additional means to effect validation of said document if said sensed data obtained during the sensing of said predetermined one and of said predetermined succeeding one of said patterns by said sensing means corresponds in nature and in sequence with said pre-programmed data within said pre-programmed memory.

2. A validator as claimed in claim 1 wherein said recognition means causes the sensed data from the patterns of said plurality of patterns to appear on a plurality of conductors as said predetermined logic level signals, wherein said pre-programmed memory includes a shift register which has a predetermined number of stages, wherein the total of said predetermined logic level signals which said recognition means develops during the sensing of all of said patterns of said plurality of patterns on said document exceeds said predetermined number of stages in said shift register, and wherein a logic element connected to the output of said shift register responds to the shifting of the data in said shift register to apply varying signals to the input of said shift register.

3. A validator as claimed in claim 1 wherein said pre-programmed memory comprises a shift register having circuitry intermediate the output and the input thereof which will modify some of said pre-programmed data when said some pre-programmed data is shifted from said output to said input of said shift register, and wherein the output of said shift register is shifted back into said input of said shift register via said intermediate circuitry as it is serially shifted out of said shift register.

4. A validator as claimed in claim 1 wherein a sensed data memory receives said sensed data developed during the sensing of said plurality of patterns on said document by said sensing means, wherein said sensed data is stored within said sensed data memory in a manner which permits said sensed data to be read in the same sequence in which the corresponding patterns on said document were sensed by said sensing means, and wherein said further means effects sequential comparing by said comparing means of the nature of said sensed data sequentially read from said sensed data memory with said pre-programmed data sequentially read from said pre-programmed memory.

5. A validator as claimed in claim 1 wherein a sensed data memory receives said sensed data developed during the sensing of said plurality of patterns on said document by said sensing means, and wherein said sensed data memory is a serially-read shift register.

6. A validator as claimed in claim 1 wherein each of said patterns comprises a plurality of spaced-apart lines, and wherein any pattern, of said plurality of patterns on said document, which is sensed by said sensing means will have all of the spaced-apart lines thereof sensed by said sensing means.

7. A validator as claimed in claim 1 wherein said pre-programmed memory has a plurality of sections to hold said plurality of discrete grouping of pre-programmed data, and wherein each of at least two sections holds a grouping of pre-programmed data which corresponds to a distinctively-different pattern.

8. A validator as claimed in claim 1 wherein said validator has a second pre-programmed memory which contains pre-programmed data, wherein a sensed data memory stores said sensed data, wherein said sensed data memory and each of said pre-programmed memories is connected to said comparing means, and wherein said comparing means simultaneously compares sensed data from said sensed data memory with pre-programmed data from said pre-programmed memories.

9. A validator as claimed in claim 1 wherein a sensed data memory stores said sensed data, and wherein fresh sensed data is stored in said sensed data memory as a result of the sensing of each pattern on said document but wherein said pre-programmed memory is re-set only after more than one pattern on said document have been sensed.

10. A validator as claimed in claim 1 wherein said patterns of said plurality of patterns on said document are arranged in groups, and wherein a pre-programmed control element effects re-setting of said pre-programmed memory after each group of patterns is sensed.

11. A validator as claimed in claim 1 wherein said patterns of said plurality of patterns on said document are arranged in groups, wherein the number of patterns in one of said groups of patterns is different from the number of patterns in another of said groups of patterns, wherein a pre-programmed control element effects re-setting of said pre-programmed memory as a result of the sensing of said one of said groups of patterns, and wherein said pre-programmed control element also effects re-setting of said pre-programmed memory as a result of the sensing of said other of said groups of patterns.

12. A validator as claimed in claim 1 wherein said patterns are grouped in a plurality of data fields, wherein said additional means includes a still further means which can provide a desired output only if all signals applied thereto have a given value, wherein said additional means includes a sub-circuit which responds to a match between the sensed data obtained during the sensing of one of said data fields and the corresponding pre-programmed data read from said pre-programmed memory to apply a signal of said given value to said still further means, wherein said additional means includes a second sub-circuit which responds to a match between the sensed data obtained during the sensing of another of said data fields and the corresponding pre-programmed data read from said pre-programmed memory to apply a second signal of said given value to said still further means, and wherein the first said sub-circuit and said second sub-circuit must apply the first said and said second signals to said still further means to enable said additional means to effect validation of said document.

13. A validator as claimed in claim 1 wherein said patterns are grouped in a plurality of data fields, wherein said additional means includes a still further means which can provide a desired output only if all signals applied thereto have a given value, wherein said additional means includes a sub-circuit which responds to a match between the sensed data obtained during the sensing of one of said data fields and the corresponding pre-programmed memory to apply a signal of said given value to said still further means, wherein said additional means includes a second sub-circuit which responds to a match between the sensed data obtained during the sensing of another of said data fields and the corresponding pre-programmed data read from said pre-programmed memory to apply a second signal of said given value to said still further means, wherein the first said sub-circuit and said second sub-circuit must apply the first said and said second signals to said still further means to enable said additional means to effect validation of said document, wherein said further means effects a plurality of comparisons by said comparing means to develop a match between the sensed data obtained during the sensing of said one of said data fields and the corresponding pre-programmed data read from said pre-programmed memory, and wherein the first said sub-circuit must continue to supply the same signal to said still further means during said plurality of comparisons.

14. A validator as claimed in claim 1 wherein said sensing means senses a further plurality of patterns on said document in a predetermined sequence to effect the developing of further sensed data, wherein said pre-programmed memory contains further pre-programmed data corresponding to said further plurality of patterns on said document, wherein said further pre-programmed data is stored within said pre-programmed memory in a manner which permits said further pre-programmed data to be read in the same sequence in which the corresponding patterns of said further plurality of patterns on said document are sensed by said sensing means, wherein said further means effects sequential comparing by said comparing means of the nature of said further sensed data, obtained during the sensing of said patterns of said further plurality of patterns by said sensing means, with said further pre-programmed data sequentially read from said pre-programmed memory, and utilization means to develop a utilization signal if said further sensed data obtained during the sensing of said patterns of said further plurality of patterns by said sensing means corresponds in nature and in sequence with said further pre-programmed data within said pre-programmed memory.

15. A validator as claimed in claim 1 wherein said patterns are grouped as a plurality of data fields, wherein said pre-programmed memory comprises a plurality of shift registers, and wherein some of said patterns in one of said data fields are identical to some patterns in another of said data fields to limit the number of shift registers in said pre-programmed memory.

16. A validator which comprises a sensing means that can sense a plurality of patterns on a document and develop a plurality of signals which have frequencies corresponding to said patterns, a memory having a plurality of elements wherein a plurality of specifically-different pattern-recognition data must be stored during the validation of an authentic document, a frequency-sensing circuit that receives said plurality of signals and that will develop an output signal if one of said plurality of frequencies corresponding to one of said patterns has a predetermined value, a second frequency-sensing circuit that receives said plurality of signals and that will develop a second and different output signal if another of said plurality of frequencies corresponding to another of said patterns has a second and different predetermined value, said sensing means responding to sequential sensing of said plurality of patterns on said document to cause the first said frequency-sensing circuit and said second frequency-sensing circuit to sequentially develop the first said output signal and said second and different output signal, means that responds to said first said output signal from said first said frequency-sensing circuit to develop predetermined pattern-recognition data which includes at least one logic level signal having a predetermined logic level and which can be stored in at least one predetermined element of said memory, said means subsequently responding to said second output signal from said second frequency-sensing circuit to develop further and different predetermined pattern-recognition data which includes at least one logic level signal having said predetermined logic level and which can be stored in at least one different predetermined element of said memory, and comparing and processing circuitry which responds to the first said predetermined pattern-recognition data to indicate that said sensing means has sensed a pattern having said one of said plurality of frequencies, said comparing and processing circuitry also responding to said further and different predetermined pattern-recognition data to indicate that said sensing means has sensed a pattern having said other of said plurality of frequencies, said comparing and processing circuitry sensing the sequence in which said first said predetermined pattern-recognition data and said further and different predetermined pattern-recognition data were developed and thereby sensing the sequence in which said pattern having said one of said plurality of frequencies and said pattern having said other of said plurality of frequencies were sensed, said comparing and processing circuitry providing a predetermined indication whenever it senses that the sequence, in which said pattern having said one of said plurality of frequencies and said pattern having said other of said plurality of frequencies were sensed, corresponds to the sequence of sensing of corresponding patterns on said authentic document, said validator responding to the sensing of a given one of said patterns by said sensing means to perform the dual functions of developing a frequency corresponding to said pattern and also of causing said comparing and processing circuitry to initiate the comparing and processing of said pattern-recognition data developed by said means because of the response to the sensing of said given one pattern, and said validator responding to the sensing of each subsequently-sensed pattern by said sensing means to perform the dual functions of developing a frequency corresponding to said subsequently-sensed pattern and also of causing said comparing and processing circuitry to initiate the comparing and processing of said further and different pattern-recognition data developed by said means because of the response to the sensing of said subsequently-sensed pattern.

17. A validator which comprises a sensor, a frequency detector, a second frequency detector, means connecting the output of said sensor to both of said frequency detectors, said sensor responding to an authentic document to develop a frequency to which one of said frequency detectors will respond but to which the other of said frequency detectors will not respond, said sensor not responding to a spurious document to develop signals to which either of said frequency detectors will respond, the first said frequency detector normally having a first signal at the output thereof but acting whenever it responds to an acceptable frequency that is applied to the input thereof to develop a second signal at said output thereof, said second frequency detector normally having a third signal at the output thereof but acting whenever it responds to a proper frequency that is applied to the input thereof to develop a fourth signal at said output thereof, a memory which has data stored therein indicative of conditions wherein the first said frequency detector responds to an acceptable frequency applied to said input thereof but said second frequency detector does not have a proper frequency applied to said input thereof and also has stored therein data indicating that said second frequency detector has a proper frequency applied to said input thereof but that the first said frequency detector does not have an acceptable frequency applied to said input thereof, a comparing means, and further means enabling said comparing means to determine whether the sensing of a document by said sensor has caused the signals at said outputs of the first said and said second frequency detectors to correspond to any data in said memory, said further means also enabling said comparing means to determine which of said frequency detectors responded to said sensing of said documents by said sensor to change the signal at said output thereof.

18. A validator which comprises a sensor that can respond to a pattern on a document, which includes a plurality of spaced-apart lines, to develop signals corresponding to the line spacing in said pattern on said document, means to respond to said signals from said sensor to provide a plurality of waveforms each of which has a zero-departing portion and a zero-approaching portion with an intervening peak where the transition occurs between said zero-departing portion and said zero-approaching portion, a peak detector which responds to said transitions which occur in said waveforms, developed by said means in response to said signals developed by said sensor, to develop corresponding output signals having a frequency corresponding to the occurrence in time of said transitions in said waveforms, and a frequency detector which can respond to said frequency, of said output signals that are developed by said peak detector, and which corresponds to the occurrence in time of said transitions in said waveforms, to determine whether said frequency of said output signals substantially equals a predetermined frequency, said peak detector not sensing the average value of the slope of said zero-departing portion of any of said waveforms and not sensing the average value of the slope of said zero-approaching portion of any of said waveforms and also not sensing an amplitude which is spaced from zero by a predetermined amount and, instead, sensing said transitions which occur in said waveforms, thereby sensing the peaks of the signals which are developed by said sensor and which correspond to the line spacing in said pattern on said document rather than to the slope or to the amplitude of those signals, thereby providing output signals with edges which correspond closely to predetermined portions of said lines on said document.

19. A validator as claimed in claim 18 wherein said output signals of said peak detector are pulses having frequencies corresponding exactly to said line spacing in said pattern on said document, wherein said edges of said output pulses of said peak detector are the leading edges of said output pulses, and wherein said predetermined portions of said lines on said document are edges of said lines.

20. A validator which comprises a sensor that senses a given pattern on a document to effect the developing of sensed data, a sensed data memory which has a plurality of stages therein, sensing-responsive means that causes the sensed data from said given pattern to appear on a plurality of conductors as logic level signals, said plurality of conductors being connected to said plurality of stages in said sensed data memory and thereby enabling said logic level signals to be applied to and stored within said plurality of stages in said sensed data memory, a pre-programmed means that can develop pattern-recognition data corresponding to said given pattern on said document, said pattern-recognition data being developed by said pre-programmed means in a manner which permits said pattern-recognition data to be read in a predetermined sequence which is the same sequence in which said sensed data in said sensed data memory is read, said pattern-recognition data being developed by said pre-programmed means in the form of logic level signals, a comparing means, further means to effect a plurality of succeeding comparisons by said comparing means of the nature of said sensed data which corresponds to said given pattern and which is sequentially read from said sensed data memory in the form of logic level signals with said pattern recognition data which is sequentially developed by said pre-programmed means in the form of logic level signals, and additional means to prevent validation of said document if, during any of said plurality of succeeding comparisons by said comparing means, of said sensed data corresponding to said given pattern, any of said sensed data which is sequentially read from said sensed data memory fails to correspond in nature and in sequence with said pattern-recognition data that is sequentially developed by said pre-programmed means.

21. A validator which comprises a sensing means that can sense a given pattern on a document and develop a signal, a circuit that receives said signal and that will develop an output signal if said given pattern has a predetermined nature, means that responds to said output signal from said circuit to develop predetermined pattern-recognition data, pre-programmed means that can develop predetermined comparative pattern-recognition data, and comparing and processing circuitry which compares said predetermined comparative pattern-recognition data with said pattern-recognition data that said means develops in response to an output signal from said circuit and which helps produce a validation signal if a proper comparison is obtained, said validator responding to the sensing of said given pattern by said sensing means to perform the dual functions of developing a signal corresponding to said given pattern and also of causing said comparing and processing circuitry to initiate the comparing and processing of said pattern-recognition data developed by said means with said predetermined comparative pattern-recognition data developed by said pre-programmed means, said pattern-recognition data which said means develops in response to an output signal from said circuit being stored temporarily within a memory, said pattern-recognition data which said means develops in response to an output signal from said circuit including a plurality of signals, said predetermined comparative pattern-recognition data developed by said pre-programmed means including a plurality of further signals, and said comparing and processing circuitry comparing corresponding ones of the first said plurality of signals with corresponding ones of said plurality of further signals a predetermined plural number of times in response to the sensing of said given pattern, and the comparisons of said ones of the first said plurality of signals and of said plurality of further signals being made sequentially at predetermined time intervals.

22. A validator which comprises sensing means that scans a plurality of patterns on a document in a pre-determined sequence to effect the developing of sensed data, a pre-programmed memory which contains pre-programmed data corresponding to said plurality of patterns on said document, said pre-programmed data being stored within said pre-programmed memory in a manner which permits said pre-programmed data to be read in the same sequence in which the corresponding patterns on said document are scanned by said sensing means, a comparing means, further means to effect sequential comparing by said comparing means of the nature of said sensed data, obtained during the sensing of said patterns by said sensing means, with said pre-programmed data sequentially read from said pre-programmed memory, and additional means to effect validation of said document if said sensed data obtained during the sensing of said patterns by said sensing means corresponds in nature and in sequence with said pre-programmed data within said pre-programmed memory, any patterns on said document representing different values being defined by differently spaced-apart lines, said sensing means developing signals having different frequencies corresponding to the spacing of said differently spaced-apart lines, frequency detectors which respond to said signals to help develop said sensed data, said frequency detectors being made in the form of printed circuits on removable circuit boards, and said validator being enabled to accept documents whereon said patterns have been transposed by making a corresponding transposition in the positions of said removable circuit boards.

23. A validator which comprises sensing means that scans a plurality of patterns on a document in a pre-determined sequence to effect the developing of sensed data, a pre-programmed memory which contains pre-programmed data corresponding to said plurality of patterns on said document, said pre-programmed data being stored within said pre-programmed memory in a manner which permits said pre-programmed data to be read in the same sequence in which the corresponding patterns on said document are scanned by said sensing means, a comparing means, further means to effect sequential comparing by said comparing means of the nature of said sensed data, obtained during the sensing of said patterns by said sensing means, with said pre-programmed data sequentially read from said pre-programmed memory, and additional means to effect validation of said document if said sensed data obtained during the sensing of said patterns by said sensing means corresponds in nature and in sequence with said pre-programmed data within said pre-programmed memory, said sensing means sensing a further plurality of patterns on said document in a predetermined sequence to effect the developing of further sensed data, said pre-programmed memory containing further pre-programmed data corresponding to said further plurality of patterns on said document, said further pre-programmed data being stored within said pre-programmed memory in a manner which permits said further pre-programmed data to be read in the same sequence in which the corresponding patterns of said further plurality of patterns on said document are sensed by said sensing means, said further means effecting sequential comparing by said comparing means of the nature of said further sensed data, obtained during the sensing of said patterns of said further plurality of patterns by said sensing means, with said further pre-programmed data sequentially read from said pre-programmed memory, utilization means to develop a utilization signal if said further sensed data obtained during the sensing of said patterns of said further plurality of patterns by said sensing means corresponds in nature and in sequence with said further pre-programmed data within said pre-programmed memory, an inhibiting circuit that inhibits said utilization means during said comparing of the first said sensed data, obtained during the sensing of the first said patterns by said sensing means, with the first said pre-programmed data sequentially read from said pre-programmed memory, and said inhibiting circuit inhibiting said additional means during said comparing of said further sensed data, obtained during the sensing of said patterns of said further plurality of patterns by said sensing means, with said further pre-programmed data sequentially read from said pre-programmed memory.

24. A validator which comprises sensing means that scans a plurality of patterns on a document in a pre-determined sequence to effect the developing of sensed data, a pre-programmed memory which contains pre-programmed data corresponding to said plurality of patterns on said document, said pre-programmed data being stored within said pre-programmed memory in a manner which permits said pre-programmed data to be read in the same sequence in which the corresponding patterns on said document are scanned by said sensing means, a comparing means, further means to effect sequential comparing by said comparing means of the nature of said sensed data, obtained during the sensing of said patterns by said sensing means, with said pre-programmed data sequentially read from said pre-programmed memory, and additional means to effect validation of said document if said sensed data obtained during the sensing of said patterns by said sensing means corresponds in nature and in sequence with said pre-programmed data within said pre-programmed memory, said sensing means sensing a further plurality of patterns on said document in a predetermined sequence to effect the developing of further sensed data, said pre-programmed memory containing further pre-programmed data corresponding to said further plurality of patterns on said document, said further pre-programmed data being stored within said pre-programmed memory in a manner which permits said further pre-programmed data to be read in the same sequence in which the corresponding patterns of said further plurality of patterns on said document are sensed by said sensing means, said further means effecting sequential comparing by said comparing means of the nature of said further sensed data, obtained during the sensing of said patterns of said further plurality of patterns by said sensing means, with said further pre-programmed data sequentially read from said pre-programmed memory, utilization means to develop a utilization signal if said further sensed data, obtained during the sensing of said patterns of said further plurality of patterns by said sensing means, corresponds in nature and in sequence with said further pre-programmed data within said pre-programmed memory, an inhibiting circuit that inhibits said utilization means during said comparing of the first said sensed data, obtained during the sensing of the first said patterns by said sensing means, with the first said pre-programmed data sequentially read from said pre-programmed memory, said inhibiting circuit inhibiting said additional means during said comparing of said further sensed data, obtained during the sensing of said patterns of said further plurality of patterns by said sensing means, with said further pre-programmed data sequentially read from said pre-programmed memory, and a pre-programmed means which causes said inhibiting circuit to inhibit said utilization means and said additional means in a predetermined sequence, whereby said additional means can effect validation of a document and said utilization means can develop said utilization signal only if the patterns on such document enable said sensing means to develop sensed data which corresponds in nature and in sequence with said pre-programmed data within said pre-programmed memory and only if said further sensed data obtained during the sensing of some of such patterns corresponds in nature and in sequence with said further pre-programmed data within said pre-programmed memory.

25. A validator which comprises sensing means that can sense a plurality of predetermined patterns on a document in a predetermined sequence to effect the developing of sensed data, a first recognition circuit to which said sensed data is applied, a second recognition circuit to which said sensed data is applied, said sensing means responding to one of said predetermined patterns on said document to effect the developing of sensed data in the form of a signal to which said first recognition circuit will respond but to which said second recognition circuit can not respond, said sensing means responding to a second of said predetermined patterns on said document to effect the developing of sensed data in the form of a signal to which said second recognition circuit will respond but to which said first recognition circuit can not respond, said sensing means not responding to a spurious pattern to develop signals to which either of said recognition circuits will respond, said first recognition circuit normally having a first logic level signal at the output thereof but acting whenever it responds to sensed data corresponding to said one predetermined pattern on said document to develop a second logic level signal at said output thereof, said second recognition circuit normally having a third logic level signal at the output thereof but acting whenever it responds to sensed data corresponding to said predetermined pattern on said document to develop a fourth logic level signal at said output thereof, said recognition circuits always providing two of said four logic level signals, pre-programmed means that can not respond to just one of said four logic level signals to develop pattern-recognition data but that responds to the developing of a predetermined combination of two of said four logic level signals to develop predetermined pattern-recognition data and that reponds to the developing of a second and different predetermined combination of two of said four logic level signals to develop a second and different predetermined pattern-recognition data, said pre-programmed means sensing the sequence in which the first said predetermined pattern-recognition data and said second and different predetermined pattern-recognition data were developed and thereby indicating the sequence in which said one predetermined pattern on said document and said second predetermined pattern on said document were sensed, and further means responsive to the indication provided by said pre-programmed means to indicate whether the sequence of sensing of said one predetermined pattern on said document and of said second predetermined pattern on said document correspond to the sequence of sensing of corresponding patterns on a valid and acceptable document.

26. A validator which comprises sensing means that can sense a plurality of predetermined patterns on a document in a predetermined sequence to effect the developing of sensed data, a first recognition circuit to which said sensed data is applied, a second recognition circuit to which said sensed data is applied, said sensing means responding to one of said predetermined patterns on said document to effect the developing of sensed data in the form of a signal to which said first recognition circuit will respond but to which said second recognition circuit can not respond, said sensing means responding to a second of said predetermined patterns on said document to effect the developing of sensed data in the form of a signal to which said second recognition circuit will respond but to which said first recognition circuit can not respond, said sensing means not responding to a spurious pattern to develop signals to which either of said recognition circuits will respond, said first recognition circuit normally having a first logic level signal at the output thereof but acting whenever it responds to sensed data corresponding to said one predetermined pattern on said document to develop a second logic level signal at said output thereof, said second recognition circuit normally having a third logic level signal at the output thereof but acting whenever it responds to sensed data corresponding to said second predetermined pattern on said document to develop a fourth logic level signal at said output thereof, said recognition circuits always providing two of said four logic level signals, pre-programmed means that senses the sequence in which the first said predetermined pattern-recognition data and said second and different predetermined pattern-recognition data were developed and thereby indicating the sequence in which said one predetermined pattern on said document and said second predetermined pattern on said document were sensed, and further means responsive to the indication provided by said pre-programmed means to indicate whether the sequence of sensing of said one predetermined pattern on said document and of said second predetermined pattern on said document correspond to the sequence of sensing of corresponding patterns on a valid and acceptable document, any patterns of said plurality of predetermined patterns on said document which have different values being defined by differently spaced-apart lines, said sensing means developing signals having different frequencies corresponding to different spacings of said differently spaced-apart lines, said first recognition circuit including a frequency detector which responds to said sensed data to develop at least one of said logic level signals, said second recognition circuit including a second frequency detector which responds to said sensed data to develop at least another of said logic level signals, said frequency detectors having the form of printed circuits on removable circuit boards, and said validator being enabled to accept documents wherein the patterns thereon have been transposed by making a corresponding transposition in the positions of said removable circuit boards.

27. A validator which comprises a sensor, a frequency detector, a second frequency detector, means connecting the output of said sensor to both of said frequency detectors, said sensor responding to a predetermined authentic pattern on an authentic document to develop a frequency to which one of said frequency detectors will respond but to which the other of said frequency detectors will not respond, said sensor responding to a second predetermined authentic pattern on said authentic document to develop a frequency to which another of said frequency detectors will respond but to which said one of said frequency detectors will not respond, said sensor not responding to a spurious pattern to develop signals to which either of said frequency detectors will respond, the first said frequency detector normally having a first signal at the output thereof but acting whenever it responds to an acceptable frequency that is applied to the input thereof to develop a second signal at said output thereof, said second frequency detector normally having a third signal at the output thereof but acting whenever it responds to a proper frequency that is applied to the input thereof to develop a fourth signal at said output thereof, pre-programmed means which responds to the developing of said second signal and to the continuing existence of said third signal to indicate that the first said frequency detector has responded to said output of said sensor to determine that an acceptable frequency has been applied to said input of said first said frequency detector and that said second frequency detector has determined that an acceptable frequency has not been supplied to said input of said second frequency detector, said pre-programmed means responding to the developing of said fourth signal and to the continuing existence of said first signal to indicate that said second frequency detector has responded to said output of said sensor to determine that an acceptable frequency has been supplied to said input of said second frequency detector and that said first said frequency detector has determined that an acceptable frequency has not been applied to said input of said first said frequency detector, a comparing means, further means enabling said comparing means to determine whether the sensing of a document by said sensor has caused the signals at said output of the first said frequency detector to cause said pre-programmed means to indicate that an acceptable frequency has been applied to said input of said first said frequency detector, said further means also enabling said comparing means to determine whether the sensing of said document by said sensor has caused the signals at said output of said second frequency detector to cause said pre-programmed means to indicate that an acceptable frequency has been applied to said input of said second frequency detector, said further means also enabling said comparing means to indicate which of said frequency detectors responded to said sensing of said authentic document by said sensor to change the signal at said output thereof, and selection-indicating means which coacts with said further means to determine the sequence in which the first said predetermined authentic pattern and said second predetermined authentic pattern on said authentic document were sensed by said sensor and thereby indicates which of a plurality of selections is desired.

28. A validator which comprises sensing means that can sense a plurality of predetermined patterns on a document in a predetermined sequence to effect the developing of sensed data, a first recognition circuit to which said sensed data is applied, a second recognition circuit to which said sensed data is applied, said sensing means responding to one of said predetermined patterns on said document to effect the developing of sensed data in the form of a signal to which said first recognition circuit will respond but to which said second recognition circuit can not respond, said sensing means responding to a second of said predetermined patterns on said document effect the developing of sensed data in the form of a signal to which said second recognition circuit will respond but to which said first recognition circuit can not respond, said sensing means not responding to a spurious pattern to develop signals to which either of said recognition circuits will respond, said first recognition circuit normally having a first logic level signal at the output thereof but acting whenever it responds to sensed data corresponding to said one predetermined pattern on said document to develop a second logic level signal at said output thereof, said second recognition circuit normally having a third logic level signal at the output thereof but acting whenever it responds to sensed data corresponding to said second predetermined pattern on said document to develop a fourth logic level signal at said output thereof, said recognition circuits always providing two of said four logic level signals, pre-programmed means sensing the sequence in which the first said predetermined pattern-recognition data and said second and different predetermined pattern-recognition data were developed and thereby indicating the sequence in which said one predetermined pattern on said document and said second predetermined pattern on said document were sensed, further means responsive to the indication provided by said pre-programmed means to indicate whether the sequence of sensing of said one predetermined pattern on said document and of said second predetermined pattern on said document correspond to the sequence of sensing of corresponding patterns on a valid and acceptable document, and selection-indicating means which responds to the sensing of additional patterns on said document by said sensing means to determine the sequence in which said additional patterns were sensed by said sensing means, and thereby indicates the particular selection that is desired.

29. A validator which comprises sensing means that can sense a plurality of predetermined patterns on a document in a predetermined sequence to effect the developing of sensed data, a first recognition circuit to which said sensed data is applied, a second recognition circuit to which said sensed data is applied, said sensing means responding to one of said predetermined patterns on said document to effect the developing of sensed data in the form of a signal to which said first recognition circuit will respond but to which said second recognition circuit can not respond, said sensing means responding to a second of said predetermined patterns on said document to effect the developing of sensed data in the form of a signal to which said second recognition circuit will respond but to which said first recognition circuit can not respond, said sensing means not responding to a spurious pattern to develop signals to which either of said recognition circuits will respond, said first recognition circuit normally having a first logic level signal at the output thereof but acting whenever it respond to sensed data corresponding to said one predetermined pattern on said document to develop a second logic level signal at said output thereof, said second recognition circuit normally having a third logic level signal at the output thereof but acting whenever it responds to sensed data corresponding to said second predetermined pattern on said document to develop a fourth logic level signal at said output thereof, said recognition circuits always providing two of said four logic level signals, preprogrammed means which responds to signals that are developed in response to the sensing of a given first of said predetermined patterns on said document and which responds to next-succeeding signals that are developed in response to the sensing of a given second of said predetermined patterns to provide an indication that an authentic document having authentically oriented predetermined patterns thereon was sensed, said preprogramming means indicating than an authentic document having authentically-oriented predetermined patterns thereon was not sensed if it receives signals that are developed in response to the sensing of said given first of said predetermined patterns on said document and to the sensing of said given second of said predetermined patterns but receives signals corresponding to a third pattern after it receives said signals that are developed in response to the sensing of said given first of said predetermined pattern on said document but before it receives said signals that are developed in response to the sensing of said given second of said predetermined patterns, said pre-programmed means being conditioned, as a result of the sensing of said given first of said predetermined patterns, to anticipate the sensing of said given second of said predetermined patterns.

Description

FIELD OF THE INVENTION

The use of one dollar and of higher denomination bills to actuate dispensing machines is becoming progressively popular. However, there are some situations where it is desirable to use scrip rather than money to effect the dispensing of a desired product, material or service. Where scrip is used, an exceptionally high degree of selectivity must be incorporated into the validator for that scrip, because there is far less risk of legal repercussions in the simulating of scrip than there is in the simulating of currency of the United States. The present invention relates to scrip validators which can provide a high degree of selectivity.

SUMMARY OF THE INVENTION

The piece of scrip that is provided by the present invention is engraved or printed with groups of patterns which can be sensed by a validator for scrip; and one of those groups of patterns will define a code which will permit that piece of scrip to be accepted only by a scrip validator or by scrip validators which have that same code stored therein. Two additional groups of patterns define codes which can cause that scrip validator or those scrip validators to automatically respond to the codes stored therein to actuate price-determining relays within a vending machine. It is, therefore, an object of the present invention to provide a piece of scrip which has a number of groups of patterns thereon, which uses one of those groups of patterns to restrict the use of that piece of scrip to a specific scrip validator or to a specific group of scrip validators, and which uses additional of those groups of patterns to cause that scrip validator or those scrip validators to automatically respond to the codes stored therein to actuate price-determining relays within a vending machine.

Each pattern is formed by a number of spaced parallel lines, and the various patterns on a piece of scrip can be given different identities merely by changing the spacing between the trailing edges of those spaced parallel lines. The patterns in each group of patterns will be sensed in a prescribed sequence, and the sequentially sensed patterns in any of those groups of patterns can be given various identities. As a result, the scrip validator of the present invention can accept a piece of scrip which has a given number of patterns of specifically different identities and yet reject a piece of scrip which has those same patterns arranged in a different sequence. In this way, the present invention makes it possible to use permutations, rather than mere combinations, of potentially usable pattern identities, and thus makes it possible to use just 15 specifically different pattern identities to make 32,760 different pieces of scrip. It is, therefore, an object of the present invention to provide pieces of scrip which have the patterns thereon formed by spaced parallel lines and to provide a scrip validator which senses the patterns on each piece of scrip in a prescribed sequence and hence can distinguish between pieces of scrip which use the same patterns in different positions thereon.

The scrip validator of the present invention stores the codes, which correspond to the codes defined by the patterns on the piece of scrip in serially shifted shift registers; and, as each pattern on the piece of scrip is sensed by the scrip validator, the data within the shift registers is serially shifted a plurality of times. The identity of any given pattern can be determined by three signals; and, by utilizing serially shifted shift registers which have seven or more stages, the present invention enables each shift register to store the pattern-identifying data for at least two patterns. In addition, the serial shifting of the shift registers permits the pattern-identifying data for the various patterns to be presented in fixed sequences. Moreover, by merely changing some of the connections to the parallel and serial input terminals of the shift registers, it is possible to change the codes stored within those shift registers. It is, therefore, an object of the present invention to provide a scrip validator which stores the codes, that correspond to the codes defined by the patterns on the piece of scrip, in serially shifted shift registers and to serially shift those shift registers a plurality of times as each pattern is being sensed.

The shift registers of the present invention are provided with data-converting subcircuits which will shift new data into those shift registers during the sensing of the patterns on a piece of scrip. Those data-converting subcircuits act to increase the code-storing capabilities of those shift registers. It is, therefore, an object of the present invention to provide a scrip validator wherein the shift registers are provided with data-converting sub-circuits which increase the code-storing capabilities of those shift registers.

A person who makes a simulation of an authentic U.S. bill exposes himself to serious legal repercussions, but a person who simulates a piece of scrip does not expose himself to such serious legal repercussions. Consequently, to be practical, a scrip validator must not only be highly selective but must be capable of being quickly and easily reprogrammed. The scrip validator of the present invention has a number of frequency-sensing circuits; and those circuits are grouped so some of them respond to one set of patterns on each piece of scrip and so the others respond to a second set of patterns on each piece of scrip. Those are made as plug-in boards which are interchangeable with each other. If one or more persons develop a piece of scrip which will be accepted by the scrip validator, it is only necessary to replace the frequency-sensing circuits for the one set of patterns on each piece of scrip with the frequency-sensing circuits for the second set of patterns on each piece of scrip and vice versa; and, at such time, that scrip validator will effectively reject that piece of scrip. It is, therefore, an object of the present invention to provide a scrip validator which has a number of frequency-sensing circuits that are made as plug-in boards which are interchangeable with each other and which are grouped so some of them respond to one set of patterns on each piece of scrip and so the others respond to a second set of patterns on each piece of scrip.

In the scrip validator of the present invention, the frequency which identifies each pattern is sensed by the combination of a digital filter and a counter. The digital filter could not provide sufficient security for the scrip validator if it was the sole test of the identity of a pattern on a piece of scrip; because the first pulse of a given frequency will set that digital filter, and then the second pulse of that same frequency would cause that digital filter to develop an output. This means that if a digital filter was used as the sole test of the identity of a pattern on a piece of scrip, any two properly spaced lines on a piece of scrip could be accepted by that digital filter. By providing the combination of a digital filter and a counter, the scrip validator of the present invention provides a strict test of the identification of each pattern because it requires the frequency which corresponds to the spacing of the trailing edges of the lines of that pattern to match the frequency of the digital filter, and it also requires that pattern to have a minimum number of lines which have that same spacing. It is, therefore, an object of the present invention to provide a scrip validator wherein the frequency which identifies each pattern is sensed by the combination of a digital filter and a counter.

Other and further objects and advantages of the present invention should become apparent from an examination of the drawing and accompanying description.

In the drawing and accompanying description, a preferred embodiment of the present invention is shown and described but it is to be understood that the drawing and accompanying description are for the purpose of illustration only and do not limit the invention and that the invention will be defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWING

In the drawing, FIG. 1 is a partially broken-away partially sectioned front elevational view of one preferred embodiment of scrip transport which can be used as part of the scrip validator of the present invention,

FIG. 2 is a rear elevational view of the scrip transport of FIG. 1,

FIG. 3 is a vertical section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 3--3 in FIG. 1,

FIG. 4 is another vertical section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 4--4 in FIG. 1,

FIG. 5 is a horizontal section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 5--5 in FIG. 3,

FIG. 6 is another horizontal section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 6--6 in FIG. 3,

FIG. 7 is a further horizontal section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 7--7 in FIG. 3,

FIG. 8 is a further vertical section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 8--8 in FIG. 4,

FIG. 9 is a still further vertical section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 9--9 in FIG. 8,

FIG. 10 is a still further horizontal section through the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 10--10 in FIG. 8,

FIG. 11 is a vertical section, on a larger scale, through the rear portion of the scrip transport of FIGS. 1 and 2, and it is taken along the plane indicated by the line 11--11 in FIG. 6,

FIG. 12 is yet another vertical section through the scrip transport of FIGS. 1 and 2, and it is taken along the broken plane indicated by the broken line 12--12 in FIG. 3,

FIG. 13 is a plan view of a piece of scrip which has eight patterns thereon,

FIG. 14 is a perspective view of four frequencysensing circuits which are made as printed circuit boards and of a board into which they are plugged,

FIG. 15 shows the relative positions which FIGS. 16-23 occupy when they are placed to display the circuit of the scrip validator,

FIGS. 16-23 are portions of the circuit of the scrip validator,

FIG. 24 is a detailed showing of the PEAK DETECTOR block in FIG. 16,

FIG. 25 is a detailed showing of one of the FREQUENCY DETECTOR blocks of FIG. 16, and

FIG. 26 is a detailed showing of the ENVELOPE DETECTOR block of FIG. 16.

DESCRIPTION OF SCRIP TRANSPORT

Referring to FIGS. 1-12, the numeral 30 generally denotes one preferred embodiment of scrip transport that is made in accordance with the principles and teachings of the present invention. The numeral 32 denotes a platform which extends outwardly from the front of that scrip transport; and that platform will receive the leading edge of each piece of scrip which is to be tested by the scrip validator of which that scrip transport is a part. A flange 34 and a flange 35 of generally triangular configurations extend upwardly from the sides of the platform 32; and that platform has an upwardly inclined inner end 38 which merges into a platen 40. An elongated flange 42 and an elongated flange 43 extend downwardly from the elongated sides of the platen 40. The numeral 45 denotes the trailing edge of the platen 40; and that trailing edge inclines downwardly and then terminates in a vertically directed lip, as shown by FIGS. 3 and 4.

The numeral 62 denotes a headed pin which is secured to the flange 42 and which is adjacent the front of the scrip transport 30. The numeral 64 denotes a further headed pin which is supported by the flange 42 and which is spaced to the right of the headed pin 62. The numeral 63 denotes an elongated pivot which is secured to the flanges 42 and 43 and which is spaced to the right of the headed pin 64.

The numeral 67 denotes a headed pin which is secured to the flanges 43 and which is in register with the headed pin 64, and the numeral 68 denotes a headed pin which is secured to the flange 43 and which is in register with the headed pin 62, all as shown by FIG. 5.

The numeral 70 denotes a leaf-type spring which is bent so the right-hand end thereof inclines upwardly to bear against the under surface of the platen 40. That spring is bent to have a downwardly opening saddle which rests upon the headed pin 64, to have an elongated portion which inclines upwardly and to the left from that saddle, and to have a bifurcated left-hand end with fingers that define an upwardly opening saddle. The numerals 72 and 74 denote springs which can be identical to the spring 70; but the bifurcated ends of those springs extend to the right rather than to the left in FIGS. 4 and 5. The downwardly opening saddle of spring 72 rests upon the headed pin 62; and hence that spring is adjacent the front of the platen 40. The downwardly opening saddle of the spring 74 rests upon the elongated pivot 63; and hence that spring is adjacent the trailing edge of that platen. The numerals 73, 75 and 77 denote leaf-type springs which preferably are identical to, and in register with, the springs 72, 70 and 74. The downwardly opening saddles of springs 73, 75 and 77 rest, respectively, upon headed pin 68, headed pin 67 and elongated pivot 63.

A short pivot 80 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 72; and that pivot rotatably supports a roller 82. A similar pivot 84 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 70; and that pivot rotatably supports a roller 86. A further similar pivot 88 is supported by the upwardly opening saddle which is defined by the fingers at the bifurcated end of the spring 74; and that pivot rotatably supports a roller 90. The numerals 89, 83 and 87 denote pivots which are in register with the pivots 80, 84 and 88 and which are supported by the upwardly opening saddles that are defined by fingers at the bifurcated ends of springs 73, 75 and 77. The pivots 89, 83 and 87 rotatably support rollers 92, 85 and 91.

The numeral 98 denotes an arm which has a hub that encircles the elongated pivot 63; and a pivot 100 is fixedly secured to the outer end of that arm. That pivot rotatably supports a roller 102. An arm 110 also has the hub thereof encircling the elongated pivot 63; and a pivot 112 is fixedly secured to the outer end of that arm. That pivot rotatably supports a roller 114. Springs, not shown, encircle the elongated pivot 63 and urge the rollers 102 and 114 upwardly relative to the platen 40.

The numeral 118 denotes an upper platen which normally is disposed in parallel relation with, and in close proximity to, the platen 40. The platen 118 has downwardly directed flanges 120 and 121 at its elongated sides; and each of those flanges has a downwardly opening slot 122 adjacent the front end thereof. The numeral 124 denotes a semi-cylindrical leading edge of the platen 118; and that semi-cylindrical leading edge is disposed forwardly of the upwardly inclined rear portion 38 of the platform 32. The platen 118 has an upwardly inclined trailing edge 126, as shown by FIGS. 3 and 4.

The numeral 140 denotes a cover for the scrip transport 30; and that cover has downwardly directed flanges 142 and 143 at the elongated sides thereof. The numeral 144 denotes a switch bracket which is secured to the cover 140; and that switch bracket holds a normally open, single-pole, single-throw switch 146 adjacent the front of the platen 118. The numeral 148 denotes a sturdy but thin actuator for the switch 146; and that actuator extends downwardly through slots in the platens 118 and 40. The leading edge of that actuator is essentially straight, but the trailing edge is convex. The configurations and inclinations of the leading and trailing edges of actuator 148 enable the leading edge and trailing edge, respectively, of a piece of scrip to easily raise that actuator upwardly out of the slot in the platen 40. As a result, the switch actuator 148 permits relatively free movement of pieces of scrip inwardly and outwardly of the scrip transport 30.

The numeral 154 denotes a second swiitch bracket which is secured to the cover 140; and that switch bracket supports a normally-open, single-pole, single-throw switch 156. The numeral 158 denotes a sturdy but thin actuator for the switch 156; and that actuator extends downwardly through slots in the platens 118 and 40. The configuruations and inclinations of the leading and trailing edges of the switch actuator 158 enable the leading edge and trailing edge, respectively, of a piece of scrip to easily raise that actuator upwardly out of the appropriate slot in the platen 40. As a result, the switch actuator 158 permits relatively free movement of pieces of scrip inwardly and outwardly of the scrip transport 30.

The numeral 160 denotes a third switch bracket which is secured to the cover 140; and that switch bracket is adjacent the rear of that cover. That switch bracket supports a normally open, single-pole, single-throw switch 162; and that switch has an actuator 164 which extends downwardly through slots in the platens 118 and 40. If a person were to attempt to pull a piece of scrip outwardly of the scrip transport 30, after the trailing edge of that piece of scrip had been moved inwardly beyond the actuator 164, that piece of scrip would be intercepted by that actuator. In that event, the actuator 164 would make it impossible for that person to recover that piece of scrip in intact form.

The numerals 188 and 190 denote pulleys which are mounted on short pivots 189 and 187 that are supported by the flange 142; and the numeral 194 denotes a pulley which is mounted on one end of an elongated shaft 182 that is rotatably supported by bushings which are mounted in the flanges 142 and 143. The pulleys 188, 190 and 194 accommodate a elongated endless belt 198; and the lower "run" of that belt is engaged by the upper portions of the rollers 82, 86 and 90. The numerals 191 and 193 denote pulleys which are mounted on short pivots 185 and 183 that are supported by the flange 143; and the numeral 195 denotes a pulley which is mounted on the other end of the elongated shaft 182. The pulleys 191, 193 and 195 support an endless belt 199. A worm wheel 200 is fixedly secured to the shaft 182; and a worm gear 202 meshes with that worm wheel. That worm gear is mounted on the output shaft 203 of a D.C. motor 562 which is enclosed by a motor housing 204 that extends upwardly from the cover 140. That motor is a reversible permanent magnet D.C. motor which drives an A.C. generator by means of an internal connection. That A.C. generator is located within the motor housing 204; and that connection is a direct mechanical connection. In the said preferred embodiment of script transport, the motor 562, the A.C. generator and the connection are parts of a type CYQM Motor With Integral Tachometer Generator which is marketed by the Barber Colman Company as model No. CYQM 23360-3. When the motor 562 is energized in the "forward" direction, it will directly drive the A.C. generator in that direction, and it will drive the lower "runs" of the belts 198 and 199 inwardly of the scrip transport 30. When the motor is energized in the "reverse" direction, it will directly drive the A.C. generator in that direction, and it will drive the lower "runs" of belts 198 and 199 outwardly of that scrip transport.

The numeral 206 denotes a mounting bracket which fixedly holds magnetic heads 208 and 210 in spaced-apart relation. Those magnetic heads are spaced both laterally and longitudinally of the elongated axis of the scrip transport 30; and hence the air gaps of those magnetic heads will sense two laterally spaced, longitudinally extending paths.

The numeral 220 denotes an elongated pivot which has the opposite ends thereof secured to the rear portions of the flanges 120 and 121 on the upper platen 118; and that pivot extends through aligned openings in the flanges 42 and 43 on the lower platen 40. As a result, the pivot 220 enables the upper platen 118 -- and the cover 140 plus the various components which are mounted on that upper platen and on that cover -- to be rotated upwardly and away from the lower platen 40. Such rotation is desirable; because it permits ready and free access to the passageway defined by the lower platen 40 and the upper platen 118. However, the upper platen 118 will normally respond to its weight, to the weight of the cover 140, and to the weight of the components mounted on that upper platen and on that cover to urge the lower face of the lower "runs" of the belts 198 and 199 into intimate engagement with the upper faces of the rollers 82, 85, 86, 90, 91 and 92. The springs 70, 72, 73, 74, 75 and 77 will yield slightly in response to the combined weights of the upper platen 118, of the cover 140, and of the components which are carried by that upper platen and by that cover; but those springs will hold the upper surfaces of the rollers 82, 85, 86, 90, 91 and 92 above the upper surface of the lower platen 40. Those rollers and the rollers 102 and 114 are in register with openings in that lower platen.

The numeral 170 denotes a switch bracket which is secured to the cover 140 a short distance to the right of the switch bracket 144, as those switch brackets are viewed in FIG. 1. The former switch bracket supports a single-pole single-throw switch 494 which has an actuator 174; and that switch is biased toward closed position. As indicated particularly by FIG. 3, the switch 494 is located adjacent the front of the scrip transport 30.

The numeral 176 denotes an elongated pivot which has the ends thereof disposed in openings in the flanges 142 and 143 on the cover 140. The numeral 178 denotes a blocking member which is U-shaped in plan, and which has downwardly extending fingers 180 and 181 at the free ends of the arms thereof. Those fingers are dimensioned to extend downwardly through slots 168 and 166 in the upper platen 118, and also to extend downwardly through slots 172 and 171 in the lower platen 40. As indicated particularly by FIG. 8, the slots 166 and 171 are in vertical registry and the slots 168 and 172 are in vertical registry. An ear 184 extends outwardly from that arm of the blocking member 178 of which the finger 181 is a part, as shown particularly by FIG. 8; and that ear underlies the actuator 174 of switch 494, as shown by FIGS. 8 and 10. An arcuate slot 213 is provided in that arm of the blocking member 178 of which the finger 181 is a part, and that slot is shown by FIG. 9. The numeral 214 denotes a torsion spring which encircles the left-hand end of the elongated pivot 176, as that pivot is viewed in FIGS. 8 and 10. One end of that torsion spring bears against the under surface of the cover 140, and the other end of that spring bears against the ear 184 on blocking member 178; and that torsion spring biases the fingers 180 and 181 of that blocking member downwardly relative to the platens 118 and 40. However, that spring can yield to permit that blocking member to be moved to the upper position shown by FIG. 9.

A solenoid 388 is mounted on the cover 140; and the plunger 389 of that solenoid has a slot in the lower end thereof. That slot accommodates a portion of the arm of the blocking member 178 which has the slot 213 therein; and a pin 391 extends through aligned openings in the plunger 389 and through the slot 213. That slot enables the solenoid 388 to rotate the blocking member 178 in the counterclockwise direction into the position of FIG. 9 without any binding of pin 391 in that slot. The numeral 393 denotes a helical compression spring which biases the plunger 389 and the blocking member 178 for movement to the position shown by FIGS. 3, 4 and 8; but that spring will yield to permit the solenoid 388 to raise that blocking member to the position shown by FIG. 9.

The numeral 46 denotes a rectangular opening in the lower platen 40 adjacent the front of that platen; and that opening accommodates the upper portion of a plastic mounting 50 for a U-shaped permanent magnet 48. Screws 52 are used to fixedly hold the upper portion of the plastic mounting 50 in position within the opening 46. That magnet will, as a tape, card, or other object is introduced into the scrip transport 30, erase any information which has been encoded into the magnetic particles on that tape, card or other object.

The numeral 216 denotes a toothed member which is mounted within an opening 217 in the upper platen 118, as shown particularly by FIG. 11. The teeth on that toothed member have gently-inclined leading edges but abruptly inclined trailing edges. The numeral 218 denotes a toothed member which is U-shaped in elevation, as shown particularly by FIG. 2; and the teeth on that toother member are on the upper edges of the sides of that toothed member. The lower edges of those sides incline upwardly from front to rear, as indicated particularly by FIG. 11. Generally L-shaped slots 222 are provided at the left-hand ends of the sides of the toothed member 218, as shown particularly by FIGS. 3, 4 and 11; and those slots accommodate the elongated pivot 63. Projections 224 are provided on each side of the toothed member 218; and one of those projections is shown in detail in FIG. 11. Helical compression springs 226 telescope downwardly over those projections; and the upper ends of those springs bear against the under surface of the platen 40 while the lower ends of those springs bear against the sides of the toothed member 218. The teeth on the upper edges of the sides of the toothed member 218 have gently inclined leading edges but abruptly inclined trailing edges, as emphasized particularly by FIG. 11.

The numeral 221 denotes a block which has a horizontally directed opening therein which can telescope over the elongated pivot 220; and that block is dimensioned to fit under the downwardly inclined trailing edge 45 of the lower platen 40. The shank of a bolt 223 extends through a horizontally directed opening in the block 221 which is set at right angles to the opening which accommodates the elongated pivot 220. A nut 225 is threaded onto the shank of the bolt 223 to hold that bolt in assembled relation with the block 221. A cam 227, which has the form of a right-circular cylinder with reduced-diameter ends, has a threaded opening therethrough which accommodates the shank of the bolt 223. The reduced-diameter ends of the cam 227 are in register with the upwardly inclined lower edges of the sides of the toothed member 218, as shown by FIG. 5.

The numeral 165 denotes a closure for the bottom of the scrip transport 30; and upwardly extending flanges on that closure extend upwardly above the lower edges of the flanges 142 and 143 of the cover 140. A hardened bearing plate 228 is provided on the upper surface of the bottom of the closure 165; and that hardened bearing plate is in register with the cam 227. That hardened bearing plate will fully support the cam 227, and it will permit repeated shifting of the position of that cam with little wear.

The numeral 147 denotes vertically directed slots which are provided in the flanges 42 and 43 of the platen 40, and those slots are in register with each other. The numeral 149 denotes a latching member which has the right-hand end thereof extending through the slot 147 in the flange 43, as indicated particularly by FIG. 12; and the numeral 151 denotes a similar latching member which has the left-hand end thereof extending through the slot 147 in the flange 42 on the platen. The right-hand end of the latching member 149 also extends into a slot 157 in the flange 121 of the upper platen 118; and the left-hand end of the latching member 151 extends into a slot 157 in the flange 120 of that upper platen. The slots 157 are similar to, and are in register with, the slots 147 in the flanges 42 and 43 of the lower platen 40. A helical compression spring 153 encircles the central portions of the latching members 149 and 151, and it urges the left-hand end of latching member 151 into the slot 157 in flange 120 while urging the right-hand end of latching member 149 into the slot 157 in the flange 121, as those latches and flanges are viewed in FIG. 12. However, that spring can yield to permit the latching members 149 and 151 to be moved inwardly until they are clear of the slots 157 in the flanges 120 and 121 of the platen 118. A rotatable latch release 155 is rotatably mounted within an opening in the closure 165 for the bottom of the scrip transport 30; and that latch release has a slot in the under surface thereof which can accommodate a screwdriver blade or other stiff object and which can respond to rotation of that screwdriver blade or other stiff object to rotate that latch release. The rotation of that latch release will enable ears, which are on the upper surface thereof and which are shown particularly by FIG. 5, to move the latching members 149 and 151 inwardly of the slots 157 in the flanges 120 and 121 of the platen 118.

The scrip transport 30 is essentially identical to the identically numbered bill transport in the Fishel et al U.S. Pat. No. 3,845,469, except that the magnetic head 210 has been shifted closer to the leading edge of the platen 118, that the magnet 48 has been added, that the blocking member 178 and the elements associated with it have been added, that the toothed members 216 and 218 and the elements associated with the latter toothed member have been added, that the closure 165 has been added, and that the latches 149 and 151 and the elements associated with them have been added. In the said preferred embodiment of scrip transport, the air gaps of the magnetic heads 208 and 210 define parallel lines which are transverse of the longitudinal axis of the platen 118 and which are spaced apart one-half of an inch. The inner faces of the magnetic heads 208 and 210 are spaced apart one-sixteenth of an inch transversely of the longitudinal axis of the platen 118.

The blocking member 178, the solenoid 388, the toothed members 216 and 218, and the adjusting members associated with those toothed members are not, per se, parts of the present invention. Those various members are disclosed and claimed in James R. Pescetto application Ser. No. 405,538 for ANTI-RETRIEVAL DEVICE which was filed on Oct. 11, 1973.

Description of Circuit of Scrip Validator: The numeral 230 in FIG. 21 denotes a TIMING BLOCK which includes a BINARY COUNTER 238, a timer 248, NOR gates 232, 235, and 236, NAND gates 240, 242 and 246, an inverter 244, resistors 250 and 252, and capacitors 254, 256 and 258. Although different timers could be used as the timer 248, a Signetics NE555V timer has been found to be very useful. The upper terminal of resistor 250 is connected to a source of regulated twelve volts D.C.; and that resistor coacts with resistor 252 and with capacitors 254, 256 and 258 to cause timer 248 to operate as a pulse generator which will apply pulses to the input terminal of BINARY COUNTER 238 at the rate of one every sixteen and seven-tenths milliseconds. Conductors 260, 262, 264, 266, 268, 270, 272 and 284 extend into that block, and conductors 278, 280, 282 and 286 extend from that block.

The numeral 288 denotes a MULTIPLEXER block which includes a multiplexer 296, NOR gates 292 and 294, an inverter 290, a resistor 298 and a capacitor 300. Although various multiplexers could be used, an RCA 4051 multiplexer has been found to be very useful. That capacitor and that resistor constitute an RC network. Conductors 262, 266, 268, 274, 276, 278 and 280 extend into that block, a conductor 302 extends from that block, and conductors 282 and 284 are shown merely passing through that block.

The numeral 304 in FIG. 22 denotes an ACCEPT LATCH block which includes an NPN transistor 316, a Zener diode 326, resistors 310, 318, 320, 322 and 324, capacitors 314 and 329, and NAND gates 306 and 308. The resistor 310 and the capacitor 314 constitute an RC network which will provide a slight delay time whenever a 0 at the upper input of NAND gate 306 is to be changed to a 1. That NAND gate and NAND gate 308 constitute an electronic "latch" 307 which will respond to the application of a 0 to the upper or middle input of NAND gate 306 to apply a continuous 1 to conductor 330 and to apply a continuous 0 to conductor 284. The transistor 316, the Zener diode 326, the capacitor 329, and the resistors 318, 320, 322 and 324 constitute a "line cording" circuit that is similar to the "line cording" circuit in Carter et al application Ser. No. 405,535, now U.S. Pat. No. 3,870,629, which is entitled PAPER CURRENCY VALIDATOR and which was filed on Oct. 11, 1973. That "line cording" circuit differs from the "line cording" circuit in the said Carter et al application in that the transistor 316 normally is non-conductive whereas the corresponding transistor in the said Carter et al application normally is conductive. In both line cording circuits, the Zener diode controls the state of conductivity of the transistor and will respond to changes in the state of conductivity of that transistor before the changes in supply voltage can cause improper operation of the overall circuit of the scrip validator. The line cording circuit in the ACCEPT LATCH block 304 is an equivalent of the line cording circuit of the said Carter et al application and is not, per se, a part of the present invention. Conductors 312 and 286 extend into that block, and conductors 284 and 330 extend from that block.

The numeral 334 denotes a COLLECT block which includes a single-pole single-throw switch 336, resistors 338 and 344, a diode 340, a capacitor 346, and an opto-coupler 342. The switch 336 will be located in the vending machine with which the scrip validator of the present invention is associated; and that switch will close momentarily each time that vending machine dispenses a product. A conductor 312 extends from that block.

The numeral 348 denotes a MOTOR START AND RUN block which includes a MOTOR CONTROLLING sub-block 354; and that sub-block includes the SPEED ADJUSTING sub-block, the SPEED MAINTAINING sub-block, and the MOTOR AND RELAY sub-block in the identically numbered MOTOR CONTROLLING block in the said Carter et al application. The MOTOR START AND RUN block 348 also includes NOR gates 350, 353 and 364, a NAND gate 360, inverters 352, 356 and 362, diodes 355 and 366, and a resistor 368. Conductors 260, 262, 268, 274, 330, 333, 436 and 439 extend into that block, conductor 330 extends from that block, and conductors 282, 284 and 302 are shown merely passing through that block.

The numeral 370 denotes a BLOCKING FINGER CONTROL block which includes NPN transistors 386 and 406, NOR gates 380 and 392, NAND gates 376 and 396, inverters 378, 382, 394 and 398, solenoid 388, diode 390, resistors 372, 384, 402, 404 and 408, and capacitors 374 and 400. Resistor 372 and capacitor 374 constitute an RC network which will slightly delay any change of a 0 at the upper input of NAND gate 376 to a 1. Resistor 402 and capacitor 400 also constitute an RC network. Conductors 260, 262, 266 and 284 extend into that block, conductors 284, 410 and 439 extend from that block, and conductors 282, 302, 330, 333 and 436 are shown merely passing through that block.

The numeral 412 in FIG. 23 denotes a VALIDATE ENABLE block which includes NOR gates 414 and 416, an inverter 422, a resistor 418, and a capacitor 420. Resistor 418 and capacitor 420 constitute an RC network which will slighly delay any change of a 0 at the input of inverter 422 to a 1. Conductors 262, 268, 330 and 435 extend into that block, conductor 424 extends from that block, and conductors 282, 284, 302, 410 and 436 are shown merely passing through that block.

The numeral 426 denotes a REVERSE LATCH block which includes NAND gates 432 and 434, NPN transistors 440 and 442, an inverter 438, a capacitor 430, and resistors 428, 444 and 446. Resistor 428 and capacitor 430 constitute an RC network which will slightly delay any change of a 0 at the upper input of NAND gate 432 to a 1. That NAND gate and NAND gate 434 constitute an electronic "latch" 437 which will respond to the application of a 0 to the upper input of NAND gate 432 to apply a continuous 1 to conductor 435 and to apply a continuous 0 to conductor 436. Conductors 282, 284, 302, and 481 extend into that block, conductors 333, 435, 436 and 449 extend from that block, and conductor 410 is shown merely passing through that block. The conductor 449 extends to a lamp 450 which is mounted in the vending machine. Whenever that lamp is illuminated, it will indicate that the inserted piece of scrip will be returned to the patron.

The numeral 478 denotes a RETURN SCRIP block which includes a single-pole single-throw switch 490, a diode 486, a capacitor 482, an opto-coupler 484, and resistors 480 and 488. That switch is located in the vending machine; and it can be actuated by a patron of that vending machine in the event the supply of desired product is exhausted or in the event that patron changes his mind and wants his piece of scrip returned to him. Conductor 481 extends from that block.

The numeral 452 denotes a SWITCH block which includes the switches 146, 156, 162 and 494. That block also includes NOR gates 460 and 468, inverters 476, 508 and 510, a diode 500, capacitors 458, 466, 474 and 502 and resistors 454, 456, 462, 464, 470, 472, 496, 498, 504 and 506. Conductor 410 extends into that block, and conductors 262, 264, 266, 268, 270, 272 and 274 extend from that block.

The numeral 512 in FIG. 16 denotes a DETECTION block which includes an amplifier 514, a PEAK DETECTOR sub-block 516, an ENVELOPE DETECTOR sub-block 548, FREQUENCY DETECTOR sub-blocks 526 and 527, counters 540 and 582, flip-flops 556 and 567, NAND gates 550, 552 and 554, a NOR gate 584, inverters 522, 524 and 542, capacitors 518, 560 and 566, and resistors 520, 558, and 564. Although different counters could be used as the counters 540 and 582, the RCA 4017 counters have been found to be very useful. Although different flip-flops could be used as the flip-flops 556 and 567, RCA 4013 flip-flops have been found to be very useful. The circuit of the PEAK DETECTOR sub-block 516 is shown in FIG. 24, the circuit of the FREQUENCY DETECTOR sub-block 526 is shown in FIG. 25, and the circuit of the ENVELOPE DETECTOR sub-block 548 is shown in FIG. 26. The capacitor 518 and resistor 520 constitute a positive going edge detector. The resistor 558 and the capacitor 560 constitute an RC network; and, similarly, the resistor 564 and the capacitor 566 constitute an RC network. A conductor extends into that block from the magnetic head 210, a conductor 424 extends into that block, and conductors 586 and 588 extend from that block.

The numeral 590 in FIG. 17 denotes a DETECTION block which includes an amplifier 592, a PEAK DETECTOR sub-block 594, an ENVELOPE DETECTOR sub-block 630, FREQUENCY DETECTOR sub-blocks 606 and 618, counters 608 and 620, flip-flops 610 and 622, NAND gates 612, 624 and 634, NOR gate 632, inverters 600, 602 and 604, capacitors 596, 616 and 628, and resistors 598, 614 and 626. Except for the fact that the FREQUENCY DETECTOR sub-blocks 606 and 618 will be set to respond to frequencies which are specifically different from the frequencies to which either of the FREQUENCY DETECTOR sub-block 526 and 527 will be set, the components and connections in the DETECTION block 590 will preferably be identical to the components and connections in the DETECTION block 512. A conductor extends into that block from the magnetic head 208, a conductor 424 extends into that block, and conductors 670 and 672 extend from that block.

The numeral 674 in FIG. 18 denotes a SIGNAL DECODING block which includes EXCLUSIVE OR gates 676, 678, 680 and 682, NOR GATES 684, 686, 688 and 706, a NAND gate 690, inverters 692 and 707, capacitors 694, 696 and 698, and resistors 700, 702 and 704. Resistor 700 and capacitor 694 constitute an RC network which will function as a differentiating network that will differentiate any change from a 0 to a 1 that will appear on conductor 712 and will apply the resultant differentiated signal to the lower input of NOR gate 706. Similarly, resistor 702 and capacitor 696 constitute an RC network and resistor 704 and capacitor 698 constitute an RC network; and those networks will function as differentiating networks which will differentiate any change from a 0 to a 1 that will appear on the corresponding conductors 710 and 708 and will apply the resultant differentiated signals to the middle and upper inputs respectively of NOR gate 706. Conductor 586, 588, 670 and 672 extend into that block, and conductors 708, 710, 712 and 714 extend from that block.

The numeral 716 denotes a COMPARISON REGISTER block which includes shift registers 718, 720, 722 and 724 and a NOR gate 726. The shift register 718 will store data which is developed by the SIGNAL DECODING block 674 as the patterns on a piece of scrip are being moved past, and sensed by, the magnetic heads 208 and 210; and hence that shift register can be regarded as a memory for sensed data. The shift registers 720, 722 and 724 store pre-programmed data, and hence those shift registers can be regarded as a memory for pre-programmed data. Although different shift registers could be used, the RCA 4021 shift registers have been found to be very useful. Conductors 708, 710, 712, 714, 936 and 952 extend into that block, and conductors 728, 730, 732 and 734 extend from that block.

The numeral 736 denotes a PATTERN REGISTER DECODING block which includes EXCLUSIVE OR gates 738, 740 and 742. Conductors 728, 730, 732 and 734 extend into that block, and conductors 744, 746 and 748 extend from that block.

The numeral 750 in FIG. 19 denotes a DATA FIELD 2 FLIP-FLOP block which includes flip-flops 752, 754 and 756. Although different flip-flops could be used as the flip-flops 752, 754 and 756, each of those flip-flops preferably is one-half of an RCA 4027 flip-flop. Conductors 424, 744, 746, 748, 971 and 975 extend into that block, and conductors 768, 770, 772, 774, 776 and 778 extend from that block. Conductors 975 connects the K inputs of those flip-flops to ground; and hence once those flip-flops have been "set", they will remain set until a 1 is applied to the reset terminals thereof.

The numeral 760 denotes a DATA FIELD 3 FLIP-FLOP block which includes flip-flops 762, 764 and 766. Although different flip-flops could be used as the flip-flops 762, 764 and 766, each of those flip-flops preferably is one-half of an RCA 4027 flip-flop. Conductors 424, 744, 746, 748 and 973 extend into that block, conductors 780, 782, 784, 786, 788, 790 and 975 extend from that block, and conductor 971 is shown merely passing through that block. Conductor 975 connects the K inputs of those flip-flops to ground; and hence once those flip-flops have been "set," they will remain set until a 1 is applied to the reset terminals thereof.

The numeral 792 denotes a DATA FIELD 2 SELECTION block which includes NOR gates 794, 796, 798 and 800. The outputs of the NOR gates 794, 796 and 798 are connected to the three inputs of the NOR gate 800. Conductors 768, 770, 772, 774, 776 and 778 extend into that block, and a conductor 801 extends from that block. The numeral 802 denotes a DATA FIELD 3 SELECTION block which includes NOR gates 804, 806, 808 and 810. The outputs of the NOR gates 804, 806 and 808 are connected to the three inputs of the NOR gate 810. Conductors 780, 782, 784, 786, 788 and 790 extend into that block, and a conductor 811 extends from that block.

The numeral 812 denotes a SELECTION DECODER block which includes NOR gates 814, 816, 818, 820, 822, 824, 826, 828 and 830. Conductors 768, 774, 778, 780, 784 and 788 extend into that block, and conductors 832, 834, 836, 838, 840, 842, 844, 846 and 848 extend from that block.

The numeral 850 denotes a PRICE LINE ENABLE block which includes sub-blocks 852, 854, 856, 858, 860, 862, 864, 866 and 868. As indicated by block 852, each of those blocks includes an NPN transistor 870, a diode 874 and a resistor 872. Conductors 832, 834, 836, 838, 840, 842, 844, 846, 848 and 871 extend into that block, and conductors 853, 855, 857, 859, 861, 863, 865, 867 and 869 extend from that block.

The numeral 894 denotes a PRICE LINE RELAY block which is located in the vending machine, and that block includes sub-blocks 896, 898, 900, 902, 904, 906, 908, 910 and 912. As indicated by block 896, each of those blocks includes a relay coil 914 and a diode 916. Conductors 853, 855, 857, 859, 861, 863, 865, 867, 869 and 873 extend into that block. The relays in the sub-blocks of the PRICE LINE RELAY block 894 will control suitable relay contacts in the vending machine.

The collector of an NPN transistor 876 is directly connected to the conductor 871 which extends into the PRICE LINE ENABLE block 850, and a resistor 878 connects that collector to a source of regulated D.C. A resistor 880 connects the emitter of that transistor to ground, and series-connected diodes 882, 884 and 886 displace the base of that transistor from ground. A NAND gate 892 has the output thereof connected to the base of transistor 876 by an inverter 890 and a resistor 888. Conductors 266 and 276 are connected to the inputs of that NAND gate. The numeral 918 in FIG. 20 denotes a CLOCK GENERATOR block which includes a flip-flop 920, registers 930 and 934, NOR gates 922 and 932, an inverter 924, a capacitor 926 and a resistor 928. The NOR gate 922 will coact with inverter 924, capacitor 926 and resistor 928 to constitute an oscillator which will develop clock pulses at the output of that NOR gate and which will apply those clock pulses to the clock input of register 930. Although different flip-flops could be used as the flip-flop 920, that flip-flop preferably is one-half of an RCA 4027 flip-flop. Although different registers could be used as the registers 930 and 934, each of those registers preferably is one-half of an RCA 4015 register. Conductor 714 extends into that block, and conductors 936 and 938 extend from that block.

The numeral 940 denotes a DATA FIELD AND VALIDATION block which includes a shift register 942, registers 954 and 982, a flip-flop 978, NOR gates 956 and 980, NAND gates 944, 958, 960, 962 and 964, inverters 950, 966, 968, 970, 972 and 988, capacitors 948, 977 and 986, and resistors 946, 975 and 984. The input terminals one, three and seven of shift register 942 are connected together and to the source of regulated plus twelve volts D.C., and input terminals two, four through six and eight are connected together and to ground. Resistor 975 and capacitor 977 constitute an RC network which will delay any change of a 1 at the input of inverter 972 to a 0. Resistor 946 and capacitor 948 constitute an RC network which will delay any change of a 1 at the input of inverter 950 to a 0. The resistor 984 and capacitor 986 constitute an RC network which will delay any change of a 1 at the input of inverter 988 to a 0. The K input of flip-flop 978 is connected to ground; and hence once that flip-flop has been set, it cannot be reset until a 1 is applied to the reset input thereof. Conductors 424, 714, 744, 801, 811 and 938 extend into that block, and conductors 260, 276, 424, 952 971 and 973 extend from that block.

The PEAK DETECTOR 516 of FIG. 24 includes an NPN transistor 636 which has the collector thereof connected to a source of 24 volts and which has the emitter thereof connected to ground by a resistor 639 and parallel-connected capacitors 656 and 658. One of those capacitors is a relatively large value capacitor and the other of those capacitors is a relatively small value capacitor to facilitate the by-passing of essentially all transients to ground. A resistor 637 is connected between the source of twelve volts and the junction between resistor 639 and capacitor 656. The transistor 636 and those resistors function as an emitter-follower which provides half-wave rectification of the signals which are applied to the PEAK DETECTOR 516. The output of that emitter-follower is a half-wave rectified signal which has an amplitude between 5 and 6 volts. Because the signals, which are applied to the base of transistor 636, were generated as magnetic lines moved into and out of register with the narrow gap of the magnetic head, those signals will have the form of narrow pulses; and hence the half-wave rectified signal will have essentially vertical leading edges.

The numeral 638 denotes a capacitor, and the numerals 640 and 642 denote back-to-back diodes. That capacitor will act as a differentiator; and those back-to-back diodes will provide a charging and discharging circuit for that capacitor. Consequently, the combination of that capacitor and of those diodes will respond to each half-wave pulse from the emitter-follower to provide a limited-amplitude, steep-sided, positive-going pulse and negative-going pulse which are contiguous. That positive-going pulse will terminate and that negative-going pulse will begin at the time the discharging of that capacitor reverse biases the diode 640 and forward biases the diode 642 in response to a half-wave pulse from the emitter-follower; and the zero crossing between that positive-going pulse and that negative-going pulse will occur immediately after the positive-going half-wave pulse from the emitter-follower reches its peak. Because the half-wave rectified signal will have essentially vertical leading edges, and because the pulses generated by the magnetic head 210 will be narrow, the PEAK DETECTOR 516 can precisely sense the zero crossings. Consequently, the output of capacitor 638 and of diodes 640 and 642 is a limited-amplitude, positive-going pulse and a limited-amplitude negative-going pulse which are contiguous and which have the zero crossing therebetween closely in register with the peak of the positive-going half-wave pulse from the emitter-follower.

The numeral 644 denotes an operational amplifier which has a feedback resistor 646 and a feedback capacitor 648. Resistors 637 and 643 supply a positive voltage to the non-inverting input of that amplifier; and the output of the combination constituted by capacitor 638 and the diodes 640 and 642 is applied to the inverting input of that amplifier. One terminal of that amplifier is connected to ground and another terminal of that amplifier is connected to the source of 12 volts.

A current-limiting resistor 650 connects the output of amplifier 640 to the input of an inverter 652, and the output of that inverter is connected to the input of an inverter 654; and the latter inverter applies the output of the PEAK DETECTOR 516 to the left-hand terminal of the capacitor 518 in the DETECTION block 512. If desired, the current-limiting resistor 650 could be connected directly to the left-hand terminal of the capacitor 518; but, in the said preferred embodiment, the operational amplifier 644 is located a substantial distance away from the capacitor 518, and hence the inverters 652 and 654 were provided to compensate for resistive and interfacing losses.

The amplifier 644 acts as a zero crossing detector and normally maintains a 0 at the output thereof. Whenever that amplifier detects zero crossings, it will apply positive-going square wave pulses to the input of inverter 652; and the leading edges of those positive-going square wave pulses will correspond closely in time with the peaks of the positive-going amplified pulses developed by the amplifier 514. Because the peaks of those positive-going amplified pulses correspond closely in time with the trailing edge-to-edge spacings of the lines in the pattern being sensed by the magnetic head 210, the leading edges of the positive-going square wave pulses at the output of the PEAK DETECTOR 516 will correspond closely in time with the trailing edge-to-edge spacings of the lines in the pattern being sensed.

The sub-block 526 in FIG. 25 includes timers 521 and 537, an NPN transistor 547, potentiometers 541 and 551, a NOR gate 559, inverters 557 and 561, diodes 534 and 535, capacitors 530, 531, 536, 539, 540, 545, 549 and 555, and resistors 532, 533, 538, 543 and 553. The components which are shown within the dotted-line enclosure 528 constitute a timer module which is mounted on a printed circuit board that is shown in FIG. 14 as being a plug-in printed circuit board. That plug-in circuit board is releasably connectable to a printed circuit board which will include the NOR gate 559, the inverters 557 and 561, capacitors 536 and 540 and resistor 538, and the corresponding NOR gates, inverters, capacitors and resistors of corresponding timer modules which are parts of the FREQUENCY DETECTOR blocks 527, 606, and 618, and which are made as plug-in printed circuit boards. The numeral 571 denotes the plug-in timer module for FREQUENCY DETECTOR 527, the numeral 573 denotes the plug-in timer module for the FREQUENCY DETECTOR 606, and the numeral 575 denotes the plug-in timer module for the FREQUENCY DETECTOR 618. By making those timer modules as plug-in printed circuit boards which are readily connectable to and separable from the circuit board 523, the present invention makes it possible to quickly and simply change the frequencies which the patterns on the pieces of scrip must cause the magnetic heads 208 and 210 to develop.

The ENVELOPE DETECTOR 548 of FIG. 26 includes a timer 569 which has a capacitor 568 connected to pin 2 thereof. Although different timers could be used, the NE555V timer marketed by the Signetics Corporation has been found to be very useful. Pin 1 of timer 569 is directly connected to ground, and pin 5 is connected to ground by a capacitor 579. Pins 4 and 8 are directly connected to a source of plus twelve volts, and a capacitor 577 is connected between that source and ground. A resistor 570 connects that source of pin 2, and a resistor 578 connects that source to the interconnected pins 6 and 7. Those interconnected pins are connected to ground by a capacitor 580, and they are connected to the emitter of a PNP transistor 583 by a diode 581. The right-hand terminal of capacitor 568 also is connected to the base of transistor 583 and to the anode of a diode 585. The cathode of that diode is connected to ground by a capacitor 587 and a resistor 589. The timer 569, the transistor 583 and the associated capacitors, resistors and diodes constitute a retriggerable monostable multivibrator.

Normally the capacitor 580 has a 0 at the upper terminal thereof; but whenever a negative-going pulse is applied to pin 2 of timer 569, that timer will develop a 1 at pin 3 thereof; and that 1 will remain at pin 3 until the charge on the capacitor 580 rises to a predetermined value -- which it will normally do at the end of 8 milliseconds.

However, if, prior to the end of that eight millisecond time interval, a further negative-going pulse is applied to pin 2 of timer 569 by the capacitor 568, that negative-going pulse also will be applied to the base of transistor 583 and will momentarily render that transistor conductive. Thereupon, capacitor 580 will be discharged by that transistor and then that capacitor will have to start charging all over again when that transistor becomes non-conductive. Each time capacitor 580 is discharged, the re-setting of the re-triggerable monostable multivibrator will be postponed for a further eight millisecond time interval. Consequently, as long as negative-going pulses are applied to the ENVELOPE DETECTOR 548 at intervals of less than eight milliseconds -- as will be the case whenever an authentic pattern is being sensed -- a 1 will continue to appear at pin 3 and hence at the output of that ENVELOPE DETECTOR.

Authentic Piece of Scrip: Referring particularly to FIG. 13, the numeral 130 denotes one preferred piece of scrip that is provided by the present invention. That piece of scrip is made from stiff paper which can be printed or engraved to provide sharp, precisely spaced lines of magnetic ink thereon. That piece of scrip is four and one-half inches long and two and five-eighths inches wide. Arrows are printed or engraved on one surface of that piece of scrip to indicate the leading edge of that piece of scrip.

The numerals 132, 134, 135, 136, 137, 138, 139 and 141 denote discrete patterns which are printed or engraved on that surface of that piece of scrip on which the arrows are printed or engraved. Although those patterns are shown by FIG. 13, those patterns will be concealed in actual use -- either by overprinting those patterns with an obscuring design or mass or by providing a thin non-magnetic light-opaque coating over the surface of that piece of scrip. Each pattern is formed by parallel lines which have exactly the same spacing between the trailing edges thereof, which have exactly the same widths, and which have at least a predetermined amount of magnetic material therein. Moreover, those parallel lines must have precisely formed leading and trailing edges.

The spacing of the lines in the patterns 132, 134, 135 and 136 are distinctively different from each other; and hence, as those patterns move past the air gaps of the appropriate magnetic heads, distinctively different frequencies will be developed. In the said preferred embodiment, the frequency defined by pattern 132 matches the frequency of FREQUENCY DETECTOR 526, the frequency defined by pattern 134 matches the frequency of FREQUENCY DETECTOR 618, the frequency defined by pattern 135 matches the frequency of FREQUENCY DETECTOR 527, and the frequency defined by pattern 136 matches the frequency of FREQUENCY DETECTOR 606. Those four patterns constitute data field 1 of the piece of scrip 130; and patterns 132 and 135 are aligned to be sensed by magnetic head 210, whereas patterns 134 and 136 are aligned to be sensed by magnetic head 208.

The spacing of the lines in the patterns 137 and 138 are distinctively different from each other; but the spacing of the lines in the pattern 137 must equal the spacing of the lines in pattern 132 or 135, and the spacing of the lines in the pattern 138 must equal the spacing of the lines in pattern 134 or 136. Pattern 137 is aligned with patterns 132 and 135, and thus will be sensed by magnetic head 210, whereas pattern 138 is aligned with patterns 134 and 136, and thus will be sensed by magnetic head 208. The patterns 137 and 138 constitute data field 2 of the piece of scrip.

The spacing of the lines in the patterns 139 and 141 are distinctively different from each other; but the spacing of the lines in the pattern 139 must equal the spacing of the lines in pattern 132 or 135, and the spacing of the lines in the pattern 141 must equal the spacing of the lines in pattern 134 or 136. Pattern 139 is aligned with patterns 132 and 135, and thus will be sensed by magnetic head 210, whereas pattern 141 is aligned with patterns 134 and 136 and thus will be sensed by magnetic head 208. 139 and 141 constitute data field 3 of the piece of scrip.

The patterns 132, 135, 137 and 139 are displaced forwardly relative to the patterns 134, 136, 138 and 141, as shown by FIG. 13. That displacement corresponds to the longitudinal displacement of the magnetic heads 210 and 208. Also the patterns 132, 135, 137 and 139 are displaced laterally from the patterns 134, 136, 138 and 141 to keep the magnetic head 208 from responding to any of the lines in the patterns 132, 135, 137 and 139, and also to keep the magnetic head 210 from responding to any of the lines in the patterns 134, 136, 138 and 141.

The patterns 132, 134, 135 and 136 are located on the piece of scrip 130 so the signal which is developed by the FREQUENCY DETECTOR and counter corresponding to each pattern is developed at a specifically different time; and, further, that the signals corresponding to patterns 132, 134, 135 and 136 are developed in succession. Similarly, the patterns 137 and 138 are located on the piece of scrip 130 so the signal which is developed by the FREQUENCY DETECTOR and counter corresponding to each pattern is developed at a specifically different time; and, further, that the signals corresponding to patterns 137 and 138 are developed in succession; and the patterns 139 and 141 are located on the piece of scrip 130 so the signal which is developed by the FREQUENCY DETECTOR and counter corresponding to each pattern is developed at a specifically different time; and, further, that the signals corresponding to patterns 139 and 141 are developed in succession.

Each of the patterns 132, 134, 135, 136, 137, 138, 139 and 141 must have at least one more line than the total count required by the counter corresponding to that pattern. This is necessary because the FREQUENCY DETECTORS do not respond to the first line of any pattern to apply a signal to the counter associated with it. Also the total number of lines in each of the patterns 132, 134, 135, 136, 137, 138, 139 and 141 must not exceed twice the count to which the counter, which is connected to the FREQUENCY DETECTOR corresponding to that pattern has been pre-set.

At-Rest Condition Of Scrip Validator: In the at-rest condition of the scrip validator, switches 146, 156, 162 and 494 of FIG. 23 are open; and, consequently, "1's" are applied to the lower inputs of NOR gates 460 and 468, and to the inputs of inverters 476 and 508. In addition, "1's" appear on conductors 264, 270 and 272. The "1's" at the lower inputs of NOR gates 460 and 468 will provide "0's" on conductors 274 and 262; and the "1's" at the inputs of inverters 476 and 508 will provide "0's" on conductors 268 and 266.

In the at-rest condition of the scrip validator, no pieces of scrip will be in the transport 30, and the belts 198 and 199 will be at rest. Consequently, "0's" will appear on the conductors 586, 588, 670 and 672 which originate in the DETECTION blocks 512 and 590 in FIGS. 16 and 17, respectively. The SIGNAL DECODING block 674 of FIG. 18 will respond to those "0's" to apply "0's" to conductors 708, 710, 712 and 714. The COMPARISON REGISTER block 716 and the PATTERN REGISTER DECODING block 736 of FIG. 18 will apply "0's" to the conductors 744, 746 and 748.

The DATA FIELD 2 FLIP-FLOP block 750, the DATA FIELD 3 FLIP-FLOP block 760, the SELECTION DECODER block 812, the DATA FIELD 2 SELECTION block 792, and the DATA FIELD 3 SELECTION block 802 of FIG. 19 leave the transistors in the sub-blocks of the PRICE LINE ENABLE block 850 non-conductive, and thereby keep the relay coils in the sub-blocks of the PRICE LINE RELAY block 894 un-energized. Also, the DATA FIELD 2 SECTION block 792 and the DATA FIELD 3 SELECTION block 802 apply "1's" to the conductors 801 and 811. The CLOCK GENERATOR block 918 of FIG. 20 will provide a 0 on conductor 936 which extends to the COMPARISON REGISTER block 716, and it will provide a 0 on conductor 938 which extends to the DATA FIELD AND VALIDATION block 940. The latter block will apply "0's" to conductors 971 and 973 which extend to the DATA FIELD 2 FLIP-FLOP block and to the DATA FIELD 3 FLIP-FLOP block. Also, the DATA FIELD AND VALIDATION block 940 will provide a 1 on conductor 260 and a 0 on conductor 276.

The TIMING BLOCK 230 of FIG. 21 will provide a 0 on conductor 282 and will provide a 1 on conductor 286; the MULTIPLEXER block 288 will provide a 1 on conductor 302. The ACCEPT LATCH block 304 of FIG. 22 will provide a 0 on conductor 330 and a 1 on conductor 284; and the COLLECT block 334 will provide a 1 on conductor 312. The MOTOR START AND RUN block 348 will permit the motor 562 within the MOTOR CONTROLLING sub-block 354 to be de-energized.

The 1, which conductor 260 applies to the upper input of NOR gate 392 in the BLOCKING FINGER CONTROL block 370 of FIG. 22 will cause that NOR gate to apply a 0 to the input of inverter 394. The 1 which that inverter will apply to the lower input of NAND gate 396 will coact with the 1 which conductor 284 applies to the upper input of that NAND gate to cause that NAND gate to apply a 0 to the input of inverter 398. The resulting 1 at the output of that inverter is applied to the lower input of NAND gate 376, to the left-hand terminal of capacitor 400 and, via resistor 404, to the base of NPN transistor 406. The conductor 266 will be applying a 0 to the upper input of NAND gate 376, and hence the 1 which inverter 398 applies to the lower input of that NAND gate will not be effective at this time. However, the 1 which inverter 398 applies to the base of transistor 406 will render that transistor conductive; and hence current will flow from the source of plus 24 volts D. C. via solenoid 388, resistor 408 and the collector-emitter circuit of transistor 406 to ground. The value of the current which can flow through resistor 408 is large enough to hold the solenoid 388 energized, but it is not large enough to enable that solenoid to move the blocking member 178 from the blocking position of FIGS. 3, 4 and 8 to the unblocking position of FIG. 9. However, at this time the blocking member 178 will be in the un-blocking position; and the value of the current flowing through solenoid 388 will be large enough to cause that solenoid to continue to hold that blocking member in that position.

The VALIDATE ENABLE block 412 of FIG. 23 will provide a 1 on conductor 424; and the REVERSE LATCH block 426 will provide a 0 on conductor 435, will provide a 1 on conductor 333, and will supply no power to the lamp 450. The RETURN SCRIP block 478 will apply a 1 to conductor 481 which extends to the REVERSE LATCH block 426.

Operation of Scrip Validator When An Authentic Piece of Scrip Is Inserted: Each authentic piece of scrip 130 will have instructions printed or engraved thereon that will indicate which face of that piece of scrip should face upwardly, and which edge of that piece of scrip should be the leading edge, when that piece of scrip is placed adjacent the platform 32 of the scrip transport 30. The leading edge of the piece of scrip 130 will be moved inwardly of that scrip transport; and, because the blocking member 178 is held in its raised position by the energization of solenoid 388, the fingers 180 and 182 of the blocking member will not bar or impede the inward movement of the leading edge of the piece of scrip 130. That leading edge will be moved far enough inwardly to cause the actuator 148 of switch 146 to close that switch; and, thereupon, a 0 will be applied to the lower input of NOR gate 460 in the SWITCH block 452 of FIG. 23. At this time, the NOR gate 392 in the BLOCKING FINGER CONTROL block 370 of FIG. 22 will be responding to the 1 on conductor 260 to apply a 0 to the upper input of NOR gate 460 and also to the upper input of NOR gate 468. Consequently, NOR gate 460 will apply a 1 to conductor 274 and thus to the lower input of NOR gate 350 in the MOTOR START AND RUN block 348 of FIG. 22. Conductor 262 will be applying a 0 to the upper input of NOR gate 350; and hence that NOR gate will apply a 0 to the input of inverter 352 -- with consequent application of a 1 to the middle input of NOR gate 353. The resulting 0 at the output of that NOR gate will back bias diode 355; and inverter 356 will respond to the consequent 0 at the input thereof to apply a 1 to the MOTOR CONTROLLING block 354. As explained in detail in the said Carter et al application, a 1 at the input of the MOTOR CONTROLLING block 354 will cause the motor 562 to operate through output shaft 203, worm gear 202 and worm wheel 200 to drive the lower "runs" of belts 198 and 199 inwardly of the transport 30; and those lower "runs" will cause the piece of scrip 130 to move inwardly of that transport.

The 1 on conductor 274 also will be applied to the A input of the multiplexer 296 in the MULTIPLEXER block 288 of FIG. 21; and, thereupon, the signal at input terminal one of that multiplexer will appear at the output terminal of that multiplexer. Under all normal and usual conditions, the conductor 276 will be applying a 0 to the lower input of NOR gate 292 on that MULTIPLEXER block, and inverter 290 in that block will be applying a 0 to the upper input of that NOR gate, and also to the upper input of NOR gate 294. As a result, NOR gate 292 will normally apply a 1 to input terminal one, and hence also to input terminals three and seven, of multiplexer 296; and, as switch 146 closes, that 1 will appear at the output of that multiplexer and hence on conductor 302. Because a 1 appears on conductor 302, the REVERSE LATCH block 426 of FIG. 23 will not reverse the motor 562. However, if for any reason, conductor 276 has been applying a 1 to the lower input of NOR gate 292, that NOR gate would have applied a 0 rather than a 1 to input terminals one, three and seven of multiplexer 296, and the output terminal of that multiplexer would have applied a 0 to conductor 302. In that event, the REVERSE RELAY block 426 would have caused the motor 562 to reverse.

As the switch 146 closed, it applied a 0 to conductor 270, and thus to the upper input of NAND gate 242 in the TIMING block 230 of FIG. 21, thereby causing that NAND gate to apply a 1 to the input of inverter 244 and also to conductor 282. The 1 on conductor 282 is applied to the lowermost input of NAND gate 434 in the REVERSE LATCH block 426 of FIG. 23; and that NAND gate and NAND gate 423 constitute an electronic "latch." Consequently, when and if the 0 at the upper input of NAND gate 434 changes from a 0 to 1; the output of NAND gate 434 will be able to change to a 0. The 1 at the input of inverter 244 in the TIMING BLOCK 230 will cause that inverter to apply a 0 to the lower input of NAND gate 246; but because BINARY COUNTER 238 has been maintaining a 0 at the upper input of that NAND gate, the application of 0 to the lower input of that NAND gate will not change the output of that NAND gate. However, that 0 will cause NAND gate 246 to continue to provide a 1 at the output thereof after the BINARY COUNTER 238 starts counting.

The belts 198 and 199 will continue to move the piece of scrip 130 inwardly of the transport 30; and, very quickly, the leading edge of that piece of script will cause actuator 158 to close switch 156. At this time, that piece of scrip will be holding both of the switches 146 and 156 closed. The closing of switch 156 will apply a 0 to the lower input of NOR gate 468 in SWITCH block 452 and will apply a 0 to conductor 272. Because conductor 410 is applying a 0 to the upper input of NOR gate 468, that NOR gate will apply a 1 to conductor 262; and that 1 will be applied to the upper input of NOR gate 350 in the MOTOR START AND RUN block 348. However, because conductor 274 has been applying a 1 to the lower input of that NOR gate, the 1 on conductor 262 will not change the output of that NOR gate. The 1 on conductor 262 also will be applied to the upper input of NOR gate 414 in the VALIDATE ENABLE block 412 of FIG. 23; and that NOR gate will apply a 0 to the middle input of NOR gate 416. At this time, NAND gate 306 in the ACCEPT LATCH block 304 is applying a 0 to conductor 330 and thus to the upper input of NOR gate 416; and NAND gate 432 in the REVERSE LATCH block 426 will be applying a 0 to conductor 435 and thus to the lower input of NOR gate 416. That NOR gate will respond to those three 0 inputs to apply a 1 to the input of inverter 422 via resistor 418; and that inverter will apply a 0 which constitutes a "validate enable" signal to conductor 424. That 0 will be applied to the lowermost input of NOR gate 584 in DETECTION block 512 of FIG. 16, and also to the lowermost input of NOR gate 632 in DETECTION block 590 of FIG. 17. At this time, the flip-flop 556 in DETECTION block 512 is applying a 0 to the uppermost input of NOR gate 584, and the flip-flop 567 is applying a 0 to the middle input of that NOR gate; and, similarly, the flip-flop 610 in DETECTION block 590 is a 0 to the uppermost input of NOR gate 632 and flip-flop 622 is applying a 0 to the middle input of that NOR gate. Consequently, NOR gate 584 will apply a 1 to the lower input of NAND gate 552; and NOR gate 632 will apply a 1 to the lower input of NAND gate 634. Because the ENVELOPE DETECTOR 548 in DETECTION block 512 is applying a 0 to the upper input of NAND gate 552, and because the ENVELOPE DETECTOR 630 in DETECTION block 590 is applying a 0 to the upper input of NAND gate 634, the NAND gate 552 will be applying 1's to the re-set terminals of counters 540 and 582, and the NAND gate 634 will be applying 1's to the re-set terminals of counters 608 and 620.

Conductor 424 also will apply 0 to the parallel serial control terminal of the shift register 942 in the DATA FIELD AND VALIDATION block 940 of FIG. 20, and thereby will "enable" the serial input of that register. The 0 on conductor 424 will be appliled to the re-set input of flip-flop 978 and to the re-set inputs of counters 954 and 982 in that block; and that 0 will "enable" that flip-flop and those counters. The 0 on conductor 424 will be applied to the re-set inputs of flip-flops 752, 754 and 756 in the DATA FIELD 2 FLIP FLOP block 750 of FIG. 19, and to the re-set inputs of the flip-flops 762, 764 and 766 in the DATA FIELD 3 FLIP FLOP block 760.

The 1, which NOR gate 468 in the SWITCH block 452 of FIG. 23 is applying to the conductor 262, will be applied to the lower input of NOR gate 392 in the BLOCKING FINGER CONTROL block 370 of FIG. 22. However, the application of that 1 will not, at this time, be significant; because conductor 260 has been applying a 1 to the upper input of that NOR gate. The 1 on conductor 262 also will be applied to the upper input of NOR gate 232 in the TIMING block 230; and the resulting 0 at the re-set terminal of BINARY COUNTER 238 permits that BINARY COUNTER to start counting in response to the pulses from the PULSE GENERATOR 248. Those pulses are applied to the input of that BINARY COUNTER at the rate of one every sixteen and seven-tenths milliseconds. Conductor 262 additionally applies the 1 thereon to the B input of multiplexer 296 in the MULTIPLEXER block 288 in FIG. 21; and that 1 will coact with the 1 at the A input of that multiplexer to connect input terminal three, and hence input terminals one and seven, to the output of that multiplexer. Under ordinary and usual conditions, the signal which will be applied to the input terminals one, three and seven at this time will be a 1; and hence a 1 will be applied to conductor 302. However, if in some way the conductor 276 had a 1 rather than a 0 thereon, NOR gate 292 would be applying a 0 to input terminals one, three and seven of the multiplexer 296; and hence a 0 would appear on conductor 302. That 0 would cause NAND gates 434 and 432 in the REVERSE LATCH block of FIG. 23 to apply a 0 to conductor 436; and that 0 would act through inverter 438, resistor 444, NPN transistor 440, and conductor 333 to cause the motor 562 to reverse.

The 0 which appeared on conductor 272 as switch 156 was closed, will be applied to the middle input of NAND gate 242 in the TIMING block 230 of FIG. 21. Although that 0 will not be effective at this time, it will enable that NANd gate to keep a 1 at the output thereof even after the switch 146 re-opens.

As the piece of scrip is moved inwardly of the transport 30 by the belts 198 and 199, the BINARY COUNTER 238 in the TIMING block 230 of FIG. 21 will continue to count. Approximately 67 milliseconds after switch 156 was closed, a 1 will appear at the binary four output of that BINARY COUNTER, and thus at the middle input of NAND gate 240. That 1 will not be significant at this time because the binary 32 output is 0 and will cause NAND gate 240 to maintain a 1 at the output thereof. The 1 will continue to appear at the binary four output of the BINARY COUNTER 238 through count seven; but approximatley 134 milliseconds after switch 156 was closed, 0 will again appear at the binary four output, and a 1 will appear at the binary eight output. However, as indicated previously herein, the 0 at the output of inverter 244 will be inhibiting NAND gate 246; and hence the 1 at the upper input of that NAND gate will be unable to change the output of that NAND gate. The 1 will continue to appear at the binary eight output through count fifteen; and while the count of twelve through fifteen, the 1 will re-appear at the binary four output. However, both NAND gates 240 and 246 will be inhibited at this time, and hence those NAND gates will continue to provide 1's at the outputs hereof. While the count is 20 through 23, a 1 will appear at the binary four output but NAND gate 240 will be inhibited; and while the count is 24 through 31, a 1 will appear at the binary eight output, but NAND gate 246 will still be inhibited. While the count is 28 through 31, a 1 will again appear at binary four output, but NAND gate 240 will still be inhibited.

As the belts 198 and 199 continue to move the piece of scrip 130 inwardly of the transport 30, the patterns 132, 135, 137 and 139 will successively engage and pass beyond the air gap of the magnetic head 210, and the patterns 134, 136, 138 and 141 will successively engage and move past the air gap of the magnetic head 208. The pattern 132 will engage the air gap of the magnetic head 210 after the switch 156 was closed but before the switch 162 is closed; but the switch 162 will be closed before the pattern 141 reaches and then moves beyond the air gap of a magnetic head 208. For the purposes of this description, it will be assumed that the signals which magnetic head 208 develops as each of the patterns 134, 136, 138 and 141 engages and moves past the air gap of that magnetic head meet the requirements of the circuitry in FIGS. 16 and 17, all as explained hereinafter in the section entitled Validation of Authentic Piece of Scrip. Similarly, it will be assumed that the signals which magnetic head 210 develops as each of the patterns 132, 135, 137 and 139 engages and moves past the air gap of that magnetic head meet the requirements of that cir