Data transfer network for variable protocol management

Abstract

A data transfer network uses an I/O subsystem to support a main host computer in managing data transfers to and from remote data terminals. The I/O subsystem may constitute one or more units called a Line Support Processor. The Line Support Processor uses internal processor means to control a plurality of line adapters each of which has a data-comm line to a data set or data terminal. Control operations by said internal processor permit selected line adapters to operate selected types of protocols using synchronous or asynchronous transmission. Data communication information and commands in high level language data are loaded into auxiliary memories in the internal processor means and into each line adapter where the internal processor means acts to convert this language data into usable protocols.

Claims

What is claimed is:

1. A data transfer network for data transfers between a main host computer and a plurality of remote data sets operating under different protocol and timing disciplines wherein said main host computer initiates I/O data transfer commands to a line support processor means having a plurality of line support processors, each one of which manages data transfers between one of said remote data sets and said main host computer, said data transfer network comprising:

(a) said main host computer connected to each one of said line support processors and including:

(a1) main memory means for storing data to be transmitted to/received from said remote data sets and including:

(a1a) a first dedicated memory area for storing a I/O data transfer commands for transmittal to said line support processors;

(a1b) a second dedicated memory area for storing operational codes for transmittal to said line support processors wherein said operational codes contain information translatable, by said line support processor, into control data for selecting timing and protocol discipline for a selected line adapter;

(a2) a main processor for selecting said I/O data transfer commands and said operational codes for communication and control of said line support processor, said processor including:

(a2a) connection means to a distribution control circuit;

(b) a base module providing backplane connection means for slide-in circuitry cards, said base module including:

(b1) said distribution control circuit functioning to connect and/or disconnect said host computer to/from a selected line support processor in line support processor means;

(b2) said line support processor means functioning to execute said I/O data transfer commands by controlling a selected line adapter to a remote data set, said line support processor means including:

(b2a) a plurality of line support processors connected to said distribution control circuit wherein each said line support processor includes:

(B2a1) interface circuit means connecting said main host computer, via said distribution control circuit, to a plurality of line adapter means and to a state machine processor means;

(b2a2) said state machine processor means including a state machine processor operating to translate said operational codes into control data for operating a selected line adapter in a desired timing and protocol discipline for managing data transfers between said selected line adapter and an associated said data set, said state machine processor means including:

(i) a first auxiliary memory storage area for receiving said operational codes from said host computer;

(ii) program memory means for enabling said state machine processor to translate said operation codes into control data for operating a selected line adapter;

(iii) said state machine processor operating to transmit said control data to said selected line adapter for selecting and managing the timing and protocol discipline for data transfers, and including:

(ie) means for selecting a particular line adapter in said plurality of line adapter means;

(iie) means for identifying the required timing and protocol discipline for said particular line adapter;

(iiie) means for generating address signals for selecting a desired control register in said particular line adapter and placing said control data therein;

(ive) means for transferring data to/from said particular line adapter;

(ve) means for selecting a group of multiplexors associated with said selected particular line adapter;

(c) said plurality of line adapter means connected to said state machine processor means and including a plurality of line adapters, wherein each line adapter includes:

(c1) a data communication line to an associated said remote data set;

(c2) a plurality of control registers holding said control data for managing data transfers according to a desired timing and protocol discipline, said control data being derived from said state machine processor means;

(d) transceiver-controller means, operating under control of said state machine processor means, for switching a data bus to connect said state machine processor to a selected line adapter or to connect said selected line adapter to a multiplexor means;

(e) said data bus connecting each of said line adapters to said transceiver-controller means;

(f) multiplexor means including:

(f1) a plurality of groups of multiplexors whereby each group of multiplexors is connected to an associated line adapter for conveying bytes of data from said remote data set to said state machine processor means for subsequent transfer to said host computer, and wherein each said group of multiplexors includes:

(f1a) coded input signal means for identifying the particular timing and protocol discipline required for the said associated line adapter.

2. The network of claim 1, wherein each of said plurality of line adapter means includes:

(a) line adapter memory means for buffering data being transferred between said state machine processor means and said remote data set; said line adapter memory means including a plurality of RAM storage means, each one of said RAM storage means being dedicated to a said plurality of line adapters.

3. The network of claim 1, wherein each one of said RAM storage means includes:

(a) memory space for receiving and storing said operational codes from said host computer.

4. The network of claim 1, wherein said state machine processor means includes:

(a) means to generate result/data for transmission to said host computer after execution of a said I/O data transfer command from said host computer.

5. An network for handling data transfer operations between a main host computer and a plurality of remote data sets, said network comprising:

(a) said main host computer being connected to a distribution control circuit means, and including:

(a1) first memory means for storing I/O data transfer commands for initiating data transfers to/from a plurality of remote data sets;

(a2) second memory means for storing operational codes for transmittal to each one of a plurality of line adapter memory means, said operational codes including control information on a variety of timing and protocol disciplines;

(a3) third memory means for storing data to be transmitted to/received from said remote data sets;

(a4) a main processor means for utilizing said first, second and third memory means for managing a plurality of line support processors;

(b) distribution control circuit means functioning to connect and disconnect said main host computer to/from a selected one of a plurality of line support processors;

(c) said line support processors operating to execute said I/O data transfer commands and for selecting the appropriate timing and protocol discipline for data transfers with each of said remote data sets, wherein each of said line support processors includes:

(c1) a data link interface circuit means connecting said distribution control circuit means to an internal processor means and to a line adapter means;

(c2) said internal processing means including an internal processor operating to translate said operational codes into control data for managing each selected line adapter to execute data transfers according to the appropriate timing and line discipline for the remote data set connected to the selected line adapter, said internal processing means including:

(c2a) auxiliary memory means for storing said operational codes;

(c2b) means for selecting a particular line adapter for data transfer operations and for identifying and enabling the said appropriate timing and protocol discipline to be used by said selected particular line adapter;

(d) said line adapter means including:

(d1) a plurality of line adapters, each of which provides a line connection to said remote data set and operates to execute data transfers between said line adapter means and said remote data set with the appropriately selected line discipline and protocol, under control of said internal processor means;

(d2) line adapter memory means for buffering data being transferred to/from said remote data set and to/from said main host computer;

(d3) switching means for connecting a selected line adapter to said internal processor or to an associated group of multiplexors in a multiplexor means;

(d4) said multiplexor means including:

(d4a) a plurality of groups of multiplexors wherein each group is connected to receive the outputs of an associated line adapter for transfer of data bytes to said line adapter memory means for subsequent handling by said internal processor;

(d4b) identification signal input means, for each group of multiplexors connected to an associated line adapter, for generating an identification signal to said internal processor means to enable said internal processor means to generate said appropriate control data for said selected line adapter;

(e) said plurality of remote data sets being connected so that each data set has its individual data communication line to an associated one of said line adapters.

Description

FIELD OF THE INVENTION

This disclosure relates to the field of data communications apparatus and is directed to a processing unit and system which provides an I/O subsystem unit between remote data sets and terminals, and a main host computer.

CROSS REFERENCES TO RELATED APPLICATIONS

This disclosure is related to the following applications which all have the same common assignee:

An application entitled "Bit-Oriented Line Adapter System", U.S. Ser. No. 355,134, filed Mar. 5, 1982, by inventors Richard A. Loskorn, Philip D. Biehl and Robert D. Catiller, now U.S. Pat. No. 4,455,622.

An application entitled "Byte-Oriented Line Adapter System", U.S. Ser. No. 355,135, filed Mar. 5, 1982, by inventors Richard A. Loskorn, Philip D. Biehl and Robert D. Catiller, now U.S. Pat. No. 4,514,824.

An application entitled "Component Selection System for a Multiple Line Adapter Organization", U.S. Ser. No. 363,592, filed Mar. 30, 1982, inventor Richard A. Loskorn, now U.S. Pat. No. 4,453,228.

An application entitled "Read Control Operations System for a Multiple Line Adapter Organization", U.S. Ser. No. 372,106, filed Apr. 27, 1982, inventor Richard A. Loskorn, abandoned and re-filed Feb. 21, 1984 as Continuation-In-Part of U.S. Ser. No. 580,292.

An application entitled "Automatic Calling Unit Control System", U.S. Ser. No. 386,409, filed June 8, 1982, inventors Richard A. Loskorn and Lyle O. Jevons, Jr., now U.S. Pat. No. 4,479,123.

SUMMARY OF THE INVENTION

A data transfer network includes a main host computer supported by an I/O subsystem which may include one or more Line Support Processor Units. The Line Support Processor units manage the transfer and storage of data to/from remote data terminals such that selected Line Adapters in the Line Support Processor Units can be controlled to handle not only a variety of transfer protocols but also both synchronous and asynchronous communications.

The host computer stores a network definition language (NDL) providing "S-operators" which are operation codes. These codes are loaded into the various line support processors (LSPs) of the system. Each of the line support processors is provided with a universal input output state machine which is provided with auxiliary extra memory storage for receiving the S-operators which the state machine can translate into specific instructions and operation execution to control multiple numbers of line adapters, each of which may have a different line discipline and protocol arrangement.

The S machine (FIGS. 1E, F, G) is a virtual machine which results from the high level S-operators provided by the host computer to the line support processors which are then translated into a lower level operating system for precise and definite instructions to each of the line adapters associated with a given line support processor.

The main host computer in the system is provided with a network definition language (NDL) which is processed through a compiler in order to generate S-operators. These S-operators are loaded into the auxiliary memories associated with each of the state machine processors of each of the line support processors wherein certain interpretive algorithms are used by the state machine processor such that the high level S-operators are converted to operating instructions by the state machine in order to handle the data comm requirements of each of the individual line adapters that go to make up the system.

The I/O subsystem designated as a Line Support Processor (LSP-Data Link Processor) can support up to 16 data-comm lines to remote data sets or data terminals for the transfer of data between a main host computer and multiple numbers of remote terminals. The LSP operates in a specialized environment where the LSP receives I/O commands and task-identifying Data Link words for execution and returns Result/Descriptor words back to the host to indicate completion/incompletion of each assigned task. The LSP is organized with slide-in cards in a Base Module which provide (a) a plurality of Line Adapters (one for each data comm line) where each Line Adapter includes a buffer memory, (b) a processor unit called a universal input/output (UIO) State Machine for executing I/O commands from the Host, and (c) a Data Link Interface Unit which connects the LSP to the Host Computer and provides logic for selection of desired Line Adapters and specific components thereon such as buffer memories, timers, USARTs or Bit-Oriented Controllers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an overall data communications system drawing showing the relationship of the host computer to the Line Support Processor and the connection to the remote terminals.

FIG. 1A is a diagram showing the MLI interface to the host and the internal interface to the Line Adapters of the Line Support Processor; FIG. 1B shows the Line Adapter interfaces to direct-connect equipment and the use of an Automatic Calling Unit; FIG. 1C shows the basic elements of the Line Adapter of the Line Support Processor. FIGS. 1D, 1E, 1F, 1G are schematics showing the use of data structures within the Line Support Processor.

FIG. 2 is a schematic drawing showing the backplane of the Base Module and the slide-in cards which go to make up the Line Support Processor.

FIG. 3 shows a dialing sequence for a type 801 Automatic Calling Unit.

FIG. 4 is a block diagram of a bit-oriented Line Adapter in the Quad version whereby four Line Adapters are configured on one slide-in card.

FIG. 5 is a block diagram of a Byte-Oriented Line Adapter in the Quad configuration of four Line Adapters on one slide-in card.

FIG. 6 is a block diagram of the State Machine Microprocessor and often abbreviated as the UIO-SM.

FIG. 7 is a block diagram of a portion of the DLI/LA card which shows an internal data path.

FIG. 8 is a block diagram of the DLI/LA card which shows the controller sequencing logic for operation of the interface card.

FIG. 9 is a block diagram of the data bus structure of a single Line Adapter which is part of the DLI/LA card.

FIG. 10 is a block diagram of the memory and memory logic portion of the DLI/LA card.

FIG. 11 is a schematic drawing of the circuitry for identifying sub-components on a selected line adapter.

BACKGROUND

The essence of data communication is the electronic transmission of encoded information or data from one point to another. In general the mechanisms of data communication physically require certain elements, these include: a transmitter or source of information, a message, a binary serial interface, a communication channel or link, and a receiver of transmitted information. In order to make the binary serial data compatible with the communication channel, there is usually required a data communications interface.

A communications channel or link is a path whereby electrical transmission can occur between two or more stations or terminals by means of, for example, a single wire, multiple wires, coaxial cable, radio frequency transmission, etc. The channel has the purpose of carrying information from one location to another, and these channels are ordinarily designated as simplex, half-duplex and full duplex in the data communication art.

A channel is characterized by its band width, such that the greater the band width of the channel, the higher the possible transmission speed. The speed is measured in terms of the number of bits per second transmitted and called the Baud rate.

Since the pulses transmitted over a communication line can be distorted by various factors, the optimum situation is such that the received signal will be an exact replica of the transmitted signal.

In that the voice telephone network in general uses "analog" transmission facilities to service data communications users, there is required an interfacing means to interface the analog channels to the digital terminals and computers. The interface unit is called a modem (modulated-demodulator) and is used to convert digital signals into analog signals or else analog signals back into digital signals. Thus, modems are devices that convert digital data from a computer or a digital terminal to a modulated carrier waveform (analog) required by the communication channel. One modem is needed at each end of the channel. It should be noted that modems are also called "data sets" and sometimes designated as DS. There are two broad categories of voice grade data sets or modems. These are "asynchronous" units and "synchronous" units. The "asynchronous" units operate at a rapid maximum data rate of 1800 bits per second over dial-up facilities and at 2,000 bits a second on preconditioned leased lines. "Synchronous" units operate generally at a maximum data rate of 4800 bits per second over dial-up lines and at 9600 bits per second on conditioned leased lines.

In asynchronous systems the transmission line is in a "Mark" (binary 1) condition in its "idle" state. As each character is transmitted, it is preceded by a start bit, or transition from mark to space (binary 0) which indicates to the receiving terminal that a character is being transmitted. The receiving device detects the start bit and the data bit that make up the character. At end of the character transmission, the line is returned to "Mark" condition by one or more stop bits and is ready for the beginning of the next character. The start and the stop bits permit the receiving terminal to synchronize itself to the transmitter on a character by character basis.

Synchronous transmission uses an internal clocking source within the modem to synchronize the transmitter and receiver. Once a synchronization character (SYN) has been sensed by the receiving terminal, data transmission then proceeds character by character without the intervening start and stop bits. The incoming stream of data bits is interpreted on the basis of the received clock supplied by the modem. This clock is usually derived from the received data through a phase locked loop. The receiving device accepts data from the modem until it detects a special ending character or a character terminal count at which time it knows that the message is over. The message block consists generally of one or two synchronization characters, a number of data and control characters, a terminating character and one or two error control characters. Between messages the communication line may idle in SYN characters or be held to "Mark".

Asynchronous transmission is advantageous when transmission is irregular; it is also less expensive due to simpler interface logic and circuitry required. However, synchronous transmission, since it eliminates the start and stop bits of each character, makes better timing use of the transmission facility. And synchronous modems offer higher transmission speeds even though they are more expensive since they require precisely synchronized clock and data.

When a number of I/O devices are required at one end of a communication channel, a multiplexor can be used to enable these devices to share one communication line, thus reducing costs. Multiplexors take low speed inputs from a number of terminals and combine them into one high speed data stream for simultaneous transmission on a single channel. At the other end of the channel a second multiplexor which operates as a "demultiplexor" reconverts the high speed data into a series of low speed inputs to the host computer.

The electrical and physical interface to the data terminal equipment is generally built to certain standards such as that established by the Electronics Industries Association such as EIA RS-232.

There are certain rules and modes which are required for the orderly and accurate transfer of data between digital units and these rules are called "protocols". For example, there are established data link control protocols (DLCs) which are rules necessary for communication between terminals and computers over the standard communication channels in order to move information accurately and efficiently. These data link control protocols provide the function of establishing and terminating a connection between two stations; insuring message integrity through error detection; providing requests for retransmission; providing positive or negative acknowledgments; providing identification of the sender and receiver by means of polling or selection; and providing special control functions such as "requests for status", "station reset", "reset acknowledge", "start", "start acknowledge", and "disconnect".

These data link control protocols can be classified in certain categories such as (i) byte control protocols (BCPs) and (ii) bit oriented protocols (BOPs). With the byte control protocols, a defined set of communication control characters monitors the orderly operation of the data link and these control characters are part of a character code set. Thus, the BCP messages are transmitted in blocks composed of a header or control field, a body or text field, and a trailer or error checking field with specialized characters used as field or block delimiters. One example of a byte control protocol is the Binary Synchronous Communications Protocol (BISYNC) developed by the IBM Corporation.

The "bit oriented" protocols (BOPs) may use only two or three specific control characters for monitoring operation of the data link. These characters are used to delimit the beginning (FLAG) and the end (FLAG, ABORT, GA) of a message frame. Upon receipt of the opening FLAG, there is a positional significance which is used to delineate the bit sequence that follows into specified fields which are designated as address, control, information, and frame check sequence fields.

In the "byte oriented" control protocol (BCP) the BCP messages are transmitted in units called "blocks". The header field contains information that identifies the address of the message destination (or source); the job number, if any; the type of message (data or control); the control action; and a positive or negative acknowledgment to ensure error-free reception of a previous message or messages. These control actions are used to reset or to initialize a secondary station, to acknowledge good or bad reception of blocks, to inquire why a response or acknowledgment has not occurred within a specific time period, or else to abort a transfer sequence. The control information is conveyed via special characters or character sequences.

The text or text field of the BCP message contains any data being transmitted.

An error check field (composed of the sequence of check bits called block check characters or BCCs) is generated and transmitted in order to ensure correct reception of information on a communication facility. BOP Messages: The "bit oriented protocol" messages are a little simpler than the byte oriented ones. The BOP messages are transmitted also in frames, and all the messages follow one standard frame of format. These bit oriented messages are independent of codes, line configurations and peripherals. They use positional significance instead of control characters or character counts that include one standard frame-format for all messages. Here a "frame" starts with an eight-bit FLAG sequence which is followed by sequences of: ADDRESS, CONTROL, INFORMATION, and FRAME CHECK, and this ends with another FLAG sequence.

When a primary station transmits, then the station ADDRESS sequence (usually one eight-bit field) designates which secondary station is to receive the balance of the transmitted frame. On the other hand, when a "secondary" station transmits, the ADDRESS then tells the primary station which secondary station originated the frame. To ensure the integrity of the data being transmitted, the ADDRESS sequence appears within each frame.

The CONTROL field of the primary station comes after the ADDRESS sequence and is generally composed of one or two eight-bit bytes. It determines the "type" of message, the send and the receive frame sequence counts, and a poll command from the primary station (or a final response from the secondary station). The primary station uses the CONTROL field to command the addressed secondary station what operation to perform. The secondary station uses the CONTROL field to respond to the primary station.

The INFORMATION field may vary in length, and the data may be configured in any code structure, such as straight binary, binary coded decimal, packed decimal, etc. Synchronization of Transmission: When using synchronous transmission, there may be four different types or methods of synchronization--bit, character, block and message. Bit synchronization is achieved through a received clock signal which is coincident with a received serial data stream. Character synchronization is accomplished by recognizing one or two "phasing" characters called SYN or sync characters.

Retransmission: The data link protocols include an error checking field to allow the receiving station to validate the message. When errors are detected, the receiving station can issue a request for "retransmission" (ARQ). There are two types of "request for transmission". These are: (i) stop and wait and (ii) continuous. Each of these provide methods for acknowledging correct "error free" reception of transmitted blocks of information.

In the "stop and wait" ARQ, the transmitter sends one block and then stops. The receiver acquires that block, subjects the block to an error check, and then sends an ACK control character back to the transmitter indicating that the block is correct, or else it sends a NAK control character to indicate an error occurred. If an ACK is returned, the transmitter sends the next block in sequence. If a NAK is returned, that particular block is retransmitted.

In the "continuous" ARQ the transmitter keeps sending one block after another without stopping. The receiver and transmitter retain individual counts of the blocks outstanding and provide buffer storage to retain those blocks. Only when an erroneous block is detected does the receiver then tell the transmitter to resend that block and all subsequent-in-transit blocks.

"Serial Data" Transmission: Serial data communication involves the use of a transmission line where "bits" of data are transmitted one after another in serial fashion. In computer systems, the serial data communication can occur in two fundamental modes. These are (i) asynchronous (not clocked) or (ii) synchronous (clocked).

Since the asynchronous mode does not use a block, it requires some other method to coordinate incoming data with the receiver's internal system. Thus typically, an asynchronous communication network keeps its communication line in an "idle" condition which is generally called a "Mark" or binary 1 condition. Then a "start" bit precedes each transmitted character to indicate that a new character is beginning and one or more "stop" bits signal the characters end and the return to the idle condition. This sequence of start bit-character data-stop bit is generally called a "frame".

In asynchronous usage the "character length" varies and may range from five to seven bits depending on the code used (BAUDOT, ASCII, and so on) and also error checking can be used on each character by using an additional bit called a "parity" bit. Thus, in the asynchronous communication of characters, much of the time consumed involves non-informational data but rather control bits such as the start bit and two stop bits.

Alternatively, the use of synchronous communication eliminates the high overhead of control bits but requires another method for achieving synchronization. Such synchronous communication networks transmit a clock signal along with the data bits in order to establish individual-bit synchronization between devices.

Certain standardized rules have been made to govern operation of networks and communication protocols are used to define the network's transmission format whether asynchronous or synchronous. Complex computer-to-computer terminal or terminal to terminal networks utilize synchronous data-communication protocols which are either character-oriented or bit-oriented.

The primary "character-oriented" protocol used as an industry standard is called Binary Synchronous Communication and is termed Bisync. This protocol requires certain control-character bit patterns (BEL, ETX, ITB, SOH, STX) in order to ensure proper network operation. Since these bit patterns constitute "control characters", they cannot also be used as a transmission of data. The Bisync protocol requires that transmission be half-duplex since receipt of a block must be "acknowledged" before another block can be transmitted.

This need for a half-duplex requirement is eliminated by the use of BOPs (bit oriented protocols). Here blocks received do not have to be acknowledged each time they are sent and thus full-duplex operation is possible in BOP networks.

There are several bit oriented protocols (BOPs) in current usage: Advanced Data Communication Control Procedure (ADCCP); High-Level Data-Link Control (HDLC); and Synchronous Data-Link Control (SDLC), and Burroughs Data Link Control (BDLC).

The most widely used bit protocol (of these types) is the SDLC. Here information is transmitted between stations in data groups termed "frames" whereby each frame comprises several fields and each field is eight or more bits long or organized in multiples of eight bits. The bits in each field of each frame are set with a specific meaning.

SDLC uses two types of stations desigated as a "primary" or "control" station and a "secondary" slave or "controlled" station. Here the protocol is code independent, and data to be transmitted must be contained in each frame's Information Field. The number of bits per character in any Information Field is limited to eight and the sending frames and the receiving frames are numbered independently. The SDLC's code independence permits full duplex operation. The organization of fields in the SDLC protocol constitutes a "frame" as shown hereinbelow.

                                      TABLE B-1
    __________________________________________________________________________
     ##STR1##
    __________________________________________________________________________

                  TABLE B-2
    ______________________________________
     ##STR2##
    ______________________________________

                  TABLE B-4
    ______________________________________
    Direction    Signal Name
    ______________________________________
    LSP .fwdarw. DCE
                 DTR       Data Terminal Ready
    LSP .rarw. DCE
                 DSR       Data Set Ready
    LSP .fwdarw. DCE
                 RTS       Request to Send
    LSP .rarw. DCE
                 CTS       Clear to Send
    LSP .fwdarw. DCE
                 SO        Special Output
    LSP .rarw. DCE
                 SI        Special Input
    LSP .fwdarw. DCE
                 DM        Dial Mode
    LSP .rarw. DCE
                 DCD       Data Carrier Detector
    LSP .rarw. DCE
                 RI        Ring Indicator
    LSP .rarw. DCE
                 SCT       Serial Clock Transmit
    LSP .rarw. DCE
                 SCR       Serial Clock Receive
    LSP .fwdarw. DCE
                 TD        Transmitted Data
    LSP .rarw. DCE
                 RD        Received Data
    ______________________________________

                  TABLE B-5
    ______________________________________
    Direction    Signal Name
    ______________________________________
    LSP .fwdarw. DCE
                 CRQ       Call Request
    LSP .rarw. DCE
                 PWI       Power Indication
    LSP .rarw. DCE
                 PND       Present Next Digit
    LSP .fwdarw. DCE
                 DPR       Digit Present
    LSP .fwdarw. DCE
                 NB1       Digit Signal 1
    LSP .fwdarw. DCE
                 NB2       Digit Signal 2
    LSP .fwdarw. DCE
                 NB4       Digit Signal 4
    LSP .fwdarw. DCE
                 NB8       Digit Signal 8
    LSP .rarw. DCE
                 DLO       Data Line Occupied
    LSP .rarw. DCE
                 ACR       Abandon Call and Retry
    LSP .rarw. DCE
                 DSS       Data Set Status
    ______________________________________

                  TABLE B-5
    ______________________________________
     ##STR3##
    A particular field is defined by the following notation:
    w: `Field Name`: Word (x) (y:z)
    w:          The letter `w` is used to
                cross-reference the verbal description
                of the field with its position in the
                associated diagram. Subfields of
                fields are not assigned individual
                field letters.
    Field Name: The name assigned to the field.
    Word (x):   The field is contained within (or
                starts in) MLI word number `x`.
    (y:z):      The field starts at the bit labelled
                `y` and is `z` bits wide.
    ______________________________________

                  TABLE B-6
    ______________________________________
    Common I/O-descriptor field definition:
    ______________________________________
     ##STR4##
     ##STR5##
     ##STR6##
    ______________________________________

                  TABLE B-7
    ______________________________________
     ##STR7##
    ______________________________________

                  TABLE B-8
    ______________________________________
    Operation Type      Code
    ______________________________________
    Extended Op Type    0000
    Initialize S-Machine
                        0001
    Update S-Machine    0010
    Monitor Switched-Line
                        0011
    Answer Switched-Line
                        0100
    Auto-Dial Switched-Line
                        0110
    Disconnect Switched-Line
                        0111
    Execute Input Process
                        1000
    Execute Output Process
                        1001
    Discontinue         1010
    Soft-Clear Line     1011
    Test LSP ID         1100
    Test Line           1101
    Dump Data-Area      1110
    ______________________________________

                  TABLE B-9
    ______________________________________
    Extended Operation Type
                        Code
    ______________________________________
    (Non extended Op Type)
                        0000
    ______________________________________

                                      TABLE B-10
    __________________________________________________________________________
    I/O Descriptor:
                Word 1  Word 2  Word 3  4 - N
    Operation Type
                A B C D A B C D A B C D A B C D
    __________________________________________________________________________
    (1)
       Initialize S-Mach
                4 1 0 3 d d e 0 g g g g h h h h
    (2)
       Update S-Machine
                4 2 0 3 d d e 0 g g g g h h h h
    (3)
       Monitor  2 3 0 1 d d e 0 --
                                  --
                                    --
                                      --
                                        --
                                          --
                                            --
                                              --
    (4)
       Answer   2 4 0 1 d d 0 0 --
                                  --
                                    --
                                      --
                                        --
                                          --
                                            --
                                              --
    (5)
       Auto-Dial
                4 6 0 2 d d 0 0 g g g g --
                                          --
                                            --
                                              --
    (6)
       Disconnect
                2 7 0 1 d d 0 0 --
                                  --
                                    --
                                      --
                                        --
                                          --
                                            --
                                              --
    (7)
       Execute Input
                a 8 c c d d 0 0 g g g g h h h h
    (8)
       Execute Output
                a 9 c c d d 0 0 g g g g h h h h
    (9)
       Discontinue
                2 A 0 1 d d e 0 --
                                  --
                                    --
                                      --
                                        --
                                          --
                                            --
                                              --
    (10)
       Soft-Clear Line
                2 B 0 1 d d e 0 --
                                  --
                                    --
                                      --
                                        --
                                          --
                                            --
                                              --
    (11)
       Test LSP ID
                2 C 0 0 --
                          --
                            --
                              --
                                --
                                  --
                                    --
                                      --
                                        --
                                          --
                                            --
                                              --
    (12)
       Test Line
                2 D 0 1 d d 0 0 --
                                  --
                                    --
                                      --
                                        --
                                          --
                                            --
                                              --
    (13)
       Dump Data-Area
                8 E 0 2 d d 0 0 g g g g --
                                          --
                                            --
                                              --
    __________________________________________________________________________
     N = The last I/Odescriptor word (48 maximum).
      0 = 9, A-F = The corresponding hexadecimal digit.
     -- = The word does not apply to the operation type.
     a = Execute Input (8 or 2); Execute Output (4 or 2).
     c = The total number of I/Odescriptor words minus one.
     d = The line number.
     e = An operationtype dependent option selector.
     g = The number of bytes of data.
     h = Depends on the operation type.

                  TABLE Y-1
    ______________________________________
    V1(x)    V0(x)        Component Addressed
    ______________________________________
    0        0            Component Requestor ID
    0        1            USART/Timer
    1        0            ACU Status
    1        1            Adapter Type - ID
                          (Identification)
    ______________________________________

                  TABLE Y-2
    ______________________________________
    Register Bit and
    Value       Signal Designation
    ______________________________________
    Bit 0 = 1   USARTCS = Chip Select-UCS
    Bit 1 = 1   TMRCS = Timer Chip Select-TCS
    ______________________________________