Control device and a method for sending and receiving information in a vending machine and the like apparatus4616323Abstract Sending and receiving of information between a coinmech control section performing controls relating to receiving and paying out of coins and a vendor control section performing controls relating to selection and vending of an article are made under the leadership of the vendor control section. Multiple kinds of information to be sent and received are previously classified into a plurality of modes and a mode including necessary information to be sent and received is designated on the side of the vendor control section by a mode selection code. Responsive to contents of the mode selection code, one of the coinmech control section and the vendor control section is brought into an information sending state and the other into an information receiving state whereby a group of information for this mode is sent and received. Claims What is claimed is: Description A control device and a method for sending and receiving information in a vending machine and the like apparatus.
TABLE 1
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Coin control data mode (input mode)
MSC being "0111" (MSC2)
order
bit 1 2 3 4 5 6 end
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0 SES PBSO INV10 INVSUB 1 1 0
1 PSO DSO INV50 1 1 1 0
2 APO MCL INV100 1 1 1 0
3 IPO CASE INV500 1 1 1 0
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The figures 10, 100 and 1000 in the row of the unit represent digits in decimal notation of the vend price data. The symbol x indicates that any desired numerical value in the respective digits in decimal notation is expressed by a 4-bit cold (e.g. a BCD code) (the case is the same with the money amount data to be described later). Thus, x represents a desired one of "0" or "1".
TABLE 3
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Settlement amount data mode (input mode)
MSC being "0011" (MSC4)
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(Since the data delivery format is the same as
Table 2, this table is omitted.)
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The row of denomination shows denominations of the respective coins used, e.g., six denominations ranging from a 10-yen coin up to a 10,000-yen bill. The numerals "1" and "10" in the row of unit respectively represent the digit of 1 and the digit of 10 in a value of effective digits in decimal notation in a count-up amount for each denomination. If, for example, three 500-yen coins have been deposited, the count-up amount is 1500 yen and the value of effective digits is "15". Accordingly, the digit of 1 is "5" and the digit of 10 is "1".
TABLE 5
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Information data mode (input mode)
MSC being "0101" (MSC6)
order
1 2 3 4 5 6 end
unit
bit 10 100 1000 --
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0 x x x 1 1 x 0
1 x x x 1 1 1 0
2 x x x 1 1 1 0
3 x x x 1 1 1 0
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The row of the unit indicates the order of digits in decimal notation in the money amount indicator on the coin mechanism side. The information data includes not only figures but alphabet letters which can be indicated in 7-segment LED. An example of figures and letters (objects to be indicated) and truth values of 4-bit information data codified in correspondence to these objects to be indicated are shown in the following Table 5-1.
TABLE 5-1
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Truth table of the information data
object
bit 0 1 2 3 4 5 6 7 8 9 H blank C P E F
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0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
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The "blank" in the row of object in table 5-1 means that the digit to which this data has been given is extinguished. In the general manner of indicating the numerical value, if, for example, data indicating "1" is given to the order of 100, "0" is automatically indicated in the lower two digits whereby the indication of "100" is obtained. If the "blank" code is used for these two lower digits, the "0" indication in the two lower digits can be extinguished. This "blank" code does not indicate general extinguishment of the indication digit but indicates clearing of a register corresponding to the indication digit. In Table 5, "x" for the bit "0" of the order 6 becomes "1" when the indication digit of the order of 1 has been extinguished and becomes "0" when the indication digit has been lighted.
TABLE 6
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Vend control data mode (output mode)
MSC being "0110" (MSC10)
order
bit 1 2 3 4 5 6 end
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0 STS OKSP PBS EP1 1 1 0
1 ACS KNSP IVS EP2 1 1 0
2 PSS KPSP MPO 1 1 1 0
3 CSS ECE 1 1 1 1 0
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"1" and "10" in the unit represent, as in the previous Table 5, the orders of 1 and 10 in the decimal number indicating the number of the collected coins. The number of the collected coins is indicated by using a decimal number of two digits and the negative number is indicated by a complement.
TABLE 9
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Count amount by coin data mode (output data)
MSC being "1100" (MSC13)
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(Since the data delivery format is the same as
Table 4, this table is omitted.)
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MSC of the external device control data mode is "0001" and its symbol is MSC8. In the rows of the order in the above tables, the order of delivery of the 4-bit parallel data in the respective modes is shown. The order of delivery of the 4-bit parallel data is so arranged that a next delivery is made when the receipt by the receiving side of the data of the same contents as the sending side has been confirmed. More specifically, the receiving side sends back the same data as the received 4-bit data to the sending side which in turn collates the sent back data with the sent data and proceeds to a next data delivery order when it has been confirmed that the two data coincide with each other. This collation is performed also in sending and receiving of the mode select code MSC, whereby the delivery of the data shown in the above tables corresponding to the respective modes is started when the mode has been confirmed on the side of the coin mechanism control section 10. Each 4-bit data which has been delivered out in each delivery order in a particular mode is stored one by one in a data pool memory MR or MRv provided in the receiving side and, when the receipt of the end code (ENDC) has finally been confirmed, the contents of the memory MR or MRv are transferred by block to predetermined locations in the RAM's 14 and 19. The CPU's 12 and 17 perform predetermined processings in accordance with the signals which have been transferred from the I/O port sections 16 and 22 and stored at the predetermined locations in the RAM's 14 and 19. Details of the data sending and receiving processings between the I/O port sections will now be described. Outline of Data Sending and Receiving Processings In the coinmech control section 10, a coinmech I/O port check program (I/OCHECK) as shown in FIGS. 4-9 is executed for data sending and receiving control through the I/O port section 16. This I/OCHECK program is executed, when required, as a subroutine in various steps in the main processing program in the coinmech control section 10. More specifically, the I/OCHECK program is suitably carried out in the course of execution by the coinmech control section of its proper processing with the peripheral input and output device 15 and sending and receiving of data between the coinmech control section 10 and the vendor control section 11 is performed during this program. In the vendor control section 11, a vendor-I/O port mode program (I/OMODE) as shown in FIG. 10 is executed for data sending and receiving control through the I/O port section 22. This I/OMODE program is executed when the vendor control section 11 demands the coinmech control section 10 to input or output a signal of a desired mode. Timing and type of the mode which the vendor control section 11 demands (select) is determined by the main processing program on the side of the vendor control section 11 and this may be designed as desired depending upon the use, function and type of the vending machine. FIG. 2 shows an example of the main processing program executed in the coinmech control section 10 in a rough outline. Details of the program are not essential for the present invention and most of it may relate to execution of processings in the coinmech control section 10. In a standby period processing 29, various processings to be executed in a standby state prior to deposition of a coin are carried out. In a money receiving processing 30, various processings to be executed upon deposition of the coin (e.g., the counting of deposited money amount, the vend possible judgement and other processings) are carried out. In a money collection processing 31, various processings to be executed upon start of the vending operation (the article delivery operation) on the side of the vendor control section 11 (e.g., subtraction of the vend price from the amount of the deposited money and other processings) are carried out. In a change return processing 32, various processings to be executed when change or deposited money should be paid out are carried out. In a trouble processing 33, processings relating to trouble detection and trouble indication are carried out. The trouble processing 33 is incorporated in the course of the above described processings 29-32 and is executed as required. The I/OCHECK program (FIG. 4) is incorporated in the course of the processings 29-33 and is executed as required and also at the start and repeating of the main routine. Since details of the respective processings 29-33 can be readily understood from the description of the 45 kinds of input and output signals SES-CACD (i.e., in the signals of the input mode, the description of the processings in the coinmech control section 10 and in the signals of the output mode, the description of the conditions of delivery of such signals), description of such details will be omitted. For example, the money collection processing 31 is started when the above described signal PSO has been given and the change return processing 32 is started when the signal APO has been given. In the coinmech control section 10, states of the signals of the output mode are established in the course of the processings 29-33 and these status are written at each step in a predetermined area of the RAM 14. In executing the I/OCHECK program, the signals of the mode required by the vendor control section 11 (i.e., the output mode) are read in a package from the predetermined area of the RAM 14 and loaded in the data pool memory MR from which the signals are delivered out through the I/O port section 16 in a predetermined format. Accordingly, operations such as scanning for establishing the states of these signals of the output mode can be performed independently and sufficiently without being affected by the vendor control section 11 at all. Similarly, processings (such as scanning) for inquiring states of the signals of the output mode from the vendor control section 11 can be performed independently and sufficiently without being affected by the minimum scanning period required for the coin mechanism side. FIG. 3 shows an example of the processing program in the vendor control section 11 in a rough outline, mainly dealing with the mode select processing. As was previously described, the timing and type of the mode to be required (selected) can be freely designed, the program of FIG. 3 is shown only by way of example for the convenience of explanation. Further, as was described in explaining the 45 kinds of input and output signals SES-CACD, there are some modes that can be suitably selected in accordance with the states of the output signals from the coinmech control section 10 and these modes are omitted in FIG. 3 for the convenience of explanation. In the standby period, processings including those of the count-up amount by coin data mode (MSC5), information data mode (MSC6), external device control data mode (MSC8), trouble monitor data mode (MSC11) and count amount by coin data mode (MSC13) are executed (block 34). In the standby period also, the processing of the vend control data mode (MSC10) is always executed (block 35). Upon deposition of a coin, the ACS signal is present and the processing of the vend price data mode (MSC3) is executed (block 36). The delivery of the vend price data in this block 36 is executed with respect to one article (i.e., the i-th article) and i changes each time this block 36 is repeated in the loop of line 41. In other words, the processings in blocks 36-40 are executed with respect to one article which is the i-th one and these processings are executed sequentially for the respective articles by repetition thereof in the loop of line 41. In block 37, the processing of MSC10 is executed and in block 38 presence or absence of the OKSP signal concerning the i-th article is examined. In block 39, light indicating the vend possible state of the i-th article which has been judged vendible is lighted. In block 40, whether or not the article selection switch for this i-th article has been turned ON is examined and, if the result is YES, preparation for the vend operation is made in block 42. Nextly, the processing for the coin control data mode (MSC2) is executed (block 43) and, after executing the processing of MSC10 (block 44), the article delivery operation is started (block 45). In blocks 46, 47, 48, 49 and 50, the processings for the coin control data mode (MSC2), collected coin number by denomination data mode (MSC12), MSC10, settlement amount data mode (MSC4) and MSC2 are executed one by one. In blocks 43, 46 and 50 for the MSC2 mode which is repeatedly executed, states of the signals to be given to the coin mechanism side are changed. In blocks 34, 35, 36, 37, 43, 44, 46-50 in which the processings of the respective modes are executed, the predetermined mode select codes MSC2-MSC13 are set in a state in which they can be delivered out and the I/OMODE program shown in FIG. 10 is executed. The basic concept of sending and receiving of the signals between the coinmech control section 10 and the vendor control section 11 through the I/O port sections 16 and 22 is as shown in the tables below. A predetermined processing is executed in response to a signal state "1" or "0" of the control signal input ports CI and CIv and the control signal output ports CO and COv are set to a signal state "1" or "0" for demanding the opposite section to effect a next operation. In this way, employing the signal states at the control signal input and output ports CI-COv as key words, the control sections 10 and 11 which are operated by programs which are independent from each other send and receive signals between them in association with each other. Table 10 shows signal conditions at the control signal input and output ports (called C port hereafter) in the control sections 10 and 11 during the input mode (as viewed from the coinmech control section 10) and Table 11 shows similar signal conditions during the output mode (as viewed from the coinmech control section 10). Contents of processings listed in the rows of input are those executed in response to "1" or "0" at the control signal input ports CI and CIv and contents of processings listed in the rows of output are those executed when the control signal output ports CO and COv are set at "1" or "0".
TABLE 10
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The signal conditions at C ports during the input mode.
vendor control section 11
Coinmech control section 10
C ports
Contents of processings
Order
C ports
Contents of processings
Order
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input
"1"
Comparison of signal
5 input
"1"
Signal at IN port is
3
CIv contents at INv port
CI set to RIN register.
and OUv port is started.
"0"
Contents of RIN are
7
"0"
Next signal is set to
1 stored in MR memory.
RPO register.
output
"1"
Contents of RPO are set
2 output
"1"
Contents of RIN are set
4
COv at OUv port and COv
CO to OU port and CO port
port is set to "1". is set to "1".
"0"
If the comparison is
6 "0"
After MR memory proces-
8
coincidence, COv port sing, CO port is set to
is set to "0". "0".
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In Tables 10 and 11, the numbers in the column of order designate the order of processings between the coinmech control section 10 and the vendor control section 11. For example, in the input mode of the coinmech control section 10 (Table 10), a signal is delivered from the vendor control section 11 to the coinmech control section 10, so that the processing for setting a next signal to be delivered out to an output port data register RPO (hereinafter referred to as "RPO register") in the vendor control section 11 is designated as "order 1". This processing is executed following the processing of the order 8 concerning the preceding signal delivery in the coinmech control section 10. More specifically, upon setting of "0" at the CO port of the coinmech control section 10 by the processing of the order 8, the control signal to be given to the CIv port of the vendor control section 11 is turned to "0" and the step proceeds to the processing of the order 1. With reference to Table 10, when the control signal given to the CIv port of the vendor control section 11 is "0", a next signal (4-bit parallel data) to be delivered to the coinmech control section 10 is set to the RPO register (order 1) and then the contents of the RPO register are set at the data output port OUv for delivery to the coinmech control section 10 and the COv port is simultaneously set to "1" (order 2). In the coinmech control section 10, a 4-bit parallel data signal which is given from the OUv port to the IN port when the control signal given from the COv port to the CI port is turned to "1" is loaded in the input port data register RIN (hereafter referred to as "RIN register") (order 3). Then the contents of this RIN register are set to an output port data register ROU (hereinafter referred to as "ROU register") and the contents of this ROU register are set at the OU port while the CO port is set to "1" (order 4). The contents of the RIN register may be supplied directly to the OU port, omitting the step of setting them to the ROU register. Thus, the data provided by the vendor control section 11 is received by the coinmech control section 10 and, when this data is stored in the RIN register, the contents of the RIN register are fed back to the vendor control section 11 through the OU port for confirmation and a signal "1" is delivered from the CO port. On the side of the vendor control section 11, the data given from the OU port to the INv port (i.e., returned for confirmation) is loaded in an input port data register RPI (hereinafter referred to as "RPI register") when the control signal given from the CO port to the CIv port is "1" and the contents of this data are compared with those of the RPO register, i.e., the contents of the OUv port (order 5). If coincidence of two contents has been confirmed as a result of the comparison, the COv port is set to "0" (order 6). When the contents of the 4-bit data (output of the OUv port) delivered from the vendor control section 11 and the 4-bit data (input to the INv port) received in the coinmech control section 10 and stored in the RIN register do not coincide with each other due to some error in transmission, the COv port is not set to "0" but remains "1". In the case of the transmission error, therefore, the step does not proceed to a next processing so that an erroneous operation of the device due to error data can be prevented. In the coinmech control section 10, the contents of the RIN register are stored in the data pool memory MR when the controlsignal given from the COv port to the CI port is turned to "0" (order 7). Since the contents of the RIN register have been fed back to the vendor control section 11 for collation and correctness of the contents of the RIN register has been confirmed, the data to be stored in the MR memory is not the signal given to the IN port but should correctly be the signal stored in the RIN register. After the storage processing in the MR memory, the CO port is set to " 0" to demand the vendor control section 11 to deliver out a signal for a next cycle (order 8). The processings for one cycle from the order 1 to order 8 in Table 10 are repeated by the number of times shown in the column of order concerning the processings of the respective input modes shown in Tables 1-5. The contents of the 4-bit data signals to be delivered out in the respective data delivery orders are as shown in Tables 1-5. The 4-bit data signals which have been stored by the processing of the order 7 for each cycle (order) are sequentially stored in the data pool memory MR and, when sending and receiving of the end code ENDC has finally been received, all signals for one mode that have been stored in the memory MR are transferred by block to a predetermined location in the RAM 14. In the coinmech control section 10, these signals which have thus been transferred by block to the predetermined location in the RAM 14 are used for performing the processings therein. Accordingly, only when all signals for one mode block have been sent and received correctly, this signal group can be utilized by the coinmech control section10 so that an erroneous operation due to an error in the signal transmission can be prevented. The output mode shown in Table 11 is treated in the same principle as in the input mode shown in Table 10. Referring to Table 11, when the control signal given to the CI port of the coinmech control section 10 is "1", a next 4-bit parallel data signal to be delivered to the vendor control section 11 is set to the ROU register (order 1). Then the contents of the ROU register are set at the OU port for delivery to the vendor control section 11 and the CO port is set to "1" (order 2). In the vendor control section 11, when the signal given from the CO port to the CIv port is "1", the 4-bit parallel data given from the OU port to the INv port is loaded in the RPI register (order 3). The contents of this RPI register are subsequently stored in the RPO register and the contents of the RPO register are set at the OUv port and the COv port is set to "0" (order 4). The contents of the RPI register may be supplied directly to the OUv port, omitting the RPO register. When the data given from the coinmech control section 10 is thus received by the vendor control section 11 and stored in the RPI register, the contents of the RPI register are fed back to the coinmech control section 10 for confirmation and a signal "0" is given from the COv port to the CI port. In the coinmech control section 10, when a signal "0" is given to the CI port, the data given from the OUv port to the IN port is loaded in the RIN register and the contents thereof are compared with the contents of the ROU register, i.e., those of the OU port (order 5). If the comparison has resulted in coincidence, the CO port is set to "0" (order 6). In the vendor control section 11, the contents of the RPI register are stored in the data pool memory MRv when the control signal given from the CO port to the CIv port is turned to "0" (order 7). After the storage processing in MRv, the COv port is set to "1" to demand the coinmech control section 10 to deliver out a next signal (order 8). The processings for one cycle from the order 1 to order 8 in Table 11 are repeated by the number of times shown in the row of order concerning the processings of the respective output modes shown in Tables 6-9. The contents of the 4-bit data signals to be delivered out in the respective data delivery orders are as shown in Tables 6-9. The 4-bit data signals which have been stored by the processing of the order 7 for each cycle (order) are sequentially stored in the data pool memory MRv in the vendor control section 11 and, when sending and receiving of the end code ENDc has finally been received, all signals for one mode that have been stored in the memory MRv are transferred by block to a predetermined location in the RAM 19. In the vendor control section 11, these signals which have thus been transferred by block to the predetermined location in the RAM 19 are used for performing the processings therein. Detailed Description of the Data Sending and Receiving Processing Program FIG. 4 shows the entire flow of the I/O check program for effecting the input and output processings through the I/O port section 16 in the coinmech control section 10. Examples of the processings 51 to 55 are shown in detail in FIGS. 5 to 9, respectively. The character "N" on the flow lines from the judgement blocks indicates "NO" and the character "Y" "YES". The MSC judgement processing 51 is executed to judge whether or not the 4-bit data that was supplied from the vendor control section 11 to the IN port of the coinmech control section 10 through the OUv port is the mode select code MSC and to effect pertinent processings, setting the mode flag MSCF to "1" when it has been judged that the data is the mode select code MSC. The details are shown in FIG. 5. The external device processing 52 is a processing executed when the external device control data mode was selected. The details are shown in FIG. 6. In the I/O processing 53, the 4-bit data signal sending and receiving processing in the input mode or output mode is executed according to the basic format shown in Tables 10 and 11 and the data sending format shown in Tables 1 to 9. The details are shown in FIGS. 7(a) and 7(b) which are connected together through junctions A and B. The signal start processing 54 is executed when the electric power is turned on or when abnormality was detected in the I/O port input and output signals of the vendor control section 11 or coinmech control section 10 to set these signals in a stand-by state by effecting the pace keeping (synchronization) of the input and output signals of the I/O port sections of both control sections 10 and 11. The details are shown in FIGS. 8(a) and 8(b) which are connected together through junctions C and D. The C port check processing 55 is effected to check whether or not the control signal supplied to the control signal input port CI sustained "0" longer than a predetermined period of time and when in the affirmative, carries out a processing against the abnormality. When an abnormality was detected in both the I/O CHECK program of the coinmech control section 10 and the I/O MODE program of the vendor control section 11, the signal "0" is continuously supplied to the control signal output ports CO and COv. The C port check processing 55 is carried out to check whether or not the signal "0" was continuously delivered from the COv port of the vendor control section 11. The I/O MODE program of the vendor control section 11 is also provided with the C port check processing for the same purpose. The details are shown in FIG. 9. The start processing finish flag STOK is set to "0" when the signal start processing 54 is to be carried out and set to "1" when this processing was executed. In FIG. 4, the I/O CHECK program starts with checking whether or not the STOK flag is "1" and if NO, carries out the signal start processing 54 and, if YES, examines whether or not the mode flag MSCF is "1". When the arrival of the mode select code MSC is awaited, MSCF=1 is judged NO and the MSC judgement processing 51 is carried out. When the mode select code MSC has been already set and the sending and receiving of the signal related to the subject mode is to be carried out, MSCF=1 is judged YES so the step proceeds to checking whether or not the contents of the mode select code register RMSC is the external device control data mode MSC8 (RMSC=MSC8). If RMSC=MSC8, the external device processing 52 is carried out and if not, I/O processing 53 is effected. When the mode select code MSC was detected in the MSC judgement processing 51, the contents of the code (said MSC2 to MSC13) are set in the MSC register. The C port check processing 55 is executed in each round of the I/O CHECK program at the end. FIG. 10 shows the entire flow of the I/O MODE program for effecting the input and output processing through the I/O port section 22 in the vendor control section 11. Examples of the processings 56, 58 to 60 are shown in detail in FIGS. 11 to 14. Although the I/O MODE program shown in FIGS. 10 to 14 and the I/O CHECK program shown in FIGS. 4 to 9 are executed separately using separate CPUs 12 and 17, the flags and registers of similar characteristics will be designated by the same reference characters between the two programs. In the MSCi processing 56, the mode select code MSC is delivered from the vendor control section 11 to the IN port of the coinmech control section 10 through the OUv port. The details are shown in FIGS. 11(a) and 11(b) which are connected together through junctions E and F. MSCi designates one of the code values MSC2 to MSC13 of the mode select code MSC. The code values MSC1, MSC7, MSC9 and MSC14, which are not referred to in the previous explanation about the modes, correspond to "1111", "1001", "1110" and "0100", respectively (all headed by LSB and expressed such that the active state is represented by the low level). There exist no modes in this embodiment which correspond to these values. The external device processing 57 is effected to carry out the data delivery processing for said external device control data mode. Detailed description thereof is omitted in respect of this embodiment. The I/O processing 58, signal start processing 59 and C port check processing 60 are provided to effect similar processings in the vendor control section 11 to those 53, 54 and 55 previously described, respectively having the same names. The details are shown in FIGS. 12(a) and 12(b), 13 and 14, respectively. FIGS. 12(a) and 12(b) are connected together through junctions G and H. The flow of processings in FIG. 10 is the same as that shown in FIG. 4 and the flags STOK, MSCF and register RMSC in FIG. 10 are also of the same characteristics as those shown in FIG. 4. The respective processings will now be described in detail in the signal sending and receiving order. (1) Sending and receiving of the mode select code Until the mode select code MSC is delivered, the mode flag MSCF on the side of the vendor control section 11 is "0" so that the MSCi processing 56 is executed in the I/O MODE program in FIG. 10. The flags and register used in the MSCi processing 56 in FIG. 11 are as follows. Fa . . . individual data sending and receiving flag Fb . . . sending finish mode select code check finish flag Fr . . . data sending mode flag (as viewed from the side of the coinmech control section 10) Ri . . . order register Meanwhile, the MSC judgement processing 51 in FIG. 5 is executed at this time in the I/O CHECK program on the coinmech side. The flags and register used in the MSC judgement processing 51 in FIG. 5 are as follows. FA . . . individual data sending and receiving flag FB . . . data block sending and receiving processing finish flag FR . . . output mode flag Ri . . . order register To deliver the mode select code MSC, the processing of block 61 in the MSCi processing 56 in FIG. 11 is first carried out to set the code MSCi to be delivered in the register RMSC. When the code is yet to be delivered, the flag Fa is "0" so that block 62 is judged NO. In that case, blocks 63 to 66 examine whether or not the contents of the register RMSC (MSCi) are MSC1, whether MSC7<RMSC<MSC1 (i.e., whether RMSC is one of MSC2 to MSC6 corresponding to the input mode of the coinmech control section 10 or the data delivery mode of the vendor control section 11), whether MSC14<RMSC<MSC9 (i.e., whether RMSC is one of MSC10 to MSC13 corresponding to the output mode of the coinmech section 10 or the data receiving mode of the vendor control section 11) and whether or not RMSC is MSC8. In the data delivery mode of the vendor control section 11, the flag Fr is set to "1" (block 67). Where any mode has been selected, the step proceeds to block 68 to clear the register RPO to "0", then set the mode select code MSCi of the register RMSC in RPO and supply this code MSCi of RPO to the OUv port. Thereafter, the flag Fa is set to "1" in block 69 and the signal "1" is supplied to the COv port. Meanwhile, if MSCi set in RMSC does not correspond to any mode, the step proceeds to block 70 to clear RPO to "0" and set all 1s in RPO (meaning absence of data), which is supplied to the OUv port. Fa is not set in this case. Once delivery of the mode select code has been started, block 62 is judged YES in the next cycle so that the signal of the CIv port is checked. Because of the active low system employed in this embodiment, CIv is normally "1" and, initially, block 71 is judged YES and the next block 72 or Fb=1 is judged NO. In block 73 for the INv port check, the INv port signal is taken, the register RPI is cleared to "0" and the INv port signal is set in RPI. Block 74 compares the signal in the register RPI taken from the INv port and the signal in the register RPO produced from the OUv port and waits until they coincide with each other. Meantime the coinmech control section 10 separately carries out the MSC judgement processing 51 in FIG. 5 whereby the CI port signal is taken in block 75 for "CI port check" and examined in block 76 to see whether or not it is "1". The indications "-port check" in blocks all mean taking in the signal supplied to the respective ports. The flowchart includes specific indications that, before new data is to be written into a register, the register must be cleared to "0" (e.g., blocks 68, 70 in FIG. 11). However, description hereinbelow will not refer to "-port check" or "register clearing processing". Initially, as before, the signal supplied from the COv port to the CI port is "1" so that block 76 is judged YES. Since the flag FB is still "0", next block 77 is judged NO so that the data from the IN port is set in the register RIN (block 78), the contents of the register RIN are set also in the ROU register and provided from the OU port (block 79), the flag FA is set to "1" (block 80) and the CO port output signal is set to "1". This processing is repeated until the CI port goes to "0". Meanwhile in FIG. 11, block 74 repeats comparing the signal returned by the processing 79 in FIG. 5 (the contents of the RPI register) and the produced signal (the contents of the RPO register). When coincidence between these signals is confirmed, the flag Fb is set to "1" (block 81) and the COv port output is set to "0" (block 82). In FIG. 5, block 76 is judged NO since the signal supplied from the COv port to the CI port has gone to "0" so that the flag FA is examined in block 83. Block 80 is judged YES as the flag FA is set so that blocks 84 to 87 examine, as before, whether or not the contents of the input register RIN (i.e, mode select code MSCi) are MSC1, whether or not MSC7>RIN>MSC1, whether or not MSC14>RIN>MSC9 or whether or not it is MSC8. As will be clear from the previous description, block 86 is judged YES in the output mode so that the output mode flag FR is set to "1" (block 88). In the output mode, input mode (where block 85 is judged YES) or the external device control data mode (where block 87 is judged YES), the mode select code MSCi in the RIN register is set in the RMSC register (block 89), the flag FB is set to "1" (block 90), the flag FA is reset to "0" (block 91), and the CO port output is set to "0" (block 92). Where block 87 is judged NO, abnormality is indicated so that the STOK flag is set to "0" (block 93) and then the CO port is set to "0". In FIG. 11, the step through YES of blocks 71 and 72 is repeated until the CIv port goes to "0". The processing of block 92 causes the CO port to go to "0", which in turn causes the CIv port to go to "0" and, accordingly, the step proceeds from NO of block 71 to NO of block 94, where the flag Fb is examined. Since the flag Fb was set in block 81, block 94 is judged YES and the flag Fr is examined in block 95. In case of the data sending mode (the input mode on the coinmech side), the processing of block 96 is carried out so that a set of 4-bit data signals (see FIGS. 1 to 5) corresponding to the mode stored in the RMSC register is drawn from a predetermined location of RAM 19 and stored in the data pool memory MRv. In the case of data receiving mode (the output mode on the coin mechanism side), block 96 is not executed. Next, the signal delivery order number corresponding to the mode stored in the RMSC register is set in the order register Ri (block 97). This signal delivery order number is the maximum (6, 12 or 18) of the numbers given in the row of order shown in Tables 1 to 9. The mode flag MSCF is then set to "1" and the flag Fa is reset (block 98). Meanwhile in FIG. 5, since the processing of block 91 has reset the FA flag to "0", the step circulates through NO of blocks 76 and 83 while the CI port input singal (i.e., the COv port output, which has been set to "0" in block 82 in FIG. 11) remains "0". Thereafter, the CI port input signal goes to "1" when, as will be described later, the processing of block 99 (FIG. 12(b)) sets the COv port to "1", and the step therefore proceeds through YES of block 76 and YES of block 77 (FB has been set to "1" in block 90) up to block 100. Block 100 judges whether or not the data is in the output mode (FR=1). If YES, a set of 4-bit data signals (see Tables 6 to 9) corresponding to the mode stored in RMSC is drawn from a predetermined location of RAM 14 and stored in the data pool memory MR. If NO (in case of input mode), this processing is not carried out. The flag FB is then reset to "0" and the signal delivery order number corresponding to the mode stored in the RMSC register is set in the order register Ri (block 101). The mode flag MSCF is then set to "1". (2) Data Sending and Receiving in the Case of Input Mode (Data delivery mode in the vendor control section 11) Thus, once mode flag MSCF is set to "1", the I/O processings 53 and 58 are executed unless the subject mode is the external device control data mode MSC8 (see FIGS. 4 and 10). In the case of input mode (as viewed from the coinmech control section 10), the output mode flag FR of the coinmech control section 10 and the data delivery mode flag of the vendor control section 11 are set or reset respectively as follows: FR="0" Fr="1" In the I/O processing 58 in the vendor control section 11 shown in FIG. 12, block 102 first examines whether or not the CIv port input signal is "1". When the first (order 1) 4-bit data is to be delivered, block 102 is judged NO because the CO port output signal on the coin mechanism side has been set to "0" by the processing of block 92 in FIG. 5. Since the Fa flag is "0", block 103 is also judged NO so that the step proceeds through YES of block 104 "Fr=1" up to block 105 which examines whether or not the order register Ri is "0". Since, as mentioned above, the Ri register is initially loaded with a predetermined signal delivery order number, "Ri=0" is judged NO and the processing of block 106 is carried out to read 4-bit data from a predetermined address of the MRv memory corresponding to the contents of the Ri register and load the RPO register therewith. It is noted that the arrangement of addresses in the MRv memory (and the MR memory as well) is contrary to the data delivery order shown in Tables 1 to 9. For instance, 4-bit data with delivery order numbers 1, 2, 3, 4, 5 and 6 are stored respectively in addresses 6, 5, 4, 3, 2 and 1 designated by the Ri register. Therefore, based on the contents of the Ri register where the order numbers corresponding to the maximum value are stored, the 4-bit data to be first delivered (order 1) is read from the MRv memory and stored in the RPO register. The contents of the RPO register are produced from the OUv port and applied to the IN port on the coin mechanism side. Block 107 examines the data block sending and receiving processing finish flag Fc. Since the Fc flag is still "0", the individual data sending and receiving flag Fa is set to "1" in block 108 and then the COv port output signal is set to "1" in block 99. These processings correspond to those of order numbers 1, 2 in Table 10. Once the delivery data is set in the OUv port, the step through NO of block 102, YES of block 103, and block 99 is repeated until "1" is supplied to the CIv port. Meantime in the I/O processing 53 in the coinmech control section 10 shown in FIG. 7, the step proceeds through NO of block 109 or "CI=1", NO of block 110 or "FR=1", and NO of block 111 or FA=1, to block 112 where the CO port is set to "0" until the COv port supplies "1" to the CI port, that is, while the CI port input is "0". When, as described above, the first 4-bit data is delivered from the vendor side and the COv port output is set to "1" (block 99 in FIG. 12), block 109 or CI=1 is judged YES so that the data block sending and receiving processing finish flag FB is examined in block 113. Since FB=0 as yet, the step proceeds to block 114 to examine FR=1. Since the data is as yet in the input mode, block 114 is judged NO so that the 4-bit data supplied from the OUv port of the vendor control section 11 to the IN port of the coinmech control section 10 is stored in the RIN register (block 115), then set in the ROU register, supplied to the OU port and returned to the vendor control section side (block 116). Thereafter, the individual data sending and receiving flag FA is set to "1" (block 117) and the CO port is set to "1". These processings correspond to those of order numbers 3, 4 shown in Table 10 previously given. In FIG. 12, as "1" has been set in the CO port, block 102 or CIv=1 is judged YES and next block 118 Fr=1 is judged YES because the data is now in the delivery mode and the Fa flag is examined in block 119. As mentioned above, since the Fa flag has been set to "1" in block 108, Fa=1 is judged YES so that the data that was returned to the INv port is set in the RPI register to compare the contents of RPI and the contents of the delivered data stored in the RPO register (block 120). If these do not coincide, the processings of blocks 102 to 120 are repeated until they coincide. When the coincidence between the two data is confirmed, the step proceeds to block 121 to judge whether or not the contents of the Ri register are "0". Unless delivery of all data in one mode is completed, Ri=0 is judged NO and a decimal 1 is subtracted from the contents of the Ri register in block 122 and the remainder becomes the fresh contents of the Ri register. In next block 123, the Fb flag and Fa flag are reset to "0". The COv port output signal is then set to "0" in block 124. These processings correspond to those of order numbers 5 and 6 in Table 10. In FIG. 7, because the COv port was set to "0", the CI port input, to which this COv port output is supplied, goes to "0". Therefore, the step proceeds through NO of block 109, NO of block 110 and YES of block 111 (because FA was set to "1" in block 117) to block 125, which examines whether or not the contents of the register Ri are "0". Unless receiving of all data in one mode is completed, Ri=0 is judged NO so that in block 126 the contents of the RIN register are stored in a predetermined address of the data table memory MR corresponding to the contents of the Ri register. Thereafter 1 is subtracted from the order number of the Ri register (block 127), the FA flag is reset to "0" and the CO port output is set to "0". These processings correspond to those of order numbers 7 and 8 in Table 10. In FIG. 12, when the CIv port input signal (i.e., the CO port output signal) has gone to "0", the step proceeds from NO of block 102 to block 103 and further through blocks 104, 105 up to block 106, where the signal to be next delivered is read from a predetermined address of the MRv memory corresponding to the contents of the Ri register (which are the remainder obtained by subtracting a 1 from the preceding contents of Ri in block 122) and set in the RPO register. Thus the order of the delivered signal advances and the same processings as above (corresponding to those of order numbers 1 to 8 in Table 10) are repeated. When delivery of all the signals in one mode is completed, the contents of the Ri register go to "0" so that block 105 in the next cycle is judged YES. Then the end code ENDC (all 0s) is set in the RPO register by the processing of block 128 and delivered from the OUv port. The COv port is then set to "1" (block 99). In FIG. 7, since the signal supplied from the COv port to the CI port has gone to "1", the step proceeds through YES of block 109, NO of block 113 and NO of block 114. Thereafter the end code ENDC is set in the RIN register and returned to the vendor control section 11 through the OU port (blocks 115, 116). Then the CO port is set to "1". In FIG. 12, since the signal supplied from the CO port to the CIv port has gone to "1", the end code ENDC returned from said OU port to the INv port is stored in the RPI register and the contents of RPI and RPO are compared (block 120). The sending and receiving of the end code ENDC is thus confirmed, whereon the step proceeds through YES of block 121 to block 129 to confirm that the contents of the RPI register are the end code ENDC. Then the data block sending and receiving processing finish flag Fc is set to "1" in block 130. Thereafter, Fb, Fa are reset to "0" and the COv port is set to "0". In the meantime, NO of block 129 indicates abnormality so that the STOK flag is reset to "0" (the Fa flag is also reset at the same time) to enable the signal start processing 59 to be effected. In FIG. 7, upon detecting that the CI port input has gone to "0", the step proceeds through NOs of blocks 109 and 110 and YESes of blocks 111 and 125 to block 131 which checks that the contents of the RIN register are the end code ENDC. If block 131 is judged YES, all the signals for one mode that have been stored in the data pool memory MR and transferred by block to a predetermined location in RAM 14 (block 132) and stored therein. Then the data block sending and receiving processing finish flag FB is set to "1" (block 133), the FA flag is reset and the CO port output is set to "0". If block 131 is judged NO, abnormality is indicated so that the memory of the MR memory is all cleared (block 134) and the STOK flag and FA flag are reset respectively to leave this I/O processing for the following signal start processing 54. In FIG. 12, because the signal supplied from the CO port to the CI port has gone to "0", block 102 is judged NO and the step proceeds through NO of block 103, YESes of blocks 104 and 105 and block 128 up to block 107 which judges whether or not Fc=1. Since Fc=1 was obtained in block 130 previously, block 107 is judged YES and the step proceeds to block 135 which clears the data pool memory MRv. Further the mode select code register RMSC, data delivery mode flag Fr, mode flag MSCF, flags Fa, Fc are reset to "0" and COv port is set to "1", respectively thereby leaving the I/O processing 58. In FIG. 7, because the signal supplied to the CI port from the COv port has gone to "1", the step proceeds from YES of block 109 to block 113 to examine the FB flag. Since the FB flag was set to "1" in block 133 previously, block 113 is judged YES so that the MR memory is cleared in block 136. Further the RMSC register and the respective flags FR, MS, CF and FB are reset and the CO port is set to "1" to leave the I/O processing 53. (3) Data Sending and Receiving in the Output Mode (or data receiving mode in the vendor control section 11) In the case of the output mode, the output mode flag FR of the coinmech control section 10 and the data delivery mode flag Fr of the vendor control section 11 are set as follows: FR=1 Fr=0 The MSCi processing 56 (FIG. 11) and the MSC judgement processing 51 (FIG. 5), before taking said modes, have been stopped with the respective control signal output ports CO, COv set to "0" (processings of blocks 82 and 92). Therefore in the first cycle of the I/O processing 53 on the coin mechanism side, block 109 in FIG. 7 is judged NO, block 110 (FR=1) YES and block 137 (FA=0) NO so that the CO port is set to "0" in block 112 and this processing is repeated. In the first cycle of the I/O processing 58 on the vendor control section side, block 102 in FIG. 12 is judged NO, block 103 (Fa=0) NO and block 104 (Fr=0) NO to proceed to block 138. Since the Fb flag has been set to "1" in block 81 (FIG. 11) in MSCi processing 56, block 138 or Fb=1 is judged YES and the step proceeds through NO of block 107 to set the Fa flag and the COv port to "1". Thus signal delivery is now demanded against the coinmech control section 10. In FIG. 7, since CI=1, the step proceeds through YES of block 109, NO of block 113, and YES of block 114 (because FR=1) to block 139 which judges whether or not FA=1. As data delivery has not yet started, the FA flag is "0", thus proceeding to block 140. Since initially a maximum order number is stored in the order register Ri, Ri=0 is judged NO so that 4-bit data (order 1 data first) is read from the address of the MR memory corresponding to the contents of the Ri register, set in the ROU register (block 141) and produced from the OU port. Then FA and the CO port are successively set to "1". The above processings correspond to those of order numbers 1 and 2 shown in previous Table 11. In FIG. 12, since CIv=1, the step proceeds through YES of block 102, NO of block 118 (because Fr=0) to "INv port check" and the 4-bit data signal supplied from the OU port on the coin mechanism side to the INv port is stored in the RPI register (block 142). Then the contents of RPI are also set in RPO and then the contents of RPO are set in the OUv port (block 143). Thus, 4-bit data received from the coin mechanism side is returned for confirmation. Then the Fb and Fa flags are reset to "0" and the COv port is set to "0". Those processings correspond to those of order numbers 3 and 4 in Table 11. In FIG. 7, since CI=0, the step proceeds through NO of block 109, YES of block 110 and YES of block 137 (because FA has already been set) to reach "IN port check", loading the RIN register with the data that has been returned to the IN port. This processing is repeated until block 144, which compares the delivered data (contents of ROU) and the returned data (contents of RIN), detects coincidence. Upon detection of coincidence, if Ri=0 is judged NO in block 148, "1" is subtracted from the order number of Ri to designate the subsequent delivery order. Then FA and the CO port are set to "0" successively. The above processings correspond to those of order numbers 5 and 6 in Table 11. In FIG. 12, since CIv=0, the step proceeds through NO of block 102, NO of block 103, NO of block 104 and NO of block 138 to reach block 145. If Ri=0 is judged NO in this block 145, the step proceeds to block 146 where the data that has been set in the RPI register is stored in the address of the MRv memory corresponding to the contents of the Ri register. Then "1" is subtracted from the order number of Ri to designate the order of the number to be delivered next. Thereafter Fa and the COv port are set to "1" successively. The above processings correspond to those of order numbers 7 and 8 in Table 11. Thus by setting the COv port to "1" when sending and receiving processing of one data has ended, delivery of next data is demanded against the coinmech control section 10 to repeat the same processings (those corresponding to order numbers 1 to 8 in Table 11) as described above. When sending and receiving of all data in one mode has finished, block 140 (Ri=0) in FIG. 7 is judged YES so that the end code ENDC is set in the ROU register (block 147) and produced from the OU port. Then the CO port is set to "1". In FIG. 12, the step proceeds through YES of block 102, NO of block 118 so that the end code ENDC supplied to the INv port is set in the RPI register and then produced from the OUv port through the RPO register. Then the COv port is set to "0". In FIG. 7, the step proceeds through NO of block 109, YES of block 110, and YES of block 137 to reach block 144 to confirm sending and receiving of the end code ENDC (RIN=ROU). The step further proceeds through YES of block 148 to block 149 to check whether or not the data returned to the RIN register is certainly the end code ENDC. If YES, the FB flag is set to "1" and the CO port to "0". If NO, abnormality is indicated so that the MR memory is cleared and the STOK flag is reset to "0". In FIG. 12, since CIv=0, the step proceeds through NO of block 102 and further through blocks 103, 104, 138 and 145 to block 150 to check whether or not the contents of the RPI register are the end code ENDC. If YES, all the signals for one mode pooled in the MRv memory are transferred by block and stored in a predetermined location of RAM 19 and the flag Fc is set to "1". Fc=1 is judged YES in next block 107 and the MRv memory, RMSC register, flags Fr, MSCF, Fa and Fc are respectively reset to "0" and the COv port is set to "1". If block 150 is judged NO, abnormality is indicated so that the contents that have been pooled in the MRv memory are cleared and the STOK flag is reset to "0". In FIG. 7, since CI=1 and FB=1, the step proceeds through blocks 109, 113 to block 136, resetting the MR memory, RMSC register and the flags FR, MSCF, and FB. The CO port is then set to "1". Thus sending and receiving of all the signals for one mode is completed to leave the I/O processings 53, 58 (as MSCF was set to "0"). (4) External Device Processing Where, for instance, an external printer is connected to the I/O port section 22 of the vendor control section 11 to print out sales data and the like stored in the peripheral memory 21, the external device control data mode (MSC8) is selected. In this case, the coinmech control section 10 executes the external device processing 52 shown in FIG. 6, virtually disregarding the signal supplied to the I/O port 16 from the vendor control section 11 side. If, for instance, the processing by an external device is completed within 3 seconds (or any other predetermined time period), the coinmech control section 10 waits 3 seconds without performing the I/O port processing operation. That is, a 3-second timer 3STM is started to provide a 3-second standby period during which the step through YES of block 151 and NO of block 152 is repeated. When the 3-second standby period has elapsed, block 152 is judged YES so that the STOK flag is reset to "0", the timer 3STM and the register RMCS are successively reset and the CO port is set to "0", thus leaving the processing 52. The reason for setting STOK and the CO port to "0" is to have the signal start processings 54 and 59 effected to ensure that the I/O port input and output of both control sections 10, 11 keep pace with each other and thereafter proceed to the normal processings 51, 53, 56 and 58. (5) C Port Check Processing Almost the same C port check processings 55 and 60 are effected on the coinmech control section side and the vendor control section side. Therefore, description will now be made below referring to FIG. 9, omitting description of FIG. 14. This C port check processing 55 starts with the checking as to whether or not the CI port input signal sustained "0" longer than a predetermined time period (e.g., 0.3 sec), followed by proper processings. If the CI port input is "1" (YES of block 153), the 0.3-second timer (0.3 TM) is reset (block 154) to end the processing 55. In case the CI port input is "0", whether or not the 0.3 TM has been started is checked and if NO, the timer is started (block 155). While the CI port input sustains "0", a check is made as to whether or not the interval timed by the 0.3 TM timer has elapsed. While the CI port input sustains "0", the timer is not reset. When the 0.3-second timed interval has elapsed, block 156 is judged YES. Normally CI=0 does not last long before the 0.3 TM timer is reset. In the case of abnormality, the COv port on the other side (or the CO port for the vendor control section 11) sustains "0" so that "0" is continuously supplied to the CI port input (CIv port input) until block 156 is judged YES. Block 157 examines whether or not the flag FD has been set to "1". Since initially FD=0, block 157 is judged NO so that the timer flag TMF is set to "1", the flags STOK and, MSCF are reset, and the ROU register is set to all 1s (indicating absence of signal), which is produced from the OU port. Then the MR memory is cleared, the RMSC register reset and the CO port is set to "0". (6) Pace Keeping Processing Pace keeping of both control sections 10 and 11 at the time the electric power source is turned on is carried out as follows: The coinmech control section 10 effects the signal start processing 54 of FIGS. 8(a) and 8(b) (since STOK is initially "0"). Because the timer flag TMF is not yet set, block 158 or TMF=1 is judged NO so that "all 1" is set in the ROU register and the OU port produces all 1s or "1111" meaning absence of signal. Then whether or not the FD flag is "1" is examined (block 159) and if NO, the Ri register and the flag FA are successively reset and the CO port is set to "0". The vendor control section 11 likewise effects the signal start processing 59 shown in FIG. 13 whereby, passing through NO of block 160 "TMF=1", the OUv port output signal is set to "1111" and the COv port to "0". In the C port check processing 55 shown in FIG. 9, the COv port output on the other side or the CI port input is checked and, upon detecting that CI=0 has lasted longer than 0.3 seconds, the processing for NO of block 157 is carried out. Then, as before, TMF is set to "1" and the CO port to "0". In the vender control section 11 also, a similar processing is effected in the C port check processing 66 in FIG. 14. In the followihg processing shown in FIG. 13, block 160 or TMF=1 is judged YES. The Fd flag is still "0" so that the 0.3 TM timer is reset, the value 2 is set in the Ri register and the flags Fa, Fd are set to "1" (block 161). The CIv port input is still "0" so that block 162 is judged NO. Upon confirming that the Fa flag is "1" and the contents of the Ri register are 2, the value 5 (code "0101") is set in the RPO register (block 163) and produced from the OUv port. Then the flag Fa is reset and the COv port output is set to "1". In the next cycle, whether or not CIv=1 is checked in block 162. If NO, Fa=1 is judged NO to come to the end of the processing. This is repeated until the CIv port goes to "1". Referring to FIG. 8, TMF=1 and block 158 is judged YES. Since the flag FD is not yet set to "1", the 0.3 TM timer is reset, the value 2 is set in the Ri register and the flag FD is set to "1". Until the CI port goes to "1", NOs of blocks 164 and 165 are repeated and the CO port is kept "0". As before, when the COv port goes to "1", the CI port input goes to "1" and block 164 is judged YES. Upon confirming that the Ri register is not "0" in block 166, the value 5 supplied to the IN port is set in the RIN register (block 167), and then in the OU port so as to be returned to the vendor control section side. Then the FA flag and the CO port are successively set to "1". In FIG. 13, "1" from the CO port causes block 162, CIv=1, to be judged YES and Fa=1 is examined (block 168). Since Fa was reset when the value 5 was delivered, block 168 is judged NO and the data returned to the INv port is set in the RPI register to compare RPO and RPI. If RPO=RPI is correct, the Fa flag is set to "1" and 1 is subtracted from the contents of the Ri register (presently "2") and the COv port is set to "0". In FIG. 8, due to the signal "0" from the COv port (which indicates that the value 5 was properly sent and received), block 164, CI=1 is judged NO. Upon confirming Ri=2, whether or not the signal taken in the RIN register is 5 is checked. If YES, 1 is subtracted from the contents of the Ri register (presently 2) to obtain the contents "1" (block 169). Then the FA flag is reset and the CO port is set to "0". Delivery of the next signal is now demanded. In FIG. 13, by "0" from the CO port, block 162, CIv=1, is judged NO and so, upon confirming that the contents of the Ri register are not "2" but "1" (YES of block 170), the value 10 (code "1010") is set in the RPO register and produced from the OUv port. Then the Fa flag is set to "0" and the COv port to "1". In FIG. 8, the processing proceeds through YES of block 164 (CI=1), NO of block 166 and, as before, the value 10 supplied to the IN port is stored in RIN and ROU and returned from the OU port to the INv port. Then FA and the CO port are successively set to "1". In FIG. 13, the processing proceeds through YES of block 162 (CIv=1), NO of block 168 and, as before, the produced data and the returned data are compared. If they coincide, Fa is set to "1" and 1 is subtracted from the contents of Ri (presently 1) to obtain the contents "0". The COv port is then set to "0". In FIG. 13, the processing proceeds through NO of block 162 (CIv=0) to block 170 to confirm that the contents of Ri are neither "2" nor "1" but "0". Then RMSC, MRv, MSCF are reset. Further the STOK flag is set to "1" to complete the signal start processing 59. The OUv port output signal is set to all 1s, the flags Fd, Fa are reset to "0" and the COv port is set to "1". In FIG. 8, by "1" of the COv port output, block 164 is judged YES. Block 166 is judged YES since the contents of the Ri register are "0", so that the 3-second timer 3STM is reset, RMSC is reset, and the OU port output signal is set to all 12 s. Then the STOK flag is set to "1" to indicate the end of the signal start processing 54. Thereafter the FD flag is reset to "0" and the CO port is set to "1". Thus, the signal start processings 54 and 59 are completed in both control sections in synchronism. As a result, in the I/O port input and output, the 4-bit signal from OU to INv and the 4-bit signal from OUv to IN are set to all 1s respectively while the control signal from CO to CIv and the control signal from COv to CI are set to "1" respectively. These signals are thus set in a standby state. The program leaves the signal start processings 54 and 59 as the STOK flag is set to "1". The pace keeping of both control sections 10, 11 at the detection of abnormality is carried out almost in the same manner as above. When abnormality occurred on the coinmech control section side (e.g., NO of block 87 in FIG. 5, NOs of blocks 131, 149 in FIG. 7), the STOK flag is reset to "0" so that the signal start processing 54 in FIG. 8 may be executed. Therefore, passing through NO of block 158, the OU port output is set to all 1s and the CO port output is kept "0". Then the C port check processing 60 on the vendor control section side (FIG. 14) is effected to detect that the CIv port input sustained "0" longer than 0.3 seconds, set the TMF flag, reset the STOK flag and set the COv port to "0". In the next cycle, the signal start processing 59 in FIG. 13 is carried out wherein the step proceeds through YES of block 160, NO of Fd=1 to set the Fd flag to "1" in block 161. Thus in the C port check processing 60 (FIG. 14) in that cycle, Fd=1 is judged YES and the TMF flag is reset to "0" (block 171). In the next cycle, block 160 in FIG. 13 is judged NO so that the OUv port output is set to all 1s and the COv port is set to "0". Thus the OU port output and the OUv port output are now both all 1s and the CO port output and the COv port output are both "0". Therefore, in the respective C port check processings, 54 and 59 abnormality of the CI port input and the CIv port input (i.e., being "0" longer than 0.3 seconds) are mutually detected and the respective TMF flags are set to "1". Based on this, the processings (signal start processings 54 and 59) are effected to send and receive the values 5 and 10 one after the other for comparison in the same manner as when the electric power source is turned on. Finally all the I/O port signals are set to "1" as before and set in the standby state. The same processings as above are carried out where abnormality occurred on the vendor control section side (e.g., NOs of blocks 129 and 150 in FIG. 12). In this case, however, the coinmech control section 10 also generates "0" continuously from the CO port when the COv port of the vendor control section 11 has been continuously "0". As mentioned above, the start processings are effected such that the I/O port signal is set in a standby state only when the proper sending and receiving of the values 5 and 10 was confirmed. This is useful for I/O port wiring short-circuiting detection as well as pace keeping of the I/O port signals of both control sections 10, 11. Specifically, because the value 5 is coded "0101" and 10 "1010", confirmation of proper sending and receiving of both codes of the values 5 and 10 means absence of short-circuiting in the wiring. The invention may be applied to automatic machines for providing (vending) services such as games as well as to vending machines for vending articles. Therefore the goods herein include services as well as articles.
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