Electronic audio communication system with user controlled message address

Abstract

An advanced electronic telecommunications system is provided for the deposit, storage and delivery of audio messages to both user and non-users with limited access provided to the non-user under the control of the user. A Voice Message System (10) interconnects multiple private exchanges (12) of a subscriber with a central telephone office (22). Individual subscriber users may access the Voice Message System (10) through ON NET telephones (18) or OFF NET telephones (24). Selected non-users may be allowed access through the OFF NET telephones (24), the scope of the access of the selected non-users being determined by a subscriber user. The Voice Message System (10) includes an administrative subsystem (60), call processor subsystem (62) and a data storage subsystem (64). The Voice Message System (10) enables the user to deposit a message in data storage subsystem (64) for automatic delivery to other addresses connected to the system. The user is also able to deposit a message in a receive-only portion of the data subsystem (60) for access by a selected non-user. The Voice Message System (10) also enables a user to access the system to determine if any messages have been in data storage subsystem (64) for him. Prerecorded instructional messages are deposited in the data storage subsystem (64) for instructing a user or a selected non-user on their progress in using the system.

Claims

What we claim is:

1. An electronic communications message system for receiving, storing and forwarding analog information from users' and limited users' telephone facilities, comprising:

electronic digital signal processing means for controlling operation of the message system;

digital memory means controlled by said electronic digital signal processing means for storing digital representations of the analog information;

the analog information comprising a first portion for routing to telephone facilities of selected recipients and a second portion for defining route data;

user access means for enabling a user to access the message system through analog signals transmitted from the user's telephone facility;

limited user access means for enabling limited access to the message system by a selected limited user via the limited user's telephone facility, the scope of said limited user's access controlled by the user through signals input through the user's telephone facility;

means for storing in said memory means digital representations of said first portion of the analog information received from the user's telephone facility;

means for storing in said memory means digital representations of the second portion of the analog information received from the user's telephone facility;

means for accessing said stored digital representations of the first portion of the analog information;

means for reproducing said first portion of the analog information in analog format from the stored digital representations; and

means for sequentially transmitting reproduced analog information to the telephone facilities of said selected recipients.

2. The message system for receiving, storing and forwarding analog information of claim 1 wherein said limited user access means comprises:

second digital memory means controlled by said electronic digital signal processing means for storing digital representations of receive-only analog information;

said receive-only analog information supplied by only one user and the access thereto controlled by said one user;

user controlled means for enabling access to the message system by said selected limited user and controlled by said one user;

means for storing in said second memory means digital representations of said receive-only analog information;

means operable only by said selected limited user for accessing said stored digital representations of said receive-only analog information;

means for reproducing said receive-only analog information in analog format in response to analog signals input through said selected limited user's telephone facility; and

means for transmitting said receive-only analog information to said selected limited user.

3. The message system for receiving, storing and forwarding analog information of claim 2 wherein said user controlled means includes forwarding means for forwarding a call to the user's telephone facility to a telephone station that automatically accesses the message system, the scope of the access controlled by said one user.

4. The message system for receiving, storing and forwarding analog information of claim 2 further comprising:

user controlled means for outputting a prerecorded reply analog prompt to said selected limited user after said receive-only analog information is transmitted to said selected limited user; and

means for storing in said second digital memory means digital representations of responsive analog information supplied by said selected limited user in response to said pre-recorded reply prompt, said stored digital representations of said responsive analog information accessible only by said one user.

5. The message system for receiving, storing and forwarding analog information of claim 4 wherein said means for storing in said second digital memory means includes means for storing digital representations of receive-only analog information which comprises audio messages.

6. The message system for receiving, forwarding and storing analog information of claim 4 wherein said means for storing in said second digital memory means digital representations of responsive analog information includes means for storing digital representations of responsive analog information which comprises audio messages.

7. The message system for receiving, storing and forwarding analog information of claim 3 and further comprising a timer for timing the beginning of said analog information transmitted from a user's telephone facility, said timer automatically disconnecting the message system from the user's telephone facility if no analog information is supplied within a predetermined interval.

8. The message system for forwarding, storing and receiving analog information of claim 1 wherein said limited user access means comprises:

a plurality of second digital memory means controlled by said electronic digital signal processing means for storing digital representations of receive-only analog information input by only one user, each of said second memory means associated with a selected limited user and accessible by said one user;

user controlled means controlled by said one user for enabling limited access to the message system from a selected limited user's telephone facility;

means for storing in each of said second memory means digital representations of said receive-only analog information;

means for accessing stored digital representations of said receive-only analog information in the associated second memory means by said selected limited user;

means for reproducing said receive-only analog information stored in said second memory means in analog format;

means for transmitting reproduced analog information from said second memory means to said selected limited user in response to analog signals from said limited user's telephone facility; and

means for storing in said second digital memory means analog information received from said selected limited user's telephone facility, said analog information accessible by only said one user.

9. The message system for receiving, storing and forwarding analog information of claim 8 further comprising inhibiting means for said one user to inhibit said selected limited user's access of the message system.

10. The message system for receiving, storing and forwarding analog information of claim 8 further comprising:

user controlled means for outputting a pre-recorded analog prompt to said selected limited user after said receive-only analog information is transmitted to said selected limited user; and

means for storing in said second digital memory means digital representations of responsive analog information supplied by said selected limited user in response to said pre-recorded prompt, said stored digital representations of said responsive analog information accessible only by said one user.

11. The message system for receiving, storing and forwarding analog information of claim 8 wherein said means for storing digital respresentations includes means for storing digital representations of receive-only analog information comprised of audio messages and wherein said means for storing analog information includes means for storing analog information comprised of audio messages.

12. The message system for receiving, storing and forwarding analog information of claim 7 further comprising:

limited user controlled means for storing in said second digital memory means responsive analog information in response to analog signals from said selected limited user's telephone facility; and

means to associate said responsive analog information with route data of said one user wherein said responsive analog information is accessible only by said one user.

13. An electronic communications message system for receiving, storing and forwarding analog information from a user's telephone facility, comprising:

an electronic digital signal processing means for controlling operation of the message system;

first digital memory means controlled by said electronic digital signal processing means for storing digital representations of the analog information;

the analog information comprising a first portion for routing to selected recipients' telephone facilities and a second portion for defining route data;

user access means for enabling the user to access the message system through analog signals transmitted from the user's telephone facility;

second digital memory means controlled by said electronic digital signal processing means for storing digital representations of receive only analog information;

said receive only analog information supplied by only one user and the access thereto controlled by said one user;

user controlled means for enabling access to the message system by a selected limited access user and controlled by said one user;

means for storing in said second memory means digital representations of said receive-only analog information;

means operable by said selected limited user for accessing said stored digital representations of said receive-only analog information;

means for reproducing said receive-only analog information in analog format in response to analog signals input through said selected limited access user's telephone facility;

means for transmitting said receive-only analog information to said selected limited user;

means for storing in said first digital memory means digital representations of said first portion of the analog information received from the user's telephone facility;

means for storing in said first digital memory means representations of the second portion of the analog information received from the user's telephone facility;

means for accessing said stored digital representations of the first portion of the analog information;

means for reproducing said first portion of the analog information in analog format from the stored digital representations; and

means for transmitting the reproduced analog information to the telephone facilities of said selected recipients.

14. An electronic communications message system for being coupled to a private branch exchange or central office for receiving, storing and forwarding analog information from a user's telephone facility, comprising;

means for transmitting analog signals from an originating user's telephone facility to a storage location;

means for storing digital representations of the analog signals received from said originating user's telephone facility;

means for enabling limited access to said stored digital representations of said originating user's analog signals by a non-originating user, the scope of said non-originating user's limited access defined by said originating user through said originating user's telephone facility, said originating user having full access to said stored digital representations of said originating user's analog signals with the limited access of said non-originating user being less than full access, said non-originating user unable to limit access to said digital representations of the originating user's analog signals;

means for converting the stored digital representations into analog information; and

means for transmitting said analog information to said originating user and said non-originating user.

15. An electronic communications message system for being coupled to a private branch exchange or central office for receiving, storing and forwarding analog information from a user's telephone facility, comprising:

electronic digital signal processing means for controlling operation of the message system;

digital memory means controlled by said electronic digital signal processing means for storing digital representations of the analog information;

the analog information including a first portion for routing to selected recipients' telephone facilities and a second portion for defining route data;

means for enabling access to the message system through analog signals transmitted from a user's telephone facility;

means for storing in said memory means digital representations of said first portion of the analog information received from the user's telephone facility;

means for storing in said memory means digital representations of said second portion of the analog information received from the user's telephone facility;

means for storing selected analog information from an originating user for limited access by a plurality of selected non-originating users, the scope of said non-originating users' limited access controlled by said originating user through signals input through said originating user's telephone facility;

means for accessing said digital representations of the first portion of the analog information;

means for reproducing the first portion of the analog information in analog format from the stored digital representations; and

means for transmitting the reproduced analog information to said selected telephone facilities.

16. The message system for receiving, storing and forwarding analog information of claim 15 wherein said means for storing selected information comprises:

second digital memory means controlled by said electronic digital signal processing means for storing digital representations of said selected information;

said second digital memory means associated with only said originating user and accessible by a plurality of selected non-originating users through telephone facilities, the scope of said access under control of said originating user;

means for storing in said second memory means digital representations of said selected information by said originating user;

means operable only by said selected non-originating users for accessing said stored digital representations of said selected information; and

means for reproducing said selected information in analog format in response to analog signals input through said selected non-originating users' telephone facilities.

17. The message system for receiving, storing and forwarding, analog information of claim 16 wherein said means operable only by said selected non-originating users for accessing said stored digital representations of said selected information further comprises means for said non-originating users to store digital representations of responsive analog information in said second digital memory means for routing to said originating user, said means activated by said originating user through analog signals transmitted through said originating user's telephone facility.

18. The message system for receiving, storing and forwarding, analog information of claim 17 wherein said means for said non-originating users to store digital representations of responsive analog information comprises:

means for outputting a pre-recorded analog prompt to said non-originating users after reproduced selected information is transmitted to said non-originating uses;

means for storing in said second digital memory means digital representations of said responsive analog information supplied by said non-originating users in response to said pre-recorded prompt; and

means for routing said responsive analog information to said originating user.

19. The message system for receiving, storing and forwarding analog information of claim 16 further comprising means for deleting portions of said selected analog information stored in said second digital memory means by said originating user.

20. The message system for receiving, storing and forwarding analog information of claim 16 further comprising means for accessing only selected portions of selected analog information by said non-originating users in response to analog signals transmitted through said non-originating users' telephone facilities.

21. An electronic communications message system for being coupled to a private branch exchange or central office for receiving, storing and forwarding analog information from a user's telephone facility, comprising:

an electronic digital signal processing means for controlling operation of the message system;

first digital memory means controlled by said electronic digital signal processing means for storing digital representations of the analog information;

the analog information comprising a first portion for routing to selected recipients' telephone facilities and a second portion for defining route data;

means for enabling access to the message system through analog signals transmitted from the user's telephone facility;

means for storing in said memory means digital representations of said first and second portions of the analog information received from the user's telephone facility;

second digital memory means controlled by said electronic digital signal processing means for storing digital representations of selected analog information from an originating user;

said second digital memory means associated with only said originating user and access thereto controlled by said originating user;

means for storing in said second memory means digital representations of said selected analog information;

means operable only by selected non-originating users for accessing said stored digital representations of said selected analog information through telephone facilities;

means for reproducing said selected information in analog format in response to analog signals input through said selected non-originating users' telephone facilities;

means for transmitting said selected analog information to said selected non-originating users;

means for accessing the digital representations of said first portion of the analog information;

means for reproducing said first portion of the analog information in analog format from the stored digital representations; and

means for transmitting reproduced analog information to said selected recipients' telephone facilities.

22. The message system for receiving, storing and forwarding analog information of claim 21 further comprising:

means for outputting a pre-recorded analog prompt to said non-originating users after reproduced selected analog information is transmitted to said non-originating users;

means for storing in said second digital memory means digital representations of responsive analog information supplied by said non-originating users in response to said pre-recorded prompt;

means operable by said originating user for accessing said stored digital representations of said responsive analog information through said originating user's telephone facility;

means for reproducing said accessed digital representations of said responsive analog information in analog format; and

means for routing said reproduced responsive analog information to said originating user.

23. An electronic communications message system for receiving, storing and forwarding analog information from a user's telephone facility, comprising:

electronic digital signal processing means for controlling operation of the message system;

first digital memory means controlled by said electronic digital signal processing means for storing digital representations of the analog information;

the analog information comprising a first portion for routing to selected recipients' telephone facilities and a second portion for defining route data;

user access means for enabling a user to access the message system through analog signals transmitted from the user's telephone facility;

a plurality of second digital memory means controlled by said electronic digital signal processing means;

means for storing in each of said second memory means digital representations of receive-only analog information input by only one user, each of said second memory means associated with a selected limited user and accessible only by said one user and said selected limited user;

user-controlled means controlled by said one user for enabling said selected limited user to access the message system from a telephone facility;

means for accessing stored digital representations of said receive-only analog information by said selected limited user;

means for reproducing receive-only analog information stored in the second memory means associated with said selected limited user in analog format;

means for transmitting reproduced receive-only analog information in said second memory means to said selected limited user in response to analog signals from said limited user's telephone facility;

means for storing in said first digital memory means analog information received from said selected limited user's telephone facility, said analog information accessible only by said one user;

means for accessing in said first memory means said stored digital representations of the first portion of the analog information;

means for reproducing said first portion of the analog information in analog format from the stored digital representations; and

means for transmitting the reproduced analog information to the telephone facilities of said selected recipients.

24. An electronic communications message system for receiving, storing and forwarding analog information from a user's and limited user's telephone facilities, comprising:

electronic digital signal processing means for controlling operation of the message system;

digital memory means controlled by said electronic digital signal processing means for storing digital representations of the analog information;

the analog information comprising audio messages for routing to selected recipients' telephone facilities and route data;

user access means for enabling a user to access the message system through signals transmitted from the user's telephone facility;

means for enabling an originating user to input a template having a plurality of audio messages arranged in a queue format and route data associated with said template;

limited user access means for enabling limited access to the message system by a selected limited user via the limited user's telephone facility, the scope of said limited user's limited access controlled by the user and restricted to receiving audio messages contained in said template and to responding with responsive analog information for routing only to said originating user;

means for storing in said memory means digital representations of said audio messages received from the user's telephone facility;

means for storing in said memory means digital representations of said route data received from the user's telephone facility;

means for accessing stored digital representations of said audio messages;

means for reproducing the audio messages in analog format from the stored digital representations; and

means for transmitting reproduced analog information to the telephone facilities of said selected recipients.

25. The message system for receiving, storing and forwarding analog information of claim 24 wherein said means for enabling an originating user to input a template includes means for enabling the user to input a template having a plurality of audio messages which comprises a selected string of analog prompts.

26. The message system for receiving, storing and forwarding analog information of claim 24 wherein said limited user access means comprises:

means for allowing the limited user to access the digital representations of only the audio messages in said template;

means for transmitting each of the audio messages in said template;

means for pausing between transmission of individual audio messages in said template to allow the limited user accessing the digital representations to provide responsive analog information; and

means for storing digital representations of said responsive analog information in said digital memory means for transmission only to said originating user.

27. The message system for forwarding, storing and receiving analog information of claim 26 wherein said means for storing digital representations of responsive analog information includes means for storing digital respresentations of responsive analog information which is comprised of an audio message.

28. The message system for receiving, storing and forwarding analog information of claim 26 wherein said means for storing digital representations of responsive analog information includes means for storing digital respresentations of responsive analog information which is comprised of tone signals.

29. The message system for receiving, storing and forwarding analog information of claim 26 further comprising means for allowing the limited user to control the sequence of transmission of the audio messages in said template.

30. The message system for receiving, storing and forwarding analog information of claim 26 further comprising means for conditioning the sequence of transmission of the plurality of audio messages in said template by the information contained in said responsive analog informaion from the limited user.

31. An electronic communications message system for receiving, storing and forwarding analog information from users' and limited users' telephone facilities, comprising:

electronic digital signal processing means for controlling operation of the message system;

digital memory means controlled by said electronic digital signal processing means for storing digital representations of the analog information;

the analog information comprising, audio messages for routing to selected recipients' telephone facilities and associated route data;

user access means for enabling a user to access the message system through signals transmitted from the user's telephone facility;

means for enabling an originating user to input a template having a string of audio messages arranged in a queue format and route data associated with said template;

means for accessing the digital representations of only the audio messages in said template by the limited user;

means for reproducing the audio messages in said template in analog format;

means for transmitting each of the audio messages in said template;

means for pausing between transmission of individual audio messages in said template to allow the limited user accessing the digital representations to provide responsive analog information;

means for storing digital representations of said responsive analog information in said digital memory means for access only by said originating user;

means for storing in said memory means digital representations of said audio messages received from the user's telephone facility;

means for storing in said memory means digital representations of said route data received from the user's telephone facility;

means for accessing said stored digital representations of said audio messages;

means for reproducing the audio messages in analog format from the stored digital representations; and

means for transmitting reproduced audio messages to the telephone facilities of said selected recipients.

32. The method of claim 1 wherein the step of enabling limited access comprises:

storing digital representations of receive-only analog information supplied by only one user, the access thereto controlled by the one user;

enabling access to the message system by the limited user and controlled by the one user;

accessing the stored digital representations of the receive-only analog information by the limited user;

reproducing the receive-only analog information in analog format in response to analog signals input through the limited user's telephone facility; and

transmitting the receive-only analog information to the limited user.

33. The method for receiving, storing and forwarding analog information of claim 32 further comprising:

outputting a pre-recorded reply analog prompt to the limited user after the receive-only analog information is transmitted to the limited user; and

storing digital representations of responsive analog information supplied by the limited user in response to the pre-recorded reply prompt;

the stored digital representations of the responsive analog information accessible only by the one user.

34. The method for receiving, storing and forwarding analog information of claim 32 further comprising timing the beginning of the analog signals transmitted from the originating user's telephone facility and automatically disconnecting the message system from said originating user's telephone facility if no analog signals are supplied within a predetermined interval.

35. A method for operating a message system to receive, store and forward analog information from a user's telephone facility, comprising:

transmitting analog signals from an originating user's telephone facility to a storage location;

storing digital representations of the analog signals received from the originating user's telephone facility;

enabling limited access to the stored digital representations of the orginating user's analog signals by a non-originating user, the scope of the non-originating user's limited access controlled by the originating user through the user's telephone facility, the originating user having full access to the stored digital representations and the limited access of the non-originating user being less than full with the non-originating user being unable to limit;

converting the stored digital representations of the analog signals received from the originating user's telephone facility into analog signals; and

transmitting the reproduced analog signals converted from the stored digital representations to the non-originating user.

36. A method for receiving, storing and forwarding analog information from a user's and a limited user's telephone facilities, comprising;

transmitting analog signals from an originating user's telephone facility to a storage location;

storing digital representations of the analog signals received from the originating user's telephone facility;

enabling an originating user to input a template having a string of audio messages arranged in a queue format and route data associated with the template;

enabling limited access to the stored digital representations by the limited user, the scope of the limted user's access controlled by the originating user and restricted to receiving audio messages in the template;

accessing the stored digital representations of the analog signals;

reproducing the accessed analog signals in analog format from the stored digital representations; and

sequentially transmitting the reproduced analog signals to the telephone facility of the originating user or the limited user.

37. A method for receiving, storing and forwarding analog information from a full-access user's and limited user's telephone facilities, comprising:

transmitting analog signals from a full-access user's telephone facility to a storage location;

storing digital representations of the analog signals received from the full-access user's telephone facility; p1 enabling limited access to the stored digital representations of the full-access user's analog signals by a limited user, the scope of the limited user's access controlled by the full-access user through the full-access user's telephone facility, the scope of the limited user's access being less than the scope of the full-access user's access such that the limited user cannot limit access to the digital representations of the full-access user's analog signals;

accessing the stored digital representations of the full-access users's analog signals;

reproducing in audio format the stored digital representations of the full-access user's analog signals; and

sequentially transmitting the reproduced full-access user's analog signals to the telephone facility of the full-access user or limited user.

Description

TECHNICAL FIELD

This invention relates to telecommunication systems, and more particularly to an electronic digital signal processor controlled telecommunication system for the deposit, storage and delivery of audio messages that affords the user an additional user controlled message address.

BACKGROUND ART

The present day telephone system provides means for its subscribers to verbally communicate with one another. The verbal communications must occur in real time and require that the sender and recipient have simultaneous access to their telephone stations for communication. If the sender is unable to initially place the call at a time when the recipient has access to his telephone, the sender must continue to repeat the call until the recipient is present. Similarly, if the sender desires to send the same verbal message to a number of recipients, he must repeat this process of establishing telephone contact with each recipient and repeating the message. Thus, the present day method of delivering verbal communications is time consuming, and in the business community the time spent in such present day verbal communications is inefficient and reduces personal productivity.

While auxiliary devices, such as telephone recording systems, may be installed for individual telephone sets, such devices do not fill the need for the rapid and efficient delivery of verbal messages in the business community. A need has thus arisen for a centralized telecommunications system which eliminates many of the inconveniences, inefficiency and time consuming requirements of the existing telephone network.

One solution to this problem has been the very recently developed voice message systems that receive audio messages from telephone stations for storage and later retrieval by another party. Normally, full access to these message systems is limited to a subscribing party who is termed a "user". In some situations, however, it is desirable to provide access to some "non-users", that is, parties that do not subscribe to the message system itself and also to certain select users. Since a non-user does not bear any portion of the burden for maintaining or operating the system, the non-user's access must be controlled by the user. The present systems allow some limited access by a non-user in that users may deliver messages to non-users by having the system call the non-user and force deliver messages to them. In addition, a particular user may have available for his use certain features that are not generally available to other users. In view of this very limited access by a non-user and the restricted use by some users, it is desirable to expand the access that these parties would have to the system and allow the user to control this access.

SUMMARY OF THE INVENTION

The present invention described and disclosed herein comprises a method and apparatus for receiving, storing and forwarding analog information from a user's telephone facility. The apparatus comprises an electronic digital signal processor for controlling the operation of the message system and a digital memory controlled by the signal processor for storing digital representations of the analog information. The analog information comprises a first portion for routing to selected recipients and a second portion for defining route data. A user access circuit enables the user to access the message systems through analog signals transmitted from the user's telephone facility. A non-user accessing circuit enables limited access to the message system by a selected non-user, the scope of the non-user's limited access being controlled by the user through signals input from the user's telephone. Digital representations of the first and second portion of the analog information are stored in the digital memory and an accessing circuit allows access to the stored digital representations of the first portion of the analog information associated with particular route data. A reproducing circuit reproduces the first portion of the analog information in analog format from the stored digital representations and a transmitter transmits the reproduced analog information to the telephone station of the selected recipient.

In another embodiment of the present invention, a second digital memory is provided to store digital representations of receive-only analog information that is stored in the second digital memory by a storing circuit. An accessing circuit accesses the stored digital representations of the receive-only analog information and a reproducing circuit reproduces the receive-only analog information in analog format in response to signals transmitted by the selected non-user. The reproduced receive-only analog information is sequentially transmitted to the selected non-user by a transmitter.

In yet another embodiment of the present invention, an apparatus is provided for non-user control for storing in the digital memory responsive analog information in response to analog signals from the selected non-user's telephone station. The responsive analog information is only associated with the route data of the one user and can only be received by the one user.

In a further embodiment of the present invention, an apparatus is provided for storing selected analog information from an originating user for limited access by a plurality of other selected non-originating users. The scope of the non-originating user's limited access is controlled by the originating user through the signals input through the originating user's telephone. Under control of the user, the non-originating user can also respond to the selected analog information transmitted to the non-originating user.

In a yet further embodiment of the present invention, an apparatus is provided for limited user access to a string of audio messages arranged in a queue format by the originating user. The scope of the limited user's access is controlled by the user and restricted to receiving audio messages contained in a template and responding with responsive analog information for routing only to the originating user. Other aspects and advantages will become apparent hereinafter.

BRIEF DESCRIPTION OF DRAWINGS

Other objects and advantages of the present invention will be apparent from the following Detailed Description of the preferred embodiments thereof and from the attached Drawings of which:

FIG. 1 illustrates a Voice Message System connected with the multiple private exchanges of a customer and the central office of the telephone company;

FIG. 2 illustrates a network of Voice Message Systems;

FIG. 3 is a block diagram of the Voice Message System of FIGS. 1 and 2;

FIG. 4 is a block diagram view of the call processor subsystem of the Voice Message System of FIG. 3;

FIG. 5 is a block diagram view of the communication port interface, port driver modules and Codecs connecting the telephone handsets (of the call processor subsystem of FIG. 4);

FIG. 6 is a block diagram view of the administrative subsystem for the Voice Message System of FIG. 3;

FIG. 7 is a block diagram view of the storage subsystem of the Voice Message System of FIG. 3;

FIG. 8 is a block diagram view of the port driver subsystem of the communication port interface of FIG. 5;

FIG. 9 is a block diagram view of the Codec of the port driver subsystem of FIG. 8;

FIGS. 10a to 10n and 10j are the schematic drawings of the Universal Control Board programmable to function as the communication port interface disk adapters and block transfer bus interface of the call processor subsystem of FIG. 4, the expander of the communication port interface subsystem of FIG. 5 and the disk adapters and block transfer bus interface of the administrative subsystem of FIG. 6.

FIG. 11 is a flow chart of the message deposit function of the voice message system;

FIG. 12 is the flow chart of the process user-I.D. subroutine of the message deposit function of the voice message system;

FIG. 13 is the flow chart of the process and addressee subroutine of the message deposit function of the voice message system;

FIG. 14 is a flow chart of the record voice message subroutine of the message deposit function of the voice message system;

FIG. 15 is a flow chart of the message delivery function of the voice message system;

FIG. 16 is a flow chart of the process user I.D. subroutine of the message delivery function of the voice message system;

FIG. 17 is a flow chart of the play voice message subroutine of the message delivery function of the voice message system;

FIG. 18 is a flow chart of the redirect special function code subroutine of the message delivery function of the voice message system;

FIG. 19 is a flow chart of the reply special function code of the message delivery function of the voice message system;

FIG. 20 is a flow chart of the save special function code subroutine of the message delivery function of the voice message system;

FIG. 21 is a flow chart of the inquiry function of the voice message system;

FIG. 22 is a visual Table of Contents of all the programs in the VMS system software;

FIG. 23 illustrates the control and data flow for the programs running in the call processors;

FIG. 24 illustrates the control and data flow for the programs residing in the master and slave processors of the administrative subsystem;

FIGS. 25a to 25c are the schematic drawings of the Codec of FIG. 9;

FIGS. 26a to 26h are the schematic drawings of the port driver subsystem of FIG. 8;

FIGS. 27a and 27b are a flow chart of an alternate embodiment of the message delivery function;

FIG. 28 is a flow chart of the message receipt subroutine in the flow chart of FIGS. 27a and 27b;

FIGS. 29a and 29b are a flow chart of the send message subroutine in the flow chart of FIGS. 27a and 27b;

FIG. 30 is a flow chart of the redirect feature;

FIG. 31 is a flow chart of the user changeable group codes feature;

FIG. 32 is a flow chart of the automatic variable time scan feature;

FIG. 33 is a flow chart of the quiet time compression feature;

FIG. 34 is a flow chart of the edit feature;

FIG. 35 is a flow chart of the DID/ICH feature;

FIG. 36 is a flow chart of the RO message address recording feature;

FIG. 37 is a flow chart for the RO message address access feature;

FIG. 38 is a flow chart for the personal information message feature;

FIG. 39 is a flow chart for the interactive voice message system feature;

FIG. 40 is a flow chart of an alternate embodiment of the message delivery feature;

FIG. 41 is a flow chart of the sequential group calling feature;

FIG. 42 is a flow chart of the status check feature;

FIG. 43 is a flow chart of the DID answer delay feature;

FIG. 44 is a flow chart of the FAX transmission feature;

FIG. 45 is a flow chart of the analog networking feature; and

FIG. 46 is a flow chart of the hybrid networking feature.

DESCRIPTION OF PREFERRERD EMBODIMENT

Referring to FIG. 1, a Voice Message System advanced verbal communication system (hereinafter "VMS") of the present invention is generally identified by the reference numeral 10. ("Voice Message System" is a trademark of Electronic Communication Systems, Inc.) The VMS system 10 is illustrated connected with a user's telephone communications network. The VMS system 10 is not limited to the particular telephone communications network illustrated in FIG. 1, as the present invention is capable of providing an improved communications network for a variety of user's telephone systems.

The telephone communications network illustrated in FIG. 1 includes multiple Private Branch Exchanges 12 (hereinafter "PBX 12") interconnected by tie lines 14 through Voice Connecting Arrangements (hereinafter "VCA") 16 to the VMS 10. The VMS 10 can also be connected to a PBX 12 with station lines. The VCA unit is supplied by the telephone company pursuant to Federal Communication Commission's tariff regulation to provide a line of demarcation between a private user's equipment and the telephone company's equipment. In addition to representing what are referred to as Private Branch Exchanges the term "PBX" also includes but is not limited to PABX (Private Automatic Branch Exchange), EPABX (Electronic Private Automatic Branch Exchange) and CBX (Computerized Branch Exchange), in addition to various off premises switching systems.

The user's telephones 18 connected to the PBX's 12 have access to the VMS 10 and are generally referred to as being on the network or "ON NET". The features of the VMS 10 may be utilized by a small customer with a single PBX 12 or by much larger customers having multiple PBX's 12 interfaced with a single VMS 10. Of course, the PBX's 12 of a large corporate customer may be separated and located in distant physical facilities. Remotely located PBX's 12 may be interconnected to a central VMS 10 by other means than the tie lines 14, e.g., they could be connected by a microwave relay system.

The user's PBX's 12 are also connected through telephone lines 20 to a central office 22, of the telephone company. In addition, the central office 22 is interconnected through tie lines 14 and VCA 16 to the VMS 10. The VMS 10 can also be connected to the central office 22 through central office trunks. Telephones 24 outside the customer's own telephone communications network or "OFF NET" allow a user access to the improved communication capabilities provided by the VMS 10.

Referring to FIG. 2, a first VMS 10 is interconnected to a user's telephone communications network as illustrated in FIG. 1 and described above. The first VMS 10 is interconnected to a second VMS 10 to form a network of VMS systems 40. The first VMS 10 interconnected with its user's telephone communication equipment comprises a first node 42 of network 40, while the second VMS 10 with its user's telephone communication equipment comprises the second node 44 of network 40. The first VMS 10 is interconnected through a MODEM 46 for modulating the communications information from the first node 42 for transmission via the transmissions link 48 to a MODEM 50. The MODEM 50 demodulates the information for use by the second VMS 10 of the second node 44. The transmission link 48 could comprise a microwave relay system for connecting nodes 42 and 44 of the VMS network 40. Such a transmission link 48 could be transmitted through a satellite communications system to provide an interconnection between distant VMS systems 10. The VMS systems are also interconnected through a public telephone network 51 for transmission of data in analog format. Of course, the number and arrangement of interconnected VMS systems 10 are not limited to the arrangement of VMS network 40 of FIG. 2.

Referring to FIG. 3, the VMS 10 of FIG. 1 includes the following subsystems: an administrative subsystem 60, call processor subsystems 62A-62C, and a data storage subsystem 64. There is only one administrative system 60 and data storage subsystem 64 for each VMS system 10, but there may be multiple call processor subsystems 62A-62C. The number of call processor subsystems 62A-62C required is a function of the number of telephone lines interfacing with the VMS 10. Thus, a VMS 10 may have one call processor subsystem 62A or any number of such subsystems. While there is one data storage subsystem 64 for the VMS 10, the size of the data storage subsystem 64 may vary, depending upon the number of disk files required for operation of the VMS 10. The data storage subsystem 64 functions as the storage medium for audio messages in the system. A message deposited from a caller is stored in the VMS system 10, and the message is later delivered to the addressee. Instructional messages are also stored in the data storage subsystem 64 to guide the user in using the VMS 10.

A block transfer bus 66 allows each call processor subsystem 62A-62C to be connected to the administrative subsystem 60, as well as allowing each of the call processor subsystems 62A-62C to communicate with one another.

Data storage buses 68A-68B connect the administrative subsystem 60, the call processor subsystem 62A-62C and the data storage subsystem 64. The administrative subsystem 60 and each of the call processor subsystems 62A-62C have access to each of the data storage buses 68A-68B. The two data storage buses 68A-68B serve two functions. First, it provides redundancy in the VMS system 10, so that, if data storage bus 68A misfunctions, data storage bus 68B allows the VMS 10 to continue to operate. Secondly, when both of the data storage buses 68A-68B are functioning, it doubles the bandwidth of the data to be transmitted between the data storage system 64 and the call processor subsystems 62A-C and administrative subsystem 60.

Referring to FIG. 4, the call processor subsystem 62A is illustrated in block diagram form. A single board computer 70 contains a microprocessor, some memory storage, and some input/output device interfaces. The single board computer 70 may be implemented by Intel's single board computer, from Intel, Model Number 80/30. The Intel 80/30 computer includes an 8085 microprocessor, a 16K RAM, 8K ROM, as well as some input/output device interfaces.

A call processor memory 72 provides memory for the call processor subsystem 62A and may be implemented by one or more individual boards containing RAM memory. A single board providing 64K bytes of RAM memory may be utilized as the call processor memory unit 72 and is commercially available from Intel as Model No. SVC064. A communications port interface 74 provides access to the communication port modules 90 of FIG. 5 described hereinbelow. Two identical disk adapters 76 and 78 interconnect with the data storage subsystem 64 of FIG. 3 through data storages buses 68A and 68B. Finally, a block transfer bus interface 80 is a hardware device required to interconnect with the block transfer bus 66 of FIG. 3.

The communication port interface 74, disk adapters 76 and 78, and the block transfer bus interface 80 are all implemented with an identical electronic unit, identified as a Universal Control Board. A Universal Control Board contains an Intel 8085 microprocessor, a RAM memory device, (approximately 500 bytes), a ROM memory device (approximately 2K-4K bytes), and a digital data bus interface. A Universal Control Board's function is determined by the program controlling the microprocessor. The schematic of a Universal Control Board is illustrated in FIGS. 10a-10m and described hereinbelow.

In addition to the memory provided in each of the Universal Control Boards, the communication port interface 74, disk adapters 76 and 78 and block transfer bus interface 80 all have access to the memory 72 of the call processor subsystem 62A. Thus, the microprocessors of these Universal Control Boards communicate with the single board computer 70 through the shared memory unit 72.

Referring now to FIG. 5, the communication port interface 74 of FIG. 4 interfaces with the communication port driver modules 90A-B through a communications port digital data bus 88. The communication port driver modules 90A-90B are identical with one another, and each port driver module 90A-B may include a maximum of 16 identical port drivers 92. An expander 94 is a device for expanding the communications port data bus 88 to the 16 port drivers 92 of each module 90A-B. The expanders 94 are also implemented by a universal control board, illustrated in FIGS. 10a-10m and described hereinbelow. Each port driver 92 is directly connected to a CODEC 96. The CODEC 96 is an abbreviated term for a circuit that functions as a coder/decoder. The CODEC 96 transforms the analog voice signal to a digital bit stream for processing in the VMS 10. The translated digital bit stream is fed up into the port driver 92 for distribution to the remainder of the VMS system 10. In addition, in transmitting a recorded message outbound from the VMS 10 to the user, the outbound digital bit stream comes from the port driver 92 into the CODEC 96 where it is translated back into an analog voice signal which is fed into the receiver of the telephone 18 of the user. A single communication port interface 74 can drive up to 32 port drivers 92, which is equivalent to 32 telephone circuits to the VMS 10.

As required by the FCC tariff regulations, the CODEC 96 interfaces through a voice connecting arrangement 98 with the telephone 18 of the user.

FIG. 6 illustrates the hardware implementing the administrative subsystem 60 of FIG. 3. The hardware implementing the administrative subsystem 60 is very similar to that implementing the call processor subsystem 62A illustrated in FIG. 4 and described above.

A single board computer 100 (hereinafter "SBC 100") operates as the central processing unit for the administrative subsystem 60, and it is implemented by a programmable single board computer, commercially available from Intel, Model No. 80/30. The SBC 100 has one input/output interface 102 connected to a cathode ray terminal 104, which serves as the operator's console for the VMS 10. The second input/output interface 106 of the SBC 100 drives a line printer 108. The line printer 108 functions to produce reports and status information concerning the operation of the VMS 10, and it also displays alarms for abnormal conditions during the system operation. One such alarm condition would result from the failure of a recorded message to be transmitted from the VMS 10 in a predetermined period of time.

A memory unit 110 comprised of printed circuit boards provides the memory for the administrative subsystem 60. The memory unit 110 may be made up of one or more individual printed circuit boards, each having 64K bytes of RAM. These printed circuit boards are commercially available from Intel, Model SBC064. A nonvolatile memory unit 112 provides memory for the administrative subsystem 60 so that the data stored in memory is not destroyed if the system loses power. The memory unit 112 could also be implemented with core memory having a capacity of 8 to 16K bytes.

Two identical disk adapters 114 and 116 interconnect through the data storage buses 68A-68B to the data storage subsystem 64 of FIG. 3. The disk adapters 114 and 116 are implemented with a Universal Control Board having its microprocessor programmed for the unit to run as a disk adapter. Finally, a block transfer bus interface 118 is connected to the block transfer bus 66 to the call processor subsystem 62A of FIG. 3. The block transfer bus interface 118 is also implemented with a Universal Control Board having a microprocessor programmed to control the unit's operation.

FIG. 7 is a block diagram view of the storage subsystem 64 of the VMS 10 of FIG. 3. FIG. 7 illustrates two identical disk storage units 120 with their associated disk controller 122. Each disk controller 122 interfaces with the remainder of the system through disk ports 124A and 124B through the data storage buses 68A and 68B. While FIG. 7 illustrates two identical disk storage units 120 with their associated disk controllers 122, the data storage subsystem 64 consists of any number of such identical units. The configuration of the VMS subsystem 10 of FIG. 3 requires a minimum of two disk storage units 120, but additional units may be added to increase the storage capacity of the system.

The entire disk storage unit 120 may be implemented by using a Storage Technology Corporation disk drive, Model Number 2700. The STC Model 2700 disk storage unit 120 is a rotating magnetic disk having a capacity for 200 million 8 bit bytes of digital or binary information. Each disk unit contains its own dedicated disk controller 122 which is built around a microprocessor. The disk controller 122 may be implemented with a Motorola microprocessor, Model Number 6801, 64K bytes of RAM memory, and it also includes a special purpose digital hardware to drive the input/output disk ports 124A and 124B into the disk unit 120 and to directly control the disk storage unit 120. As additional disk storage units 120 are added to the system, their associated disk ports 124A and 124B are connected to the data storage buses 68A and 68B.

The VMS system 10 is provided with a minimum of two disk storage units 120, since the functioning of the disk storage units 120 is essential to the entire VMS system. The two data storage buses 68A and 68B are provided to achieve redundancy in the system. If one of the buses goes out of service, then the other bus still has access to all of the disk units 120 through the single remaining bus. With a single data bus in operation, the system will still operate, but it will not have the same throughput capability in terms of the amount of data that can be processed by the VMS 10. However, when both disk storage buses 68A and 68B are running at normal operation, this allows twice as much information to be fed into and out of the storage system 64 than could be accomplished with a single data storage bus.

A separate disk controller 122 dedicated to the operation of each disk storage unit 120, enables blocks of information to be more efficiently transferred within the VMS 10. For example, in transferring a block of information from the call processor subsystem 62A or the administrative subsystem 60 to or from the disk storage unit 120, the transfer does not occur in real time from one of the data storage buses 68A or 68B onto the disk unit 120. The block of information is transferred into the RAM storage of the disk controller 122, and then the disk controller 122 controls the operation of transferring the block of information from its RAM directly into the disk unit 120. In this way, the VMS 10 storage bus 68A or 68B is not tied up for the period of time it takes to write a block of information directly onto the disk 120; rather, it is occupied only for the period of time it takes to transfer that block of information into the RAM of the disk controller 122.

FIG. 8 is a block diagram view of one of the port drivers 92 of FIG. 5. The central control unit of the port driver 92 is an Intel 8085 microprocessor 130 connected by an internal bus 132 to the remainder of the port driver system 92. The microprocessor 130 is programmed to control a digital logic hardware device, identified as a bus interface logic unit 134. The bus interface logic 134 is an 8 or 16 bit wide parallel data path serving as the electrical interface between the expander 94 in all of the port drivers 92. The bus interface logic 134 consists of a bus backpane into which are plugged the boards for the port drivers 92 and expanders 94.

Voice data buffers 136 and 138 are connected to the remaining components of the port driver 92 through the internal bus 132. The voice data buffers 136 and 138 function to temporarily store the incoming or outgoing data bit streams of the digitized voice signal incoming or outgoing to the CODEC 96. The voice data buffers 136 and 138 interface through a CODEC interface logic unit 140 to the CODEC 96. A ROM memory unit 142 stores the program for the microprocessor 130.

The operation of the dual voice data buffers 136 and 138 may be illustrated by the example of digitized voice data being received by the port driver 92 from the CODEC 96. The voice data entering the port driver 92 is temporarily stored in one of the dual voice data buffers 136 or 138. When the selected voice data buffer is full, that entire block of data is transmitted out to the expander 94 up to the communication port interface 74 of the call processor 62A. At the same time when the port driver 92 senses that the first voice data buffer is full, the second voice data buffer is used to store the subsequent voice data from the CODEC 96. The port driver system 92 is programmed to control the dual voice data buffers 136 and 138 in the transmitting mode and the storing mode. The voice data buffers 136 and 138 are implemented in RAM semiconductor memory in the range of 512-2K bytes.

FIG. 9 is a block diagram of the CODEC 96 of FIG. 5. A delta modulator 150 (hereinafter "DM 150") is connected to the port driver 92. The DM 150 functions as either a coder for converting analog signals to digital signals, or a decoder for converting digital signals to analog signals. The operating mode of the DM 150, whether it is functioning as a coder or decoder, is controlled by one of the interface signals 152 to the port driver 92. The DM 150 implements a particular technique for converting analog to digital and digital to analog.

The DM 150 decodes the digital wave form to an analog signal and passes it through filter 154 which is a voice band filter with a cutoff frequency of approximately 2700 hertz. The analog signal from the filter 154 is fed into a VCA interface logic 156, through a VCA 158 to the ON NET telephone 18. The VCA 158 is required by FCC Tariff Regulations as the line of demarcation between the equipment of the telephone company and the equipment of a private user.

The analog signal from the telephone 18 is transmitted through the VCA 158 and VCA interface logic 156 to an automatic gain control circuit 160, which serves to amplify the analog voice signal from the VCA. The amplified analog signal is then passed through another band pass filter 162 for passing frequencies in the range of approximately 300 hertz to 2700 hertz. The filtered analog signal is then fed into the DM 150, which is functioning as a coder, and transformed into a digital bit stream to be fed to the port driver 92.

The first function of the CODEC 96 has been described above in providing the data path for the incoming and outgoing voice signals from the telephone 18 to the VMS system 10. An ancillary function of the CODEC 96 is provided by a tone receiver 164, which receives the analog wave forms generated by the signal from a touchtone type of telephone 18 and converts these waveforms to digital information corresponding to the tone received. A tone generator circuit 166 provides the analogous function in converting digital signals from the VMS 10 to the receiver of the user telephone 18. The tone generator 166 functions to generate touchtone as well as progress tone acknowledging the status of the operation of the VMS 10. The tone generator 166 functions to form the outgoing dialing in a touchtone system. A pulse dialing path 168 is provided to receive pulse dialing coming in from a rotary telephone 18, and it also functions to do the outbound dialing to a rotary telephone 18.

FIGS. 10a-10m illustrate the Universal Control Board which is programmable to serve a number of functions in the VMS 10 described above. Universal Control Boards are utilized in the call processor subsystem 62A illustrated in FIG. 4 to function as the communication port interface 74, the disk adapters 76 and 78 and the block transfer interface bus 80. In addition, the expander 94 illustrated in FIG. 5 is implemented with a Universal Control Board. In the administrative subsystem 60, Universal Control Boards are programmed to function as the disk adapters 114 and 116 as well as the block transfer interface bus 118. The storage subsystem 64 illustrated in FIG. 7 utilizes a Universal Control Board to function as the disk controllers 122.

The hardware for implementing the Universal Control Boards is illustrated in FIGS. 10a-10m and described hereinbelow. The hardware of the Universal Control Board is identical for each of the above-described applications in the VMS 10. The programs stored in the ROM of each Universal Control Board determines its function. For instance, the communication port interface 74, disk adapters 76 and 78 and block transfer bus interface 80 of the call processor subsystem 62A comprise individual Universal Control Boards with identical hardware. The software program stored in the ROM determines whether the particular Universal Control Board functions as a communication port interface 74 or disk adapters 76-78 or the block transfer interface bus 80.

FIGS. 10a, 10b and 10c illustrate the basic microprocessor section of the board and includes a microprocessor 200 and memory input/output combination chips 202 and 204. The chips 202 and 204 have random access memory and I/O port features, while another combination chip 206 has a read only memory (ROM) in conjunction with I/O ports. Microprocessor 200 is available commercially from Intel as Model No. 8085; the combination chips 202 and 204 with RAM memory are commercially available from Intel Model No. 8155; and the ROM combination chip 206 is available from Intel as Model No. 8755.

A crystal 208 is the source of the clock signal for the microprocessor 200, determining how fast it will run and how much time is allotted for execution of an instruction.

As shown in FIG. 10c, reset circuitry 210 controls the start-up of the microprocessor 200 when it is turned on and provides the means for resetting microprocessor 200. There are three different ways in which the microprocessor 200 may be restarted. First, the "power on" reset signal comes into one pin of a reset OR gate 212 and goes through an inverter 214 to the microprocessor 200. The "power on" reset signal originates when system power is turned on and a resistor 216 slowly charges a capacitor 218. Manual reset switch 220 is provided to manually reset the system by generating a grounded signal through an invertor 222 and an invertor 224 to the input of the OR gate 212 to cause a reset any time it is desired by the operator. The second method of restarting the microprocessor 200 is from the IORST signal originating from another Universal Control Board connected to the same bus to provide a reset signal to reset OR gate 212. The third way to reset the microprocessor 200 is through the general system reset signal passing through inverters 222 and 224 to one pin of the reset OR gate 212. This signal is a general system reset and typically means that the reset occurred because everything in the system has been reset. This general system reset signal may be originated from another push button located elsewhere in the system, like reset switch 220, which individually resets this particular microprocessor 200.

The reset signal from the OR gate 212 is fed separately through inverters 226 and 228 to become reset signals "RST1" and "RST2" to provide logic resets to other logic on the Universal Control Board other than the microprocessor 200.

As shown in FIG. 10j, an extended memory unit 170 is provided as an extension to the memory of the microprocessor 200. The extended memory 170 comprises four functional units: (1) an address latch 172, (2) EPROM memory units 174, 175, 176, 177, and 178, (3) RAM memory units 180, 181, 182, 183, 184, and 186, and (4) address decoding chips 187, 188, 189, 190, 191, 192 and 193.

The address latch 172 is conditioned by the control signal ALE to capture the address information (ADO-AD7) on an address data bus 230. The latched address is stored in address latch 172, which feeds its output to all the EPROM chips 174-178 as well as all the RAM chips 180-186.

The address decoding chips 187-193 decode the high order address signals A10, A11, A12, A13, as well as the control signals RD and WR. These signals are used to generate the output signals RAM1, RAM2 and RAM3. These signals control the activation of the individual EPROM chips 174-178 and RAM chips 179-186.

The EPROM memory units 174-178 contain the stored program of the Universal Control Board's 8085 processor. The combination of the address latch signals and the individual address decode signals control which EPROM chip and which byte in the EPROM chip, is selected. The EPROM chips apply the selective data to the bus 230.

The RAM memory units 180-186 contain variable bytes of data which are used by the Universal Control Board's 8085 processor. The RAM memory chips 179-186 are selected by the address decode signals RAM1, RAM2, and RAM3. The RAM memory units 179-186 are selected in pairs, each chip in the pair asserts four bits on the address data bus 230. Signals from the address latch 172 control which byte in the selected RAM chip is asserted on address data bus 230. The RAM chips 179-186 also use the signal WR to store data in the RAM chip from the address data bus 230.

As shown in FIGS. 10a, 10b and 10d an address data bus 230 is a bidirectional bus operating in a time multiplexed fashion. Part of the time the bus 230 represents an address memory that needs to be involved in a particular instruction, and at other times the bus 230 represents data that is involved in a particular transaction and an instruction. This means the data can be going into or out of memory or into or out of an input/output port. The address data bus 230 connects the signals ADO-AD7 to one side of the bus repeater 232 for regenerating the data bus. The data signals D0-D7 are connected through a data bus 234 to a memory address register 236 and a word count register 238. A control bus 240 interconnects the various controls and timing signals from the microprocessor 200 to the rest of the components in the combination chips 202, 204 and 206 to instruct these devices in handling the signals on the address data bus 230.

The ALE signal originating in microprocessor 200 is the address latch used to tell the other components when the address data bus has an address on it. The other chips, 202, 204 and 206, have internal address registers which use the strobe to latch whatever information is on the address data bus 230 to save the address.

The IOM signal originates with the microprocessor 200 to tell the other components connected to the microprocessor 200 that the particular data transaction is either input/output or memory. The state of the signal tells the combination chips 202, 204 and 206, having input/output functions and memory functions, that the data on the data lines and address on the address lines should be used to control either the input/output ports or the memory ports. If the IOM signal is high, this represents an input/output transaction; and if the signal is low it represents a memory transaction, either a read or write transaction.

The next strobe signal of the microprocessor 200 is the RD read signal which is a timing signal to tell the other components that the microprocessor 200 is to perform a read function.

The next strobe signal is the WR write strobe originating with the microprocessor 200 to tell the other system components that the microprocessor 200 is to perform a write transaction, i.e., that it's going to originate in the microprocessor and end up in an external component.

The next control signal is the RESET signal originating in the microprocessor 200 which initializes the other combination chips 202, 204 and 206.

The final control signal on the control bus 240 is the CLK signal, which is a timing signal to the other combination chips 202, 204, and 206 so that the whole system is synchronized.

The remaining signals, A8-A15, originating from the microprocessor 200 to the ROM combination chip 206 to select which system component is to be involved in a particular input/output or memory transaction. As shown in FIG. 10a, address signals A11-A13, connected to an address decoder 244, may further select one of the chips 202, 204 and 206 in the system to be involved in a transaction through its output signals DC0, DC1, and DC2. In addition, address decoder 244 also enables the microprocessor 200 to select the desired ROM by outputting one of ROM1, ROM2, ROM3, ROM4, and ROM5 signals. As shown in FIG. 10d, the address signals A13-A15 are connected to an input/output decoder 246 to decode these addresses into five unique signals to select certain registers to control the memory address register 236 and the word count register 238 of FIG. 10e. Of the five decoding signals provided by the input/output decoder 246, three of them LDM0, LDM1 and LDM2, are used by the memory address register 236. The remaining two decode signals of the input/output decoder 246, LDM3 and LDM4, are used by the word count register 238.

The memory address register 236 consists of address memory registers 248, 250, 252, 254, and 256. The function of the memory address register 236 is to address memory which is exterior to the Universal Control Board and connected to the Intel bus. The Intel bus is the main bus which connects all the Universal Control Boards to one system. The memory address register 238 can be loaded through input/output commands to an initial starting address, which allows another controller in the board to command it, incrementing its value through the INCDMA signal coming into one pin of an AND gate 258. The INCDMA signal comes from a bus timing control circuit 540 (FIG. 10m) on the Universal Control Board. The other signal to the AND gate 258, MARINH, originates from a ROM sequencer 290 (FIG. 10f) on the Universal Control Board and described below.

The output of the memory address register 236 is transmitted to address drivers 260, which consist of separate drivers 262, 264, 266, 268, and 270 connected to the memory address registers 248, 250, 252, 254, and 256, respectively. The address drivers 260 take the memory address bits individually from the address registers 248-256 and condition them to be placed on the Intel bus.

As shown in FIG. 10e, the word count register 238 consists of registers 272, 274, 276, and 278 having their inputs connected to the data bus bar 234 for receiving the data signals D0-D7. The word count register 238 may have a starting count loaded into its registers through an input/output command from the microprocessor 200. The word count register 238 is controlled by the INCDMA signal for generating an output signal, word count zero (WCZERO) signal, to control how many bus transactions occur. For protocol on the Universal Control Board, the WCZERO signal is passed through an inverter 280 to output the signal as WCZERO.

As shown in FIG. 10f, a ROM sequencer 290 functions to control most of the logic on the Universal Control Board under the command of the microprocessor 200. The ROM sequencer 290 controls bus transactions and controls transactions with whatever other device is connected to the Universal Control Board on the other side of its cable.

The ROM sequencer 290 includes very high-speed memories in the form of interconnected PROMS 292, 294, 296 and 298. The input to the PROMS 292-298 is its address and its output is program instruction for other components of the Universal Control Board. The first four bits comprising the output of the PROM 292 is the next address of the ROM program, and it is stored in the next address register 300. The PROM 294 has as its output the four signals LOCKOK, MARINH, WRTINH, and MUXCON, which are applied elsewhere to the Universal Control Board. The PROM 296 has three bits of its program output to control an output latch 302, which is a way for the program to express what it would like to do in terms of output. The output latch 302 implements three signals: "STOP", "BUSREQ" AND "RDONE". The output latch 302 is controlled by AND gate 304, having its input terminals connected to a 5 megahertz clock signal and a pullup signal. The fourth bit from the PROM 296 occurs in real time and is the DMA START signal, which is applied to a bus timing control circuit 540 of FIG. 10m. Finally, the last PROM 298 has three of its four bits of the program instruction to control an input multiplexer 306 to sample the various signals to see what their state is. The PROM 298 program output selects the input multiplexer 306 address and the output of the multiplexer stored as part of the next address register 301. The fourth bit of program instruction from the PROM 298 is the BREADY signal to a cable timing control circuit 340 of FIG. 10g.

As discussed above, four of the eiqht address bits for each of the PROMS 292, 294, 296, and 298 come from the next register address 300. A fifth address bit, SRRA4, comes from the output of the input multiplexer 306 through part of the next address register 301. The remaining three address bits of the PROMS 292-298 are controlled by the signals RA0, RA1, and RA2 which come from the input/output port of the ROM combination chip 206 of the microprocessor circuit. The signals RA0, RA1 and RA2 are fed through inverters 308, 310 and 312 through a PROM control bus 314 to the inputs of the PROMS 292-298. A fourth signal, RA3, from the ROM combination chip 206 is fed to a flip-flop 316 controlled by a 5 megahertz clock signal to generate a reset signal RSTM which goes to the next address register 300 and a reset signal RSTM which goes to the output latch 302. The RA3 signal allows the microprocessor 200 to turn off the ROM sequencer 290 when the ROM sequencer 290 has finished a particular function requested of it.

The microprocessor 200 controls the ROM sequencer 290 by the three-bit command RA0, RA1 and RA3 which specifies the program function to be performed, setting a 0 in the RA3 bit which will release the ROM sequencer 290 by taking away the reset. When the ROM sequencer 290 finishes performing its function, it sets the "STOP" bit at the output latch 302 which the microprocessor circuit can sample through the RAM combination chip 202, and the ROM combination chip 206 responds by resetting the flip-flop 316, turning the ROM sequencer 290 off. The reset bit RSTM also serves as a fail-safe mechanism by allowing the ROM sequencer 290 only a certain amount of allotted time to perform its function. If too much time elapses, then the microprocessor circuit performs an error recovery procedure by unconditionally resetting the ROM sequencer 290.

The ROM sequencer 290 includes a bus cycle counter 318. The bus cycle counter 318 determines how many bus transactions have occurred by being incremented by the signal INCDMA every time a bus transaction occurs. By selecting a particular one of the Q outputs of the bus cycle counter 318, QA, QB, QC, and QD, the counter can be adjusted to count by 2, 4, 6, or 8. Bus cycle counter 318 functions to prevent the ROM sequencer 290 from monopolizing time on the Intel bus when the ROM sequencer 290 is doing a bus block transfer. During a bus block transfer the ROM sequencer in effect locks out the other Universal Control Boards on that bus. Bus cycle counter 318 causes the ROM sequencer 290 to periodically give up control of the bus so that some of the Universal Control Board can use it. The output signal from the bus cycle counter 318 is the BUSCOUNT signal to one input of the input multiplexer 306.

The input multiplexer 306 allows the ROM sequencer 290 to sample the state of a number of functions. An AND gate 320, receiving input signals MUXCON and LOCK, has its output applied to one input terminal of the input multiplexer 306. The DONE signal from the cable timing control circuit 340 is applied to another input terminal of the input multiplexer 306. The CONNECT signal from the output of the contention logic circuit 460 is applied as another input signal of the input multiplexer 306. The DMACOMP signal is from the bus timing control circuit 540; another input signal. The WCZERO signal from the word count register 238 is also applied as an input signal.

The final input signal to the input multiplexer 306 is the BOTHD signal from a flip-flop 322. Flip-flop 322 has one pin connected to the output of AND gate 324, having its two inputs connected to the DONE signal from the cable timing control circuit 340, and the DMACOMP signal from the bus timing control circuit 540. The two "DONE" signals are connected to the input of the AND gate 324 to set the flip-flop 322. When the ROM sequencer 290 samples the input connected to the BOTHD signal of the input multiplexer 306, it can reset the flip-flop 322 by the RDONE signal originating from the output latch 302 and fed through an inverter 326. The flip-flop 322 may also be reset by the signal RST2 from the reset circuitry 210.

A clock circuit 330 takes a ten (10) megahertz signal through an inverter 332 and feeds it through the flip-flop 322 to the ROM sequencer 290. The ten (10) megahertz clock signal is also fed through another inverter 334 to a divide-by-two flip-flop 336 to generate a 5 megahertz clock signal (5MCK) and an inverted 5 megahertz clock signal (5MCK) for use elsewhere on the Universal Control Board.

As shown in FIG. 10g, cable timing control circuit 340 participates in the bus timing on the cable by originating one of the two signals on the cable and sampling the other. The signal DMAOUT is an output command signal generated by the cable timing control circuit 340 and the DMAIN signal originated on the cable bus driver circuit. The BREADY signal is derived from the fourth output bit of the PROM 298 of the ROM sequencer 290 (FIG. 10f) and is connected to the inputs of NAND gates 342 and 344. A second input of the NAND gate 342 is connected to the WRITE signal from the ROM combination chip 206 and the WCZERO from the inverter 280 of the word count register 238. The output of the logic NAND gates 342 and 344 are fed through an OR gate 346 to produce the READY output signal as one input to the D input of a D-type flip-flop 347. The flip-flop 347 has its Q output connected to one input of a three input NAND gate 348 and the clock input thereof connected to the ten magahertz clock. The NAND gate 348 also has its input tied to the DONE signal feed back from the output of the cable timing control circuit 340 and the DMACOMP signal from the output of the bus timing control circuit 540 (FIG. 10m). The output of the NAND gate 348 is fed through an inverter 350 to one pin of an input multiplexer 352. The input address of the multiplexer 352 is controlled by the state lines STB0, STB1 and STB2 as the output of a counter 354. Counter 354 essentially reflects the state of the cable timing control circuit 340. The input multiplexer 352 is sampling the DMAIN signal fed through flip-flop 356 which generates the output signals DMAINSY and DMAINSY as the inputs to multiplexer 352.

The output of the input multiplexer 352 goes to an output multiplexer 358 to allow certain signals to occur when the proper input is detected. The output multiplexer 358 waits in state 0 until it receives a logic 1 from the output of the input multiplexer 352 which would cause the output multiplexer 358 to have an output on its state 0, causing a ST0Y signal output. The ST0Y output signal goes through OR gate 360 and inverter 362 to reset the DONE signal from the ouput of a flip-flop 364. The ST0Y signal is also fed through OR gate 366 to set the DMAOUT signal at the output of flip-flop 368. The presence of the DMAIN response from another Universal Control Board is sampled by the input multiplexer 352, and if it is in state 1 it causes the output multiplexer 358 and the signal ST1Y be fed through OR gate 370 and inverter 372 to pin K of the flip-flop 368, causing DMAOUT to be reset. The input multiplexer 352 will change state upon a negative response from the other end of the cable of DMAIN going away, indicating that information has been taken off the cables. The change in state of the input multiplexer output 352 may cause the state 2 output ST2Y, to be generated by the output multiplexer 358 which is fed through the OR gate 374 to set the DONE output on the DONE flip-flop 364. The DONE signal is fed back to the input multiplexer 306 of the ROM sequencer 290 to indicate that the byte successfully moved to the other Universal Control Board. The output multiplexer 358 also has an output signal ST3Y fed through OR gate 376 and inverter 378 to reset the counter 354.

The sequence described above for setting and resetting the DONE and DMAOUT signals is basically the same whether the cable timing control circuit 340 is in the slave or master mode. The master mode operation was described above where the DONE flip-flop 364 and DMAOUT flip-flop 368 were set and reset by the signals ST0Y, STlY and ST2Y from the output multiplexer 358.

If the cable timing control circuit 340 is to operate in the slave mode, which means it is receiving a byte of data to be transmitted down a cable from another Universal Control Board, the slave signal will be generated from the ROM combination chip 206 to control the counter 354. The slave signal input to the counter 354 causes it to start out in state 4. The ST4Y signal is fed through one input of OR gate 360 and inverter 362 to reset the output of the DONE flip-flop 364. Response from the control board on the other end of the cable is the DMAIN signal sampled by the input multiplexer 352 to cause a state 5 output at the output multiplexer 358. The ST5Y signal is fed through the OR gate 366 to set the DMAOUT flip-flop 368. The cable timing control circuit 340 then waits for the DMAIN signal to go down which is detected by the input multiplexer 352 causing the state of the output multiplexer 358 to change to state 6. The ST6Y signal is fed through OR gate 374 to set the DONE output of flip-flop 364 and also fed through OR gate 370 and inverter 372 to reset the output of DMAOUT flip-flop 368. The output multiplexer 358 slave mode also has the output signal ST7Y fed through OR gate 376 and inverter 378 to reset the counter 354.

FIGS. 10h and 10i illustrate the circuit providing the data path for the movement of a piece of data. Bus data drivers/receivers 400 and 402 are integrated circuit chips which function as translation devices for data flowing between the bus and the Universal Control Board. The bus data drivers/receivers are controlled by NOR gate 404 having one of its input from the CONNECT signal from a contention logic circuit 460 (FIG. 10k) and an input from the BDSEL (board select) signal from an address decode circuit 490 (FIG. 10-l). A NOR gate 406 also controls the data drivers/receivers 400 and 402 and has its inputs connected to the REN signal and the IOR signal.

The data DB0-DB7 connected internally on the Universal Control Board moves through data bus 408 to command/status register of RAM combination I/O Chip 204 (FIG. 10b) and to the input of holding registers 410 and 412. The STROBE signal from the bus timing control circuit 540 (FIG. 10m) is fed through inverter 414 to a register 410. The INCDMA signal and READ signal are the inputs of NAND gate 416 having its output REN to the register 412. The REN signal is also fed through an inverter 418 and through one input of the NOR gate 406. The output of the NOR gate 406 is connected to the bus data drivers/receivers 400 and 402.

Holding register 420 has its input connected to the output of holding register 410 to generate an overlapped transaction. A byte of data loaded into register 410 from the bus is immediately transferred to the register 420, so that register 410 is ready to read another byte of data from the bus. The cable timing control circuit 340 is running simultaneously with the bus timing control circuit 540 to send bytes of data through the cable while the bus timing control circuit 540 is reading bytes of data from the bus. Holding registers 410 and 420 create this overlapped transaction when moving data from the bus memory to the cable. The output of register 420, IB0-IB7, is placed on cable bus 422 to cable bus drivers 424 and 426, which serve as translation devices to take the data from the internal environment of the board and put it on the external environment of the cable. A parity generator 428 takes the eight data bits IB0-IB7 and generates a ninth data bit, IB8, which is an odd parity representation of the rest of the data. The IB8 output of the parity generator 428 is input to a line driver 429 to generate the PAR signal. A RESSTBIN signal is also input to the other D-input of the line driver 429, the B output of which is connected to an optional jumper 431 to generate a RESSTB signal and a SYSRESET signal. The jumper 431 is added to make the connection, as shown by the dashed lines, to generate the output signals.

The holding registers 412 and 420 provide an overlapped condition in input, when data is moving from the cable into the bus memory. Data received by cable drivers/receivers 424 and 426 is transferred through a register 430 to a bus 432 as data bits OR0-OR7 as the input of holding register 420. The data stored in the holding register 420 is immediately moved into the holding register 412, so that register 420 is available to do another transaction simultaneously, moving the first data byte into holding register 412. Thus, holding register 420 switches functions depending on whether the system is in the input or output function in order to provide the overlapped condition.

A parity checking generator 434 takes the eight data bits RD0-RD7 from the cable drivers/receivers 424 and 426 to generate a ninth data bit, RD8, which is an odd parity representation of the rest of the data. Generation of the parity bit is stored in flip-flop 436 which generates the signal PARER to the RAM combination chip 202 of the microprocessor circuit.

The holding register 420 is clocked by three different functions through an OR gate 438. One function is the input function when the system is reading from the cable. In this input function, the READ signal and the DMAINSY signal are the inputs to a NAND gate 440, which has its output connected to the input terminal of the OR gate 438. In the output function, the WRITE and G1012 signals are connected to the input terminals of NAND gate 442 which has its output connected to OR gate 438. The third function of the holding register 420 involves single byte transfers on the bus, transfers which do not involve the cable. The DATACLK signal from the RAM combination chip 202 is fed through one input terminal of the OR gate 438.

A bus address switch 450 is also connected to the cable bus 422 to provide a unique address for a Universal Control Board. The microprocessor circuit through its RAM combination chip 202 has an output signal RDSWT connected to the bus address switch 450 to read the preset switches which are the input to the bus address switch 450. The switch 450 has eight inputs labeled SW0, SW1, SW2, SW3, SW4, SW5, SW6 and SW7 referring to the number of switches present. By selectively grounding a combination of switches, a unique code can be manually placed into an individual Universal Control Board. This is part of the initialization function of the microprocessor circuit.

The microprocessor circuits of the Universal Control Boards communicate with one another to determine which Universal Control Boards have access to the cable bus and to determine whether they are in the master or slave mode. The DATAIN, IINTR and SDATAIN signals from the microprocessor circuit are switched through a control multiplexer 452 to switch the three signals to either a master cable bus driver/receiver 454 or a slave cable bus driver/receiver 456. If microprocessor 200 is in the master mode, the control signals are switched to the master cable bus driver/receiver 454. If the SLAVE.1 signal is received by the control multiplexer 452, the microprocessor 200 is in the slave mode and the control signals are directed to the slave cable bus driver/receiver 456.

In the master mode, the driver/receiver 454 is driving the interrupt line, INTR, and the request lines, DMAREQ and DATAREQ. In the master mode, the slave cable bus driver/receiver is receiving the attention, ATTEN, signal as well as the response signals, DMARESP and DATARESP. In the Universal Control Board in the slave mode, just the reverse happens. The master driver/receiver 454 is receiving the interrupt signal, INTR, and the request signals, DATAREQ and DMAREQ. The slave driver/receiver is driving the attention signal, ATTEN and the response signals, DMARESP and DATARESP.

As shown in FIG. 10k, access to the bus is controlled by contention logic circuit 460. The contention logic circuit 460 is controlled by three signals, BUSY and BPRN from the bus and BUSREQ from the ROM sequencer 290. The BUSY signal is an indication that the bus is busy with a transaction in progress. The BPRN signal is an indication of whether or not the Universal Control Board has priority. The BUSREQ signal is generated by the ROM sequencer 290 when it is doing either signal or block mode transfers. The OVERRIDE signal is from an input/output port of the ROM input/output port chip 206. A bus request flip-flop 462 may be set by either the BUSREQ signal or the OVERRIDE signal. The BUSREQ signal is fed through an inverter 464 to one input of an OR gate 468 having its second input terminal tied to the OVERRIDE signal. The output of OR gate 468, SBREQ, sets the bus request flip-flop 462. The BREQ signal from the output of the flip-flop 462 is fed through inverter 470 to appear as the signal BREQ which goes on the bus to some external logic which will arbitrate bus priority. This external controller determines priority and upon receipt of priority for the requesting Universal Control Board the BPRN signal is received by the control board fed through inverter 472 to one input terminal of NAND gate 474. The BREQ signal is fed back through the output of the bus request flip-flop 462 to another input gate of the NAND gate 474. When the bus is no longer busy, the BUSY signal is fed through an inverter 476 and inverter 478 to the third input terminal of NAND gate 474. The output of NAND gate 474 is the output signal SCON fed through an inverter 480 to set a connect flip-flop 482. The output connect signal is fed back through inverter 484 to generate the BUSY signal. The only way to reset the bus request flip-flop 462 is for the bus request signal to be reset. A BUSCLK signal is received from the bus and fed through an inverter 486 as the bus clock signal to the bus request flip-flop 462 and the connect flip-flop 482. The connect flip-flop 482 has an override circuit 487 attached to the input thereof. The override circuit generates the signal CONOVRIDE to connect a pullup to the flip-flop 482.

As shown in FIG. 10-1, an address decode circuit 490 functions to decode the addresses AA0-AA7 from address drivers 262 and 264. Address signals AA4-AA7 are fed through address decoders 492 and 494 to generate output signal BDSEL, the board select signal. The other four signals AA3-AA0 are fed through address decoder 496 to select one of three functions on the board. The input/output reset function, the IORST signal, is fed through an inverter 498 and one input terminal of NAND gate 500. The other input of NAND gate 500 is from the IOW signal from the bus timing control circuit 540. The input/output reset function indicates that some other controller on the bus desires this Universal Control Board to be reset, and the IORST signal is fed to the reset circuitry 210 described hereinabove.

The remaining two functions decoded by the address decoder 496 are used to communicate with one of the input/output ports of the RAM input/output combination chip 204. The integrated combination chip 204 can be configured through software to function as either a status register or a command register. The command register function is fed from the address decoder 496 through an inverter 502 to one input terminal of NAND gate 504. The second input terminal of NAND gate 504 is controlled by the IOW signal. The output of NAND gate 504 is the CMDW signal to port A of the RAM combination I/O chip 204. The output from the inverter 502 is also fed to one input of NAND gate 506 having its other input connected to the IOR signal from the bus timing control circuit 540 (FIG. 10m). The output of NAND gate 506 is the signal STATR which goes to port B of the RAM combination I/O chip 204.

The command register functions to allow some other control board to load data into the register so that it can be read and responded to by the microprocessor circuit. The status register functions to allow the microprocessor circuit to store information here and some other Universal Control Board can read that information through the bus and the address decode circuit 490.

A third function of the address decoder 496 is an output fed through both input terminals of NAND gate 508 which has its output applied as one input to NAND gate 510. The outputs of NAND gates 506 and 510 are fed to the inputs of OR gate 512 which has its output connected to the input of NAND gate 514 which has its output connected to a data bus interface device 516.

Reviewing the three commands implemented through the address decoder device 496, the output of NAND gate 504 loads a byte of data into the command register of the RAM combination I/O chip 204. The output of NAND gate 506 creates and simultaneously resets the status register of the RAM I/O chip 204, while the output of NAND gate 510 reads the status register of chip 204 without resetting it. The output of the status and command registers, DB0-DB7, is placed on the DB data bus 408 (FIG. 10h).

A bus slave timing circuit 520 receives the strobes IOWC and IORC from the output of the bus timing control circuit 540. The IOWC signal is fed through inverters 522 and 524 to one input of OR gate 526. The IORC signal is fed through inverters 528 and 530 to the other input of OR gate 526. The output of OR gate 526 is input to shift register 532 to generate an output XACK fed through an inverter 534 to be conditioned as the signal XACK. The XACK signal is an acknowledgement to the bus that read and write strobes have been detected and the board select address has been detected. The board select signal is fed through an inverter 536 to the shift register 532. Shift register 532 also has a clock signal, CCLK, fed through an inverter 538.

FIG. 10m illustrates the bus timing control circuit 540. A NAND gate 542 has its input connected to the READ signal and the DMASTART signal from the ROM sequencer 290. The output of the NAND gate 542 is connected to one input terminal of OR gate 544. The second input terminal of the OR gate 544 is connected to the output terminal of AND gate 546, having its input terminals connected to the WRITE signal, the WCZERO signal and the DMASTART signal from the ROM sequencer 290.

The output of the OR gate 544 sets flip-flop 547. The output of flip-flop 547 is the origin of the INCDMA signal and it is also fed through an inverter 550 for the AEN signal. The output of the flip-flop 547 also controls the input of a flip-flop 552 for setting the DMACOMP signal to be fed to the ROM sequencer 290. The output of a flip-flop 548 is used to set one input of AND gate 554.

The XACK signal from the bus slave timing circuit 520 is fed through an inverter 556 to set a flip-flop 558. One output terminal of the flip-flop 558 is connected to a second flip-flop 560 having its output fed back to the K terminals of the flip-flops 558 and 560. The second output terminal of the flip-flop 558 is identified as the RACK signal connected to the second input terminal of an AND gate 554.

The output of the AND gate 554 is connected to one input terminal of AND gate 562 and AND gate 564. The second input terminal of the AND gate 562 is the MEMCY signal from the ROM combination I/O chip 202. The output of AND gate 562 is connected to the first input terminal of AND gates 566 and 568. The second input terminal of AND gate 566 is the WRITE signal from the ROM combination I/O chip 206, and the second input terminal of AND gate 568 is the READ signal also from the ROM combination I/O chip 206. The output of AND gate 566 is fed through an inverter 570 and identified as the MRDC signal, and the output of the AND gate 568 is fed through inverter 572 identified as the output signal MWTC.

The AND gate 564, having one input terminal connected to the output of AND gate 554, has a second input terminal connected to the IOCY signal from the RAM combination I/O chip 202. The output of AND gate 564 is fed to input terminals of AND gates 574 and 576. The second input terminal of the AND gate 574 is the READ signal, and the second input terminal of the AND gate 576 is the WRITE signal. The output of AND gate 574 is fed through an inverter 578 and is the IOWC signal used as an input to the bus slave timing circuit 520. The output of the AND gate 576 is fed through an inverter 580 which has as its output the IORC signal used as another input to the bus slave timing circuit 520.

Referring now to FIG. 10n, there is illustrated a schematic diagram of the reset circuitry for individually resetting one of the Universal Control Boards that is connected to the VMS system. An inverter 582 has the input thereof connected to one of the switch inputs on the bus address switch 450 (FIG. 10h), and the other input thereof is connected to one input of NOR gate 584. The output of the NOR gate 584 is connected to the input of an inverter 586, the output of which is input to the jumper board 431 of FIG. 10i. A NOR gate 588 has one input thereof connected to the input of the inverter 582, the other input thereof connected to the output of the inverter 586 and the output thereof connected to one input of a NOR gate 590. The output of the NOR gate 590 is connected to the input of an inverter 592 which has its output connected to the "B" input of an IC 594. The IC 594 is a parallel shift register, of which the output is conditioned by an inverter 596 to provide the output signal INIT . The output of the inverter 592 is also connected to the CLEAR input of the IC 594. The clock input of the IC 594 is connected to the 5MCK. A comparator 598 receives the inputs RD0, RD1, RD2, and RD3 on the A0-A3 input thereof. And the SW0, SW1, SW2, and SW3 signals on the B0-B3 inputs thereof. The output of the comparator 598 is input to the other input of the NOR gate 590. The comparator 598 compares the bit word on the input A0-A3 with the bit word on the input B0-B3. The inputs to the B0-B3 input are taken from the inputs to the bus address switch 450 (FIG. 10h) and denote the unique code for a given Universal Control Board. When the A0-A3 inputs correspond to that on the B0-B3 inputs, the output is activated and the B input of the IC 594 is activated. The switch signal SW7 that is connected to both the input of the inverter 582 and the input of the NOR gate 588, denotes the Universal Control Board that is selected as the master board.

In the VMS system, one of the Universal Control Boards is designated as the master board and input SW7 of the bus address switch 450 is grounded. This places a high logic signal on the A input of the IC 594 and allows the INI to control the operation of the NOR gate 588. If the board is not designated as the master board, a high signal is input to the inverter 582 and the NOR gate 588 which activates the NOR gate 584 and deactivates the NOR gate 588. This prevents the INI signal from activating the IC 594 and allows the comparator 598 to control the NOR gate 590, thus controlling the IC 594. The reset circuitry of FIG. 10n allows the VMS system to selectively reset only one of the Universal Control Boards without resetting all at one time.

The VMS 10 utilizes several microprocessor controlled Universal Control Boards connected to one bus instead of a single minicomputer. The Intel bus is the main bus which connects all the microprocessors together. The Universal Control Board has two distinct capabilities for moving data around in the VMS 10. First, the microprocessor 200 of the Universal Control Board may transfer data in single bytes in and out of the bus memory at a relatively slow rate to communicate with other microprocessors 200. Secondly, the Universal Control Board may also control the transfer of data in block form at a very high rate of speed through the cable or data bus interconnecting the Universal Control Boards. The ROM sequencer 290 has the function of coordinating the timing of the transfer of information from one cable to another cable with the microprocessor 200 instruction transfers to or from the bus.

The VMS 10 is an advanced communication system for audio signals, including facsimile, data, cryptographic and voice signals. The VMS 10 implemented in the preferred embodiment is described above in connection with voice signals, but the concept of the communication system has application for other audio signals as well. The VMS 10 of the preferred embodiment allows users to deposit voice messages which are recorded and later delivered to the intended recipients. In addition, users may call the VMS 10 at any time and inquire if any messages have been deposited for them. The VMS 10 may also answer a telephone while the user is absent or otherwise unavailable to receive the call and record a voice message for subsequent delivery to the user.

While the VMS 10 is intended primarily for use within medium to large corporations, it may be effectively used to improve the operator efficiency of any communication system. It offers an improved method of communications and at the same time it provides an excellent return on invested capital, achieved through increased personnel productivity at all levels within the company, as well as through personnel reduction and elimination of many existing, costly communication facilities. The VMS 10 also provides a number of usage reports to monitor the operation of the system.

The three basic features of the VMS 10, DEPOSIT, DELIVERY and INQUIRY, have been simplified to provide an easy to use system. The VMS 10 includes instructional and "canned" messages ("Voice Message System", "VMS", and "Voice-messages" are trademarks of applicants' assignee VMX, Inc. Each of the three basic features of the VMS 10 will be described below.

FIGS. 11 to 14 represent the flow chart for the DEPOSIT feature of the VMS 10. "DEPOSIT" is the procedure by which one or more voice messages are placed into the VMS 10 for subsequent delivery. Referring to FIG. 10, the DEPOSIT procedure is initiated by dialing into the VMS 10 to access the system 600, causing the VMS 10 to answer 602 by playing a canned massage, such as "This is VMS."

A timer is started when the VMS 10 answers a call and identifies itself at step 602. The user then must complete the entire DEPOSIT process within a preset time interval (for example, 4 minutes). Approximately 30 seconds before this interval expires the VMS 10 will begin signaling the user with an alarm, such as a "beep" every 3 seconds. If the user has not completed the DEPOSIT operation by the end of the time interval, the VMS 10 will abort the DEPOSIT operation and terminate the user's access to the system.

After the VMS 10 answers 602, the user then dials a unique authorization number 604 for identification purposes to gain access to the system. The VMS 10 will allow the user a preset amount of time to dial a signed authorization number, e.g., 45 seconds. Upon entry of a valid authorization number, the VMS 10 responds with a short progress tone indicating it is ready to process an addressee 606. When all addresses have been entered, the user dials an End-of-Address indicator, e.g., "0," and VMS 10 will provide a record-mode "idle" tone, such as a repeating "beep-beep . . . " signal. The next step in the DEPOSIT routine 608 determines if the end of record indicator has been entered. If it has not, he returns to step 606 for the entry of an addressee number. If it has determined that a "0" was dialed, the user dials "1," removing the VMS 10 idle tone which enables this to record a voice message 610. At the conclusion of the recording step 610, the user may elect to either DEPOSIT another message 612, inquire for messages 614 or hang up 616.

In the system's step 606 in processing an addressee, the user may dial one or more addresses to which the voice messages are to be sent. "Addressees" are generally no more than telephone numbers, local extension numbers, distant company locations, or "off net" long distance numbers. A system parameter may be entered from the console to set the maximum number of individual addresses which may be entered. In addition, a distribution list code may be used as an address. This is a three digit address which is automatically translated by the VMS 10 into the previously defined individual telephone numbers of the group. The user of the VMS 10 in this way may send a single voice message to a number of people by using a single address, analogous to using a distribution list for a memo or letter. The VMS 10 will then deliver the voice message independently to each person within the group.

The VMS 10's step 604 for processing a user ID is set forth in further detail in FIG. 12. The procedure is initiated by the user dialing the identification code digits 618. The user may dial an "*" 620, if he discovers a dialing error before dialing the last digit. The VMS responds with a single "beep-beep" tone 622 to acknowledge that the user is allowed to redial the identification code. The VMS 10 next validates the identification code of the user 624. In determining the validity of the code 626, the VMS 10 acknowledges if a valid code has been entered 628 with an aud1ble signal, such as a single "beep." This completes the user-ID processing 604 to allow the user to proceed to process an addressee 606 (FIG. 11). However, if the user identification code has been determined to be invalid, the VMS 10 determines if this is the first or second invalid entry 630. If it was the first attempt to enter a valid user code, the VMS 10 plays a canned message 632, such as: "The ID (.sub.----) is not valid. Please try again." The program then returns the user to program step 618 for redialing of the identification code. If the second try for the validity test 630 determines that this is the second entry of an invalid code, the VMS 10 plays a canned massage and hangs up 634. The canned massage at step 634 would be: "The ID you entered is again not valid. Please dial (.sub.----) for information or assistance. Thank you. " There is an alternative to the progress tone provided at program step 628 to the VMS 10's acknowledgement of a valid ID code. A canned massage may instruct the user as follows: "To deposit a message, you may now dial the addressees. For any other function dial the 3 digit special function code." The user may access the VMS 10 through a special code to provide for verbal instructional commands in lieu of progress tones.

FIG. 13 is a flow chart of the process and addressee program step 606 of FIG. 11. In the first program step 635, the user dials digits for an addressee. If the user discovers a dialing error before dialing the last digit he may branch to program step 636 by dialing a "*" to delete the addressee number. The VMS 10 responds with an audible signal, 638 "beep-beep," and allows the user to redial the addressee. Upon the user's entry of the digits for an addressee, the program provides for the VMS 10 to validate the addressee 640. The program step 642 determines the validity of the addressee. If a proper addressee code has been entered, the VMS acknowldeges with an audible signal 644, "beep." If the user discovers a dialing error after dialing a complete addressee and receiving acknowledgement from the VMS 10, he may branch to program 646 by dialing "*" on a touch signaling phone or "7" on a rotary phone. The VMS 10 program next responds with an audible signal 650, "beep-beep" and allows the user to reenter at program step 635 to dial the digits for the addressee. If at the validity determination step 642, the VMS 10 determines that an invalid addressee number has been entered, the signal, "beep-beep-beep," and allows the user to redial the addressee.

Referring to FIG. 14, the record voice message block 610 of FIG. 11 is shown in greater detail. The VMS 10 emits a repetitive audible tone such as an idle tone prior to the recording of any message. The user dials "1" in block 654 to remove the idle tone from the VMS 10 and to allow the user to record a voice messge 656. During the speaking of the voice message, the following dial commands are available to control the recording procedure:

    ______________________________________
    DIAL COMMAND   VMS ACTION
    ______________________________________
    1              Start recording.
    1              Stop recording and return the
                   record mode idle tone.
    3              Back up (approximately 10
                   seconds) and start playing.
    4              Back up to the beginning of the
                   voice message and start playing.
    9              Skip forward (approximately 10
                   seconds) and play.
    99             Skip forward to end of recorded
                   data and return to the record
                   mode idle tone.
    ______________________________________

    ______________________________________
    DIAL COMMAND   VMS ACTION
    ______________________________________
    2              Start Playing.
    2              Stop playing, followed by
                   nonlaying indicator, a periodic
                   "beep."
    3              Back up and play approximately
                   the last 10 seconds.
    4              Back up to the beginning of the
                   voice message and start playing.
    9              Skip forward approximately 10
                   seconds and play.
    99             Skip forward to end of message.
    ______________________________________