Card reader-data link processor4392207Abstract A peripheral-controller for a card reader is designated as a Card Reader-Data Link Processor and is used for controlling and reading data from a card reader for later transmittal to a main host computer. The peripheral controller is made of a slide-in Common Front End card (CFE) and a Peripheral Dependent Board (PDB) card. A PROM control store in the Common Front End provides micro-code operators for the Peripheral Dependent Board circuitry to execute. A memory buffer in the CFE receives and stores both raw data from the card reader and also translated data processed by circuitry in the PDB which can provide selected data formats as ordered by the main host system. Claims What is claimed is: Description FIELD OF THE INVENTION
TABLE O-SS
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(Generalized Pattern)
Status- Status State
Mnemonic Count Usage or Meaning
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Cleared STC = 0
Entered by the DLP when it is cleared. This
status is also shown if the DLP is not present,
it has a PROM parity error, or it has been
taken off-line by the Maintenance Card.
Disconnect STC = 1
Used by the DLP to indicate that no more
transfers are possible during the connection, or
to indicate that the DLP is unable to accept a
new I/O descriptor.
Reserved STC = 2
Reserved for expansion. Detection of this status
results in an error.
Idle STC = 3
Indicates that the DLP can accept a new I/O
descriptor, or that a DLP receiving this new
descriptor requires additional descriptor words.
Read STC = 4
Indicates that data is being transferred to the
host system by the DLP.
Send Description Link
STC = 5
Indicates that the descriptor link is being sent,
to the host system.
Receive Descriptor Link
STC = 6
Indicates that the DLP needs to receive, or is
receiving the descriptor link.
Result Descriptor
STC = 7
Indicates that the result descriptor is being sent
to the host system.
Write STC = 8
Indicates that the DLP needs data from the
host system.
Encoded Status
STC = 9
Indicates that the DLP is sending special status
information on the data lines.
Port Busy STC = 10
The host is waiting on port busy, but the LEM
has a request from another DLP.
I/O Descriptor LPW
STC = 11
Indicates that the DLP requires the I/O
descriptor LPW.
Break STC = 12
Indicates the end of a data message, and the
DLP now wants an LPW.
Break Enable
STC = 13
Indicates the desire by the DLP to transmit
another message to the host system. The host
system may accept or refuse this request.
Character Transfer
STC = 14
Used by certain DLPs to resolve the contents
of the last data word that has been received
from the host system.
Result Descriptor LPW
STC = 15
Indicates that the final word of the result
descriptor is being sent to the host system and
is followed by the approriate LPW.
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INFORMATION TRANSFERS: All information transfers between the DLP I/O subsystem and the host system are asynchronous and accomplished by means of control strobes. On the other hand, transfers between Distribution Card and the DLP are synchronous. The various types of information transfers are briefly described hereinunder. SYSTEM TRANSMIT: When information is ready to be sent to the I/O subsystem, the host system emits a pulse (SIO) to the DLP I/O subsystem. When the subsystem has received data it then emits a pulse (LCPST) over to the host system. At this point the next transfer takes place beginning with a SIO signal. Resynchronizing of the asynchronous signals occurs in the Distribution Card (DC). Upon receipt of the host system strobe, the Distribution Card synchronously sets the STIOL level to the DLP. STIOL is synchronously reset when LCPSTL is "true" from the DLP. The answer to the host system occurs as soon as LCPSTL is "true" from the DLP. If this is the case, STIOL is "true" for only one clock period and the host system strobes are immediately answered. Data from this system is latched in the Distribution Card on the trailing edge of the host system strobe. SYSTEM RECEIVE: When the host system can accept another word of data from the DLP I/O subsystem, it emits a pulse (SIO) to the subsystem. In turn, when the subsystem is capable of sending a new word it emits a pulse (LCPSTL) to the host system. Upon receipt of the host system strobe, the Distribution Card synchronously sets the STIOL "level" to indicate that a new cycle can begin. The new cycle is completed and the host system is strobed when LCPSTL is "true" and STIOL is synchronously reset. LCPSTL can be "true" before the SIO is received. If this is the case, STIOL is "true" for only one clock period and the host system's strobe pulses are immediately followed by subsystem strobe pulses with new data. Data to the host system is latched in the Distribution Card on the leading edge on the subsystem strobe pulse to the host system. LINE TURN: In the course of a message transfer, it is sometimes necessary to change the information direction. The host system and the DLP coordinate in this turnaround of bi-directional lines. The DLP controls the data direction in the base module with a backplane line called I/O send (IOSND/). I/O send, when low, directs the data lines toward flow into the host system. The DLP initiates the "line turn" with a status transition that requires a change in information direction. Two situations occur here: 1. Host System Transmit to Host System Receive: If the host system detects a status change when it receives an acknowledge (on the information transfer that requires it to receive information) the host system sends another strobe to acknowledge the "status change". The DLP detecting the host systems "acknowledge" raises the I/O send and begins transmission to the host system. 2. Host System Receive to Host System Transmit: If the host system acknowledges an information transfer in conjunction with a status change that requires a line turnaround, the DLP inactivates the I/O send and sends another DLP strobe to the host system. When the host system receives the "acknowledge" (that the base lines have been turned), then the host system begins to transmit to the DLP. DLP BASE ADDRESS: As the DLP base backplane is made up of common lines running the length of the base, the printed circuit cards, which form the DLP, can function in almost any set of slide-in card locations. The base address chosen for a DLP is "jumpered" on the DLP card (FIG. 3). The base address serves only to make the DLP unique within the base. The DLP's global priority is not affected by its base address. This priority is selected on the Distribution Card (DC). There are two backplane line functions that are linear: the DLP request and the DLP address. They are allocated eight lines each (0-7). The request and address jumpers must correspond. DLP ID (IDENTIFICATION): Upon receiving a TEST/ID OP code, the DLP returns a two-word result descriptor (R/D). The second word contains DLP ID information. Digits A and B of the ID word are a predetermined bit pattern specifying the type of DLP. Digits C and D of the ID word are a bit pattern specified by field-installed jumpers, and are used to uniquely identify the DLP. The ID word for the DLP is formatted as follows: ##STR1## I/O DESCRIPTORS: The I/O descriptor is transmitted in 17 parallel bits including odd parity. The DLP OP codes are limited to the following four types. 1. Read 2. Write 3. Test 4. Echo Operations that do not transfer data are considered "test". Thus, a test is defined as an operation that results in the host system receiving a result descriptor only. Echo is a maintenance operation that causes the DLP to accept a buffer load of data from the host system, and then return it back to the host system. This allows a quick confidence check of the I/O data path as far as the DLP buffer is concerned. Also, the various translation logics can be checked by an echo operation. DLPs that require further information associated with the basic operations obtain that information in the form of variants. The first I/O descriptor transfer contains the four OP code bits and up to 12 variant code bits. Further variants are transferred in 16 parallel bit increments and are not limited to any size. RESULT DESCRIPTORS: A result descriptor is transmitted to the host system along 17 parallel bits including odd parity. The first four bits (one digit) of the first word of the DLP result descriptor are common for every DLP. These first four bits are shown as follows:
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Bit Significance
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A8 Not ready peripheral
A4 I/O Descriptor error
A2 MLI Vertical parity error
A1 MLI longitudinal parity error
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The B, C and D digits of the "DLP result descriptor" will vary according to the type of data link processor involved. FIG. 4A shows a block diagram of the Common Front End, 10.sub.c, (which is sometimes designated as a "Common I/O" unit). The maintenance control bus 30, coming from the Maintenance Card 20.sub.0m provides input to a receiver 15 which has one output to the address multiplexer 12 and another output on bus 37 to the peripheral dependent board (PDB) 80. The Distribution Card data bus 32 provides input to receiver 16 while line 31 provides another input (RCV/) to receiver 16 from the peripheral dependent board 80. One output of receiver 16 is fed to the address multiplexer 12; while the other output forms bus 38 as a data bus to the PDB 80. Receiver 17 has one input from the Maintenance Card data bus 34 and another control. SIMRCV/ (simulate receive) input line 33 from the peripheral dependent board PDB 80. Receiver 17 provides an output to the address multiplexer 12 and an output to the data bus 38. Bus 35 from PDB 80 provides another input to the address multiplexer 12, while the low order address bit (AO) from the PDB 80 on line 16 provides an input to the PROM 13. PROM 13 provides a bus to the PROM register 14, which register also has an input from AND gate 24 which has two inputs, one of which constitutes the PROMCLK/ line and the other input is from the parity check circuit 18 to signal whether or not a parity error has been detected. PROM register 14 has an output on bus 40 for maintenance display signals and connects to the common backplane of the base module. Another output of the PROM register 14 connects to the Request Status Latches circuit 19 which feeds its output to drivers 20 to provide signals designated IOSF (I/O Send flip-flop) Status, REQ (request) and EMREQ (emergency request) which are interrupts to the host. This bus also connects to the common backplane. The PROM register 14 outputs include: the control lines of bus 43, the PDR usage bus 44 and the multiplexer enable bus 45, all of which connect to the peripheral dependent board, PDB 80. A Random Access Memory or RAM buffer storage 22 will be seen having four sets of inputs from the peripheral dependent board 80. These inputs are: the chip select line 50, the write enable line 51, the RAM data in-bus 52 and the RAM address bus 53. The output bus of RAM 22 is designated as the RAM data-out bus 22.sub.a which connects to the peripheral dependent board 80. COMMON FRONT END-CARD (CFE) Referring to FIG. 4A which shows a block diagram of the Common Front End (CFE) 10.sub.c, the central operative element of the Common Front End is the PROM controller and storage unit 13. The PROM storage 13 consists of 13 separate PROM chips which may have a total storage capacity of 1024 52-bit words. This includes odd parity. As seen in FIG. 4A, the Common Front End also contains the receivers 15, 16 and 17, for the data link processor (DLP) interfaces with the Distribution Card on data bus 32 and the maintenance card on control bus 30. The "enable" signals for these buses are driven by the peripheral dependent board (PDB) 80. The data link processor RAM storage buffer 22 has a capacity of 1024 17-bit words which includes odd parity. The RAM storage unit 22 is controlled entirely by the peripheral dependent board 80. The following Table IA lists a glossary of various signals and terms used in the Common Front End. The Table IB is a glossary of terms used in the peripheral dependent board PDB 80 of the Card Reader-Data Link Processor.
TABLE IA
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COMMON FRONT END CARD GLOSSARY OF TERMS
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A0 BROP
PROM address bit 0. When high, a 16-way PROM address branch is se-
lected.
A1
PROM address bit 1. BRST
When high, use stack register for PROM address.
A2
PROM address bit 2. BUFFEND/
Active low, from PDB, used to stop burst mode.
A3
PROM address bit 3. CLK8
8-megahertz clock.
A4
PROM address bit 4. CLK8/
8-megahertz clock not.
A5
PROM address bit 5. CLKEN
High active, clock conditioning level.
A6
PROM address bit 6. CLKEN/
Low active, used to enable clock on PDB and
A7 CFE.
PROM address bit 7.
CLKST
A8 When high, PROM clock is disabled.
PROM address bit 8.
CLOCK..0
A9 8-megahertz backplane clock from MC.
PROM address bit 9.
CLOCK/
ADLOC/ CFE control logic clock.
When high, DLP is MC addressed or DLP address
is not valid. CLR/
Active low, logic clear term.
ADRVLD/0
When low, LOCnn/.0 is valid.
CLRD
AF Active high, logic control term.
When high, strobe I/O has been received.
AF/ CLRLAT
When low, strobe I/O is sent to the PDB.
Active high, logic term used to control SCLR.
BASLCL/0 CONECT/
When low, the base is in local.
Active low, DC is connected to DLP.
BR6
A branch line from PDB for PROM address selec-
CS/
tion. Active low, RAM chip select level.
DATAA8/0 - DATAPR/0 LCLCLR/0
17-bit data bus from DC.
Active low, clear level from MC.
DBUSA8 - PARITY/0 LCPAD
17-bit data bus. Active high, DLP is addressed by DC or MC.
DBUSn LCPAD/
9-bit bus used as input to PROM address MPXs.
Active low, DLP is addressed by DC or MC.
DIOSND/0 LCPADF
Active low, I/O SEND Level to MC.
Active high, DLP is addressed by DC or MC.
DLCPST/0 LCPCON/0
Active low, DLP strobe to MC.
Active low, DLP is connected to DC.
DPLY01/0- DPLY10/0 LCPRQn/0
Ten display lines to MC.
Active low, DLP request levels to DC.
DSEL1/- DSEL4/ LCPSTL
Multiplexor address lines for data selection to dis-
Active high, DLP strobe level.
play lines.
LCPSTL/0
DESL8/ Active low, DLP strobe level to DC.
Active low, multiplexor chip select line for input
to display lines. LCSTU1/0- LCSTU8/0
Four-DLP status lines to DC.
DSIMA8/0 - PARSIM/0
17-bit data bus from MC.
LOCAL/
Active high, DLP is not MC addressed, or address
DSIMn is not valid.
9 bits of DSIM lines, used to become DBUSn.
LOCAL/.1
DSTAT1/0- DSTAT8/0 Active low, DLP is MC addressed.
Four DLP status lines to MC.
LOCnn/.0
EMREQ Local address lines from MC.
Active high, DLP emergency request.
MLCPAD/0
EMRREQ/0 Active low, DLP is addressed MC.
Active low, DLP emergency request to DC.
MSTCLR/0
GPRIF/ Active low, base power-up clear from MC.
Peripheral bus control term to PDB.
MSTIOL/0
GPRIF/.0 Active low, maintenance strobe I/O from MC.
Active low, from MC, disconnects PDB peripheral
cable. MTERM/.0
Active low, maintenance terminate from MC.
GRP0/
Active low, controls 16-line display to MC.
OFFLN
INRAMA8 - INRAMPR Active high, MC has localized the CFE.
17 RAM input data lines.
OFFLN/
IOSF Active low, the DLP is in local.
I/O SEND flip-flop to PDB.
IOSND/.0 OFFLNE/0
I/O SEND to DC. Active low, off-line control level from MC.
OPDEC1 START/.0
PROM address A0 bit from PDB when 16-way
Active low, from MC, allows clock in
single-pulse
branching. mode.
OPDECX STCKA8- STCKA0
PROM address bits A1-A3 from PDB, when
PROM address lines used during stack branching.
16-way branching.
STCLKEN
PARSIM/0 Active when going high, counts up the stack
regis-
Data simulate parity line from MC.
ter +1.
PER STIOL/.0
Active high, PROM output parity is even (an er-
Active low, strobe I/O from DC.
ror).
STOPB
PERF Active high, used to stop burst mode.
Active high, PROM parity error is present.
STOPB/
PERF/ Active low, stop burst mode to PDB.
Active low, PROM parity error (disables clocks).
STOPF
PROMCLK/ A 2-way PROM branching bit.
PROM clock.
SW1/
RAM Active low, used to do PROM maintenance read.
17 bits of RAM addressed by RAMAD0
RAMAD9. SWH.1/.0
Active low, SW1/ from MC.
RAMA8 - RAMPR
17 bits of RAM output information.
TERMF
A 2-way PROM branching bit.
RCV/
Active low, enables data bus from DC.
TERMF/
Active low, used to terminate burst mode.
REQ
Active high, DLP request for DC attention.
TERM/..0
Active low, terminate level from DC.
SCLR
Active high, synchronized clear, sets PROM ad-
TEST5 and TEST6
dress = 0. 2-way PROM branching bits from PDB.
SEL2/ - SEL6/ TEST8- TEST14
Active lows, to PDB, for MPX enables.
2-way PROM branching bits from PDB.
SELCLR/0 WE/
Active low, clear line from DC.
Active low, RAM write enable level.
SEMREQ/ #BRANCH1- #BRANCH5
Active low, an emergency request is present in the
PROM branching control lines
base.
#CONST0- #CONST7
SIMRCV/ Multipurpose PROM outputs, PDB-dependent.
Active low, enable MC DSIM lines, for PDB.
#G3 - #L4
SP/....0 PDB dependent PROM outputs (see PDB Glossary
Active low, single-pulse mode from MC.
of Terms).
#LCPSTL/
ST1-ST8 Active low, DLP strobe level, from PROM con-
DLP status lines internal CFE.
toller to DC.
#LDINT/ #NEXT0- #NEXT8
Active low, (load interface) PROM MLI bus con-
PROM address bits.
trol level.
#PARITY
#LDSTK/ PROM parity bit (odd).
Active low, allows stack register load of current
PROM address. This level is held high during all
+5V
microcode subroutines. VCC from power supply.
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DISTRIBUTION CARD INTERFACE: As previously indicated in FIG. 2, data link processors are housed in a base module unit. Each data link processor, consisting of two cards, slides into the base module housing having a common backplane to which the printed circuit boards of a data link processor are connected. All communications between the Common Front End 10.sub.c and the Distribution Cards such as 20.sub.0d, 20.sub.1d are performed through the data link processor base module backplane as 20.sub.0B of FIG. 3. The backplane is common to all cards that are installed in a base module. Table II shows a list of all the backplane signals that occur on the Distribution Card interface to the Common Front End. The 17-bit wide data portion of the bus 32, FIG. 4A, is received from Distribution Card (DC) on the Common Front End (CFE). This same 17-bit bus is driven in the opposite direction (by drivers on the PDB) when the data link processor is sending data back to the Distribution Card. The enabling levels that control the direction of this bus are generated on the peripheral dependent board.
TABLE II
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Distribution Card/CFE Interface
Level Pin # Direction
Definition
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LCSTU8/0 123 to DC DLP status bit 8
LCSTU4/0 023 to DC DLP status bit 4
LCSTU2/0 126 to DC DLP status bit 2
LCSTU1/0 026 to DC DLP status bit 1
LCPCON/0 074 to DC DLP is connected
IOSND/.0 124 to DC DLP is sending
EMRREQ/0 191 to DC DLP has emergency request
LCPRQ7/0 163 to DC DLP #7 has request
LCPRQ6/0 063 to DC DLP #6 has request
LCPRQ5/0 164 to DC DLP #5 has request
LCPRQ4/0 064 to DC DLP #4 has request
LCPRQ3/0 165 to DC DLP #3 has request
LCPRQ2/0 065 to DC DLP #2 has request
LCPRQ1/0 166 to DC DLP #1 has request
LCPRQ0/0 066 to DC DLP #0 has request
LCPSTL/0 024 to DC DLP strobe
STIOL/.0 127 to CFE Strobe I/O
TERM/..0 072 to CFE Terminate
SELCLR/0 167 to CFE Selective clear
LCPAD7/0 176 to CFE DLP #7 is addressed
LCPAD6/0 076 to CFE DLP #6 is addressed
LCPAD5/0 177 to CFE DLP #5 is addressed
LCPAD4/0 077 to CFE DLP #4 is addressed
LCPAD3/0 178 to CFE DLP #3 is addressed
LCPAD2/0 078 to CFE DLP #2 is addressed
LCPAD1/0 179 to CFE DLP #1 is addressed
LCPAD0/0 079 to CFE DLP #0 is addressed
DATAA8/0 106 Bi-Dir Data bit
DATAA4/0 006 Bi-Dir Data bit
DATAA2/0 108 Bi-Dir Data bit
DATAA1/0 008 Bi-Dir Data bit
DATAB8/0 110 Bi-Dri Data bit
DATAB4/0 010 Bi-Dri Data bit
DATAB2/0 117 Bi-Dri Data bit
DATAB1/0 017 Bi-Dir Data bit
DATAC8/0 119 Bi-Dri Data bit
DATAC4/0 019 Bi-Dir Data bit
DATAC2/0 121 Bi:Dir Data bit
DATAC1/0 021 Bi-Dri Data bit
DATAD8/0 132 Bi-Dri Data bit
DATAD4/0 032 Bi-Dir Data bit
DATAD2/0 134 Bi-Dir Data bit
DATAD1/0 034 Bi-Dir Data bit
PARITY/0 136 Bi-Dir Data parity bit (odd)
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MAINTENANCE CARD INTERFACE: All communications between the Common Front End 10.sub.c and the Maintenance Card (as 20.sub.0m) take place on the data link processor's base module backplane. Table III shows a list of all the backplane signals that occur between the Common Front End and the Maintenance Card.
TABLE III
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Maintenance Card/CFE Interface
Level Pin # Direction
Definition
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DSTAT8/0 044 to MC DLP ststus bit 8
DSTAT4/0 145 to MC DLP status bit 4
DSTAT2/0 045 to MC DLP status bit 2
DSTAT1/0 146 to MC DLP status bit 1
DLCPST/0 140 to MC DLP strobe
DIOSND/0 144 to MC DLP is sending
MSTIOL/0 040 to CFE Strobe I/O
MTERM/.0 184 to CFE Terminate
MLCPAD/0 154 to CFE DLP is addressed
BASLCL/0 161 to CFE Base is in local
MSTCLR/0 172 to CFE Base clear
LCLCLR/0 174 to CFE Local clear
SWH.I/.0 058 to CFE Maintenance switch #1
SP/....0 147 to CFE Single-pulse mode
START/.0 149 to CFE Allow clock(s)
CLOCK..0 048 to CFE 8 Mhz clock
ADRVLD/0 043 to CFE Local address is valid
LOC16/.0 187 to CFE Local address bit 16
LOC08/.0 087 to CFE Local address bit 8
LOC04/.0 188 to CFE Local address bit 4
LOC02/.0 088 to CFE Local address bit 2
LOC01/.0 189 to CFE Local address bit 1
OFFLNE/0 073 to CFE DLP is off line
GPRIF/.0 061 to CFE Gate off peripheral interface
DSEL8/.0 060 to CFE Display select bit 8
DSEL4/.0 085 to CFE Display select bit 4
DSEL2/.0 186 to CFE Display select bit 2
DSEL1/.0 086 to CFE Display select bit 1
DPLY01/0 054 to MC Display line
DPLY02/0 155 to MC Display line
DPLY03/0 055 to MC Display line
DPLY04/0 156 to MC Display line
DPLY05/0 056 to MC Display line
DPLY06/0 157 to MC Display line
DPLY07/0 057 to MC Display line
DPLY08/0 067 to MC Display line
DPLY09/0 168 to MC Display line
DPLY10/0 068 to MC Display line
DSIMA8/0 112 Bi-Dir Data simulate line A8
DSIMA4/0 012 Bi-Dir Data simulate line A4
DSIMA2/0 113 Bi-Dir Data simulate line A2
DSIMA1/0 013 Bi-Dir Data simulate line A1
DSIMB8/0 114 Bi-Dir Data simulate line B8
DSIMB4/0 014 Bi-Dir Data simulate line B4
DSIMB2/0 115 Bi-Dir Data simulate line B2
DSIMB1/0 015 Bi-Dir Data simulate line B1
DSIMC8/0 027 Bi-Dir Data simulate line C8
DSIMC4/0 128 Bi-Dir Data simulate line C4
DSIMC2/0 028 Bi-Dir Data simulate line C2
DSIMC1/0 129 Bi-Dir Data simulate line C1
DSIMD8/0 029 Bi-Dir Data simulate line D8
DSIMD4/0 130 Bi-Dir Data simulate line D4
DSIMD2/0 030 Bi-Dir Data simulate line D2
DSIMD1/0 131 Bi-Dir Data simulate line D1
PARSIM/0 137 Bi-Dir Data simulate parity line (odd)
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MAINTENANCE FACILITIES: In FIG. 2 certain maintenance facilities are provided. These consist of a console 50.sub.c (which may include a cathode ray tube CRT, a mini-disk, etc.) and the Maintenance Card, as 20.sub.0m, plus other software packages and hardware which are included in the DLP. Under programmatic control, the console 50.sub.c can be used to manipulate the DLP in such a manner as to determine its internal state for given operations and to compare it to a known correct state by use of the Maintenance Card 20.sub.0m. Thus, diagnosis of a failing DLP can be made. The console is the interface between the host system and the host system operator, as well as being the maintenance interface to the I/O subsystem. Maintenance of the Card Reader-Data Link Processor originates at the console, when in the off-line mode; and from the host system, when in the on-line mode of operation. A data base can be supplied on flexible diskettes or magnetic tape to perform diagnosis of the data link processor (DLP). The selection of the test and type of module can be done at the host system by a field engineer or a host system operator. DIAGNOSTIC TESTING MODES: There are two modes of diagnostic testing, (a) off-line and (b) on-line. In either mode the units undergoing tests are not available to the host system as a resource and must be placed off-line prior to running diagnostics. Diagnostic programs use the console-to-maintenance card interface in the diagnosis of the subsystem modules. These programs can perform a card test on the addressed unit by means of a maintenance data base that is stored on flexible diskettes or is resident in the host system. OFF-LINE MODE: This mode implies the following: 1. The host systems resources are not available. 2. The test data base is console-diskette-resident. 3. The operator unit supply control information. ON-LINE MODE: This mode implies the following: 1. The host systems resources are available. 2. The test data base is host-system-resident. 3. A host resident program performs the diagnosis. Confidence test programs can be developed which use the massage level interface (MLI) to ascertain a confidence level of the I/O subsystem unit or units under test. These tests may be used to isolate a failing unit so that maintenance can be invoked to determine if the cause of the failure is in an I/O subsystem module or in the peripheral device. PERIPHERAL-DEPENDENT BOARD INTERFACE: As seen in FIG. 3 the peripheral dependent board (PDB) and the Common Front End card are provided with foreplane connectors 80.sub.a, 80.sub.b, 80.sub.c, 80.sub.d and 80.sub.a1, 80.sub.b1, 80.sub.c1. The interface between the Common Front End and the peripheral dependent board is made of three 50-pin foreplane connectors 80.sub.a, 80.sub.b and 80.sub.c. Table IV lists the connectors and shows the pin numbers together with the logic names of the signals involved specifically for the Card Reader-Data Link Processor.
TABLE IV
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CFE Foreplane Connectors: CR-DLP
Pin #-Side $-Side
Connector Number Signal Signal
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Element 80a1, FIG. 3
1 00 RAMA4 RAMPAR
1 01 RAMA1 RAMA8
1 02 RAMB4 RAMA2
1 03 RAMB1 RAMB8
1 04 GND RAMB2
1 05 RAMC4 RAMC8
1 06 RAMC1 RAMC2
1 07 RAMD4 RAMD8
1 08 RAMD1 RAMD2
1 09 INRAMB8 INRAMA8
1 10 INRAMB4 INRAMA4
1 11 INRAMB2 INRAMA2
1 12 INRAMB1 INRAMA1
1 13 INRAMC2 INRAMC8
1 14 INRAMC1 INRAMC4
1 15 SIMRCV/ RCV/
1 16 DBUSA4 DBUSA8
1 17 DBUSA1 DBUSA2
1 18 DBUSB4 DBUSB8
1 19 DBUSB1 DBUSB2
1 20 GND DBUSC8
1 21 DBUSC4 DBUSC2
1 22 DBUSC1 DBUSD8
1 23 DBUSD4 DBUSD2
1 24 DBUSD1 DBUSPR
Element 80b1, FIG. 3
2 25 WE/ GND
2 26 RAMAD9 CS/
2 27 RAMAD7 RAMAD8
2 28 RAMAD5 RAMAD6
2 29 GND RAMAD4
2 30 RAMAD3 RAMAD2
2 31 RAMAD1 RAMAD0
2 32 GPRIF/ PERF/
2 33 IOSF DSEL8/
2 34 DSEL4/ DSEL2/
2 35 DSEL1/ SW1/
2 36 GND CONECT/
2 37 GND LOCAL/
2 38 GND CLR/
2 39 GND SEMREQ/
2 40 INRAMD2 INRAMD8
2 41 INRAMD1 INRAMD4
2 42 TEST14 INRAMPR
2 43 TEST12 TEST13
2 44 TEST10 TEST11
2 45 GND TEST9
2 46 TEST8 TEST6
2 47 TEST5 OFFLN/
2 48 AF/ BUFFEND/
2 49 GND CLKEN/
Elemental 80c1, FIG. 3
3 50 OPDEC4 OPDEC8
3 51 OPDEC1 OPDEC2
3 52 SEL6/ TERMF/
3 53 SEL4/ SEL5/
3 54 GND BR6
3 55 #L3 #L4
3 56 #L1 #L2
3 57 #K3 #K4
3 58 #K1 #K2
3 59 #J3 #J4
3 60 #J1 #J2
3 61 #I3 #I4
3 62 #I1 #I2
3 63 #H3 #H4
3 64 #H1 #H2
3 65 STOPB/ #G4
3 66 #CONST6 #G3
3 67 #CONST4 #CONST7
3 68 #CONST2 #CONST5
3 69 #CONST0 #CONST3
3 70 GND #CONST1
3 71 #BRANCH3 #BRANCH2
3 72 BRANCH1 SEL3/
3 73 SEL2/ GND
3 74 GND A0
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The following Table V is a listing of the signal lines connecting the Peripheral (Card Reader) to the peripheral-connector on the PDB card 80.
TABLE V
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Signal Lines Between Card Reader and
Peripheral Dependent Board (PDB 80)
Peripheral
Connector 20-Conductor Signal
On PDB Coax Cable Name
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$75
$76
$77 $C INFO04/
$78 $D INFO12/
$79 $E CSP/
$80 $F INFO02/
$81 $G INFO10/
$82 $H CRRL/
$83 $I "FLOATING"
$84 $J SCCL/
$85 $K CREL/
$86 $L INFO01/
$87 $M INFO08/
$88 $N INFO03/
$89 $P INFO06/
$90 $Q INFO11/
$91 $R INFO05/
$92 $S INFO09/
$93 $T CCL/
$94 $U INFO07/
$95 $V "FLOATING"
$96 $W "FLOATING"
$97
$98
$99
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NOTES
1. #75 thru #99 are grounded.
2. $75 thru $76 and $97 thru $99 are grounded.
THE PROM CONTROL-STORE: The PROM control-store 13 shown in FIG. 4A is made up of 13 PROM chips located on the CFE card 10.sub.c. These chips are combined to make up a 52-bit micro-code instruction word. The address lines of the 13 PROM chips are bused together so that all of the individual address lines are common to every single chip. The chip select on each PROM chip is always enabled (grounded). The data output of the 13-chip PROM matrix forms the 52-bit word. This word is read out of the address that is present on the common input address line A0-A9 (FIG. 4A). The PROMs herein are basically unclocked devices so that means are required to synchronize their outputs with an eight megahertz clock which feeds through gate 24. This is done by making use of register chips 14. The register chips contain eight flip-flops each. Thus, seven chips are used to synchronize and latch the 52-bit micro-code word. This latched micro-code instruction word is used to control the operation of the entire data link processor. Every eight megahertz clock pulse latches the next subsequent word into the register chip 14. Different types of data link processors require their own unique micro-code. Thus, all Common Front End cards will contain identical hardware except for the 13 PROM chips. Although the PROM word physically contains 52-bits, only 49 bits are used by the micro-code program. The remaining three bits are not parity checked. Tables VIa and VIb indicate that 49-bit micro-code word, by bit position and name. All PROM output signal names are preceded by a "pound sign" (#) so that they are easily recognizable. Bit 32 of the micro-code word is the odd parity bit. The CFE card is made to continually check for odd parity and it halts the micro-code program if a parity error (even parity) occurs on any 49-bit PROM micro-code word.
TABLE VIa
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PROM Output Signals
Bit Name Bit Name
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48 #NEXT9
47 #NEXT7 23 #LDINT/
46 #NEXT6 22 #LDSTK/
45 #NEXT5 21 #G3
44 #NEXT4 20 #G4
43 #NEXT3 19 #H1
42 #NEXT2 18 #H2
41 #NEXT1 17 #H3
40 #NEXT0 16 #H4
39 #NEXT8 15 #11
38 #BRANCH1 14 #12
37 #BRANCH2 13 #13
36 #BRANCH3 12 #14
35 #BRANCH4 11 #J1
34 #BRANCH5 10 #J2
33 #LCPSTL/ 09 #J3
32 #PARITY 08 #J4
31 #CONST7 07 #K1
30 #CONST6 06 #K2
29 #CONST5 05 #K3
28 #CONST4 04 #K4
27 #CONST3 03 #L1
26 #CONST2 02 #L2
25 #CONST1 01 #L3
24 #CONst0 00 #L4
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MAINTENANCE CONTROL: As seen in FIG. 4A, the Common Front End contains receivers 15, 16, 17 which include decoding logic. Receiver 17 is used for operation of the maintenance control lines 33, 34. Table VII shows the addressing signals for maintenance mode of the data link processor. Thus, this Table lists all possible Maintenance Card to Common Front End addressing codes with the response of any given data link processor. The Maintenance Card (MC) has the ability to address any one of eight DLPs in the base module.
TABLE VII
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Address Codes: DLP Maintenance Mode
Addressing (Maintenance Card to CFE)
Line Address Address
Local Valid Equal Action
(BASLCL/0)
(ADRVLD/0)
(LOCnn/.0)
Produced
__________________________________________________________________________
1 1 X Normal on-line mode
1 0 1
1 0 0 Standard local mode, all
maintenance available
0 0 0 Local Mode with base in
local
0 0 1 Base in local and the DLP
clocks are disabled
0 1 X Base single-pulse
__________________________________________________________________________
1 = high.
0 = low.
X = don't care.
The high order address line from the Maintenance Card (LOC 16/.0) must be "high" in order to address a DLP. It will be seen that all backplane signals are low active. The other four address lines provide encoding for DLP selection. The CFE does not decode the maintenance address until the Maintenance Card indicates the address is valid and stabilized by driving ADRVLD/0 low. The Maintenance Card drives four lines which are used to enable unique maintenance features in any given DLP or connection module. When in local mode, the CFE uses one of these lines (SWH.1/.0) for allowing the Maintenance Card to drive the address lines of the CFE PROM 13. When this line (SWH.1/.0) is low, the peripheral dependent board drives RCV/high and drives SIMRCV/low, as well as not driving the 17-line data bus 32. Table VIII shows a list of the Maintenance Card lines which drive the PROM address lines in this local mode. This feature of the maintenance operation is used to verify PROM controller 13 integrity.
TABLE VIII
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Maintenance Lines Driving PROM Address
PROM
Address Maintenance
Line Line (Data Simulation)
______________________________________
A9 DSIMC8
A8 DSIMC4
A7 ASIMA8
A6 DSIMA4
A5 DSIMA2
A4 DSIMA1
A3 DSIMB8
A2 DSIMB4
A1 DSIMB2
A0 DSIMB1
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RAM BUFFER: The Common Front-End 10.sub.c of FIG. 4A contains a random access memory buffer (RAM) 22. This buffer memory 22 has a specifically designed organization (FIG. 4F) for use in storage of data from the Card Reader mechanism. This RAM buffer (data RAM) consists of 1,024 17-bit words. All inputs and outputs to this RAM are received by or driven by the peripheral dependent board PDB 80. The designation for the open collector line (60 nanosecond read access RAM) is RWON. This storage area is used to store the data, the OP code, the descriptor links, the descriptor links longitudinal parity word (LPW) and the various flags that are required to properly control the operation of the data link processor. DLP ADDRESS AND REQUEST JUMPERS: There are eight backplane lines which are used by the Distribution Card(s) to address any one given data link processor (DLP). Likewise, eight backplane lines are used by the data link processors (DLPs) to indicate a service request to the Distribution Cards. The 16 lines are unique in that only one data link processor (DLP) can use a given request line. Further, the request lines are graded by priority. Once the priority of a data link processor is determined, that priority request line is "jumpered" for use on the Common Front End Card (FIG. 3). The request and the address lines are identically numbered and operate as pairs. Therefore, once a request priority level is determined and jumpered, the corresponding address line is jumpered on the Common Front End Card. DLP LOCAL ADDRESS JUMPERS: The Common Front End Card requires a minimum of two and a maximum of three jumpers (FIG. 3) to implement its local maintenance address. This address is used by a Maintenance Card, as 20.sub.0m, to address a data link processor as 20.sub.00. The data link processor's local address must always correspond to its on-line DLP address. STACK REGISTER: The stack register 11 consists of three binary counter chips. This register contains the value of the current PROM address, or the value of the address to be used when returning from a subroutine by way of a stack-branch operation. The Card Reader-Data Link Processor will be seen to be made of two slide-in printed circuit cards. These are the Common Front End (CFE) card and the Peripheral Dependent Board (PDB). Each of these two boards are totally different in function and structure; however, when they are used together they make up the totality of the Card Reader DLP. The primary function of the CFE 10 is to provide a device in which to store and execute the applicable micro-code. The micro-code is used to sequence the operation of the data link processor (DLP). The Random Access Memory (RAM.sub.22) is housed on the Common Front End Card and provides internal data link processor storage for various uses such as data storage, translation storage, etc. The peripheral dependent board (PDB), on the other hand, contains the necessary logic to interface the peripheral device (as, for example a Card Reader) to the host system through the message level interface (MLI). (The message level interface 15.sub.i will also be seen in U.S. Pat. No. 4,162,520 in FIGS. 1A, 2 and 3). The logical elements of the PDB are controlled by using the micro-code coming from the Common Front End (CFE). However, also, many signals are passed from the peripheral dependent board to the Common Front End to allow logical decision-making by the micro-code. As seen in FIG. 4A there are interfaces to the front plane (double arrow) and to the backplane (single arrow) which involve the Maintenance Card. These MC lines will be seen as lines 30, 34 and 40. MAINTENANCE CARD CONNECTION: There is a Maintenance Card Common Front End interface (MC/CFE) which is used when the Maintenance Card (MC) requires connection to a data link processor in order to perform normal maintenance functions. The maintenance card tries to connect to a DLP by driving the appropriate local maintenance address line (LOCnn/.0) and the signal ADRVLD/0 (address valid) low. This action causes the addressed CFE 10.sub.c to recognize the MC connection and to drive the logic term LOCAL/.1 low. The LOCAL/.1 term is used to enable a backplane receiver chip which allows the MC to take the DLP off-line (OFFLINE/0 signal coming from the MC goes low). If the MC takes a DLP off-line, it is unavailable to the host system. If the DLP is off-line it does not see any DC (Distribution Control Card) attempts at connection, and all DLP requests to the DC are inhibited. The Maintenance Card always takes the data link processor off-line when maintenance routines are called for. This is done so that maintenance functions (such as single-pulse, and PROM verification) do not interfere with normal distribution control card operations to the on-line data link processors. The logic term LOCAL/.1, when low, is also used to enable the following functions: 1. It allows GPRIF/.0 (from the Maintenance Card) to turn off the data link processors peripheral interface. 2. It becomes LOCAL/ which is used by the peripheral dependent board PDB for bus interface directional control logic. 3. It is used to allow the Maintenance Card (MC) local clear and PROM verification (SW1/) function. 4. It is used by the Common Front End Card (CFE) for the development of the clock-enable term CLKEN. DISTRIBUTION CARD CONNECTION: The following discussion involves the connection mechanism as used by the Distribution Control Card/Common Front End Card interface (DC/CFE) when the Distribution Control Card requires connection to a data link processor. This connection will be initiated by a Distribution Control Card (DC) poll test or by a data link processor (DLP) initiated poll request. The connection logic is shown in FIG. 4D. The CONST lines 4-7 are fed as input to a 4-bit binary counter J3-C. The output of this counter is fed to a tri-state inverter C4-C to provide, as output, the "status" lines LCPSTU--. The data link processor address LCPADn/0 and the off-line signal OFFLN provide inputs to buffer chip M5-C whose output is fed through inverter P4-C to form the LCPAD signal to NAND gate M3-C. NAND gate M3-C also has signal inputs for parity error (PERF/) and off-line (OFFLN/). The output of NAND M3-C is the signal CONECT/ which connects to the PDB bus directional control PROM and also provides inputs to inverters C4-C, C4-C1, E4-C and also to the buffer F4-C. The CONECT/ also is formed as input to NAND B3-C having an output which is fed to NOR gate A4-C. The NOR gate A4-C is fed to inverter B4-C to form the logic control signal CLRD. The outputs of the inverter C4-C1 form the signal IOSND/.0 (input-output send) and the signal LCPCON/0 (data link processor connected). The buffer F4-C provides a distribution card strobe output and a distribution card terminate signal. The inverter E4-C provides a strobe level signal LCPSTL/0 (data link processor strobe level). The Distribution Control Card (DC) will attempt to connect to a data link processor (DLP) by driving the appropriate DLP address line (LCPADn/0) low. This backplane signal is applied to a buffer chip (M5-C) which is enabled when the data link processor (DLP) is on-line. The output of the buffer chip is then fed through an inverter (P4-C) and applied to a 3-legged NAND gate (M3-C) to become the term-CONECT/. This CONECT/ term is used to enable the following set of signals on the DC/CFE interface: 1. LCPCON/0. This line goes low when the DLP is connected. 2. LCPSTUn/0. These are the four data link processors status lines. 3. IOSND/.0. This is the state of the I/O-send flip-flop. 4. LCPSTL/0. This is the data link processor strobe signal. 5. STIOL/.0. This is the host system strobe signal. 6. TERM/.0. This is the host system terminate signal. 7. SELCLR/0. This is the Distribution Card (DC) to the data link processor (DLP) selective clear signal. 8. DATAxn/0. This is the 17-bit data bus. All these backplane signals are low active and are enabled only when (a) the CFE is properly addressed by the Distribution Control Card (DC) and (b) a connection is possible, that is, when the data link processor is on-line, and there is no PROM parity error. The actual state of the enabled lines is dependent upon the logical condition of the data link processor and the Distribution Control Card (DC) at the time of the connection. DATA LINK PROCESSOR REQUESTS: A DLP request is the method by which a data link processor can notify the Distribution Control Card that it needs host system attention. A request can be considered to be a DLP interrupt (REQ) to the Distribution Card (DC). A DLP request is made to the Distribution Control Card when the DLP drives its jumpered request line (LCPRQn/0) low, or when the DLP drives its jumpered request line and EMRREQ/0 (emergency request) low. Both types of these requests can be generated on the Common Front End Card (CFE) by the PROM stored micro-code program. When the micro-code program drives the PROM output line #LDINT/ (load interface) low, the signals #CONST1 (for emergency request), and #CONST2 (for request) are loaded into a register called the request latch 19 (FIG. 4A) at CLK8/time. Combinational type logic on the Common Front End allows "emergency request" to be enabled on the backplane anytime it occurs, if the data link processor is "on-line". If a DLP issues an emergency request, it also issues a non-emergency request. This is done so that the Distribution Control Card can determine which DLP is doing the emergency-requesting. The backplane line EMRREQ/0 is common to all data link processors in the base module, and the LCPRQn/0 lines are each unique. If a data link processor issues a non-emergency request, it is "enabled" on the backplane only if the data link processor is on-line and no other data link processors in the base module are doing any emergency requesting. DATA LINK PROCESSOR DATA TRANSFER RATE: Two possible modes of operation govern the data transfer rate between the data link processor DLP and the main host system 10. These modes are called (a) demand mode and (b) burst mode. Demand mode causes data transfers to occur at a rate of less than four megahertz. Burst mode permits data word (16-bit) transfers to occur at a four megahertz rate, that is, 64 megabits per second. The data link processor (DLP) and the Distribution Control Card (DC) send "strobe acknowledge" signals back and forth to each other when they present or accept data. The DLP sends the term LCPSTL/0 (DLP strobe level) to the Distribution Control Card, and the Distribution Control Card sends STIOL/.0 to the data link processor. These strobing signals are exchanged during both the demand mode and the burst mode operations. The data transfer rate is determined by the speed at which these strobe signals are exchanged. FIG. 4E shows a data transfer timing diagram from the Distribution Control Card (DC) to the data link processor. The Common Front End Card (CFE) receives a STIOL/.0 signal from the Distribution Control Card, and synchronizes it with the 8-megahertz clock by the use of a Schottky J-K flip-flop whose outputs are named AF (synchronous flop) and AF/. The synchronized strobe level AF is used on the Common Front End Card for PROM address bit A0 micro-code testing. The AF/ signal is available for use on the peripheral dependent board (PDB) by way of a foreplane connector pin. DEMAND MODE: During buffer loading operations, the Distribution Card (DC) informs the data link processor that data is available by driving STIOL/.0 low. The data link processor micro-code program informs the Distribution Card that it has accepted the data that is on the Distribution Card interface line by driving the PROM logic term #LCPSTL/ low. #LCPSTL/ becomes LCPSTL/0 to the Distribution Card and causes the Distribution Card (DC) to drive the STIOL/.0 high until the next new word of data is available. During buffer read operations, the Distribution Card informs the data link processor that it is ready to accept new data by driving STIOL/.0 low. The data link processor micro-code instructions inform the Distribution Card that new data is available on the Distribution Card interface line by driving the PROM logic term #LCPSTL/ low. #LCPSTL/ becomes LCPSTL/0 to the Distribution Control Card. The Distribution Card informs the data link processor that it has accepted the data by driving the STIOL/.0 high. The direction of the data flow is controlled by the PROM output term #CONST3. The term #CONST3 is clocked into the request latch 19 at PROM signal #LDINT/ (Load system interface) time and becomes IOSF (I/O send flop). The state of IOSF is sent to the Distribution Control Card as ISOND/.0, and is used to inform the Distribution Control Card of the interface bus line direction. The state of IOSF is also sent to the peripheral dependent board (PDB) 80. The PDB 80 uses IOSF to assist in developing the interface bus line directional control logic. This logic determines which data link processor bus is active and what drivers or receivers must be used. CLEAR FUNCTIONS: The CFE card 10.sub.c makes use of combinational type logic to implement its clearing functions. A description of clearing functions applicable to all data link processors using the Common Front End Card follows: Power-Up Clear: A power-up clear signal is provided to the base module from either the power supply of the cabinet or from some external source as determined by the host system 10. This signal is attached via coaxial cable to a pin of the maintenance card backplane connector. The Maintenance Card uses this signal to create the master clear, MSTCLR/0. The signal MSTCLR/0 clears all data link processors that are on-line. Base Clear: The base clear function is provided by a pushbutton switch located on the Maintenance Card foreplane connector. The switch is ORed with the power-up clear and performs the same function as a power-up clear. Maintenance Local Clear: If the Maintenance Card is connected to a data link processor, the Maintenance Card can clear the data link processor by driving LCLCLR/0 low (clear level from Maintenance Card). Host System Master Clear: The host system 10 can issue a master clear signal across its message level interface 15.sub.i (MLI). The Distribution Control Card (DC) contains a host system jumper option which, if installed, causes the master clear (MSTCLR/0) to go "low". This signal clears all the data link processors that are not addressed by the Maintenance Card. If the Distribution Control Card host system option jumper is not installed, then the host master clear signal is not passed through the Distribution Control Card to the backplane. Host System Selective Clear: The host system 10 can clear a single data link processor during a standard poll test operation by driving the message level interface (MLI) line TRM+Mc/l low. This action causes the Distribution Card to drive SELCLR/0 low. The SELCLR/0 being "low" causes the connected data link processor to clear. FIG. 3 shows in schematic form the physical structure of the Common Front End (CFE) card 10.sub.c while FIG. 4A shows the basic circuit block diagram of the Common Front End Card. Included in the CFE is the clear circuitry shown in FIG. 4B. It will be seen that NOR gate 113 has inputs from NAND gates 110 and 111 in addition to an input from inverter 114 which is fed by buffer 112. The output of gate 113 is fed to buffer 115 and also to inverter 116. Inverter 116 feeds its signal to a Schottky data register chip 117 which provides an output to the PROM address multiplexer 12 of FIG. 4A. The output of data register 117 is also used to provide one of the inputs to NAND gate 118. A "low" signal which results on the output of the NOR gate 113 occurs if any one of the following conditions is met: 1. MSTCLR/0 and OFFLN are both "low". 2. SELCLR/0 and CONECT/ are both low. 3. LCLCLR/0 and LOCAL/ are both low. The "low" output of NOR gate 113 is used to perform the following functions: 1. The output is fed through a buffer chip 115 to become signal CLR/. CLR/ clears the PROM parity error flip-flop (and flip-flops SOTB, AF, and TERMF) on the CFE 10.sub.c. 2. CLR/ is sent to the peripheral dependent board (PDB) 80 to clear the specific peripheral-dependent logic. 3. The low output signal of NOR gate 113 is sent through an inverter 116 and is applied to one input of the data register chip 117. It is sent as the logic term CLRD. The signal CLRD is double synchronized with CLOCK/ and becomes the signal SCLR (synchronized clear). 4. The signal SCLR from register 117 is used to force the PROM clock-disabling term CLKST (clock stop) "low". This is done in the event that a PROM parity error may hve caused CLKST to go high. 5. The SCLR signal is used to disable the PROM address multiplexer chips 12. This forces the PROM address lines to all zeros. Address zero is the starting address of all data link processor micro-code programs. CFE CLOCK CONTROL: The clock control logic in the CFE 10.sub.c uses combinational type logic (NAND gates, NOR gates, inverters, buffers, and a Schottky data register chip), in order to enable or disable the always-present 8-megahertz backplane clock (CLOCK . . . O). The circuitry for the CFE clock control is shown in FIG. 4C. The CFE clock control logic constantly monitors the state of the maintenance bus 30 to determine how it should supply clock signals to the data link processor. In Table VII there was shown the available clock control options and the maintenance bus line states that are necessary to cause the various options to be active. Table VIII showed the maintenance lines for driving the PROM address lines A0-A9. In the CFE clock control circuitry shown in FIG. 4C, it will be seen that the NAND gate A3 has three inputs and the NAND gate 13-1 has four inputs. The first input to NAND gate A3 is from the data register C3 along the SCLR line. The second input to gate A3 is the line PERF/. The PERF signal is the PROM parity flip-flop signal. When "high", it indicates that an error has been detected on the PROM output register 14, thus stopping the DLP clock. The PERF/ signal is the complement of PERF. The third input to gate A3 is from the PROMCLK/ output of NOR H4-1. The first input to gate 13-1 is the SCLR line. The second input to gate 13-1 is the PERF/ line. The third input to gate 13-1 is from the CLKEN line and the fourth input to gate 13-1 is the output of the buffer N5-1. The NAND gate M3 has one input from inverter P4 (ADLOC) and another input coming from the inverter B4-1 (BASLCL/0). The input for the data register C3 comes from NOR gate A3-2 which has one input from inverter B4, one input coming from NOR gate A3-1, and one input coming from the line START/.0. The NOR gate A3-1 has two inputs, one of which is the line BASLCL/0 and the other input is the line LOCAL/.1. The output of gate A3 is fed to the input of NOR gate H4-1. The output of NAND gate 13-1 is fed to the input of NAND gate H4-13. The output of inverter H5 (CLOCK . . . O) is fed to both the input of gate H4-2 and gate H4-13. The output of gate A3 is fed to the input of NOR gate H4-1 to form the signal line PROMCLK/. The output of NAND gate H4-13 is fed to buffer 14-1 and to buffer G4. NORMAL ON-LINE MODE: When certain of the following conditions are met, then all data link processor clocks are active at the 8-megahertz rate. These conditions are: 1. BASLCL/0 is high (the base module is not in local). 2. LOCAL/.1 is high (the DLP is not Maintenance Card (MC) addressed). 3. PERF/ is high (no PROM parity error). The signals BASLCL/0 and LOCAL/.1, both being "high", causes a "high" on to one input of the Schottky data register C3. This register chip is clocked by the always-present signal CLOCK/. This signal is derived from the backplane clock signal CLOCK . . . O after a triple inversion. One output of the register chip C3 becomes the logic term clock enable (CLKEN). The signal clock enable is NANDed on two gates (A3-4 and 13-1) using the signals FERF/, SW1/, and the output of NAND gate M3. Gate M3 has inputs which are: a. The signal ADLOC/ (after inversion). The ADLOC/ is low when the DLP is not addressed by the MC, or when ADRVLD/0 is high. b. The backplane signal BASLCL/0 (after inversion). The output of NAND gate A3-4 becomes the signal logic term B (P-CLKEN) and this is NANDed with the signal CLOCK . . . O (after inversion by inverter H5 which is fed as one input to gate H4-2). The output of gate H4-2 is fed through a NOR gate H4-1 to form the signal PROMCLK/. This signal PROMCLK/ is used to clock the PROM date registers 14 and the stack register 11 of FIG. 4A. The output of NAND gate 13-1 becomes the signal CLKEN/. This signal CLKEN/, when "low", enables the 8-megahertz backplane clocks on the peripheral dependent board, PDB 80. The CLKEN/ signal is NANDed with the signal CLOCK . . . O (after inversion) at the gate H4-13. The output of gate H4-13 is fed through one inverter buffer 14-1 and also through one non-inverting buffer G4 to become the signals respectively CLK8/ and CLK8 (8-megahertz clock). These clock signals are used in the Common Front End Card 10.sub.c. STANDARD LOCAL MODE: The standard local mode of "maintenance" is operative under the following conditions: (Also see Table VII). 1. BASLCL/0 is high (base is not in local). 2. ADRVLD/0 (address valid) is low: and the LOCnn/.0 lines on the maintenance bus are valid. 3. The LOCnn/.0 lines equal the local address jumpers on the CFE 10.sub.c. This equal comparison together with the ADRVLD/0 being low, forces LOCAL/.1 into low. LOCAL/.1 low means that the DLP is "Maintenance Card addressed". In this mode all the maintenance functions are available; for example, the Maintenance Card can now: 1. Select the single-pulse mode. 2. Perform PROM micro-code verification. 3. Set up known conditions by manipulating the PROM address during single-pulse operations, and test for known predicted results by sampling the maintenance bus display (DPLY) and the data simulate (DSIM) lines. SINGLE-PULSE MODE: After the Maintenance Card has localized the data link processor (DLP), it can place the DLP in a single-pulse mode by driving the signal SP . . . O into "low". This action forces the logic term CLKEN into "low" because the NOR gate A3-2 of FIG. 4C is disabled by the following logic: 1. Signal SP/ . . . O is inverted into "high" and disables the top input line of gate A3-2. 2. The signal LOCAL/.1 is low because the DLP is not Maintenanced Card addressed. This action disables the middle input line of gate A3-2 because of the high signal output of gate A3-1. The signal START/.0 is high and disables the third input of gate A3-2. When gate A3-2 is disabled, a low signal is set into the data register C3 at CLOCK/time. The output signal CLKEN, when low, turns off NAND gates A3-4 and 13-1, and causes their outputs to go high and to disable the NAND gates H4-2 and H4-13. When these two gates are disabled, the DLP clocks are turned off. Once the DLP is placed into a single-pulse mode, the Maintenance Card can issure from 1 to 4,096 clocks by driving the START/.0 low. START/.0 is a pulse which effectively is a window around a desired number of clocks that the Maintenance Card wants issued. During the time frame when START/.0 is low, the high signal output of gate A3-2 is clocked into the data register C3 by the always-present clock signal CLOCK/. The CLKEN now becomes a pulse rather than a level, and the DLP clocks are enabled only during the low active time span of START/.0. After the data link processor (DLP) has been placed into the single-pulse mode, the Maintenance Card can take the DLP out of it by driving SP/ . . . O high. The signal SP/ . . . O, when high, forces a high level input into register C3 as follows (FIG. 4C): The signal SP/ . . . O is inverted low by the inverter B4. This low signal is fed into NOR gate A3-2 and causes its o | ||||||