In-circuit programming architecture with ROM and flash memory

Abstract

An architecture for an integrated circuit with in-circuit programming includes a microcontroller on an integrated circuit and one or more banks of non-volatile memory which store instructions, including an in-circuit programming (ICP) set of instructions. Using a control program stored on the device, the device interactively establishes an in-circuit programming exchange with a device external to the integrated circuit and uses data obtained in the exchange to update software for the microcontroller. Portions of the ICP code which are likely to change between different application environments are stored in reprogrammable flash memory cells. Other portions of the ICP code, which are not likely to change between different application environments, are stored in space-efficient mask ROM memory cells. In this way, the ICP system can be flexibly adapted to different application environments, while conserving on silicon area occupied the ICP system.

Claims

What is claimed is:

1. An apparatus for in-circuit programming of an integrated circuit, comprising:

a processor on the integrated circuit which executes instructions;

an external port on the integrated circuit through which data is received from an external source;

a first memory array comprising non-volatile memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; and

a second memory array on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.

2. The apparatus for in-circuit programming of claim 1, wherein the non-volatile memory cells in the first memory array comprise a plurality of floating gate memory cells.

3. The apparatus for in-circuit programming of claim 1, wherein the second memory array comprises a plurality of non-volatile memory cells.

4. The apparatus for in-circuit programming of claim 1, wherein the second memory array comprises a plurality of mask ROM cells.

5. The apparatus for in-circuit programming of claim 1, wherein the second memory array comprises a plurality of floating gate memory cells.

6. The apparatus for in-circuit programming of claim 1, wherein the sequencing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor.

7. The apparatus for in-circuit programming of claim 1, wherein the sequencing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.

8. The apparatus for in-circuit programming of claim 6, wherein the processor controls the erasing, programming and verifying operations for the first memory array through a control register coupled to the first memory array.

9. The apparatus for in-circuit programming of claim 1, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a timer function included in the processor.

10. The apparatus for in-circuit programming of claim 1, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor.

11. The apparatus for in-circuit programming of claim 1, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.

12. The apparatus for in-circuit programming of claim 1, further including a watch dog timer coupled to the processor which triggers recovery from errors during the processor's execution of the in-circuit programming instructions.

13. The apparatus for in-circuit programming of claim 1, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.

14. The apparatus for in-circuit programming of claim 1, wherein the external port comprises a serial port.

15. The apparatus for in-circuit programming of claim 1, wherein the external port comprises a parallel port.

16. The apparatus for in-circuit programming of claim 1, wherein the external port is configurable to operate as a parallel port or a serial port.

17. The apparatus for in-circuit programming of claim 1, including a plurality of ports to external data sources, and wherein the port in the plurality of ports used for the external port is determined by instructions in the set of instructions for controlling the in-circuit programming steps.

18. An apparatus for in-circuit programming of an integrated circuit, comprising:

a processor on the integrated circuit which executes instructions;

an external port on the integrated circuit through which data is received from an external source;

a first memory array comprising floating gate memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port;

a second memory array comprising mask ROM cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling, sequencing and timing of the in-circuit programming steps of erasing, programming, and verifying the instructions in the first memory array; and

a control register coupled to the first memory array through which the processor controls the erasing, programming, and verifying in the first memory array.

19. The apparatus for in-circuit programming of claim 18, further including a watch dog timer coupled to the processor which triggers recovery from errors during the processor's execution of the in-circuit programming instructions.

20. The apparatus for in-circuit programming of claim 18, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.

21. The apparatus for in-circuit programming of claim 18, wherein the external port comprises a serial port.

22. The apparatus for in-circuit programming of claim 18, wherein the external port comprises a parallel port.

23. The apparatus for in-circuit programming of claim 18, wherein the external port is configurable to operate as a parallel port or a serial port.

24. The apparatus for in-circuit programming of claim 18, including a plurality of ports to external data sources, and wherein the port in the plurality of ports used for the external port is determined by the instructions in the set of instructions for controlling the in-circuit programming steps.

25. In an integrated circuit including a processor and an external port, a method for in-circuit programming of the integrated circuit, comprising:

providing on the integrated circuit a first memory array comprising non-volatile memory cells, and a second memory array;

receiving an in-circuit program command from an initiator external to the integrated circuit;

in response to the in-circuit program command, using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions in the first memory array; and

using the processor to execute a set of instructions from the first memory array to control the transfer of a set instructions into the integrated circuit from an external source through the external port.

26. The method for in-circuit programming of the integrated circuit of claim 25, wherein the set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions in the first memory array is stored in the second memory array.

27. The method for in-circuit programming of the integrated circuit of claim 25, wherein the non-volatile memory cells in the first memory array comprise floating gate memory cells.

28. The method for in-circuit programming of the integrated circuit of claim 25, wherein the second memory array comprises a plurality of mask ROM cells.

29. The method for in-circuit programming of the integrated circuit of claim 25, wherein the second memory array comprises a plurality of non-volatile memory cells.

30. The method for in-circuit programming of the integrated circuit of claim 25, wherein the second memory array comprises a plurality of floating gate memory cells.

31. The method for in-circuit programming of the integrated circuit of claim 25, wherein the step of using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions includes controlling the sequencing of the erasing, programming and verifying operations.

32. The method for in-circuit programming of the integrated circuit of claim 25, wherein the processor controls the erasing, programming and verifying operations for the first memory array through a control register coupled to the first memory array.

33. The method for in-circuit programming of the integrated circuit of claim 25, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a timer function included in the processor.

34. The method for in-circuit programming of the integrated circuit of claim 25, wherein the step of using the processor to execute a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying instructions includes controlling the timing of the erasing, programming and verifying operations.

35. The method for in-circuit programming of the integrated circuit of claim 25, including the step of providing a watch dog timer coupled to the processor which triggers recovery from errors during the processor's execution of the in-circuit programming instructions.

36. The method for in-circuit programming of the integrated circuit of claim 25, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.

37. The method for in-circuit programming of the integrated circuit of claim 25, wherein the external port comprises a serial port.

38. The method for in-circuit programming of the integrated circuit of claim 25, wherein the external port comprises a parallel port.

39. The method for in-circuit programming of the integrated circuit of claim 25, wherein the external port is configurable to operate as a parallel port or a serial port.

40. The method for in-circuit programming of the integrated circuit of claim 25, wherein the integrated circuit further includes a plurality of ports to external data sources, and further including the step of determining the port in the plurality of ports used for the external port by using the processor to execute instructions in the set of instructions for controlling the in-circuit programming steps.

41. An apparatus for in-circuit programming of an integrated circuit, comprising:

a processor on the integrated circuit which executes instructions;

an external port on the integrated circuit through which data is received from an external source;

a first memory array comprising electrically programmable non-volatile memory cells on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the transfer of instructions into the integrated circuit from the external source through the external port; and

a second memory array comprising read only memory (ROM) on the integrated circuit, which stores instructions for execution by the processor, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.

42. The apparatus for in-circuit programming of claim 41, wherein the nonvolatile memory cells in the first memory array comprise a plurality of floating gate memory cells.

43. The apparatus for in-circuit programming of claim 41, wherein the second memory array comprises a plurality of mask ROM cells.

44. The apparatus for in-circuit programming of claim 41, wherein the sequencing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.

45. The apparatus for in-circuit programming of claim 41, wherein timing of the erasing, programming and verifying operations for the first memory array is controlled by a set of instructions executed by the processor and stored in mask ROM cells in the second memory array.

46. The apparatus for in-circuit programming of claim 41, wherein the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.

47. The apparatus for in-circuit programming of claim 41, wherein the external port comprises a serial port.

48. The apparatus for in-circuit programming of claim 41, wherein the external port comprises a parallel port.

Description

COPYRIGHT NOTICE PURSUANT TO 37 C.F.R. 1.71(E)

A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

BACKGROUND

1. Field of the Invention

The present invention relates to integrated circuits having a non-volatile memory for storing sequences of instructions for execution by a microcontroller on the integrated circuit, and more particularly to techniques for accomplishing in-circuit programming to update and modify stored sequences of instructions.

2. Related Art

Integrated circuit microcontrollers have been developed which include arrays of non-volatile memory on the integrated circuit for storing sequences of instructions to be executed by the microcontroller. The sequences of instructions are stored in read-only memory (ROM), which must be programmed during manufacturing of the device, and cannot be updated. In an alternative approach, the instructions are stored in an EPROM array. However, these devices require special hardware to program the EPROM array before the device is placed in the circuit. In yet other systems, EEPROM memory is used for storing instructions. EEPROM has the advantage that it can be programmed much more quickly than EPROM, and can be modified on the fly. In yet another approach, flash memory is used to store instructions, which allows for higher density and higher speed reprogramming of the non-volatile memory. When a device combines a reprogrammable non-volatile memory, such as EEPROM or flash memory with a microcontroller, the device can be reprogrammed while it is in a circuit, allowing in-circuit programming based on interactive algorithms.

The ability to interactively download instruction sets and data to a remote device can be very valuable in a network environment. For example, a company can service a customer's equipment without requiring the customer to bring the equipment to a service center. Rather, the company can execute diagnostic functions using the in-circuit programming capability of the customer's equipment across a communication channel such as the Internet or telephone lines. In this way, software fixes can be downloaded to the customer's equipment, and the equipment can be reenabled with corrected or updated code.

Example prior devices which include this capability include the AT89S8252 microcontroller, manufactured by Atmel of San Jose, Calif., and the P89CE558 single chip microcontroller, manufactured by Philips Semiconductors of Eindhoven, The Netherlands. According to the architecture of the Philips P89CE558 microcontroller, mask ROM is utilized for the in-circuit programming (ICP) set of instructions, which are used by the microcontroller to update flash memory on the chip. Thus, the Philips microcontroller requires a dedicated mask ROM module to store fixed ICP code for each individual environment. In order to adapt the ICP code for a particular environment, the environment must be known before manufacturing of the device is complete so that the mask ROM can be properly coded. Furthermore, the ICP communication channel is fixed to a serial RS232 port in the Philips microcontroller. This limits the use of the microcontroller to a relatively narrow range of applications, and makes it difficult to utilize the ICP function in a dynamic communication environment, where the serial port may not match well with the communication channel across which the updated software is provided.

According to the architecture of the Atmel AT89S8252 microcontroller, a dedicated serial peripheral interface (SPI) port on the chip is used for the updating of flash memory. This SPI port has the disadvantage that it is implemented with inflexible program logic; modification of the in-circuit programming technique cannot be accomplished because of the inflexibility of the SPI port. The Atmel chip has further disadvantages; complicated hardware must be added to the chip for handshaking with the ICP initiator and emulating the erase/program/verify wave forms for the flash memory; the SPI bus is not always the best choice for diverse system applications; extra system logic is required to modify the original reset circuits, which are used by the in-circuit programming algorithms; and complex SPI driver and receiver logic must be attached to the chip.

What is needed is an architecture for in-circuit programming which maintains flexibility in the in-circuit programming process while minimizing the amount of silicon real estate occupied by the flash memory used to implement the in-circuit programming functions.

SUMMARY

The present invention provides an architecture for a microcontroller system on an integrated circuit supporting in-circuit programming. This system maintains flexibility in the in-circuit programming process by storing some of the in-circuit programming (ICP) code in flash memory where it can be easily altered using the in-circuit programming process, and storing portions of the ICP code that do not need to be modified in more space-efficient mask ROM cells on the integrated circuit. In particular, ICP code which handles the communication involved in the in-circuit programming process is stored in flash memory so that it may be easily modified to accommodate a number of different communication formats and protocols. Code to implement the erase, program, and verify portions of the in-circuit programming process are kept in space-efficient mask ROM cells on the integrated circuit.

The flash memory array in the present invention is further simplified by implementing the state machine for the erase, program and verify functions of the flash memory in software stored in mask ROM. Timing functions for the erase, program, and verify functions, which are typically implemented in hardware, are also implemented in software stored in the mask ROM. The design of the flash memory in the present invention is thereby simplified and the amount of silicon real estate occupied by the flash memory is consequently reduced. In this way, the in-circuit programming architecture according to the present invention effectively maintains flexibility in the in-circuit programming system, while reducing requirements for silicon real estate occupied by the in-circuit programming system.

Accordingly, the present invention can be characterized as an apparatus for in-circuit programming of an integrated circuit compromising a processor on the integrated circuit which executes instructions. The integrated circuit includes an external port through which data is received from an external source. The integrated circuit also includes a first memory array comprising non-volatile memory cells for storing instructions for execution by the processor, including instructions for controlling the transfer of additional instructions into the integrated circuit from the external source through the external port. The integrated circuit also contains a second memory array which stores instructions for execution by the processor, including a set of instructions for controlling the in-circuit programming steps of erasing, programming and verifying the instructions in the first memory array.

According to one aspect of the invention, the second memory array comprises a plurality of non-volatile mask ROM cells.

According to another aspect of the present invention, the sequencing of the erase, program and verify operations during the in-circuit programming process is accomplished through software which is stored in mask ROM cells in the second memory array.

According another aspect of the present invention, the timing of the erase, program and verify operations of the in-circuit programming process is accomplished by the processor executing software stored in mask ROM cells in the second memory array.

According to yet another aspect of the present invention, the processor controls the erase, program and verify operations involved in the in-circuit programming process by writing commands to a control register, which is coupled to the first memory array.

According to another aspect of the present invention, the apparatus for in-circuit programming further includes a watch dog timer coupled to the processor, which triggers recovery from deadlock errors during the processor's execution of in-circuit programming instructions.

According to another aspect of the present invention, the external port through which data is received from an external source is configurable to operate as a parallel or a serial port.

According to another aspect of the present invention, the first memory array comprises a plurality of separately erasable blocks of non-volatile memory cells.

According to yet another aspect of the invention, the integrated circuit includes a plurality of ports to external data sources, such as one or more serial ports, one or more parallel ports, and potentially one or more specialized communication ports. The port in the plurality of ports which is used for receiving in-circuit programming instructions from an external source is determined by instructions in the in-circuit programming code itself, and thus can be dynamically altered.

According to another aspect of the invention, the integrated circuit includes a data path for programming and verifying the first memory array and optionally, the second memory array, independent of the in-circuit programming instructions. Thus, using multiplexed I/O pins or the like, original software can be loaded into the device during manufacture or prior to mounting the chip into the system.

Other aspects and advantages of the present invention can be seen upon review of the figures, the description, and the claims which follow.

DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a system for in-circuit programming of an integrated circuit in accordance with an aspect of the present invention.

FIG. 2 is a diagram of the address space containing instructions to be executed by microcontroller 100 in accordance with an aspect of the present invention.

FIG. 3 is a diagram showing how the present invention is integrated into a system including a communication channel and an in-circuit programming initiator 340 in accordance with an aspect of the present invention.

FIG. 4A is the first portion of a flow chart of the in-circuit programming process in accordance with an aspect of the present invention.

FIG. 4B is a second portion of a flow chart of the in-circuit programming process in accordance with an aspect of the present invention.

FIG. 4C is the third portion of a flow chart of the in-circuit programming process in accordance with an aspect of the present invention.

DESCRIPTION

The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiment shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

FIG. 1 is a block diagram of a system for in-circuit programming in accordance with an aspect of the present invention. All of the components illustrated in FIG. 1 reside on an integrated circuit. Microcontroller 100 executes instructions from mask ROM module 160 and multiple time programming module 140. Multiple time programming module 140 is a simplified flash memory array which is divided into a plurality of independently erasable blocks of flash memory cells. Multiple time programming module 140 also contains status bits and boot vector 146 which directly connect to microcontroller 100. Multiple time programming module 140 also contains code to implement ICP communication handler 142 as well as user code 144 to implement user-defined functions for microcontroller 100. Microcontroller 100 includes connections to devices external to the integrated circuit through I/O ports 120, interrupt lines 122 and other signals 124. Interrupt lines 122 and other signals 124 are generally used to coordinate and synchronize communications through I/O ports 120. Microcontroller 100 additionally includes timer 105, which implements timing functions for microcontroller 100. Watch dog timer 110 is coupled to microcontroller 100 and is used to detect deadlocks in the operation of microcontroller 100.

Microcontroller 100 issues an instruction address 126 which feeds into address inputs of both mask ROM module 160 and multiple time programming module 140. Instruction address 126 indexes instructions within mask ROM 160 and multiple time programming module 140. Instructions from mask ROM module 160 and multiple time programming module 140 feed through multiplexer (MUX) 130 which selectively switches these instructions into microcontroller 100. Additionally, status bits and boot vector 146, which are part of multiple time programming module 140, feed into microcontroller 100.

In a preferred embodiment of the present invention, the boot vector is not part of the flash memory array within multiple time programming module 140. It is, instead, a separate register within multiple time programming module 140, which is selectively outputted from multiple time programming module 140 when a particular address and particular control signals are inputted in multiple time programming module 140.

Microcontroller 100 controls the operation of multiple time programming module 140 through flash control registers 150. Flash control registers 150, include control register 152 and timing register 154. Microcontroller 100 write control codes to flash control registers 150 to control the erase, program and verify functions of the in-circuit programming process for code within multiple time programming module 140. Control codes for a preferred embodiment of the present invention are illustrated in Tables 1 and 2.

Table 1 contains a listing of the bit patterns which feed onto control register 152 to control erase, program and verify functions for multiple time programming module 140.

                  TABLE 1
    ______________________________________
    .COPYRGT. 1996 Macronix International, Co., Ltd.
    FMCON: Flash Module Control register
                 FMCON›7:4!: Reserved
    FMCON›3:0!: i.e. MS›3:0! of MTPG2 module
                              normal read MTP module at DPTRIPA›15:0!
    location;
    this is the default value after
             reset:
    0001:      erase 0-64KB as well as LOCK bits
    0010:      block erase; erase 0-16K if DPTR ›2:0! =  000
                    erase 16-32K if DPTR ›2:0! =  010
             erase 32-48K if DPTR ›2:0! =  100
             erase 48-56K If DPTR ›2:0! =  110
             erase 56-64K if DPTR ›2:0! =  111
            0011:
             program byte at DPTR/PA ›15:0! with data =
                    FMDATA/DQ›7:0!
    0100:      verify erased byte at DPTR/PA ›15:0!
    0101:      verify programmed byte at DPTR/PA ›15:0!
                    program lock
    0110:    bits,           program LOCK›1! to be 1 if DPTR ›1:0! =  00
                                                 program LOCK›2! to be 1 if
                    DPTR ›1:0! =  01
                                               program LOCK›3! to be I if
                    DPTR ›1:0! =  1x
            verify three programmed lock bits
    1001:      erase status bits as well as boot vector
    1010:      program status bits or boot vector;
                           program SBIT›1:0! if DPTR›0! =  0 with
              FMDATA/DQ›1:0!
              program BVEC›7:0! if DPTR›0! =  1 with
              FMDATA/DQ›7:0!
             verify programmed status bits or boot vector;
               verify SBIT›1:0! if DPTR›0! =  0
              verify BVEC›7:0! if DPTR›0! =  1
            read Manufacture ID or Device ID
    ______________________________________

                  TABLE 2
    ______________________________________
                 FMTIM: Flash Module Timing register, used by software to
    emulate the
    waveform needed for flash operations.
    FMTIM›7!: VPP Enable bit.
    FMTIM›6!: Module Enable bit
    FMTIM›5!: Read Enable bit
    FMTIM›4!: Write Enabie bit
    FMTIM›3:0!: Reserved
    ______________________________________

                                      TABLE 3
    __________________________________________________________________________
    ;.COPYRGT. 1996 Macronix International Co., Ltd.
    ; SFR define
    .EQU      FMCON, 0x40H ; Flash Module CONtrol register
    .EQU          FMTIM, 0x41H
                                                 ; Flash Module TIMing
                           register
                                                                      ; used
                           by s/w to emulate the emulate
                                                                      ; the
                           waveform needed for flash
                           operations
    .EQU          delay1, 0xFAH
                                                ; Tck 1/Fosc (ns)
                                                                ; delayl =
                           (256 - 2000/(Tck*12) + 1)
                                                            ; delay2 =
                           (500000000/(Tck* 12 *
    .EQU          delay2, 0x1AH
                                                65536)
    ; Subroutine: Erase full chip
    ERASE:
    MOV       FMCON, #00010010b
                           ; chip erase
    MOV            FMTIM, #11000000b
                                         ; VPP in and CEB is active
    LCALL        DELAY2us                           ; delay tVPS or tCES
                           (2us)
    MOV            FMTIM, #1l0l0000b
                                           ; WEB is active
    LCALL        DELAY1s                            ; delay tEW (erase time)
    MOV            FMTIM, #11000000b
                                         ; disable WEB
    LCALL        DELAY500ms
                                                   ; delay tER (0.5s)
    MOV            FMTIM, #00000000b
                                          ; clear FMTIM
    MOV            FMCON, #00000000b
                                             ; clear FMCON
    RET
    ; Subroutine: Verify erased byte
    ERASE.sub.-- VERIFY:
    MOV       FMCON, #00010010b
                           ; verify chip erase
    MOV            FMTIM, #1l000000b
                                          ; VPP in, CEB is active
    MOV            DFTR, #00H
                                                 ; Address
    LCALL       DELAY2us                              ; delay tMS (2us)
    MOV           FMTIM, #11100000b
                                         ; OEB is active
    MOV           R1, #00H
    MOV           R0, #00H
    NOP
    NOP
    LOOP.sub.-- E:
    ; MOVX    A,@DPTR      ; read Flash
    CJNE      A,#0xFFR, ERASE.sub.-- FAIL
    INC           DPTR
    DJNZ         R0, LOOP.sub.-- E
    DJNZ         R1, LOOPE
    MOV           R7, #0xFFH
                                                    ; erase verify passed
    SJMP         END.sub.-- EV
    ERASE.sub.-- FAIL:
    MOV       R7,A         ; erase verify fail
    END.sub.-- EV:
    MOV       FMTIM, #0000000b
                           ; clear FMTIM
    MOV           FMCON, #0000000b
                                              ; clear FMCON
    RET
    ; Subroutine: Program byte
    ; DPTR: program address
    ; A: program data
    PROGRAM.sub.-- B:
    MOV       FMCON, #00010001b
                           ; program byte
    LCALL      PROGRAM
    MOV          FMCON, #00000000b
                                             ; clear FMCON
    RET
    ; Subroutine Verify Byte
    ; DPTR: verify address
    ; A: verify data
    VERIFY.sub.-- B:
    MOV       FMCON, #00010011b
                           ; verify byte
    MOV            FMTIM, #110000000b
                                        ; VPP in, CEB active
    MOV            B, A
    LCALL        DELAY2us                             ; delay tPV(2us)
    MOV            FMTIM, #111l00000b
                                        ; OEB is active
    NOP                                     ; delay 4 NOP
    NOP
    NOP
    NOP
    CJNE          A, B, VERIFY.sub.-- B.sub.-- FAIL
    MOV            R7, #0xFFH
                                                   ; verify passed
    SJMP          END.sub.-- PV
    VERIFY.sub.-- B.sub.-- FAIL
    MOV       R7, A        ; program verify fail
    END.sub.-- PV:
    MOV       FMTIM, #00000000b
                           ; clear FMTIM
    MOV            FMCON, #00000000b
                                            ; clear FMCON
    RET
    ; Subroutine: Program LOCK bits
    ; which lock bit being programmed depends on DPTR ›2:0!
    PROGRAM.sub.-- L:
    MOV       FMCON, #00010100b
                           ; program LOCK bit
    LCALL       PROGRAM
    MOV           FMCON, #00000000b
                                            ; clear FMCON
    RET
    ; Subroutine: Verify LOCK bits
    VERIFY.sub.-- L:
    MOV       FMCON, #00010101b
                           ; verify three programmed lock bits
    LCALL       VERIFY.sub.-- L.sub.-- S
    MOV           FMCON, #00000000b
                                             ; clear FMCON
    RET
    ; Subroutine: Program Status bit
    PROGRAM.sub.-- S:
    MOV       FMCON, #00010110b
                           ; program State bit
    LCALL       PROGRAM
    MOV           FMCON, #00000000b
                                            ; clear FMCON
    RET
    ; Subroutine: Verify programmed status bit
    VERIFY.sub.-- S:
    MOV       FMCON, #00010111b
                           ; verify state bit
    LCALL       VERIFY.sub.-- L.sub.-- S
    MOV           FMCON, #00000000b
                                            ; clear FMCON
    RET
    ; Subroutine: PROGRAM
    PROGRAM:
    MOV       FMTIM, #11000000b
                           ; VPP in, CEB active
    LCALL       DELAY2us                             ; delay tVPS or tCES or
                           tMS (2us)
    MOV           FMTIM, #11010000b
                                        ; WEB is active
    LCALL       DELAY100us                         ; delay tPW(100us)
    MOV           FMTIM, #11000000b
                                          ; disable WEB
    LCALL       DELAY2us                              ; delay tPR (2us)
    MOV           FMTIM, #00000000b
                                             ; clear FMTIM
    RET
    ; Subroutine: Verify LOCK bits or State bit
    VERIFY.sub.-- L S:
    MOV       B, A
    MOV           FMTIM, #01000000b
                                             ; VPP = 5V, CEB active
    LCALL       DELAY2us                               ; delay tVPS or tCES
                           or tMS (2us)
    MOV           FMTIM, #11100000b
                                           ; OEB is active
    NOP
    NOP
    NOP
    NOP
    CJNE         A, B, VERIFY.sub.-- LS.sub.-- FAIL
    MOV           R7, #0xFFH
                                                    ; verify LOCK or State
                           bit passed
    SJMP         END.sub.-- VLS
    VERIFY.sub.-- LS.sub.-- FAIL
    :
    MOV       R7, A        ; verify LOCK or state fail
    END.sub.-- VLS:
    MOV       FMTIM, #00000000b
                           ; clear FMTIM
    RET
    ; Subroutine: DELAY2us
    DELAY2us:
         PUSH IE
                  EA
                  TH1, #0xFFH
              MOV
                  TL1, #delay1
             MOV
                  TCON, #00H
            MOV
                  TMOD, #10H
                                              ; TIMER1, MODE 1
           SETB
                 TR1                                 ; start TIMER1
    LOOP1:
         JNB      TF1,LOOP1
                  TCON, #00H
                                              ; clear TF1 and TR1
              POP
                  IE
             RET
    ; Subroutine: DELAY100us
    DELAY100us
    MOV       R7, #0x32H
    LOOP2:
         LCALL
              DELAY2us
         DJNZ    R7, LOOP2
         RET
    ; Subroutine: DELAY500ms
    DELAY500ms:
         PUSH IE
                  EA
                  R7, #delay2
                  TCON, #00H
              MOV
                  TMOD, #10H
                                              ; TIMER1, MODE 1
    LOOP4:
          MOV     TH1, #00H
             MOV
                  TL1, #00H
            SETB
                 TR1
    LOOP3:
          JNB      TF1, LOOP3
            MOV
                  TCON, #00H
                                             ; clear TF1 and TR1
           DJNZ
                 R7, LOOP4
          POP     IE
         RET
    ; Subroutine: DELAY1s
    DELAY1s:
    LCALL     DELAY500ms
    LCALL       DELAY500ms
    RET
    .END
    __________________________________________________________________________

• Inventors
  Sun, Albert C.; Chen, Chang-Lun; Lee, Chee-Horng;
• Assignee
  Macronix International Co., Ltd. (TW)
• Published
  May-4-1999
• Current US Classes:
  710/8
  711/103
  712/37
  719/321
• Application #
  818389
• International Classes
  G06F 012/06; G06F 013/20
• Field of Search
  395/181 395/800.37 395/828 395/183.12 395/681 395/282 395/182.11 395/290 395/309 395/833 395/800.73 711/103 365/185.22 365/185.08 365/185.09 365/185.29 365/185.24
• Examiner
  Pan; Daniel H.
• Agent
  Wilson Sonsini Goodrich & Rosati
• US Patent References:
  5018096
  5163147
  5276839
  5278976
  5404494
  5444664
  5444861
  5467286
  5495593
  5564032
  5574926
  5579479
  5581723
  5603056