Data processing device and method of operation with context switching

Abstract

A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Claims

What is claimed is:

1. A processor comprising:

A. a semiconductor chip;

B. a processor formed on the chip, the processor including an ALU and selected registers that are associated with the ALU, each selected register being formed of a pair of first and second registers, the ALU storing program data in one of the first and second registers for each selected register;

C. a context change signal lead formed on the semiconductor chip, the context change signal lead carrying a signal having a first state indicating a context of a first set of program instructions operating on first data stored in the selected registers and a second state indicating a context of a second set of program instructions operating on second data stored in the selected registers; and

D. context switching circuitry formed on the semiconductor chip, the context switching circuitry being connected to the selected registers and the context change signal lead, the context change switching circuitry connecting one of the pair of first and second registers, for each selected register, to hold the first data in response to the first state of the context change signal and connecting the other of the pair of first and second registers, for each selected register, to hold the second data in response to the second state of the context change signal.

2. The processor of claim 1 in which the selected registers include an accumulator, an accumulator buffer, an auxiliary register, a compare register, an index register, a processor mode status register, a product register, a status register 0, a status register 1, a temporary register for multiplier, a temporary register for shift count and a temporary register for bit test.

3. The processor of claim 1 in which the context change signal lead receives a hardware interrupt signal forming the context change signal.

4. The processor of claim 1 in which the context change signal lead receives a signal indicating one of an interrupt, a software trap, and a subroutine.

5. The processor of claim 1 in which the processor includes a hardwired multiplier coupled to the ALU.

6. The processor of claim 1 in which each selected register includes the first register having an output connected to the input of the second register and the second register having an output connected to the input of the first register and the context switching circuitry moving the first data from the first register to the second register for each selected register.

7. The processor of claim 1 in which each selected register includes the first and second register both having an input coupled to receive data from the ALU and the context switching circuitry changes the flow of data being received by a selected register from the first register to the second register.

8. The processor of claim 1 in which the context switching circuitry includes a multiplexer selectively switching data from the ALU to the first and second registers of each selected register.

9. The processor of claim 1 in which the context switching circuitry includes a clock signal connected to each first and second register of each selected register selectively to clock data from the ALU into one and the other of the first and second registers.

10. The processor of claim 1 in which the selected registers include an accumulator and a product register.

11. A digital signal processor comprising:

A. a semiconductor chip;

B. a digital signal processor formed on the chip, the processor including an ALU and an accumulator and product register that are associated with the ALU, each of the accumulator and product register being formed of a pair of first and second registers, the ALU storing program data in one of the first and second registers for each of the accumulator and product register;

C. an interrupt signal lead formed on the semiconductor chip, the interrupt signal lead carrying an interrupt signal having a non-interrupt state indicating a context of a first set of program instructions operating on first data stored in the accumulator and product register and an interrupt state indicating a context of an interrupt set of program instructions operating on second data stored in the accumulator and product register; and

D. context switching circuitry formed on the semiconductor chip, the context switching circuitry being connected to the accumulator and product register and the interrupt signal lead, the context change switching circuitry connecting one of the pair of first and second registers, for each of the accumulator and product register, to hold the first data in response to the first state of the interrupt signal and connecting the other of the pair of first and second registers, for each of the accumulator and product register, to hold the second data in response to the second state of the interrupt signal.

Description

NOTICE

(C) Copyright 1989 Texas Instruments Incorporated. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever.

This invention relates to data processing devices, electronic processing and control systems and methods of their manufacture and operation.

BACKGROUND OF THE INVENTION

A microprocessor device is a central processing unit or CPU for a digital processor which is usually contained in a single semiconductor integrated circuit or "chip" fabricated by MOS/LSI technology, as shown in U.S. Pat. No. 3,757,306, issued to Gary W. Boone and assigned to Texas Instruments Incorporated. The Boone patent shows a single-chip 8-bit CPU including a parallel ALU, registers for data and addresses, an instruction register and a control decoder, all interconnected using the von Neumann architecture and employing a bidirectional parallel bus for data, address and instructions. U.S. Pat. No. 4,074,351, issued to Gary W. Boone and Michael J. Cochran, assigned to Texas Instruments Incorporated, shows a single-chip "microcomputer" type device which contains a 4-bit parallel ALU and its control circuitry, with on-chip ROM for program storage and on-chip RAM for data storage, constructed in the Harvard architecture. The term microprocessor usually refers to a device employing external memory for program and data storage, while the term microcomputer refers to a device with on-chip ROM and RAM for program and data storage. In describing the instant invention, the term "microprocessor" will be used to include both types of devices, and the term "microprocessor" will be primarily used to refer to microcomputers without on-chip ROM. Since the terms are often used interchangeably in the art, however, it should be understood that the use of one of the other of these terms in this description should not be considered as restrictive as to the features of this invention.

Modern microcomputers can be grouped into two general classes, namely general-purpose microprocessors and special-purpose microcomputers/microprocessors. General purpose microprocessors, such as the M68020 manufactured by Motorola, Inc. are designed to be programmable by the user to perform any of a wide range of tasks, and are therefore often used as the central processing unit in equipment such as personal computers. Such general-purpose microprocessors, while having good performance for a wide range of arithmetic and logical functions, are of course not specifically designed for or adapted to any particular one of such functions. In contrast, special-purpose microcomputers are designed to provide performance improvement for specific predetermined arithmetic and logical functions for which the user intends to use the microcomputer. By knowing the primary function of the microcomputer, the designer can structure the microcomputer in such a manner that the performance of the specific function by the special-purpose microcomputer greatly exceeds the performance of the same function by the general-purpose microprocessor regardless of the program created by the user.

One such function which can be performed by a special-purpose microcomputer at a greatly improved rate is digital signal processing, specifically the computations required for the implementation of digital filters and for performing Fast Fourier Transforms. Because such computations consist to a large degree of repetitive operations such as integer multiply, multiple-bit shift, and multiply-and-add, a special-purpose microcomputer can be constructed specifically adapted to these repetitive functions. Such a special-purpose microcomputer is described in U.S. Pat. No. 4,577,282, assigned to Texas Instruments Incorporated and incorporated herein by reference. The specific design of a microcomputer for these computations has resulted in sufficient performance improvement over general purpose microprocessors to allow the use of such special-purpose microcomputers in real-time applications, such as speech and image processing.

Digital signal processing applications, because of their computation intensive nature, also are rather intensive in memory access operations. Accordingly, the overall performance of the microcomputer in performing a digital signal processing function is not only determined by the number of specific computations performed per unit time, but also by the speed at which the microcomputer can retrieve data from, and store data to, system memory. Prior special-purpose microcomputers, such as the one described in said U.S. Pat. No. 4,577,282, have utilized modified versions of a Harvard architecture, so that the access to data memory may be made independent from, and simultaneous with, the access of program memory. Such architecture has, of course provided for additional performance improvement.

The increasing demands of technology and the marketplace make desirable even further structural and process improvements in processing devices, application systems and methods of operation and manufacture.

Among the objects of the present invention are to provide improved data processing devices, systems and methods that reduce competition of compare functions and arithmetic computation functions for processor resources; to provide improved data processing devices, systems and methods that simplify operations and provide architectural solutions that increase processing efficiency where intensive computation and comparison operations coexist; to provide improved data processing devices, systems and methods with applications to improved gain controls; and to provide improved data processing devices, systems and methods to better adapt computers to pattern recognition, complex information processing and control generally.

SUMMARY OF THE INVENTION

In general, one form of the invention is a data processing device that includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context.

Generally, another form of the invention is a system of signal processing apparatus including an analog-to-digital converter for producing a digital signal corresponding to an analog input by a conversion process and for producing an interrupt signal when conversion is complete. Digital processing circuitry having a memory and a processor connected to the analog-to-digital converter is responsive to the interrupt signal to enter the digital signal into the memory. The processor includes first registers and respectively corresponding second registers to at least some of the first registers, a multiplier and an arithmetic logic unit. The processor also includes circuitry for simultaneously loading a particular first register and its corresponding one of the second registers with the same digital signal in a first context of operation and then in response to the interrupt signal changing to a second context of operation to selectively load the first registers leaving the second registers unmodified and holding the values subsisting from the first context of operation, thereby effectuating a zero-overhead interrupt context switching.

Other device, system and method forms of the invention are also disclosed and claimed herein. Other objects of the invention are disclosed and still other objects will be apparent from the disclosure herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set forth in the appended claims. The preferred embodiments of the invention as well as other features and advantages thereof will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein:

FIGS. 1A and 1B are two halves of an electrical diagram in block form of an improved microcomputer device including a CPU or central processor unit formed on a single semiconductor chip;

FIG. 2 is a block diagram of an improved industrial process and protective control system;

FIG. 3 is a partially pictorial, partially block electrical diagram of an improved automotive vehicle system;

FIG. 4 is an electrical block diagram of an improved motor control system;

FIG. 5 is an electrical block diagram of another improved motor control system;

FIG. 6 is an electrical block diagram of yet another improved motor control system;

FIG. 7 is an electrical block diagram of an improved robotic control system;

FIG. 8 is an electrical block diagram of an improved satellite telecommunications system;

FIG. 9 is an electrical block diagram of an improved echo cancelling system for the system of FIG. 8;

FIG. 10 is an electrical block diagram of an improved modem transmitter;

FIG. 11 is an electrical block diagram equally representative of hardware blocks or process blocks for the improved modem transmitter of FIG. 10;

FIG. 12 is an electrical block diagram equally representative of hardware blocks or process blocks for an improved modem receiver;

FIG. 13 is an electrical block diagram of an improved system including a host computer and a digital signal processor connected for PCM (pulse code modulation) communications;

FIG. 14 is an electrical block diagram of an improved video imaging system with multidimensional array processing;

FIG. 15 is an electrical block diagram equally representative of hardware blocks or process blocks for improved graphics, image and video processing;

FIG. 16 is an electrical block diagram of a system for improved graphics, image and video processing;

FIG. 17 is an electrical block diagram of an improved automatic speech recognition system;

FIG. 18 is an electrical block diagram of an improved vocoder-modem system with encryption;

FIG. 19 is a series of seven representations of an electronic register holding bits of information and illustrating bit manipulation operations of a parallel logic unit improvement of FIG. 1B;

FIG. 20 is an electrical block diagram of an improved system for high-sample rate digital signal processing;

FIG. 21 is an electrical block diagram of architecture for an improved data processing device including the CPU of FIGS. 1A and 1B;

FIG. 22 a schematic diagram of a circuit for zero-overhead interrupt context switching;

FIG. 23 is a schematic diagram of an alternative circuit for zero-overhead interrupt context switching;

FIG. 24 is a schematic diagram of another alternative circuit for zero-overhead interrupt context switching;

FIG. 25 is a flow diagram of a method of operating the circuit of FIG. 24;

FIG. 26 is a block diagram of an improved system including memory and I/O peripheral devices interconnected without glue logic to a data processing device of FIGS. 1A and 1B having software wait states on address boundaries;

FIG. 27 is a partially block, partially schematic diagram of a circuit for providing software wait states on address boundaries;

FIG. 28 is a process flow diagram illustrating instructions for automatically computing a maximum or a minimum in the data processing device of FIGS. 1A and 1B;

FIG. 29 is a partially graphical, partially tabular diagram of instructions versus instruction cycles for illustrating a pipeline organization of the data processing device of FIGS. 1A and 1B;

FIG. 30 is a further diagram of a pipeline of FIG. 29 comparing advantageous operation of a conditional instruction to the operation of a conventional instruction;

FIG. 31 is an electrical block diagram of an improved video system with a digital signal processor performing multiple-precision arithmetic using conditional instructions having the advantageous operation illustrated in FIG. 30;

FIG. 32 is a block diagram of status bits and mask bits of a conditional instruction such as a conditional branch instruction;

FIG. 33 is a block diagram of an instruction register and an instruction decoder lacking provision for status and mask bits;

FIG. 34 is a block diagram detailing part of the improved data processing device of FIG. 1A having an instruction register and decoder with provision for conditional instructions with status and mask bits;

FIG. 35 is a partially schematic, partially block diagram of circuitry for implementing the status and mask bits of FIGS. 32 and 34;

FIG. 36 is a pictorial of an improved pin-out or bond-out configuration for a chip carrier for the data processing device of FIGS. 1A and 1B illustrating improvements applicable to configurations for electronic parts generally;

FIG. 37 is a pictorial view of four orientations of the chip carrier of FIG. 36 on a printed circuit in manufacture;

FIG. 38 is a pictorial of an automatic chip socketing machine and test area for rejecting and accepting printed circuits of FIG. 37 in manufacture;

FIG. 39 is a processing method of manufacture utilizing the system of FIG. 38;

FIG. 40 is a version of the improved pin-out configuration in a single in-line type of chip;

FIG. 41 is another version of the improved pin-out configuration;

FIG. 42 is a pictorial of a dual in-line construction wherein the improved pin-out configuration is applicable and showing translation arrows; and

FIG. 43 is a pictorial of some pins of a pin grid array construction wherein the improved pin-out configuration is applicable.

Corresponding numerals and other symbols refer to corresponding parts in the various figures of drawing except where the context indicates otherwise.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

An architectural overview first describes a preferred embodiment digital signal processing device 11.

The preferred embodiment digital signal processing device 11 of FIGS. 1A and 1B implements a Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures, program and data, for full-speed execution. Instructions are included to provide data transfers between the two spaces.

The device 11 has a program addressing circuit 13 and an electronic computation circuit 15 comprising a processor. Computation circuit 15 performs two's-complement arithmetic using a 32 bit ALU and accumulator 23. The ALU 21 is a general-purpose arithmetic logic unit that operates using 16-bit words taken from a data memory 25 of FIG. 1B or derived from immediate instructions or using the 32-bit result of a multiplier 27. In addition to executing arithmetic instructions, the ALU 21 can perform Boolean operations. The accumulator 23 stores the output from the ALU 21 and provides a second input to the ALU 21 via a path 29. The accumulator 23 is illustratively 32 bits in length and is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high and low order accumulator words in data memory 25. For fast, temporary storage of the accumulator 23 there is a 32-bit accumulator buffer ACCB 31.

In addition to the main ALU 21 there is a Peripheral Logic Unit (PLU) 41 in FIG. 1B that provides logic operations on memory locations without affecting the contents of the accumulator 23. The PLU 41 provides extensive bit manipulation ability for high-speed control purposes and simplifies bit setting, clearing, and testing associated with control and status register operations.

The multiplier 27 of FIG. 1A performs a 16.times.16 bit two's complement multiplication with a 32-bit result in a single instruction cycle. The multiplier consists of three elements: a temporary TREG0 register 49, product register PREG 51 and multiplier array 53. The 16-bit TREG0 register 49 temporarily stores the multiplicand; the PREG register 51 stores the 32-bit product. Multiplier values either come from data memory 25, from a program memory 61 when using the MAC/MACD instructions, or are derived immediately from the MPYK (multiply immediate) instruction word.

Program memory 61 is connected at addressing inputs to a program address bus 101A. Memory 61 is connected at its read/write input/output to a program data bus 101D. The fast on-chip multiplier 27 allows the device 11 to efficiently perform fundamental DSP operations such as convolution, correlation, and filtering.

A processor scaling shifter 65 has a 16-bit input connected to a data bus 111D via a multiplexer (MUX) 73, and a 32-bit output connected to the ALU 21 via a multiplexer 77. The scaling shifter 65 produces a left-shift of 0 to 16 bits on the input data, as programmed by instruction or defined in a shift count register (TREG1) 81. The LSBs (least significant bits) of the output are filled with zeros, and the MSBs (most significant bits) may be either filled with zeros or sign-extended, depending upon the state of the sign-extension mode bit SXM of the status register ST1 in a set of registers 85 of FIG. 1B. Additional shift capabilities enable the processor 11 to perform numerical scaling, bit extraction, extended arithmetic, and overflow prevention.

Up to eight levels of a hardware stack 91 are provided for saving the contents of a program counter 93 during interrupts and subroutine calls. Program counter 93 is selectively loaded upon a context change via a MUX 95 from program address bus 101A or program data bus 101D. The PC 93 is written to address bus 101A or pushed onto stack 91. On interrupts, certain strategic registers (accumulator 23, product register 51, TREG0 49, TREG1, TREG2, and in registers 85: ST0, ST1, PMST, ARCR, INDX and CMPR) are pushed onto a one deep stack and popped upon interrupt return; thus providing a zero-overhead, interrupt context switch. The interrupts operative to save the contents of these registers are maskable.

The functional block diagram shown in FIGS. 1A and 1B outlines the principal blocks and data paths within the processor. Further details of the functional blocks are provided hereinbelow. Refer to Table A-1, the internal hardware summary, for definitions of the symbols used in FIGS. 1A and 1B.

The processor architecture is built around two major buses (couples): the program bus 101A and 101D and the data bus 111A and 111D. The program bus carries the instruction code and immediate operands from program memory on program data bus 101D. Addresses to program memory 61 are supplied on program address bus 101A. The data bus includes data address bus 111A and data bus 111D. The latter bus 111D interconnects various elements, such as the Central Arithmetic Logic Unit (CALU) 15 and an auxiliary register file 115 and registers 85, to the data memory 25. Together, the program and data buses 101 and 111 can carry data from on-chip data memory 25 and internal or external program memory 61 to the multiplier 27 in a single cycle for multiply/accumulate operations. Data memory 25 and registers 85 are addressed via data address bus 111A. A core register address decoder 121 is connected to data address bus 111A for addressing registers 85 and all other addressable CPU core registers.

The processor 13, 15 has a high degree of parallelism; e.g., while the data is being operated upon by the CALU 15, arithmetic operations are advantageously implemented in an Auxiliary Register Arithmetic Unit (ARAU) 123. Such parallelism results in a powerful set of arithmetic logic, and bit manipulation operations that may all be performed in a single machine cycle.

The processor internal hardware contains hardware for single-cycle 16.times.16-bit multiplication, data shifting and address manipulation.

Table A-1 presents a summary of the internal hardware. This summary table, which includes the internal processing elements, registers, and buses, is alphabetized within each functional grouping.

                  TABLE A-1
    ______________________________________
    Internal Hardware
    UNIT       SYMBOL     FUNCTION
    ______________________________________
    Accumulator
               ACC(32)    A 32-bit accumulator
               ACCH(16    accessible in two halves:
               ACCL(16)   ACCH (accumulator high) and
                          ACCL (accumulator low). Used
                          to store the output of the ALU.
    Accumulator
               ACCB(32)   A register used to temporarily
    Buffer                store the 32-bit contents of
                          the accumulator. This
                          register has a direct path
                          back to the ALU and therefore
                          can be arithmetically or
                          logically operated with the
                          ACC.
    Arithmetic ALU        A 32-bit two's complement
    Logic Unit            arithmetic logic unit having
                          two 32-bit input ports and one
                          32-bit output port feeding the
                          accumulator.
    Auxiliary  ARAU       A 16-bit unsigned arithmetic
    Arithmetic Unit       unit used to calculate
                          indirect addresses using the
                          auxiliary, index, and compare
                          registers as inputs.
    Auxiliary  ARCR       A 16-bit register used in use
    Register              as a limit to compare indirect
    Compare               address against.
    Auxiliary  AUXREGS    A register file containing
    Register File         eight 16-bit auxiliary
                          registers (AR0-AR7), used for
                          indirect data address
                          pointers, temporary storage,
                          or integer arithmetic
                          processing through the ARAU.
    Auxiliary  ARP        A 3-bit register used as a
    Register              pointer to the currently
    Pointer               selected auxiliary register.
    Block Repeat
               BRCR       A 16-bit memory-mappped
    Counter Register      counter register used as a
                          limit to the number of times
                          the block is to be repeated.
    Block Repeat
               PAER       A 16-bit memory-mapped
    Counter Register      register containing the end
                          address of the segment of code
                          being repeated.
    Block Repeat
               PASR       A 16-bit memory-mapped
    Address Start         register containing the start
    Register              address of the segment of code
                          being repeated.
    Bus Interface
               BIM        A buffered interface used to
    Module                pass data between the data and
                          program buses.
    Central    CALU       The grouping of the ALU,
    Arithmetic            multiplier, accumulator, and
    Logic Unit            scaling shifters.
    Circular   CBCR       An 8-bit register used to
    Buffer Control        enable/disable the circular
    Register              buffers and define which
                          auxiliary registers are mapped
                          to the circular buffers.
    Circular   CBER1      Two 16-bit registers
    Buffer End            indicating circular buffer
    Address               end addresses. CBER1 and
                          CBER2 are associated with
                          circular buffers one and two
                          respectively.
    Circular Buffer
               CBSR1      Two 16-bit registers
    Start Address
               CBSR2      indicating circular buffer
                          start addresses. CBSR1/CBSR2
                          are associated with circular
                          buffers one and two
                          respectively.
    Data Bus   DATA       A 16-bit bus used to route
                          data.
    Data Memory
               DATA       This block refers to data
               MEMORY     memory used with the core and
                          defined in specific device
                          descriptions. It refers to
                          both on and off-chip memory
                          blocks accessed in data memory
                          space.
    Data Memory
               DMA        A 7-bit register containing
    Address               the immediate relative address
    Immediate             within a data page.
    Register
    Data Memory
               DP(9)      A 9-bit register containing
    Page Pointer          the address of the current
                          page. Data pages are 128
                          words each, resulting in 512
                          pages of addressable data
                          memory space (some locations
                          are reserved).
    Direct Data
               DATA       A 16-bit bus that carries the
    Memory Address
               ADDRESS    direct address for the data
    Bus                   memory, which is the
                          concatenation of the DP
                          register and the seven LSBs of
                          the instruction (DMA).
    Dynamic Bit
               DBMR       A 16-bit memory-mapped
    Manipulation          register used as an input to
    Register              PLU.
    Dynamic    TREG2      A 4-bit register that holds a
    Bit Pointer           dynamic bit pointer for the
                          BITT instruction.
    Dynamic    TREG1      A 5-bit register that holds a
    Shift count           dynamic prescaling shift count
                          for data inputs to the ALU.
    Global Memory
               GREG(8)    An 8-bit memory-mapped
    Allocation            register for allocating the
    Register              size of the global memory
                          space.
    Interrupt Flag
               IFR(16)    A 16-bit flag register used to
    Register              latch the active-low
                          interrupts. The IFR is a
                          memory mapped register.
    Interrupt Mask
               IMR(16)    A 16-bit memory mapped
    Register              register used to mask
                          interrupts.
    Multiplexer
               MUX        A bus multiplexer used to
                          select the source of operands
                          for a bus or execution unit.
                          The MUXs are connected via
                          instructions.
    Multiplier MULTI-     A 16 .times. 16 bit parallel
               PLIER      multiplier.
    Peripheral PLU        A 16-bit logic unit that
    Logic Unit            executes logic operations from
                          either long immediate operands
                          or the contents of the DBMR
                          directly upon data locations
                          without interfering with the
                          contents of the CALU
                          registers.
    Prescaler  COUNT      A 4-bit register that contains
    Count Register        the count value for the
                          prescaling operation. This
                          register is loaded from either
                          the instruction or the dynamic
                          shift count when used in
                          prescaling data. In
                          conjunction with the BIT and
                          BITT instructions, it is
                          loaded from the dynamic bit
                          pointer of the instruction.
    Product    PREG(32)   A 32-bit product register used
    Register              to hold the multiplier
                          product. The high and low
                          words of the PREG can also be
                          accessed individually using
                          the SPH/SPL (store P register
                          high/low) instructions.
    Product    BPR(32)    A 32-bit register used for
    Register Buffer       temporary storage of the
                          product register. This
                          register can also be a direct
                          input to the ALU.
    Program Bus
               PROG DATA  A 16-bit bus used to route
                          instructions (and data for the
                          MAC and MACD instructions)
    Program Counter
               PC(16)     A 16-bit program counter used
                          to address program memory
                          sequentially. The PC always.
                          contains the address of the
                          next instruction to be
                          executed. The PC contents are
                          updated following each
                          instruction decode operation.
    Program    PROGRAM    This block refers to program
    Memory     MEMORY     memory used with the core and
                          defined in specific device
                          descriptions. It refers to
                          both on and off-chip memory
                          blocks accessed in program
                          memory space.
    Program Memory
               PROG AD-   A 16-bit bus that carries the
    Address Bus
               DRESS      program memory address.
    Prescaling PRESCALER  A 0 to 16-bit left barrel
    Shifter               shifter used to prescale data
                          coming into the ALU. Also
                          used to align data for
                          multi-precision operations.
                          This shifter is also used as a
                          0-16 bit right barrel shifter
                          of the ACC.
    Postscaling
               POST-      A 0-7 bit left barrel shifter
    Shifter    SCALER     used to post scale data coming
                          out of the CALU.
    Product    P-SCALER   A 0, 1, 4-bit left shifter
    Shifter               used to remove extra sign bits
                          (gained in the multiply
                          operation) when using fixed
                          point arithmetic. A 6-bit
                          right shifter used to scale
                          the products down to avoid
                          overflow in the accumulation
                          process.
    Repeat     RPTC(16)   An 8-bit counter to control
    Counter               the repeated execution of a
                          single instruction.
    Stack      STACK      A 8 .times. 16 hardware stack used
                          to store the PC during
                          interrupts and calls. The
                          ACCL and data memory values
                          may also be pushed onto the
                          popped from the stack.
    Status     ST0,ST1,   Three 16-bit status registers
    Registers  PMST, CBCR that contain status and
                          control bits.
    Temporary  TREG0      A 16-bit register that
    Multiplicand          temporarily holds an operand



                          for the multiplier
    Block Move BMAR       A 16-bit register that holds
    Address Register      an address value for use with
                          block moves or multiply
                          accumulates.
    ______________________________________

                  TABLE A-2
    ______________________________________
    Memory Mapped Registers
    ADDRESS
    NAME  DEC    HEX    DESCRIPTION
    ______________________________________
          0-3    0-3    RESERVED
    IMR    4      4     INTERRUPT MASK REGISTER
    GREG   5      5     GLOBAL MEMORY ALLOCATION
                        REGISTER
    IFR    6      6     INTERRUPT FLAG REGISTER
    PMST   7      7     PROCESSOR MODE STATUS REGISTER
    RPTC   8      8     REPEAT COUNTER REGISTER
    BRCR   9      9     BLOCK REPEAT COUNTER
                        REGISTER
    PASR  10     A      BLOCK REPEAT PROGRAM ADDRESS
                        START REGISTER
    PAER  11      3     BLOCK REPEAT PROGRAM ADDRESS END
                        REGISTER
    TREG0  2     C      TEMPORARY REGISTER USED FOR
                        MULTIPLICAND
    TREG1 13     D      TEMPORARY REGISTER USED FOR
                        DYNAMIC SHIFT COUNT
    TREG2 14     E      TEMPORARY REGISTER USED AS BIT
                        POINTER IN DYNAMIC BIT TEST
    DBMR  15     F      DYNAMIC BIT MANIPULATION REGISTER
    AR0   16     10     AUXILIARY REGISTER ZERO
    AR1   17     11     AUXILIARY REGISTER ONE
    AR2   18     12     AUXILIARY REGISTER TWO
    AR3   19     13     AUXILIARY REGISTER THREE
    AR4   20     14     AUXILIARY REGISTER FOUR
    AR5   21     15     AUXILIARY REGISTER FIVE
    AR6   22     16     AUXILIARY REGISTER SIX
    AR7   23     17     AUXILIARY REGISTER SEVEN
    INDX  24     18     INDEX REGISTER
    ARCR  25     19     AUXILIARY REGISTER COMPARE
                        REGISTER
    CBSR1 26     1A     CIRCULAR BUFFER 1 START ADDRESS
                        REGISTER
    CBER1 27     1B     CIRCULAR BUFFER 1 END ADDRESS
                        REGISTER
    CBSR2 28     1C     CIRCULAR BUFFER 2 START ADDRESS
                        REGISTER
    CBER2 29     1D     CIRCULAR BUFFER 2 END ADDRESS
                        REGISTER
    CBCR  30     1E     CIRCULAR BUFFER CONTROL REGISTER
    BMAR  31     1F     BLOCK MOVE ADDRESS REGISTER
    ______________________________________

    ______________________________________
    AR(ARP) + INDX -- AR(ARP)
                          Index the current AR by
                          adding a 16-bit integer
                          contained in INDX.
    AR(ARP) - INDX -- AR (ARP)
                          Index the current AR by
                          subtracting a 16-bit
                          integer contained
                          in INDX.
    AR(ARP) + 1 -- AR(ARP)
                          Increment the current AR
                          by one.
    AR(ARP) - 1 -- AR(ARP)
                          Decrement the current
                          AR by one.
    AR(ARP) -- AR(ARP)    Do not modify the
                          current AR.
    AR(ARP) + IR(7-0) -- AR(ARP)
                          ADD an 8-bit immediate
                          value to current AR.
    AR(ARP) - IR(7-0) -- AR(ARP)
                          Subtract an 8-bit
                          immediate value from
                          current AR.
    AR(ARP) + rc(INDX) -- AR(ARP)
                          Bit-reversed indexing,
                          add INDX with reverse
                          carry (rc) propagation.
    AR(ARP) - rc(INDX) -- AR(ARP)
                          Bit-reversed indexing,
                          subtract INDX with
                          reverse-carry (rc)
                          propagation.
    if (AR(ARP) = ARCR) then TC = 1
                          Compare current AR
    if (AR(ARP)gt ARCR) then TC = 1
                          with ARCR and if
    if (AR(ARP)lt ARCR) then TC = 1
                          comparison is true then
    if (AR(ARP)neq ARCR) then TC = 1
                          set TC bit of the
                          status register (ST1)
                          to one. If false then
                          clear TC.
    if(AR(ARP) = CBER) then AR(ARP) = CBSR
                          If at end of circular
                          buffer reload start
                          address
    ______________________________________

    ______________________________________
    BIT    NAME       FUNCTION
    ______________________________________
    0-2    CAR1       Identifies which auxiliary register is
                      mapped to circular buffer 1.
    3      CENB1      Circular buffer 1 enable = 1/disable = 0.
                      Set 0 upon reset.
    4-6    CAR2       Identifies which auxiliary register is
                      mapped to circular buffer 2.
    7      CENB2      Circular buffer 2 enable = 1/disable = 0.
                      Set 0 upon reset.
    ______________________________________

                  TABLE A-3
    ______________________________________
    Examples of Carry Bit Operation
    C   MSB    LSB           C   MSB   LSB
    ______________________________________
    X   FFFF   FFFF   ACC      X   0000  0000 ACC
        +       1                  -     1
    1   0000   0000            0   FFFF  FFFF
    X   7FFF   FFFF   ACC      X   8000  0001 ACC
        +      1      (OVM = 0)    -     2    (OVM = 0)
    0   8000   0000            1   7FFFF FFFF
    1   0000   0000   ACC      X   FFFF  FFFF ACC
        +      0      (ADDC)       -     1    (SUBB)
    0   0000   0001            1   FFFF  FFFE
    ______________________________________

    ______________________________________
    PM             RESULTING SHIFT
    ______________________________________
    00             NO SHIFT
    01             LEFT SHIFT OF 1 BIT
    10             LEFT SHIFT OF 4 BITS
    11             RIGHT SHIFT OF 6 BITS
    ______________________________________

                  TABLE A-4
    ______________________________________
    Status Register Field Definitions
    FIELD  FUNCTION
    ______________________________________
    ARB    Auxiliary Register Pointer Buffer. ST1 bits
           15-13. Whenever the ARP is loaded, the old
           ARP value is copied to the ARB except during an
           LST instruction. When the ARB is loaded via a
           LST1 instruction, the same value is also copied
           to the ARP.
    ARP    Auxiliary Register Pointer. ST0 bits 15-13.
           This three-bit field selects the AR to be used
           in indirect addressing. When ARP is loaded, the
           old ARP value is copied to the ARB register.
           ARP may be modified by memory-reference
           instructions when using indirect addressing, and
           by the LARP, MAR, and LST instructions. ARP is
           also loaded with the same value as ARB when an
           LST1 instruction is executed.
    BRAF   Block Repeat Active Flag. PMST bit 0. This
           bit indicates whether (BRAF = 1) or not (BRAF =
           0) block repeat is currently active. Writing a
           zero to this bit deactivates block repeat. BRAF
           is set to zero upon reset.
    C      Carry Bit. ST1 bit 9. This bit is set to 1 if
           the result of an addition generates a carry, or
           reset to 0 if the result of a subtraction
           generates a borrow. Otherwise, it is reset
           after an addition or set after a subtraction,
           except if the instruction is ADD or SUB. ADD
           can only set and SUBH only reset the carry bit,
           but does not affect it otherwise. The single
           bit shift and rotate instructions also affect
           this bit, as well as the SETC, CLRC, LST1
           instructions. Branch instructions are provided
           to branch on the status of C. C is set to 1 on
           a reset.
    CAR1   Circular Buffer 1 Auxiliary Register. CBCR
           bits 2-0. These three bits identify which
           auxiliary register is assigned to circular
           buffer 1.
    CAR2   Circular Buffer 2 Auxiliary Register. CBCR
           bits 6-4. These three bits identify which
           auxiliary register is assigned to circular
           buffer 2.
    CENB1  Circular Buffer 1 Enable. CBCR bit 3. This bit,
           when set to 1, enables circular buffer 1. When
           set to zero, disables circular buffer 1. Set to
           zero upon reset.
    CENB2  Circular Buffer 2 Enable. CBCR bit 7. This bit,
           when set to 1, enables circular buffer 2. When
           set to zero circular buffer 2 is disabled.
           CBEN2 is set to zero upon reset.
    CNF    On-chip RAM Configuration Control bit. ST1 bit
           12. If set to 0, the reconfigurable data RAM
           blocks are mapped to data space; otherwise, they
           are mapped to program space. The CNF may be
           modified by the CNFD, CNFP, and LST1
           instructions. RE- resets the CNF to 0.
    DP     Data memory Page pointer. ST0 bits 8-0. The
           9-bit DP register is concatenated with the 7
           LSBs of an instruction word to form a direct
           memory address of 16 bits. DP may be modified
           by the LST, LDP, and LDPK instructions.
    FO     Format bit. ST1 bit 3. This bit is used to
           configure the serial port format.
    FSM    Frame Synchronous Mode bit. ST1 bit 5. This bit
           is used in configuration of the framing mode of
           the serial port.
    HM     Hold Mode bit. ST1 bit 6. When HM = 1, the
           processor halts internal execution when
           acknowledging an active HOLD-. When HM = 0, the
           processor may continue execution out of internal
           program memory but puts its external interface
           in a high-impedance state. This bit is set to 1
           by reset.
    INTM   Interrupt Mode bit. ST0 bit 9. When set to 0,
           all unmasked interrupts are enabled. When set
           to 1, all maskable interrupts are disabled.
           INTM is set and reset by the DINT and
           EINT instructions. RS- and 1ACK- also set INTM.
           INTM has no effect on the unmaskable RS- and
           NM1- interrupts. INTM is unaffected by the LST
           instruction.
    IPTR   Interrupt vector pointer PMST bits 15-11. These
           five bits point to the 2K page where the
           interrupt vectors reside. This allows the user
           to remap interrupt vectors to RAM for boot
           loaded operations. At reset these bits are all
           set to zero. Therefore the reset vector always
           resides at zero in the program memory space.
    MP/MC- MicroProcessor/MicroComputer bit, PMST bit 3.
           When set to zero the on-chip ROM is enabled.
           When set to one the on-chip ROM is not
           addressable. This bit is set to the inverse of
           TXM at reset.
    NDX    Enable Extra Index Register. PMST bit 2. When
           set to 0, the ARAU uses ARO for indexing and
           address compare. When set to 1, the ARAU uses
           INDX for indexing and ARCR for address compare.
           Upon reset, this bit is set to zero.
    OV     Overflow Flag bit. ST0 bit 12. As a latched
           overflow signal, OV is set to 1 when overflow
           occurs in the ALU. Once an overflow occurs, the
           OV remains set until a reset, BV, BNV, or LST
           instructions clears OV.
    OVLY   OVerLAY the on-chip program memory in data
           memory space. PMST bit 5. If set to zero the
           memory is addressable in program space only. If
           set to one it is addressable in both program and
           data space. Set to zero at reset.
    OVM    Overflow Mode bit. ST0 bit 11. When set to 0,
           overflowed results overflow normally in the
           accumulator. When set to 1, the accumulator is
           set to either its most positive or negative
           value upon encountering an overflow. The SOVM
           and ROVM instructions set and reset this bit,
           respectively. LST may also be used to modify
           the OVM.
    PM     Product Shift Mode. ST1 bits 1-0. If these two
           bits are 00, the multiplier's 32-bit product or
           buffer is loaded into the ALU with no shift. If
           PM = 01, the PREG or BPR output is left-shifted
           one place and loaded into the ALU, with the LSB
           zero-filled. If PM = 10, the PREG or BPR output
           is left-shifted by four bits and loaded into
           the ALU, with the LSBs zero-filled. PM = 11
           produces a right shift of six bits,
           sign-extended. Note that the PREG or BPR
           contents remain unchanged. The shift takes
           place when transferring the contents of the PREG
           or BPR to the ALU. PM is loaded by the SPM and
           LST1 instructions. The PM bits are cleared by
           RS-.
    RAM    Enable/Disable on-chip RAM. PMST bit 4. Set to
           inverse of TXM at reset. If set to zero the
           on-chip program RAM is disabled. If set to one
           the on-chip program RAM is enabled.
    SXM    Sign-Extension Mode bit. ST1 bit 10. SXM = 1
           produces sign extension on data as it is passed
           into the accumulator through the scaling
           shifter. SXM = 0 suppresses sign extension.
           SXM does not affect the definition of certain
           instructions; e.g., the ADDS instruction
           suppresses sign extension regardless of SXM.
           This bit is set and reset by the SSXM and RSXM
           instructions, and may also be loaded by LST1.
           SXM is set to 1 by reset.
    TC     Test/Control Flag bit. ST1 bit 11. The TC bit
           is affected by the BIT, BITT, CMPR, LST1, NORM,
           CPLK, XPLK, OPLK, APLK, XPL, OPL, and APL
           instructions. The TC bit is set to a 1 if a bit
           tested by BIT or BITT is a 1, if a compare
           condition tested by CMPR exists between ARCR and
           another AR pointed to by ARP, if the
           exclusive-OR function of the two MSBs of the
           accumulator is true when tested by a NORM
           instruction, if the long immediate value is
           equal to the data value on the CPLK instruction,
           or if the result of the logical function (XPLK,
           OPLK, APLK, XPL, OPL or APL) is zero. Fourteen
           conditional branch, call and return instructions
           provide operations based upon the value of TC:
           BBZ, BBZD, BBNZ, BBNZD, CBZ, CBZD, CBNZ,
           CBNZD, RBZ, RJBZD, RBNZ, RBNZD, CEBZ,
           and CEBNZ.
    TRM    Enable Multiple TREG's. PMST bit 1. 


When TRM
           is set to zero, any write to any of TREG0, TREG1
           or TREG2 writes to all three. When TRM
           is set to one, TREG0, TREG1, and TREG2 are
           individually selectable. TRM is set to zero at
           reset.
    TXM    Transmit Mode Bit. ST1 bit 2. This bit is
           used in configuration of the transmit clock pin
           of the serial port.
    XF     XF pin status bit. ST1 bit 4. This bit
           indicates the current level of the external
           flag.
    ______________________________________

    ______________________________________
    SPLK 021h, CBCR
                 Store Peripheral Long Immediate
    ______________________________________

    ______________________________________
    OPLK 088h, CBCR
                  Set bit 7 and bit 3 in CBCR
    ______________________________________

                  TABLE A-5
    ______________________________________
    Interrupt Locations and Priorities
    LOCATION    PRI-
    NAME  DEC    HEX    ORITY  FUNCTION
    ______________________________________
    RS-    0      0     1 (highest)
                               EXTERNAL RESET SIGNAL
    INT1-  2      2      3     EXTERNAL USER INTERRUPT #1
    INT2-  4      4      4     EXTERNAL USER INTERRUPT #2
    INT3-  6      6      5     EXTERNAL USER INTERRUPT #3
    INT4-  8      8      6     EXTERNAL USER INTERRUPT #4
    INT5- 10     A       7     EXTERNAL USER INTERRUPT #5
    INT6- 12     C       3     EXTERNAL USER INTERRUPT #6
    INT7- 14     E       9     EXTERNAL USER INTERRUPT #7
    INT8- 16     10     10     EXTERNAL USER INTERRUPT #8
    INT9- 18     12     11     EXTERNAL USER INTERRUPT #9
    INT10-
          20     14     12     EXTERNAL USER INTERRUPT
                               #10
    INT11-
          22     16     13     EXTERNAL USER INTERRUPT
                               #11
    INT12-
          24     18     14     EXTERNAL USER INTERRUPT
                               #12
    INT13-
          26     1A     15     EXTERNAL USER INTERRUPT
                               #13
    INT14-
          28     1C     16     EXTERNAL USER INTERRUPT
                               #14
    INT15-
          30     IE     17     EXTERNAL USER INTERRUPT
                               #13
    INT16-
          32     20     18     EXTERNAL USER INTERRUPT
                               #14
    TRAP  34     22     N/A    TRAP INSTRUCTION VECTOR
    NMI   36     24      2     NON-MASKABLE INTERRUPT
    ______________________________________

    ______________________________________
    APL,K   and the DBMR or a constant with data memory value
    CPL,K   Compare DBMR or constant with data memory value
    OPL,K   or DBMR or a constant with data memory value
    SPLK,K  store long immediate to data memory location
    XPL,K   XOR DBMR or a constant with data memory value
    ______________________________________