Modular system controller for a transition machine4379326Abstract A modular system controller for a transition machine enables expansion of throughput in multiprocessing operations. The modular system controller may be embodied utilizing separate identical system controllers for computing disjoint computational problems or may utilize a plurality of identical subcomponents of the system controller for enabling a vertical or horizontal expansion of data constructs utilized in the transition machine. Claims What is claimed is: Description TABLE OF CONTENTS
TABLE I
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Descriptor Definition
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STATUS
a 4-bit read/write register
whose bits are labeled L, I, X
and O, and which contains the
following synchronization, pro-
tocol and mode request informa-
tion:
a binary status indicator used
to prevent the processors from
accessing the system control-
ler interface registers while a
system transition is in pro-
gress. When a processor re-
quests a system transition, it
loads the appropriate data val-
ues in the X, INDEX, TYPE and V
registers and sets the L dis-
crete true. This requests exe-
cution of the System Control-
ler which resets the L discrete
(sets it false) when the re-
quired transition is completed.
I
a binary status indicator used
to indicate to the System Con-
troller whether a normal or load
transition is being requested.
The I flag is set true by the
processor when the system tran-
sition required is a load tran-
sition. The I bit remains true
until the processor resets it
upon load completion.
X
a binary status indicator used
to indicate to the System Con-
troller whether an entry or exit
system transition is requested.
The X flag is set true by the
processor when the system tran-
sition required is the result of
a subsystem exiting, and X is
set false by the processor for
a subsystem entry transition.
During a load transition X is
ignored.
O
a binary status indicator set
by the System Controller to no-
tify the processor that no sub-
system is currently eligible.
The O bit is set true by the
System Controller when an entry
transition results in no eligi-
ble subsystem. The O bit is set
false by the System Controller
when an entry transition re-
sults in an eligible subsystem.
The O bit is ignored on exit and
load transitions.
TYPE.sub.p
a register used to con-
tain the type indentifi-
cation of the p.sup.th proces-
sor. The System Control-
ler uses this register to
select the next eligible
subsystem appropriate to
the requesting processor.
TYPE.sub.p is fixed for a
given processor with its
processor category. Dur-
ing entry transitions the
System Controller returns
the EXECUTE, READ, WRITE,
and INDEX values associat-
ed with an eligible sub-
system, whose type is a
compatible category with
the value contained in the
TYPE.sub.p register. TYPE.sub.p is
ignored during subsystem
exit and load transi-
tions.
INDEX
a register used to contain the
indentification of either the
next eligible subsystem, the
row currently being loaded, or
the subsystem currently being
exited depending upon the type
of transition being requested.
At the completion of each sub-
system entry transition, the
System Controller loads INDEX
with the index of the next eli-
gible subsystem whose type is
of a compatible category with
the value contained in the
TYPE.sub.p register for the proces-
sor. During a load transition,
INDEX is loaded by the processor
with the System Controller row
number for the row of constructs
currently being loaded.
When a subsystem exit transi-
tion is requested, INDEX will
contain the subsystem identifi-
cation provided to it by the
System Controller at completion
of the entry transition. Pro-
cessor interrupts are forwarded
to the System Controller by an
exit transition using an INDEX
value dedicated in the System
Controller for that purpose.
In certain of the implementa-
tions disclosed herein, the IN-
DEX register value will be
treated as though it were com-
posed of two separate values,
where the most significant bits
in the register indicate the
specific System Controller i-
dentification, and the least
significant bits indicate the
specific subsystem index within
that particular system control-
ler.
EXECUTE
a register used to provide
the entry point of the subsystem
whose identification is in IN-
DEX. This register is loaded by
the System Controller and is
read by the processors during
subsystem entry transitions.
EXECUTE is loaded by the pro-
cessor and read by the System
Controller during a load tran-
sition. During exit transi-
tions EXECUTE is unused.
READ
a register used to provide the
pointer(s) to the global data
item(s) accessible to the asso-
ciated subsystem in a read ca-
pacity. READ is loaded by the
System Controller during an en-
try transition and is loaded by
the processor during a load
transition. READ is unused
during an exit transition.
WRITE
a register which provides the
pointer(s) to the global data
item(s) accessible to the asso-
ciated subsystem in a write ca-
pacity. WRITE is loaded by the
System Controller during an en-
try transition and is loaded by
the processor during a load
transition. WRITE is unused
during an exit transition.
V
a register used to provide the
variable update vector loaded
by the processor upon comple-
tion of a subsystem. This vec-
tor allows a subsystem to return
variable data conditions to the
system status vector. (For the
specific implementation de-
scribed in the appendices,
this allows the subsystem to
modify only selected data ele-
ments of the S vector since any
attempt to modify unauthorized
elements will be masked out by
the T and F vectors, stored in-
ternally to the System Control-
ler).
During a load transition V is
loaded by the processor with the
new S vector to be loaded in the
S register. V is unused during
an entry transition.
TYPE.sub.i
a register used to contain the
type of processor required to
execute the i.sup.th subsystem.
During a load transition TYPE.sub.i
is loaded by the processor with
the processor category required
by the subsystem whose row of
data constructs is being loaded
into the System Controller.
TYPE.sub.i is unused during entry and
exit transitions.
A
a register which provides a method for
the processor to load the System
Controller A matrix. During
load transition the A register
contains the vector to be loaded
in the row of the System Con-
troller's A matrix specified by
INDEX. The A register is unused
during entry and exit transi-
tions.
T
a register used to provide a
method for the processor to load
the System Controller's T ma-
trix. During load transitions
the T register contains the
vector to be loaded in the row
of the System Controller's T
matrix specified by INDEX. The
T register is unused during en-
try and exit transitions.
F
a register which provides a
method for the processor to load
the System Controller's F ma-
trix. During load transitions
the F register contains the
vector to be loaded in the row
of the System Controller's F
For each System Controller there is one set of interface data and control registers as described above. To insure proper operation of each System Controller, no processor may modify these registers while the System Controller is active (i.e., if the L bit in the STATUS register is true). The processors also must be synchronized so that only one processor modifies these registers at a time. This can be accommodated in various ways, for example, a binary semaphore can be employed to avoid the critical section problem and synchronize the processors. Alternatively, a multiport organization can be employed where each processor has a dedicated set of interface registers and a multiport controller resolves multiple processor access contention. The multiport controller performs the actual data transfer between the dedicated processor interface registers and the actual system controller registers (similar to the operation of a multiport memory controller). Because of this the processor interface procedures do not require synchronization precautions. The multiport controller implementation therefore accommodates a simpler interface description, and is utilized in the following description. System Controller Functional Operation Detailed Description There are basically three types of allowed processors/System Controller interactions, namely entry, exit and load transitions. For each type of interaction specific processor actions and System Controller responses are described below. Entry Transition When a processor is in an idle state requesting an activity, it will first wait until the logic segment of the System Controller is not busy which is indicated by the L bit in the STATUS register being set false. At that time it will store its processor type identification into the register, TYPE.sub.p (if not previously initialized). The X bit in the STATUS register will be set false to indicate a procedure entry is being requested, and the L discrete in the STATUS register will be set true to signal the System Controller to initiate a transition. The processor will then wait until the System Controller has completed its operation which is indicated by the L discrete in the STATUS register being reset false by the System Controller. When the System Controller detects that a transition is to be initiated (by the L bit in the STATUS register having been set), it will determine whether the entry, exit, or load transition has been specified. If the entry transition is specified, the matrix dot product is performed with the S vector and the R matrix to obtain the next eligible procedure of a type compatible with the processor TYPE.sub.p register. If such an eligible procedure is determined its index is stored in the INDEX register, the procedure access pointer is stored in the register EXECUTE, and the data access pointers are stored in the registers READ and WRITE. The active protection specification for the procedure (the A vector) is used to update the system status vector to preclude inappropriate simultaneous execution of the same procedure in another processor. If no eligible procedure exists for the processor, the System Controller will set the 0 bit in the STATUS register true. In this case the system status vector remains unchanged. Access authorization to the interface registers is returned to the processor by resetting the L discrete in the STATUS register. When the processor detects that access authorization has been given by the L bit of the STATUS register being set false, it first checks to see if any procedures are eligible. This is accomplished by examining the 0 bit in the status register. If the 0 bit is true, indicating no procedures are currently eligible, the processor puts itself into procedure entry mode and reinitiates the entry sequence. If the 0 bit is false, indicating a procedure is eligible, the READ and WRITE registers are obtained to set up the data access linkages, and the EXECUTE register is obtained to set up control linkages. Control is passed to the specified procedure using the EXECUTE register value. The procedure may (in addition to whatever data processing activities are appropriate to it) compute a V register value. Exit Transition When a procedure exits, the processor will copy its V register value into the V register of the system controller interface, and set the exit discrete X, in the STATUS register true to indicate a procedure is being exited. The processor will then activate the System Controller by setting the L discrete in the STATUS register true, and set itself into an entry request mode. When the System Controller detects that a transition is to be initiated (by the L discrete in the STATUS register having been set), it will determine whether the entry, exit, or load transition has been specified. If the exit transition is specified, the value in the INDEX register is used to index into the data constructs, providing the data to incorporate the change in the system status vector caused by the exit procedure. The V register is accessed to perform this update. Then the System Controller indicates its readiness to honor further requests by resetting the L discrete in the STATUS register. Load Transition When a load transition is initiated under software control, the processor will first wait until the logic segment of the System Controller is not busy (indicated by the L discrete in STATUS being set false). At that time the processor will store in the INDEX register the number of the row in the System Controller matrices which is to be loaded. The data to be loaded into each of the EXECUTE, READ, WRITE TYPE.sub.i, A, T, F, and R matrices will be placed into the corresponding interface registers and the initial S vector will be placed in the V register. The load procedure is essentially an application program that transfers the System Controller data constructs from processor main memory to the System Controller. The processors sets the I discrete in the STATUS register true to indicate a load transition is being initiated and then activates the System Controller logic by setting the L discrete true in the STATUS register. The processor then resets itself into any one of the transition modes, entry, exit, or load depending on which transition is required. (It should be noted that the load procedure assumes there are no entry or exit transitions being performed for other processors. This can be guaranteed by assuming a load procedure is entered as the last eligible activity in the data constructs, when all processors are idle. Initializing S=0 will guarantee this status until load complete, at which time the initial S vector is passed.) SYSTEM CONTROLLER DETAILED COMPONENT DESIGN As shown in FIG. 3, the System Controller 10 is comprised of a synchronization and control logic circuit 14, a data constructs section 16, a procedure eligiblity determination logic circuit 18, and a system status update logic circuit 20. A specific detailed design for each of these four components is described below. Data Constructs As shown in FIG. 4, the data constructs section 16 of the System Controller 10 contains the System Controller memory. The memory may comprise eight random access memory modules, one for each of the R, A, F, T, TYPE.sub.i, EXECUTE, READ, and WRITE arrays. Each element (row) of the R, A, F, and T arrays contains the same number of bits, which is equal to the number of bits which comprise the system status register. It is not essential that memory word widths and individual array word-widths be identical as will become apparent. Depending on the machine application and the organization of the System Controller memory load logic, these memories can be either read only (ROM, PROM, etc.) or read/write. For purposes of illustration, read/write memories are utilized which are loaded by the processors. There are a total of 14 input/output interfaces for the data constructs section 16, each of which is described in the following Table II.
TABLE II
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DEFINITION
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ADDRESS
a multiple bit address bus
that is capable of addressing
each element of the R, A, T, F,
TYPE.sub.i, READ, WRITE, and EXECUTE
arrays. The arrays are addres-
sed concurrently, e.g., if AD-
DRESS = 2 then the second ele-
ment of each array is addressed.
CE
a one bit signal that enables
the eight memory modules to be
read or written. When CE is
true (i.e., logical 1) the con-
tents of each array element in-
dicated by ADDRESS is read
(R/--W = "1") or written (R/--W =
"0") to or from the associated
data bus. When CE is false
(i.e., logical "0") no array can
be read or written.
R/--W
a one bit signal input to each
of the eight memory modules that
specify a read or write action.
When R/--W is true (i.e., logical
"1") and CE is true (i.e., logi-
cal "1") the contents of the
array element indicated by AD-
DRESS is output on the corres-
ponding data bus. When R/--W is
false (i.e., logical "0") and CE
is true (i.e., logical "1") the
contents of each data bus is
written into associated ar-
ray element specified by AD-
DRESS.
S.sub.NEW
a multibit data input to the
read/write S register. S.sub.NEW
contains the updated status
vector returned by the system
status update logic as the re-
sult of an entry, exit or load
transition.
S.sub.LATCH
a control signal which, when
enabled (transitions from logi-
cal "0" to logical "1"), causes
the contents of S.sub.NEW data input
to be latched into the S regis-
ter. When S.sub.LATCH is disabled
(logical "0") the contents of
the S register remains unchanged
independent of changes in S.sub.NEW.
R.sub.i
T.sub.i
F.sub.i
multiple bit, bidirectional
A.sub.i data buses. Data from each
EXECUTE.sub.i of the eight memory modules
READ.sub.i are output to (or input from)
WRITE.sub.i the associated data buses.
TYPE.sub.i
a multiple bit bus on
which the contents of the S reg-
ister is output.
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Procedure Eligibility Determination Logic The procedure eligibility determination logic circuit 18 is contained within the System Controller 10 and contains the combinational logic necessary to determine procedure eligibility during entry transitions. A subsystem is eligible if the type of processor making the request (content of the TYPE.sub.p interface register) is equivalent to the processor type required by the selected subsystem (content of the TYPE.sub.i data bus), and all data conditions in the S vector relevant to enabling the subsystem are true (i.e., the vector resulting from forming the logical "OR" of the ith row of the R array and the current system status vector, S, contains all ones). FIG. 5 is a block diagram of the procedure eligibility determination logic. In reference to FIG. 3 and FIG. 5, line 30 represents a multiple bit data bus which contains the current contents of the TYPE.sub.p register in the processor/system controller interface 12. Line 32 is a multiple bit data bus which contains the processor type associated with the subsystem currently indexed, namely, TYPE.sub.i. Line 34 represents a multiple bit data bus which contains the R vector associated with the subsystem currently indexed, namely, R.sub.i. Line 36 is a multiple bit data bus from the S register of the data constructs section 16 (FIG. 4) which feeds the current contents of the S register to the procedure eligibility determination logic circuit 18. The output of the circuit 18 is a single data bit representative of a single component of the eligibility vector E along output line 38. E is logical "1" when the indexed subsystem is eligible and logical "0" otherwise. The logical expression for E may be written as follows: ##EQU1## Where the symbol is used to denote logical equivalence, and denotes the logical "AND" of each element of the vector operated on resulting in a single signal that will be true (i.e., logical "1") if and only if all elements in the vector are true, e.g., ##EQU2## The logic circuitry of FIG. 5 implements the above equation. In reference to FIG. 5 the signal along data bus lines 30 and 32 are fed to a multibit comparator 40 which produces a single output bit along line 42. The output bit is a logical 1 only if the data on the TYPE.sub.p data bus (line 30) is idential to the data on the data bus (line 32) corresponding to TYPE.sub.i (all bits equivalent), and otherwise the output along line 42 is a logical 0. The data bits along bus lines 34 and 36 are input to an OR gate which is represented in FIG. 5 by a single conventional OR symbol. It is understood, however, that each of the corresponding bits along lines 34 and 36 are separately OR'ed similar to the circuit shown in FIG. 6. The line running traverse of the input and output lines of the logical OR thus indicate the multiple OR circuit of FIG. 6. AND circuits are similarly represented in the drawings, e.g., FIG. 7. The definition utilized in the circuit design is such that S.sub.j =1 if the j.sup.th data condition is true, and R.sub.ij =0 of the j.sup.th data condition is relevant to procedure i. Consequently, the OR, AND sequential logic is appropriate. Thus, in reference to FIG. 5, the multiline output of OR gate 46 is fed to a corresponding multiple input AND gate 48 which provides a single output along line 50 to AND gate 52. A second input of AND gate 50 is derived from the output of comparator 40 along line 42. System Status Update Logic Circuit The system status update logic circuit 20 contains the combinational logic required to perform updates to the system status vector, S, appropriate to the transition being initiated. During an entry transition, the logical expression for the S.sub.NEW vector generated is: S.sub.NEW =S.sub.OLD .andgate.A.sub.i During an exit transition, the logical expression for the S.sub.NEW vector generated is: S.sub.NEW =(S.sub.OLD .andgate.T.sub.i).orgate.(A.sub.i .andgate.T.sub.i).orgate.(T.sub.i .andgate.F.sub.i).orgate.(V.andgate.F.sub.i) This expression is summarized by Table B.2 given in Appendix B. During the load transition, the logical expression for S.sub.NEW is: S.sub.NEW =V FIG. 7 is a block diagram of the system status update logic circuit 20. As shown in FIG. 7, the system status update logic circuit 20 comprises a plurality of OR and AND logic circuits (See FIG. 6 for clarification) identified by numbers 60, 62, 64, 66, 68 and 70. AND gates 64, 66, and 68 have one group of inverting input terminals and one group of non-inverting input terminals. Element 70 is a multiple input/output OR gate (see FIG. 6) wherein each input/output line is a multiple bit data bus. The output of OR gate 70 is fed to an input terminal of a 3-to-1 multiplexer 72 along lines 74. A second group of inputs to multiplex 72 is fed in along lines 76 from the output of AND gate 60. A third input is fed to multiplexer 72 along lines 78. The output of multiplex 72 is a data bus 80 representative of the new status vector S.sub.NEW and is fed to the S register of the data constructs section 16 (see FIGS. 3 and 4). The inputs (generally data buses) to update circuit 20 are fed in along lines 82, 84, 86, 88, 90, 92 and 94. Line 82 carries the single bit I discrete value from the system STATUS register of the interface 12. Line 84 carries the single X bit from the STATUS register. These two signals determine the select code at terminals SEL1, SEL2 of the multiplexer 72. If I is true (SEL1=1) a load transition is indicated (regardless of X) and multiplexer 72 passes the current V vector from lines 94 and 78 to the output data bus 80. If I is false (SEL1=0) the S.sub.NEW output is determined by the value of the X bit of the STATUS register. If X is true, S.sub.NEW is shown by the logical expression set forth above. This logical equation is associated with an exit procedure and is achieved using the condition code 01 for SEL1, SEL2=01. Associated logic circuits include input lines 86, 88, 90, 92 and 94, AND gates 60, 62, 64, 66, 68 and OR gate 70. When both X and I are false, SEL1, SEL2=0, 0, the new status vector is simply given by S.sub.OLD .andgate.A.sub.i and corresponds to an entry transition using AND gate 60 and lines 76. Synchronization and Control Logic Circuit The synchronization and control logic circuit 14 contains the clocked sequential logic required to control the operation and internal connections of all the components of the System Controller. The various input and output lines associated with the logic circuit 14 are generally shown in FIGS. 3 and 8 with a detailed schematic diagram illustrated in FIGS. 9A and 9B. The function of the L, I and X bits of the STATUS register and the INDEX register of the interface 12 have been set forth above (see Table I for example). Similarly, ADDRESS, CE, R/W and S.sub.LATCH have already been defined (see, for example, Table II). These latter signals are all generated by the synchronization and control logic circuit 14 and fed primarily to the data constructs section 16. The ADDRESS bus is also latched into the INDEX register of the interface 12 during entry transitions when an eligible subsystem is detected. Several additional signals are associated with the synchronization and control logic circuit 14. An ENTRY LATCH signal is a one bit control signal output by the synchronization and control logic circuit 14 to the processor interface registers. This signal causes the current values of the EXECUTE, READ, WRITE and the ADDRESS data buses to be latched into the EXECUTE, READ, WRITE and INDEX register in the processor interface 12. This signal is enabled only during entry transitions when an eligible subsystem is detected. The L RESET is a one bit control signal output by the synchronization and control logic circuit 14 to the processor interface registers. When enabled, this signal causes the L discrete of the processor interface STATUS register to be set false (i.e., logical "0"). The synchronization and control logic circuit 14 enables this signal at the completion of each transition. E is a one bit data signal input to the synchronization and control logic circuit 14 from the procedure eligibility determination logic circuit 18. This signal represents the eligibility (E="1") or non-eligibility (E="0") of the subsystem currently indexed. The E signal is used by the synchronization and control logic during entry transitions to detect an eligible subsystem. A specific embodiment of the synchronization and control logic is shown in FIG. 9. Other logic combinational arrangements are possible with the design criteria simply being to reproduce the various outputs of FIG. 8 with the various possible combinations of the input variables L, I, X, E and INDEX. The state diagram is shown in FIG. 10. In FIG. 10, the symbol .phi. indicates a "don't care" condition. The design of the logic circuit from the state diagram may be done in accordance with well known techniques as set forth, for example, by M. M. Mano, Computer Logic Design, Prentice-Hall, Inc., (1972), pp. 200-236. The state assignments utilized in the logic design are as follows:
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J-K Flop J-K Flip
Flop Flop
State
120 122 124 126 State
120 122 124 126
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A = 0 0 0 0 G = 1 1 0 0
B = 0 0 0 1 H = 1 1 0 1
C = 0 0 1 0 I = 1 0 1 1
D = 0 1 0 0 J = 1 0 0 0
E = 1 0 0 1 K = 1 1 1 0
F = 1 0 1 0 L = 1 1 1 1
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For implementing the state diagram four JK flip-flops 120, 122, 124 and 126 are used together with a clock generator 128 and loadable counter 130. With regard to the state assignments above, the most significant bit corresponds to flip-flop 120, the next most significant bit to flip-flop 122, etc. Counter 130 is loaded by the INDEX register from interface 12. The detail timing diagrams are illustrated in FIGS. 11-14 in reference to the design description set forth below. System Controller Internal Operation The System Controller has three internal modes of operation, one for each of the entry, exit and load transitions. During an entry transition (initiated by the L discrete of the interface STATUS register being set true) the synchronization and control logic circuit 14 begins accessing successive rows (i.e., each successive element of the eight memory modules) of the data construct matrix arrays, causing them to be output on their respective data buses. As each element is output, the subsystem eligibility determination logic circuit 18 computes the eligibility of the associated subsystems, and the system status update logic circuit 20 generates the S.sub.NEW vector based on the current system status vector and the A vector associated with the subsystem indexed. It will be recalled that the A vector is used to preclude inappropriate simultaneous execution of the same subsystem in another processor. If the subsystem is found eligible, the synchronization and control logic circuit 14 causes the S register to latch the S.sub.NEW vector, transfers access and control information (i.e., EXECUTE.sub.i : READ.sub.i ; WRITE.sub.i ; and ADDRESS) from the associated data buses to the processor interface registers (i.e., into the EXECUTE, READ, WRITE and INDEX registers respectively), and returns access authorization to the processor by resetting the L busy discrete in the interface STATUS register. If no subsystem is found eligible the synchronization and control logic circuit 14 notifies the processor by setting the 0 discrete in the interface STATUS register and returns access authorization to the processor. In this instance, no system status vector update occurs. Accessing successive rows of the R matrix and recycling to i=0 at each new entry transition enables the computer programmer to establish a priority application program sequence. Thus subsystems of a higher priority are placed earlier in the row sequence. It is noted however that such a sequential accessing is not required, and indeed, even a random accessing technique would be possible. An alternate approach which involves computing the matrix dot product in parallel as opposed to the sequential method described above is also possible. FIG. 11 represents the timing diagram of the control and data signals in the System Controller during an entry transition resulting in an eligible subsystem being detected which is associated with the address row three of the data constructs. It is assumed for the purpose of illustration that each memory array of the data constructs contains only four rows. FIG. 12 represents a similar timing diagram for an entry transition where no subsystem is detected as eligible. During an exit transition, the synchronization and control logic circuit 14 accesses one row (i.e., one element from each of the eight memory modules) in the data constructs section 16. The value stored in the INDEX register is used as the address to select the appropriate row. As each element is output on its associated data bus, the system status updated logic circuit 20 generates the S.sub.NEW vector from the current S vector, the T, F and A vectors associated with row indexed, and the V vector returned by the processor in the V register of the interface 12. The synchronization and control logic circuit 14 causes the S register to latch the S.sub.NEW vector and returns access authorization to the processor by resetting the L discrete in the STATUS register. FIG. 13 represents the timing diagram of the control and data signals in the System Controller during an exit transition. During a load transition the synchronization and control logic circuit 14 first causes the content of each of the interface data registers, R, A, T, F, EXECUTE, READ, WRITE, V, and TYPE.sub.i to be transferred to the associated data buses. Next, a row (i.e., one element from each of the eight memory modules) in the data constructs section 16 is accessed in a write mode. The value stored in the INDEX register of interface 12 is used to select the row accessed. This causes the content of each data bus to be written into the addressed element of the associated memory module. The synchronization and control logic circuit 14 latches the S.sub.NEW vector which is input from the interface 12 V register and returns access authorization to the processor by resetting the L discrete in the STATUS register. FIG. 14 represents the timing diagram of the control and data signals in the System Controller during a load transition. MODULAR CONSTRUCTION OF SYSTEM CONTROLLER In the following description of the invention, several modular construction approaches are set forth which take advantage of standardized components in various cascaded configurations to increase overall System Controller capacity. These are in addition to (and in support of) the modular increases in processing power available in transition machines by adding individual processors and memories. The embodiments described below can be implemented individually or in combination to obtain designated performance characteristics. Modular Disjoint Expansion In one embodiment of the invention a modular disjoint expansion of the System Controller may be utilized. Effectively, a plurality of System Controllers 10a, 10b, 10c may be utilized each with its associated multiport controller interface 12a, 12b, 12c as shown in FIG. 15. The configuration is particularly appropriate for batch processing wherein many disjoint computations may be running contemporaneously across all processors. If a processor is locked out of one System Controller, e.g., 10a, it may still be provided access to a subsystem through another System Controller, e.g. 10b. Each of the System Controllers 10a, 10b, 10c etc. is configured as shown in FIG. 3 and operates to enable subsystems specified within its data construct section independently of the other System Controllers. Each data construct section within the System Controllers 10a, 10b, 10c etc. is configured as shown in FIG. 4 having its own separate READ, EXECUTE, WRITE, TYPE, A, T, F and R registers independent of the comparable registers in other data construct sections of other System Controllers. The complete disjoint configuration of the transition machine of FIG. 15 effectively prevents interprocessor access contention over the System Controllers. Any convenient number of disjoint System Controllers and corresponding interface registers may be utilized depending upon the size of the processing required. The disjoint configuration requires a slight modification to the standard processor/system controller interface procedure. Specifically, a means of indicating the specific System Controller that contains the data constructs for each active subsystem must be provided. This is required to ensure that when the subsystem exits, the exit transition is performed by only the System Controller that dispatched the subsystem originally. These are numerous methods to incorporate this capability. For example, with the configuration shown in FIG. 15, the processor can maintain an indicator of the specific System Controller which contains the data constructs for the procedure currently being executed. This is facilitated by the fact each set of system controller interface registers are uniquely addressable. The operational flow diagram of the processor interface procedure for this configuration is shown in FIG. 15a. This approach requires only a very minor modification to the standard processor/system controller interface logic 12 as shown in FIG. 16. Modular Conjoined Expansion An additional method of expanding the capability of the System Controller in accordance with the teachings of the invention is to expand the effective size of the data constructs section either horizontally or vertically. A horizontal expansion of the data construct capacity enables more data conditions to be utilized, and a vertical expansion of the data construct capacity enables a greater number of subystems to be included within the system, effectively increasing the number of programming steps possible in solving the algorithm. In both the horizontal and vertical expansion embodiments, modularity is achieved using a plurality of fixed word-length conventional memory sections 16, procedure eligibility determination logic circuits 18, system status update logic circuits 20 and a single synchronization and control logic circuit 14. In order to reduce the amount of logic required to implement the conjoined horizontal expansion of the System Controller, the data constructs section 16 and procedure eligibility determination logic circuits 18 of the standard System Controller have been broken down into more basic components, as shown in FIGS. 17 and 18 respectively. The data constructs section 16 comprises a memory component 1000 in which any one of the various data constructs R, A, T, F, TYPE.sub.i, READ, WRITE and EXECUTE can be stored and a separate register component 1002 in which the S vector can be stored. The procedure eligiblity determination logic circuit 18 is seen to comprise a type comparison component 1004 and a dot product component 1006. The type comparison component compares the two type indicator inputs (TYPE.sub.i and TYPE.sub.p) for logical equivalence, generating one component of the procedure eligiblity indicator. The dot product component 1006 generates another component of the procedure eligibility indicator based on the system status vector (S) and the requirements vector (R.sub.i) which are input thereto. Horizontally Expanded System Controller A horizontally expandable System Controller 210 and modified interface 212 is illustrated in FIGS. 19A, 19B, and 19C. The System Controller 210 is seen to comprise a synchronization and control logic circuit 214, a plurality of data constructs memory components 216a-216t (where at least the memories within each modulor unit, such as 216e-216b will have compatible characteristics such as word-width), a plurality of data constructs register components 217a, 217b, 217c, and 217d, a procedure eligibility determination logic type comparison component 219, a plurality of procedure eligibility determination logic dot product components 218a, 218b, 218c, and 218d, and a plurality of status update logic circuits 220a, 220b, 220c and 220d. The synchronization and control logic circuit 214 is configured as shown in FIGS. 9A and 9B; each of the data construct memory components 216 and 217 is configured as shown in FIG. 17; each procedure eligibility determination logic circuit component 218 and 219 is configured as shown in FIG. 18; and each system status update logic circuit 220 is configured as shown in FIG. 7. Data construct section components 216e, 216f, 216g, 216h, and 217a, procedure eligibility determination logic circuit 218a and the system status update logic circuit 220a form a modular unit 225a as shown by the dotted line in FIG. 20A. A second modular unit 225b is formed by the data construct section componetns 216i, 216j, 216k, 216l, and 217b, procedure eligibiity determination logic circuit 218b and the system status update logic circuit 220b. Additional modular units 225c and 225d are made up from their elements 216m, 216n, 216o, 216p, 217c, 218c, 220c, and elements 216q, 216r, 216s, 216t, 217d, 218d, and 220d, respectively. In accordance with the principles of the invention any number of modular units 225 may be employed as will become clear with respect to the operation of the circuit of FIG. 19. Inasmuch as each of the modular units 225a-225d is identical, the following description is applicable to any one unit, and consequently, no suffix is utilized unless a particular unit is intended. Within each modular unit 225, the data construct section components 216 and 217, procedure eligibility determination logic circuit component 218 and status update logic circuit 220 are interconnected with one another in a similar fashion to that shown in FIG. 3. The primary difference between the interconnection of the elements between FIG. 3 and FIG. 19 is the utilization of a multiple input AND gate 227. The inputs of AND gate 227 are connected to receive the outputs of the procedure eligibilty determination logic circuit components 218 and 219 along the lines 238a-238e. The output of AND gate 227 is fed along a line 239 to the input of a synchronization and control logic circuit 214. This input signal to the synchronization and control logic circuit 214 functions the same as the input E signal to synchronization and control logic circuit 14 of FIG. 3. ANDing all of the outputs of the procedure eligibility determination logic circuit components 218 and 219 of the individual modular units is required inasmuch as each modular unit operates with only a part of the system status vector (a component group of data conditions), and eligibility of a particular subsystem is only appropriate if each of the partial dot products of the system status vector S and the relevance matrix R indicates a true eligibility. Additionally, the type of processor making the request must be equivalent to the processor type requirement for the indexed subsystem. As a consequence, a given subsystem is eligible if an only if all of the outputs of the procedure eligibility determination logic circuit components 218a-218d and the type comparison component 219 are ANDed together. In effect, the R, T, F and A matrices as well as the S vector are partitioned by the modular unit arrangement into multiple groups of columns modulo M. M is the number of columns available in a modular unit 225, i.e. the number of columns in each of the R, T, F, and A matrices and the S and V vectors within the data construct section components 216 and 217 and is determined by the word-width of the memories that are selected for the particular implementation. The interface 212 is configured similar to the interface of FIG. 3 but has been expanded to accommodate the modifications as required by the horizontal expansion of the System Controller. The interface 212 is seen to comprise a STATUS register 240 and an INDEX register 242 utilized in all entry, exit and load transitions and a READ register 244, WRITE register 246 and EXECUTE register 248 utilized during entry and load transitions. All these registers are used in a similar fashion as described in relation to FIG. 3. Additional registers are also utilized such as V registers 250-253 (exit and load transition) and the TYPE.sub.p register 255 (entry transition). The V register is composed of four separate registers, one for each of the four modular units 225 as illustrated. The V vector is effectivley broken down into components modulo M. Components V.sub.0, V.sub.1, V.sub.2, and V.sub.3 are stored respectively in registers 250, 251, 252, and 253. Each component is fed to a separate one of the modular units 225. Numerous registers of the interface 212 are utilized only during the load transition. These registers comprise the A, T, F, R, and TYPE; registers of FIG. 3. For the horizontally expanded System Controller of FIG. 19, however, the first four of these registers are likewise broken down modulo M so that again one component of each of these data constructs is fed to each of the modular units 225. For example, the A construct is broken up into components A.sub.0, A.sub.1, A.sub.2 and A.sub.3. Each component is fed to a separate one of the modular units 225. Likewise, the constructs T, F and R are also broken up in a similar fashion. These load registers of the processor/system controller interface must thus be expanded in accordance with the number of modular units 225 utilized in forming the entire System Controller. As shown in FIG. 19, register 260 stores component A.sub.0, register 261 stores component T.sub.0, register 262 stores component F.sub.0 and register 263 stores component R.sub.0. A single TYPE.sub.i register 264 is connected to the data constructs section memory component 216d that is dedicated for storing the processor type requirements for each subsystem. The TYPE.sub.i register 264 is to be distinguished from the entry TYPE.sub.p register 255. As an alternate embodiment, however, a multiplexing arrangement may be utilized where a single interface register would be employed for the run time (entry transition) and load operations. The multiplexing unit would be responsive to the I bit of the status register 240 for example to switch data within the single TYPE register as appropriate for entry or load operations. The numerous other components of the A, T, F and R matrices are shown in FIG. 19 and identified by numerals 270-273 for the second component, 280-283 for the third component and 290-293 for the fourth component. The number of components naturally corresponds to the number of modular units 225. These register sets have been drawn together in the interface 212 to simplify the description of the modular units 225 in the System Controller. However, each of these registers, for example the A registers, may be contiguous as is the V register (contiguous register 250-253 storing components V.sub.0, V.sub.1, V.sub.2 and V.sub.3). In operation, when a procedure entry transition is initiated, all of the component groups are enabled simultaneously by the common synchronization and control logic circuit 214. The component groups of the modular units 225 generate component procedure eligibility indicators E.sub.0, E.sub.1, E.sub.2 and E.sub.3 based on the four groups of M data conditions maintained by the entire System Controller. The type comparison component 219 also generates a component, designated E.sub.t, of the procedure eligibility indicator. For a given subsystem to become eligible for execution it must be found eligible in all component groups. Consequently, each component of the eligibility indicator E is connected to AND gate 227 and fed to the synchronization and control logic circuit 214 along the line 239. The synchronization and control logic circuit 214 operates as in FIGS. 9A and 9B to control the output of the data construct section 216. The procedure entry transition continues until an eligible procedure is detected, or it is detected that no procedures are currently eligible. Assuming a subsystem is found eligible, the interface 212 is loaded with the appropriate values of the READ register 216a, WRITE register 216b, and EXECUTE register 216c, the updated S vector is generated and latched in each of the component groups of the modular units 225, and the L busy discrete in the STATUS register 240 is reset. When a procedure exit transition is initiated, all of the modular units 225 are enabled simultaneously and perform the appropriate system status update to the M data conditions maintained in each modular unit 225 in a parallel fashion. The L busy discrete of the status register 240 is then reset, completing the procedure exit transition. The V vector returned by any individual processor to the interface 212 may be transferred sequentially into the registers 250-253 by the processor during an exit transition. The complete V vector, V.sub.0, V.sub.1, V.sub.2 and V.sub.3 is then fed in parallel to the modular units 225. When a load transition is initiated, the data from the load registers, namely registers 260-263, 270-273, 280-283 and 290-293 are transferred simultaneously to the appropriate data construct section 216 of the modular units 225. The TYPE.sub.i register 264 is loaded simultaneously into the TYPE data construct section 216d. Data from the registers 244, 246, 248, 250-253 are also transferred simultaneously to the appropriate data constructs sections 216 of the modular units 255. The registers 250-253 are used to load the status vector S whose components S.sub.0, S.sub.1, S.sub.2 and S.sub.3 are stored in registers 217a-217d. This loading is achieved via the logic circuit of FIG. 7. When the data transfer is complete, the L bit of the STATUS register 240 is reset. For the horizontally expanded System Controller as illustrated in FIG. 19, the worst case transition time depends only upon the number of rows (N) in the modular unit 225. Effectively, the time required to perform an entry, exit or load transition remains constant and is independent of the horizontal size of the System Controller once the interface registers have been loaded. Vertically Expanded System Controller FIGS. 20-22 illustrate a vertically expanded embodiment of a System Controller 310 and associated interface 312. As in the horizontally expandable System Controller, the vertically expanded System Controller comprises a plurality of modular units 325 designated as 325a, 325b, 325c and 325d. Each modular unit 325 comprises a plurality of data construct memory components 316, a procedure eligibility determination logic 318 and a system status update logic circuit 320. A single synchronization and control logic circuit 314 and a single data constructs register component 317 are employed and are interconnected to the modular units 325 as shown. The four circuits 314, 316, 317 and 320 are the same as their counterpart circuits 214, 216, 217 and 220 previously described in relation to FIG. 19. Circuit 318 is the same as its counterpart circuit 18 shown in FIG. 6. In the vertically expanded System Controller 310, the matrices A, T, F and R as well as the TYP.sub.i, READ, WRITE and EXECUTE arrays are partitioned into multiple groups of rows modulo N. N is the number of rows supported by the standardized component or the modular unit 325. Each of these groups of data constructs is loaded into a separate group data construct memory components 316a1 . . . 316a8, 316b1 . . . 316b8, 316c1 . . . 316c8, and 316d1 . . . 316d8 through the processor interface registers 312. A single system status vector S is maintained in the data constructs section register component 317 on which each modular unit 325 operates. The interface 312 is seen to comprise a STATUS register 340, INDEX register 342, and a plurality of registers identified as READ register 344, WRITE register 346, EXECUTE register 348, V register 350 and TYPE.sub.p register 355. The interface 312 also comprises a plurality of registers used only during the load transition. These registers comprise TYPE.sub.i register 360, R register 364, A register 365, T register 366 and F register 367. The prime difference between the interface 312 and the previously described interface 212 of FIG. 19 or interface 12 of FIG. 3 is the utilization of a two-field INDEX register 342. The first field of the INDEX register is a group selection field 380, and the second field of the INDEX register 342 is a displacement field 382. The group selection field 380 designates which component group, namely which modular unit 325 contains the row in question (the subsystem being indexed). The displacement field 382 designates which row within the selected modular unit 325 actually contains the desired information. The group selection field 380 is embodied herein by a two-bit field designation H.sub.1 and H.sub.2. Additional logic circuitry is described for selecting the particular modular unit 325 designated by the bits H.sub.1 and H.sub.2 and to multiplex data and control signals appropriately to and from the selected modular unit. In general there will be log.sub.2 N bits allocated to the group selection function. (The nomenclature y indicates the first integer value greater than or equal to y.) In order to achieve appropriate routing of the data and control signals, the System Controller of FIG. 20 further comprises a status selection logic circuit 400, a load control logic circuit 402, an entry/load bidirectional multiplexer 404 and a load multiplexer 406. The status selection logic circuit 400 is shown in detail in FIG. 21, and the load control logic circuit 402 is shown in detail in FIG. 22. As shown in FIG. 21, the status selection logic circuit 400 is seen to comprise a priority encoder 410, OR gate 412, a two-to-one multiplexer 414, a NOR gate 416 and a status multiplexer 418. The priority encoder 410 has input lines 420a-420d connected to receive the outputs E.sub.0, E.sub.1, E.sub.2, E.sub.3 of the corresponding procedure eligibility determination logic circuits 318a-318d. Lines 420a-420d are also connected to the inputs of the multiple input OR gate 412 which provides a single output E.sub.master along a line 422. Line 422 is in turn interconnected as an input to the synchronization and control logic circuit 314 of FIG. 20A. The output of the priority encoder 410 depends upon the particular values along its input lines 420a-420d. The truth table for the priority encoder 410 is shown in the following Table III.
TABLE III
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INPUT LINES 420 OUTPUTS
420d 420c 420b 420a 424a 242b
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0 0 0 0 0 0
X X X 1 0 0
X X 1 0 0 1
X 1 0 0 1 0
1 0 0 0 1 1
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Legend:
X = don't care
1 = true
0 = false
The binary output of the priority encoder 410 effectively establishes a coded priority sequence such that assuming simultaneous eligibility of subsystems within each modular unit 325, priority is assigned to the first unit, namely modular unit 325a. Absent an eligible subsystem within modular unit 325a the next priority is given to modular unit 325b etc. The output of the priority encoder is connected via lines 424a and 424b to multiplexer 414 (FIG. 21) as well as entry/load bidirectional multiplexer 404 (FIG. 20). The binary coded output from the priority encoder which feeds the multiplexer 404 effectively routes the address designation values of interest to the READ register 344, WRITE register 346 and EXECUTE register 348 from the appropriate one of the modular units 325. Further inputs to the multiplexer 414 (FIG. 21) are provided by the multiple input NOR gate 416 along a select line 426. The two inputs to the NOR gate 416 are provided by the I and X bits from the STATUS register 340. The output of NOR gate 416 is high during an entry transition and low during either an exit or load transition. The four data inputs to the multiplexer 414 are provided by the most significant bits of the INDEX register 342, namely, the H.sub.1 and H.sub.2 bits of the group selection field 380 and the coded output of the priority encoder 410. (In general there will be log.sub.2 N outputs from the priority encoder and log.sub.2 N bits H.sub.1, H.sub.2, . . . H .sub.log.sbsb.2.sub.N .) An entry transition provides a high output along the select line 426 effectively passing the signals along the input lines 424a and 424b to the output of the multiplexer 414 along lines 428a and 428b. During an exit or load transition, the low output signal along the select line 426 effectively feeds the group selection field H.sub.1, H.sub.2 from the input of the multiplexer 414 to its output along the output lines 428a and 428b. In turn, lines 428a and 428b are interconnected to the status multiplexer 418. Status multiplexer 418 has a plurality of input data bus lines 430a-430d and a single output data bus line 432. The select inputs along lines 428a and 428b determine which of the input lines 430a-430d is fed to the output line 432. The truth table for designating operation of the multiplexer 418 is shown below in Table IV.
TABLE IV
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INPUTS OUTPUT
428a 428b 432
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0 0 430a
0 1 430b
1 0 430c
1 1 430d
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The input lines 430a-430d of the multiplexer 418 are fed from the corresponding outputs of the modular units 325a-325d. In particular, input lines 430a-430d are fed from the outputs of the system status update logic circuits 320a-320d providing updated system status output signals S.sub.0, S.sub.1, S.sub.2 and S.sub.3 respectively. The output of the multiplexer 418 is fed as a S.sub.new master signal along line 432 (FIG. 20) as an input signal to the data construct register component 317. A circuit diagram of the load control logic circuit 402 is shown in FIG. 22. The load control logic circuit 402 is seen to comprise a binary decoder 440 and a load multiplexer 442. The input to the binary decoder 440 is taken from the high order bits of the INDEX register, mainly the group selection field 380. These bits H.sub.1 and H.sub.2 are the same as those utilized in the multiplexer 414 of FIG. 21. The binary decoder 440 provides output signals along the four lines 444a-444d which are fed to the inputs of the load multiplexer 442. The operation of the binary decoder 440 is defined by Table V below.
TABLE V
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INPUTS OUTPUTS
H.sub.1
H.sub.2 444a 444b 444c 444d
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0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
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The load multiplexer 442 effectively selects between two groups of input lines, each group having four lines therein as determined by the input along a select line 446. Select line 446 is fed from the I bit of the STATUS register 340 (FIG. 20A). During a load transition I=1 and the output of the binary decoder 440 is effectively passed to the output of the load multiplexer 442 along its output lines 448a-448d. When I=0, namely during an entry or exit transition, the CE signal from the synchronization and control logic circuit 314 is fed identically to each of the output lines 448a-448d of the load multiplexer 442. The operation of the circuits illustrated in FIGS. 20-22 may be understood in reference to a description of the entry, exit and load transitions. When an entry transition is initiated, all of the component groups, namely, the modular units 325 are enabled simultaneously by the common synchronization and control logic circuit 314. The modular units 324 generate procedure eligibility indicators E.sub.0 -E.sub.3 in parallel for the particular row indexed by the synchronization and control logic circuit 314. The system status update logic circuits 320a-320d of the modular units 325 generate the updated system status signals S.sub.0 -S.sub.3 in parallel for the particular row indexed. In the representative example of four modular units 325 there will be, in effect, four separate eligibility indicators E.sub.0 -E.sub.3 and four updated system status vectors S.sub.0 -S.sub.3 generated in parallel. If any of the eligibility indicators correspond to a subsystem eligible condition (E=1), the synchronization and control logic circuit 314 causes the S.sub.new vector for the modular unit 325 containing the eligible subsystem to be latched into the common S register of the data constructs register component 317. The selection of which of the vectors S.sub.0 -S.sub.3 will in fact be passed on as the new system status vector (termed the system status master vector, S.sub.new master) is determined by the priority encoder 410 as per truth Table III. Thus, although all of the system status update logic circuits 320a-320d may in fact compute their own S vector, only one of these vectors will be passed on and become the new system status vector depending upon the output of the priority encoder 410. During the entry transition, multiplexer 414 selects the input lines 424a and 424b (since the output of NOR gate 416 is high) and passes signals generated thereon to its output along lines 428a and 428b. These output lines are, in effect, the select lines for the status multiplexer 418 and are utilized to select one of the status vectors S.sub.0, S.sub.1, S.sub.2 and S.sub.3. The synchronization and control logic circuit 314 also addresses each of the data construct memory components 316 for passing the appropriate data to the READ register 344, WRITE register 346 and EXECUTE register 348 of the interface 312. Appropriate multiplexing from the data construct sections 316a-316d into the interface READ, WRITE and EXECUTE registers is determined by the entry/load bidirectional multiplexer 404 utilizing again the output of the priority encoder 410. Thus, once a particular modular unit 325a-325d is selected during an entry transition, a status vector appropriate to that selected modular unit is latched into the S register and the READ, WRITE and EXECUTE addresses are passed from that selected unit to the READ, WRITE and EXECUTE registers of the interface 312. The displacement field of the INDEX register 342 is loaded with the row number of the eligible procedure (i.e. ADDRESS) and the group selection field 380 is loaded with the output of the priority encoder 410 (i.e., lines 424a and 424b) which indicates the component group 325 that contains the eligible procedure. If no procedure is determined eligible during an entry transition, the 0 bit in the STATUS register 340 is set true, otherwise it is set false. The L bit is then set false to allow a subsequent access by processors to the interface 312 and System Controller 310. When a procedure exit transition is initiated, all component groups, namely, all of the modular units 325 are enabled simultaneously and generate in parallel an updated system status vector, S.sub.0 -S.sub.3, for the row specified by the displacement field 382 of the INDEX register 342. The status selection logic circuit 400 then selects the appropriate one of the updated status vectors which is to be stored in the data construct register component 317. The selection of the status vector for the S.sub.new master signal along line 432 is now made by means of the group selection field 380 which provides inputs to the multiplexer 414 (FIG. 17). In the exit transition mode the output of NOR gate 416 is low thereby selecting the H.sub.1, H.sub.2 bits forming the group selection field 380, and these bits in turn are utilized as the select inputs to the status multiplexer 418 thereby selecting one of the calculated outputs of the system status update logic circuits 320a-320d as the new system status vector. The selected calculated output of the system status update logic circuit 320 corresponds to the modular unit 325 being designated by the exiting processor. The L bit of the status interface register 340 is then reset to allow subsequent access by the data processors. When a load transition is initiated, the data from the processor/System Controller interface register 312 is transferred to the particular modular unit 325 specified by the group selection field 380 of the INDEX register 342 and into the particular row of the data construct memory components 316 as specified by the displacement field 382 of the INDEX register 342. This selection is performed by the load control logic 402. The select line 446 of the load multiplexer 442 is controlled by the I bit of the STATUS register 340. When I is high (logical 1) the lines 444a-444d which feed the load multiplexer 442 are passed to the output lines 448a-448d. The code present on the input lines 444a-444d is generated by the binary decoder 440 in response to the code of the group selection field 380 as per Table V. The output of the load multiplexer 442 along the output lines 448a-448d control the CE terminals of the data construct section 416a-416d, respectively. As a consequence, the load control logic circuit 402 controls which of the data construct sections 416 will be enabled for loading data along its input lines. The data to be loaded into the data construct memory components 316 is fed by means of the registers of the interface 312. These registers include the TYPE.sub.i register 360, READ register 344, WRITE register 346, EXECUTE register 348, R register 364, A register 365, T register 366 and F register 367. The inputs from these registers are multiplexed into the modular units 325 by means of the load multiplexer 406 and the entry/load bidirectional multiplexer 404. The load multiplexer has its select lines controlled by the group selection field 380 of the INDEX register 342. This establishes a data path from the interface registers 360, 364, 365, 366 and 367 to only the data constructs memory components 316a-316d that are to be loaded. The select lines of the entry/load multiplexer 404 are also set equal to the group selection field 380 of the INDEX register during load transitions, as described previously in relation to the status selection logic of FIG. 21. A data path is therefore, also established from the interface registers 344, 346 and 348 by the entry/load bidirectional multiplexer 404 to only the data constructs memory components 316 a-316d that are to be loaded. As a consequence, only the appropriate data construct sections 316a-316d is enabled and loaded by the load registers of the interface 312. Once all of the data has been transferred, the L bit of the status interface register 340 is reset, completing the load transition. It is to be noted that during the load transition, the status selection logic circuit 400 permits the current value of the V interface register to be fed as an output S.sub.new master along line 432 therefore providing an input to the data construct section register component 317 for loading the initial system status vector. In the vertically expanded System Controller 310, the worst case transition time depends only upon the number of rows N in the modular unit 325. Thus, the time required to perform an entry or exit transition remains constant independent of the total number of rows maintained by the System Controller. While there has been described and illustrated specific embodiments of the invention, it will be clear that variations in the details of the embodiments specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claims. APPENDIX A In the implementation of the model of parallel computation, specific definitions are assigned to the set of constructs R, S and E and the matrix algebraic operation, ".multidot." on these constructs which effect a transition system. Definition A.1. The system status vector, S is a set of binary status indications on the data set d such that for every data condition there is an associated status indications, S.sub.j in S if and only if S.sub.j is relevant to enabling some procedure in the system. S.sub.j =1 if the associated data condition is met, S.sub.j =0 otherwise. Definition A.2. The system eligibility vector, E is a set of binary status indications on the set of unary predicates, R.sub.i, indicating whether R.sub.i is currently satisfied, enabling the associated procedure. E.sub.i =1 indicates the associated unary predicates are satisfied; E.sub.i =0 otherwise. Definition A.3. A system status condition, S.sub.j is relevant to enabling procedure i if and only if the data condition whose status is indicated by S.sub.j is included in the unary predicates, R.sub.i. Proposition A.1. The unary predicates, R.sub.i can be represented as a set of binary relevance indications associated (and in conjunction) with each of the conditions whose status is maintained in S. This proposition follows directly from the previous definitions. Definition A.4. The relevance matrix, R is comprised of binary relevance indications, r.sub.ij indicating the relevance of system status condition j to enabling procedure i. Relevance is indicated by r.sub.ij =0, irrelevance by r.sub.ij =1. Definition A.5. The logical dot product, P of a matrix M times a vector, V with compatible dimensions is defined as the vector, P=M.multidot.V, where ##EQU3## Proposition A.2. The system eligibility vector, E can be computed appropriate to a given state of the system by taking the logical dot product of the relevance matrix R and the system status vector, S. Proof: From Definiti | ||||||