Apparatus and method for scheduling virtual circuit data for DMA from a host memory to a transmit buffer memory

Abstract

A method of scheduling the transmission of cells from a network node involves storing entries in a schedule table at predetermined locations, wherein each location represents a point in time at which a cell is to be transmitted. Each entry in the table contains a pointer to a list of virtual circuits having cells scheduled for transmission at the time corresponding to the location of the entry in the table. When a VC has a cell to be transmitted at a particular time, the VC is queued to the head, rather than the tail, of the list of VCs pointed to by the pointer located at the entry in the table corresponding to the time at which the cell is to be transmitted. The VC is therefore the first VC transmitted from the list of VCs.

Claims

What is claimed is:

1. An apparatus for scheduling transmission of data units, the scheduling apparatus comprising:

a schedule table having a plurality of entries, each entry representing a time at which a data unit is to be transmitted, each entry pointing to a data structure of data units scheduled for transmission at the time represented by the entry; and

a scheduler operative such that when a particular data unit is to be a first data unit transmitted at a particular time, the scheduler changes the schedule table entry representing the particular time such that the entry points to the particular data unit and such that the particular data unit becomes a first data unit in a data structure scheduled to be transmitted at the particular time.

2. The apparatus of claim 1, wherein:

each entry of the schedule table includes:

a head pointer pointing to a beginning of a list of data units scheduled for transmission at the time represented by the entry, and

a tail pointer pointing to an end of the list of data units; and

the scheduler is operative such that when a particular data unit is to be a first data unit transmitted at a particular time, the scheduler changes the head pointer of the schedule table entry representing the particular time such that the head pointer points to the particular data unit, and such that the particular data unit becomes a beginning of a list of data units scheduled to be transmitted at the particular time.

3. An apparatus for scheduling transmission of cells for different virtual circuits from a network node, the scheduling apparatus comprising:

a schedule table having a plurality of entries each entry representing a time at which a cell is to be transmitted, each entry including:

a head pointer pointing to a beginning of a list of virtual circuit numbers, each virtual circuit number representing a virtual circuit having cells scheduled for transmission at the time represented by the entry and

a tail pointer pointing to an end of the list; and

a scheduler operative such that when a particular virtual circuit has a cell that is to be the first cell transmitted at a particular time, the scheduler adjusts the head pointer of the schedule table entry representing the particular time such that the head pointer points to the virtual circuit number representing the particular virtual circuit, and such that the virtual circuit number becomes a beginning of a list of virtual circuit numbers that represent virtual circuits with cells scheduled to be transmitted at the particular time.

4. A method of scheduling transmission of data units, the method comprising:

storing entries in a schedule table, each entry representing a time at which a data unit is to be transmitted, each entry pointing to a data structure of data units scheduled for transmission at the time represented by the entry; and

when a particular data unit is to be a first data unit transmitted at a particular time, changing the schedule table entry representing said particular time such that the entry points to the particular data unit such that the particular data unit becomes a first data unit of a data structure scheduled to be transmitted at the particular time.

5. The method of claim 4, wherein:

each entry in the schedule table includes:

a head pointer pointing to a beginning of a list of data units scheduled for transmission at the time represented by the entry, and

a tail pointer pointing to an end of the list of data units; and

the method further comprising, when a data unit is to be the first data unit transmitted at a particular time, changing the head pointer of the schedule table entry representing the particular time such that the head pointer points to the particular data unit, and such that the particular data unit becomes a beginning of a list of data units scheduled to be transmitted at the particular time.

6. A method of scheduling transmission of cells for different virtual circuits from a network node, the method comprising:

storing entries in a schedule table, each entry representing a time at which a cell is to be transmitted, each entry including:

a head pointer pointing to a beginning of a list of virtual circuit numbers, each virtual circuit number representing a virtual circuit having cells scheduled for transmission at the time represented by the entry, and

a tail pointer pointing to an end of the list; and

when a particular virtual circuit has a cell that is to be the first cell transmitted at a particular time, adjusting the head pointer of the schedule table entry representing the particular time such that the head pointer points to the virtual circuit number representing the particular virtual circuit, and such that the virtual circuit number becomes a beginning of a list of virtual circuit numbers that represent virtual circuits with cells scheduled to be transmitted at the particular time.

7. The apparatus of claim 1, wherein the apparatus is an asynchronous transfer mode adapter.

8. The apparatus of claim 1, wherein each entry of the schedule table defines a linked list.

9. The apparatus of claim 1, further comprising:

a work list having a first entry that includes a work list head pointer and a work list tail pointer, the first entry defining an ordered list of data units scheduled for transmission; and

wherein the scheduler is operative to append a schedule table entry to a tail of the work list, such that the data structure of data units scheduled for transmission at the time represented by the schedule table entry are at an end of the ordered list.

10. The apparatus of claim 2, wherein each entry of the schedule table further includes a valid bit, wherein when the valid bit of an entry is set to a first logic level, the entry is valid.

11. The apparatus of claim 3, wherein the different virtual circuits are of a variable bit rate class.

12. The method of claim 4, wherein each entry of the schedule table defines a linked list.

13. The method of claim 4, further comprising:

storing a first entry in a work list, the first entry including a work list head pointer and a work list tail pointer, the first entry defining an ordered list of data units scheduled for transmission; and

appending a schedule table entry to a tail of the work list, such that the data structure of data units scheduled for transmission at the time represented by the schedule table entry are at an end of the ordered list.

14. The method of claim 5, wherein each entry of the schedule table further includes a valid bit, wherein when the valid bit of an entry is set to a first logic level, the entry is valid.

15. The method of claim 6, wherein the different virtual circuits are of a variable bit rate class.

16. The apparatus of claim 3, further comprising:

a work list having a first entry that includes a work list head pointer and a work list tail pointer, the first entry defining an ordered list of virtual circuit numbers representing virtual circuits having cells scheduled for transmission; and

wherein the scheduler is operative to append a schedule table entry to a tail of the work list, such that the list of virtual circuit numbers representing virtual circuits having cells scheduled for transmission at the time represented by the schedule table entry are at an end of the ordered list.

17. The method of claim 6, further comprising:

storing a first entry in a work list, the first entry including a work list head pointer and a work list tail pointer, the first entry defining an ordered list of virtual circuit numbers representing virtual circuits having cells scheduled for transmission; and

appending a schedule table entry to a tail of the work list, such that the list of virtual circuit numbers representing virtual circuits having cells scheduled for transmission at the time represented by the schedule table entry are at an end of the ordered list.

Description

FIELD OF THE INVENTION

The present invention relates generally to the field of computer networks, and, more particularly, to the scheduling of data transfers from a host to a network end-node adapter such that data is available for transfer from the adapter to the network in a timely manner.

BACKGROUND OF THE INVENTION

Asynchronous Transfer Mode (ATM) is a class of digital switching technologies for computer networks. ATM is a cell based technology; that is, compared to common packet technologies such as X.25 or frame relay, ATM transfers short, fixed length units of information called cells. Accordingly, larger packets or protocol data units (PDU's) from a source are broken up into these fixed length cells for transmission, and then reassembled at their destination.

ATM is a connection based technology, meaning that all communications between two stations occur via a virtual circuit (VC) which is initially established between them. ATM is designed to support users having diverse requirements for service. For example, a given VC may be established in accordance with a constant bit rate (CBR) or variable bit rate (VBR) service type. Once established, the service type for a given VC is maintained in accordance with quality of service (QoS) parameters for that type.

In order to control the transmission of VBR cells from an ATM adapter over multiple VCs, it is known to employ a scheduling process which scans a schedule table having multiple entries. Each entry in the schedule table contains a pointer to a list of VCs to be transmitted at a given time. This table is scanned at the link rate. For each entry, a cell for the VC at the head of the list pointed to by that entry is transmitted on the link.

Once a cell for a given VC is transmitted on the link, the VC is rescheduled into the schedule table at a location dictated by the QoS parameters for the VC. In the past, the VC has simply been queued to the tail of the linked list pointed to by the table entry at which it is rescheduled. This method of scheduling has been found to result in less than optimum performance. An improved method of scheduling is therefore desired.

SUMMARY OF THE INVENTION

According to the broad aspects of the present invention there is provided an apparatus and method for scheduling the transmission of data units. Accordingly, a schedule table stores entries at locations, each location representing a point in time at which a data unit is to be transmitted. Each entry corresponds to a data structure of data units scheduled for transmission at the time corresponding to the location of the entry in the table. When a data unit is to be transmitted at a particular time, a scheduler writes the data unit to the data structure corresponding to the entry at the location in the schedule table corresponding to the time at which the data unit is to be transmitted. The scheduler writes the data unit to the data structure such that the data unit is the first of the data units in the data structure to be transmitted.

As applied in networking applications, the invention provides an apparatus and method for scheduling the transmission of cells from a network node. Accordingly, entries are stored in a schedule table at locations, wherein each location represents a point in time at which a cell is to be transmitted. Each entry in the table contains a pointer to a list of virtual circuits (VCs) having cells scheduled for transmission at the time corresponding to the location of the entry in the table. When a VC has a cell to be transmitted at a particular time, the VC is queued to the head of the list of VCs pointed to by the pointer located at the entry in the table corresponding to the time at which the cell is to be transmitted.

By queuing VCs to the head of the schedule table lists, rather than to the tail of the lists as is done in traditional schedulers, high rate VCs which are more sensitive to transmission latencies are more likely to be transmitted at their scheduled times. It can therefore be appreciated that the foregoing represents a significant performance advantage, particularly in the field of ATM network adapters.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment of the invention will be described with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a system having a host system connected to a network via an adapter;

FIG. 2 depicts the format for an ATM cell;

FIG. 3 is block overview of the adapter of FIG. 1;

FIG. 4 is a top-level functional block diagram of the SAR controller in the adapter of FIG. 3;

FIG. 5 illustrates a classical IP packet residing in the host memory of the host system shown in FIG. 1;

FIGS. 6A-B is a block diagram of the segmentation engine of the SAR controller shown in FIG. 4;

FIG. 7 illustrates the organization of the local memory shown in FIG. 3;

FIG. 8A is a block diagram showing the host system, PCI bus, PCI bus interface and the tx pending slot FIFO, the block diagram serving to illustrate the tx pending slot controller in the PCI bus interface;

FIG. 8B is a timing diagram of a PCI bus burst write transaction;

FIG. 9 is a flow diagram depicting a method used by the tx pending slot controller 186 of FIG. 8A for performing a burst write of data to the tx pending slot FIFO;

FIG. 10 illustrates the layout of a tx pending slot FIFO entry in the tx pending slot FIFO;

FIG. 11 is a depiction of the tx active slot lists residing in control memory on the adapter of FIG. 2;

FIG. 12 is a depiction of the tx free slot list in the local memory on the adapter of FIG. 2;

FIG. 13 shows the format of the active slot list entry in the active slot lists;

FIG. 14 is a layout of the transmit VC state table in the local memory;

FIG. 15 illustrates the format of an AAL5 packet carrying two MPEG protocol data units (PDUs);

FIGS. 16a-b are block diagrams of the tx data FIFO of FIG. 6, in unsegmented and segmented mode respectively;

FIG. 17 is a block diagram of the fifo.sub.-- remain controller of FIG. 6;

FIG. 18 is a flow diagram of the operation of the fifo.sub.-- remain counter of FIG. 17;

FIGS. 19a-c illustrate the three types of tx DMA request FIFO entries: Data DMA request entry (FIG. 19a), Idle Slot Report Request Entry (FIG. 19b) and RM Cell Request Entry (FIG. 19c);

FIG. 20a is a detailed block diagram of the schedule table and VC list of FIG. 6;

FIG. 20b is a block diagram of a worklist utilizing the VC list shown in FIG. 20a;

FIG. 21 is a high level flow diagram showing the operation of the tx rate scheduler and tx DMA scheduler FSMs of FIG. 6;

FIGS. 22a-j show a detailed flow diagram of the operation of the tx rate scheduler FSM of FIG. 6;

FIGS. 23a-f show a detailed flow diagram of the operation of the tx DMA scheduler FSM of FIG. 6;

FIG. 24 illustrates a tx data synch FIFO SOC control longword;

FIGS. 25a-b show a detailed flow diagram of the operation of the tx DMA FSM of FIG. 6;

FIG. 26 is a block diagram illustrating the tx data FIFO of FIG. 6 holding three entries;

FIG. 27 illustrates a tx data FIFO SOC control longword;

FIGS. 28a-d is a detailed flow diagram of the operation of the tx cell FSM of FIG. 6;

FIG. 29 is a block diagram of the tx data FIFO and tx phy FSM of FIG. 6;

FIGS. 30a-d show a detailed flow diagram of the operation of the tx phy FSM of FIG. 6;

FIG. 31 illustrates the layout of a tx report queue entry of the tx report queue of host memory (FIG. 1);

FIG. 32 is a flow diagram of a method of performing tx raw cell report frequency mitigation;

FIG. 33 is a flow diagram of a method of reporting status for data other than raw cell data;

FIG. 34 illustrates an AAL5 packet stored in three rx slots;

FIG. 35 is a block diagram of the reassembly engine of the SAR controller;

FIG. 36 illustrates in rx pending slot FIFO entry of the rx pending slot FIFO of the reassembly engine;

FIG. 37 depicts the format of a rx VC state table entry;

FIG. 38 is an illustration of the rx data FIFO;

FIGS. 39A-C illustrate the formats for the three types of Rx Cell SOD entries: rx data AAL5 Cell SOD entry (A), rx data raw cell SOD entry (B) and rx AAL5 status report SOD entry (C);

FIG. 40 illustrates the format of an rx raw cell status longword;

FIGS. 41A and 41B depict the rx AAL5 and raw cell report queue entries, respectively, of the rx report queue shown in host memory (FIG. 1);

FIG. 42 shows the rx.sub.-- raw.sub.-- report.sub.-- hldoff field in the SAR.sub.-- Cntrl2 register CSRs.

FIG. 43 is a flow diagram illustrating a method of performing rx raw cell status report frequency mitigation.

FIG. 44 shows the layout of the rx.sub.-- slot.sub.-- cong.sub.-- th register in CSRs;

FIG. 45 is a flow diagram showing the rx congestion control method performed by the SAR controller in conjunction with the driver.

FIG. 46 depicts the layout of the INT CSRs from FIG. 4;

FIG. 47 is a flow diagram of the interrupt-on-completion interrupt request frequency mitigation method.

FIG. 48 illustrates the interrupt block and the PCI bus interface signals involved in IOC interrupt request generation;

FIG. 49 shows the system from FIG. 1 having a host system coupled to a peripheral unit by an interface;

FIG. 50 depicts the format of the message type field of an RM cell; and

FIG. 51 is a logical representation of the generation of the CI bit in a backwards RM cell header.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, there is illustrated a system 10, which includes an adapter 12 coupled to an end-system shown as a host system 14 and a network 16. The host system 14 and adapter 12 each are connected to and communicate with one another over a system bus 18. The adapter 12 is connected to and directly interfaces with the network 16. The host system 14, system bus 18 and adapter 12 in the illustrated configuration thus represent a "network" node 19. This type of network node is an end-system network connection, sometimes referred to as an "end" node.

In pertinent part, the host system 14 includes a central processing unit (CPU) 20 coupled to a host memory 22. The host memory includes a driver 24 and a buffer memory 26. A user application 28 (executing in the CPU 20) provides, via networking software layers (not shown), network-bound user data to the driver 24 as protocol data units (PDUs).

In the illustrated embodiment, the buffer memory 26 includes transmit (tx) slots 30 and receive (rx) slots 32. The driver utilizes the tx slots 30 to store the PDUs awaiting transmission. The rx slots 32 are used to store data received from the network 16 via the adapter 12.

Further included in the host memory are report data structures 34 for storing status reports provided to the host system 14 by the adapter 12. The report data structures include a transmit (tx) report queue 36 and a receive (rx) report queue 38. Additionally, there is provided in the host memory a lookup table 40 for physical-to-virtual address mapping.

Now referring to FIG. 3, there is shown a preferred implementation of the adapter 12 (from FIG. 1) as an Asynchronous Transfer Mode (ATM) adapter. Because the description of this embodiment contains numerous acronyms and terms that are associated with ATM, the description of the adapter 12 in FIG. 3 follows a very brief discussion of ATM networks. Additional information can be had with reference to "ATM User-Network Interface Specification, Version 3.1", and other documents published by the "ATM Forum".

An ATM network is a cell-based network in which fixed-length cells relating to different media are statistically multiplexed together and have random time intervals between them. The ATM cells are transmitted in slots in the payload of, e.g., the frames of a SONET signal.

ATM messages move through the network over virtual circuits (VCs), which are set up by and established between the end nodes in the network. Each message in an ATM network is made up of one or more of the fixed-length cells. Referring to FIG. 2, an ATM cell 42 is shown to be 53 bytes long. The ATM cell 42 is typically divided into a 5-byte header 44 and a 48-byte payload 46. As shown, the ATM header 44 includes the following: a generic flow control field 48, a virtual path (VPI) identifier 50, a virtual channel identifier (VCI) 52, a payload type identifier (PT) field 54, and a cell loss priority (CLP) field 56. The ATM header 44 further includes a header error control (HEC) field 58. The GFC field 48 is used to ensure that users are given fair access to transmission facilities. The VPI 50 identifies a virtual path between two nodes. The virtual path is simply a collection of channels associated with the same user endpoint. The VCI 52 identifies a virtual channel between two nodes. A virtual channel is a unidirectional virtual circuit (VC) associated with a particular user. The PT field 54 is used to differentiate between cells carrying user data and cells carrying ATM control information, such as OAM cells. The CLP field 56 indicates the eligibility of a cell being discarded during a period of congestion. The HEC field 58 is used to detect corruption of the information contained in the ATM header 44. The payload field 46 contains the data portion of a cell.

Referring now to FIG. 3, the adapter 12 includes a Segmentation and Reassembly (hereinafter referred to as simply "SAR") controller 62, which interfaces directly to the system bus 18. In this embodiment, the system bus 18 is a 32-bit PCI bus with Universal I/O. The SAR controller 62 is connected to a crystal oscillator 64, which provides a timing source for the SAR controller, as well as one or more adapter-resident devices indicated as peripheral devices 66 via a peripheral bus 68. The peripheral devices 66 include (but are not limited to) LEDs, MAC address PROM and PCI subsystem ID registers.

The SAR controller 62 is further connected to a PHY device 70, which implements the ATM physical layer. As shown, the PHY device 70 includes a Transmission Convergence (TC) sublayer device 72 and a Physical Media Dependent (PMD) sublayer device 74. The TC sublayer device 72 defines line coding, scrambling, data framing and synchronization. The PMD sublayer device 74 typically includes the functions for transmitter, receiver and timing recovery that allow connection to the transmission media of the network 16, also referred to as the network bus 16. In the embodiment of the invention illustrated in FIG. 3, the network bus 16 is indicated as being of the SONET STS-3c/STM-1 type. The SONET STS-3c/STM-1 transmission rate is specified to be 155.52 Mb/s. It can be seen from the figure that peripheral bus 68 also provides access to PHY layer devices (not shown) in the PHY device 70.

Additionally, the adapter includes a local memory 76, which is connected to the SAR controller 62 and provides storage for numerous data structures utilized by the SAR controller 62 and the host system 14 (from FIG. 1) for various key functions. In this embodiment, the local memory 76 supports 1K VC mode memory requirements. The internal organization of the local memory 76 and the different data structures contained therein will be described in detail later.

FIG. 4 is a top-level diagram illustrating the general architecture of the SAR controller 62. The SAR controller 62 has three interfaces that include the following: a PCI bus interface 78 with a 32-bit wide data bus, a PHY interface 80 and a peripheral bus interface 82.

The PCI bus interface 78 connects the SAR controller to the PCI bus 18, and therefore couples the SAR controller 62 to the host system 14 via the PCI bus 18. Although not shown in FIG. 1, the host system 14 may include a PCI bus interface or PCI bridging logic, depending on the configuration of the host system and whether the PCI is serving as a local or system bus. The SAR controller 62 masters the PCI bus in its master mode and allows the host system 14 to access the SAR controller 62 in slave-mode operation. The PCI bus interface 78 implements a 32-bit data buffer to provide a data path to and from the host system. This block also includes PCI configuration space registers (not shown).

On the line-side of the SAR controller 62, the PHY interface 80 implements the industry-standard UTOPIA data path handshake protocol in conformance with the UTOPIA interface specification. The UTOPIA interface consists of an 8-bit wide data path and associated control signals in both the tx and rx directions. Consequently, ATM cells pass between the ATM and PHY layers through the UTOPIA interface.

Although not shown, the SAR controller 62 may also be connected directly to devices implementing the ATM layer of the UTOPIA specification (as opposed to the PHY layer) through a Reversible UTOPIA mode of operation. In Reversible UTOPIA mode, the SAR controller 62 acts as the UTOPIA PHY layer at the line-side interface. This is particularly useful in ATM switch applications, where the SAR controller 62 may be connected to the switch fabric through the same mechanism as all other ports in the switch.

The peripheral interface 82 is connected to the PCI bus interface 78. Through the peripheral interface 82, the host system may access the various on-adapter peripheral devices. As already mentioned, these peripheral devices may include a MAC address PROM and LEDs, as well as PCI subsystem and subsystem vendor ID registers. Additional devices could include error-logging EPROM and CSRs in the PHY device. In the embodiment of the present invention, the peripheral interface 82 directly supports a 64 KB address space and an 8-bit wide data path.

The SAR controller 62 also includes a clock generation block 84, which generates and distributes clock signals to the various components of the SAR controller 62, and a number of internal control and status registers (CSRs), which are shown in FIG. 3 as CSRs 86. The CSRs 86 are coupled to the PCI bus interface 78, a segmentation engine 88 and a reassembly engine 90. As shown in the figure, the CSRs include interrupt CSRs 92, which are coupled to an interrupt logic block 94. Together, the interrupt CSRs 92 and interrupt logic block 94 compose an interrupt block 96 (indicated in dashed lines).

An address map for the CSRs 86 is provided in Table 1 below.

                  TABLE 1
    ______________________________________
    CSR            Read/Write
                             LW Address Default
    ______________________________________
    Tx.sub.-- Pending Slots
                   WO        0 .times. 0 - 0 .times. F
                                        N.A.
    Rx.sub.-- Pending Slots
                   WO        0 .times. 10 -
                                        N.A.
                             0 .times. 1F
    SAR.sub.-- Cntrl1
                   RW        0 .times. 20
                                        00000040
    SAR.sub.-- Cntrl2
                   RW        0 .times. 21
                                        00001001
    Intr.sub.-- Status
                   RW1C      0 .times. 22
                                        00000000
    Intr.sub.-- Enb
                   RW        0 .times. 23
                                        00000000
    Intr.sub.-- Hldoff
                   RW        0 .times. 24
                                        00000000
    Tx.sub.-- FS.sub.-- List.sub.-- Ptrs
                   RW        0 .times. 25
                                        00000000
    Tx.sub.-- Report.sub.-- Base
                   RW        0 .times. 26
                                        00000000
    Rx.sub.-- Report.sub.-- Base
                   RW        0 .times. 27
                                        00000000
    Tx.sub.-- Report.sub.-- Ptr
                   RO        0 .times. 28
                                        00000000
    Rx.sub.-- Report.sub.-- Ptr
                   RO        0 .times. 29
                                        00000000
    Rx.sub.-- Slot.sub.-- Cong.sub.-- Th
                   RW        0 .times. 2A
                                        00000000
    Tx.sub.-- ABR.sub.-- ADTF
                   RW        0 .times. 2B
                                        00000000
    Tx.sub.-- ABR.sub.-- Nm.sub.-- Trm
                   RW        0 .times. 2C
                                        00000000
    Peephole.sub.-- Cmd
                   RW        0 .times. 2D
                                        40000000
    Peephole Data  RW        0 .times. 2E
                                        80000000
    Rx.sub.-- Raw.sub.-- Slot.sub.-- Tag
                   RO        0 .times. 2F
                                        00000000
    Rx.sub.-- CellCnt
                   RO        0 .times. 30
                                        00000000
    Rx.sub.-- AAL5.sub.-- DropPKTCnt
                   RO        0 .times. 31
                                        00000000
    Rx.sub.-- Raw.sub.-- DropCellCnt
                   RO        0 .times. 32
                                        00000000
    Tx.sub.-- CellCnt
                   RO        0 .times. 33
                                        00000000
    Real.sub.-- Time
                   RO        0 .times. 34
                                        00000000
    Current.sub.-- Time
                   RO        0 .times. 35
                                        00000000
    Test.sub.-- Cntrl
                   RW        0 .times. 36
                                        00000000
    ______________________________________
     NOTES:
     RW = Read/Write
     RW1C = Read/Writeone-to-clear
     RO = Read only
     WO = Writeonly

                  TABLE 2
    ______________________________________
    Tx DMA request FIFO 125 Entry Type Decoding
    RM        DMA.sub.-- SIZE <5:0>
                             ENTRY TYPE
    ______________________________________
    0         >0             Data DMA Request
    0         0              Idle Slot Report
                             Request
    1         N.A.           RM Cell Request
    ______________________________________