Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memory6587894Abstract According to the present invention, a system for reordering commands to achieve an optimal command sequence based on a target response restriction is disclosed. A data queue coupled to a command queue is arranged to store a time indicating when the data transfer will appear on the data bus between the controller for an already issued request to the target device as well as arranged to store the burst bit and the read/write bit (r/w). The system also includes a collision detector coupled to the data queue and the command queue arranged to detect the possible collisions on the data bus between the issued command that is stored in the command queue and already issued commands that are stored in the data queue. A queues and link controller is coupled to the collision detector and the data queue and the command queue and is arranged to store and reorder commands to be issued wherein the controller calculates the new issue time of commands as well as a time when the data appears on the data bus. Claims What is claimed is: Description FIELD OF THE INVENTION
TABLE 1
OLD COMMAND
NEW COMMAND page close page open Read Write
page close 5 N
page open
Read
Write
Once the physical constraints of the resource are determined for a particular universal command component, a determination is made at 606 whether or not there are additional command components included in the universal command. If there are no additional command components, then the universal command and the associated component timing specifications are stored at 608. On the other hand, if there are additional command components included in the universal command, then control is passed back to 604 where the corresponding physical timing constraints for that component is determined. However, in order to track a state of the physical pages in the shared memory 108 having a number of memory banks, for example, a large number of resource tags which would require a large amount of cache memory dedicated to the resource tag buffer 114. This would slow the performance of the universal controller 104 since it would require substantial amounts of time to retrieve particular resource tags for particular pages of memory each of which may be located in disparate locations. Referring to FIG. 7A, in one embodiment, a page hit/miss controller 702 is included in the universal controller 104 arranged to reduce the number M of page registers 704 smaller than the number N of memory banks in a multi-bank memory 706 since not every bank has its representation in the M page registers 704. In operation, each of the M page registers 704 stores address and status data of an open page and a random page register number generator 708 generates a random integral number less than or equal M corresponding to the page register that has to be replaced by the status of an open page. A comparator 710 compares an incoming system address with the bank number and the page address of all the M registers in parallel with four possible results. 1) If the comparator 710 indicates a hit, then the required page of the requested bank is open and ready to access; 2) If the comparator 710 indicates that there is a bank hit and a page miss, then the universal controller 104 must close the old page using the page address from the page register and open a new page using the page address from the system address; 3) If the comparator 710 indicates a bank and a page miss, the universal controller 104 must close any old page of the bank which number is given by the random page number generator, open a new page using the system address and finally accessing the requested bank; and 4) bank and page miss, but at least one page register is unused then this register will be used and new page will be opened. In some embodiments, the random number page generator 708 is replaced by a Least Recently Used (LRU) comparator 712 as shown in FIG. 7B determines which of the M registers 704 has been unused the longest amount of time (i.e., least recently used). In addition to tracking the states of the physical pages in the multi-bank memory 704, a bank access controller 800 shown in FIG. 8 includes N bank registers 802 corresponding to the number of memory banks N included in the multi-bank memory 704. The bank register 802 includes a bank number field 804 that defines an identifying number of the bank for which the information in the associated bank is stored. The bank register 802 also includes a bank status field 806 indicating the status of the particular bank identified by the bank number in the bank number field 804. In a particular embodiment, the bank status field 806 can take on values such as those presented in Table 2.
TABLE 2
Bank Register Elements Description
Bank Number Identifies bank for which the information in
bank register is stored
Bank Status Indicates status of bank:
"00" - invalid entry
"01" - the bank counter value is decreased unit
its value reaches 0. If bank counter is greater
than 0, access to this bank are prohibited.
"10" - the bank is closed.
"01" - the bank counter value is decreased until
it reaches 0. if bank counter is greater than 0,
then accesses to all banks in the memory
are prohibited
Bank Timer If bank counter is greater than 0, then the
accesses to memory according to the bank
status value are prohibited.
With the development of high speed packet oriented memories such as synchronous link dynamic random access memory (SLDRAM) that deliver bus data rates in the range of 400 to 800 Mb/s/pin, the problems caused by memory access conflicts are greatly increased. Referring initially to FIG. 9A, an exemplary SLDRAM based multi-processor system 900 in accordance with an embodiment of the invention is shown. The multi-processor system 900 includes processors 902 connected to a controller 904 by way of a system bus 906. The universal controller 904, in turn, is connected to synchronous link DRAM (SLDRAM) 908 and SLDRAM 910 by way of a SLDRAM bus composed of a uni-directional command bus 912 and a bi-directional data bus 914. It should be noted that even though only two SLDRAMs is shown in FIG. 9A, any number of SLDRAMs can be connected to the universal controller 904 by way of the busses 912 and 914. In some cases, the SLDRAMs can take the form of a buffered module that includes any appropriate number of SLDRAMs such as, for this discussion, the SLDRAM 908. An initialization/synchronization (I/S) bus 916 connecting the universal controller 904 to each of the SLDRAMs 908 and 910 provides a signal path for initialization signals as well as synchronization signals generated by the universal controller 904. In one embodiment of the invention, packetized command, address, and control information from the universal controller 904 are selectively sent to the SLDRAM 908 and SLDRAM 910 on the command bus 912. The data bus 914 is arranged to transmit packetized write data from the universal controller 904 to selected ones of the SLDRAM 908 and SLDRAM 910. Alternatively, the data bus 914 is also configured to transmit packetized read data from selected ones of the SLDRAM 908 and SLDRAM 910 back to the universal controller 904. It should be noted that the command bus 912 and the data bus 914 typically operate at the same rate, i.e. 400 MB/s/p, 600 MB/s/p, 800 MB/p/s, etc. A number of control signals generated by the universal controller 904 and carried by the command bus 912 include, for example, a differential free running clock signal (CCLK), a FLAG signal, a command address signal CA, a LISTEN signal, a LINKON signal, and a RESET signal. Typically, packet commands are formed of 4 consecutive 10-bit words where the first word of a command is indicated by a `1` in the first bit of the FLAG signal. In a preferred embodiment, both edges of the differential free running clock CCLK are used by the SLDRAM 908 and 910 to latch command words. The SLDRAM 908 and 910 respond to the LISTEN signal being HIGH by monitoring the command bus 912 for incoming commands. Alternatively, the SLDRAM 908 and 910 respond to the LISTEN signal being LOW by entering a power saving standby mode. The LINKON signal and RESET signals are used to, respectively, shutdown and power up to a known state selected ones of the SLDRAM 908 and 910, as desired. For the remainder of this discussion, the SLDRAM 908 only will be discussed with the full knowledge, however, that any number of SLDRAMs can be connected to the universal controller 904 as deemed appropriate. As discussed above, a typical SLDRAM device, such as the SLDRAM 908, is hierarchically organized by memory banks, columns, rows, and bits as well as into regions of memory. It is important to note that each of these hierarchical levels can in fact be observed to have different operational characteristics from one another. Such operational characteristics include, but are not limited to such parameters as memory access time, chip enable time, data retrieval time etc. It should be noted that the banks within the multi-bank memory will typically have the same operational characteristics whereas regions are defined to be different devices, such as different memory types or different memory groups each having different command and data latencies. For example, a local memory group can be connected directly to the memory controller and a second, non-local memory group located on a board where intervening drivers increase command and data latencies with respect to the local memory group. In other cases, each of the various memory chips that go to form a multi-chip module can be considered to be a different memory region. More specifically with reference to the system of FIG. 9A, the SLDRAM 908 is a multichip module having 4 memory chips, A, B, C, and D each capable of being individually accessed by the command bus 912, the data bus 914, and the I/S bus 916. Since each of the memory chips A-D can have different operational characteristics (typically supplied by the manufacturer), in order to optimally schedule command and data packets, the universal controller 904 is capable of using the operational characteristics of a particular hierarchical level and/or memory regions accordingly. By way of example, FIG. 9B shows a representative timing diagram for an exemplary SLDRAM bus transaction in accordance with the multi-processor system 900 shown in FIG. 9. During operation, the processors will typically generate processor command packets such as, for example, a Read command 950 and a Write command 952 for which the appropriate memory bank(s) of the SLDRAM 908 responds accordingly. Typically, the Read command 950 and the Write command 952 are pipelined on the system bus 906 based upon the particular requirements of the processors 902 from which they are generated and not for optimal SLDRAM performance. A system clock CLK.sub.sys (not shown) provides the necessary timing signals. For this example, a processor 902a generates the Read command 950 having a memory address MA.sub.1 located in memory chip A of the SLDRAM 908 while a processor 902b generates a Write command 952 having a memory address MA.sub.2 also located in memory chip A of the SLDRAM 908. In this example, the Read command 950 is output to the system bus 906 prior to output of the Write command 952. The universal controller 904 receives the Read command 950 first and proceeds to process the command based upon the command itself and the command address MA.sub.1 using destination address specific information stored within the universal controller 904. Once the minimum issue time is determined, the universal controller 904 then generates an SLDRAM command packet READ 960 corresponding to the received processor command 950 and issues it to the command bus 912. Generally, the SLDRAM command packet is organized as four 10 bit words as illustrated in Table 3 representative of a 64M SLDRAM with 8 banks, 1024 row addresses, and 128 column addresses. As shown, there are 3 bits for the bank address (BNK), 10 bits for row address (ROW), and 7 bits for column address (COL). It should be noted that many other organizations and densities are possible and can be accommodated within the 40 bit format described as well as any other format as may be determined as appropriate. During power up, the universal controller 904 organizes the command packet based upon polling of the SLDRAMs for such factors as the number of banks, rows, columns, and associated operating characteristics which is then stored by the universal controller 904. The first word of the command packet contains the chip ID bits. An SLDRAM will ignore any command that does not match the local ID. Chip ID is assigned by the universal controller 904 on power-up using the initialization and synchronization signals. In this way, the universal controller 904 uniquely addresses each SLDRAM in the multi-processor system 900 with resorting to generating separate chip enable signals or glue logic.
TABLE 3
SLDRAM COMMAND PACKET STRUCTURE
FLAG CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1
CA0
1 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
CMD5
0 CMD4 CMD3 CMD2 CMD1 CMD0 BNK2 BNK1 BNK0 RW9
RW8
0 ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 0
0
0 0 0 0 COL6 COL5 COL4 COL3 COL2
COL1 COL0
Since the Read command 950 and the Write command 952 are pipelined, the universal controller 904 receives Write command 952 (or it could have been stored in a buffer) some period of time after receipt of the Read command 950 and subsequently issues an SLDRAM command packet WRITE 962 corresponding to the Write command 952. The universal controller 904 uses MA.sub.2 specific characterization data as well as the issue time (i.e., the time of issuance) of the READ command 960 to generate a minimum issue time and a data offset for WRITE 962 in order to prevent interference with the previously issued READ command 960 since the same bank (A) is being accessed by both commands. In this way, the universal controller 904 is capable of dynamically scheduling the issuance of SLDRAM command packets based at least upon particular destination address device operating characteristics as well as the current state of the command and data packet stream. Referring now to FIG. 10 illustrating a block diagram of a memory controller 1000 in accordance with an embodiment of the invention. It should be noted that the memory controller 1000 is but one possible embodiment of the universal controller 104 shown in FIG. 1 and should not, therefore, be construed as limiting the scope of the invention. The memory controller 1000 includes a system interface 1002 that connects, by way of the system bus 906, the processors 902 to a memory scheduler 1006 (referred to as the scheduler). In one embodiment of the invention, the system interface 1002 is configured to provide for both the transmission of memory command packets and associated write data packets generated by the processors 902 to the memory command packet scheduler 1004. In the situation where the scheduler 1006 indicates that all internal buffers are full and new commands can not be accommodated, the system interface 1002 holds any new commands until such time as the scheduler 1006 indicates it is ready to accept new commands. A synchronous link media access controller (SLiMAC) 1008 provides a physical interface between the scheduler 1006 and the SLDRAM 908. More specifically, the SLiMAC 1008 includes a command interface 1010 and a data interface 1012 connecting the SLiMAC 1008 to the SLDRAM 908 by way of the command bus 912 and the data bus 914, respectively. In a preferred embodiment of the invention, the command interface 1010 transfers memory commands from the SLiMAC 1008 to the SLDRAM 908 accompanied by the associated command clock CCLK. It should be noted that in some embodiments, the SLiMAC 1008 incorporates a clock doubler which uses an interface clock signal ICLK (which is capable of running at approximately 100 MHz) to generate the command clock signal CCLK which typically runs at 200 MHz. In one embodiment of the invention, the data interface 1012 both receives and transmits data on the data bus 914. It should be noted that the width of the data bus 914 can be as large as necessary to support as many SLDRAMs are required. In order to therefore provide the necessary bandwidth, as many data interfaces as needed can be included in the SLiMAC 1008. By way of example, if the data bus 914 is 32 bits wide (16 bits per SLDRAM, for example) then the SLiMAC 1008 can include 2 data interfaces each capable of handling 16 bits associated with a particular SLDRAM. In this way, the size of the data interfaces included in the SLiMAC 1008 can be closely matched to the particular configurations of the SLDRAMs connected thereto. In much the same way as with the command interface 1010, the SLiMAC 1008 is capable of providing a data clock signal DCLK that accompanies the read data transferred from the SLDRAM 908 to the SLiMAC 1008. In one embodiment of the invention, the data clock DCLK is generated by using the clock doubler to double the interface clock ICLK frequency from approximately 100 MHz to approximately 1000 MHz. It should also be noted that the interface clock signal ICLK, the command clock signal CCLK, and the data clock signal DCLK are all phase synchronous. In a preferred embodiment of the invention, the scheduler 1006 includes a restriction block 1016 arranged to receive system command and associated system address data from the system interface 1002 connected thereto. The restriction block 1016 provides SLDRAM command packet data and associated timing information to a reordering block 1018. A write buffer 1020 receives write data from the system interface 1002. As directed by the scheduler 1006, read data is transferred from the data interface 1012 through a read buffer 1022 connected to the data bus 914 is arranged to provide read data to the system interface 1002. An initialization/synchronization (I/S) block 1024 connected to the I/S bus 916 provides appropriate initialization and/or synchronization signals to the SLDRAM 908 as required. In operation, the scheduler 1006 receives pipelined memory command packets generated by the processors 902. Typically, the memory command packets are composed of a memory command and associated memory address. In one embodiment of the invention, the scheduler 1006 decodes the memory address associated with the received new command in order to determine the destination address to which the memory command and associated data packet (if any) are directed. Once decoded, the scheduler 1006 uses destination address specific device characterization data stored therein as well as information associated with a just prior issued memory command to issue a new SLDRAM command packet. The new SLDRAM command packet is output to the command bus 912 and ultimately to the SLDRAM identified by the CHIP ID included in the SLDRAM command packet. As part of the scheduling process, the scheduler 1006 determines the minimum amount of time after the issuance of the just prior issued command required before the issuance of the new command. Since, as described above, each hierarchical level, such as for example, a memory bank, of a SLDRAM can have different operating characteristics (usually provided by the manufacturer), the scheduler 1006 polls each SLDRAM it services during initialization. In some embodiments, the memory specific parameters (such as timing) can be written directly into the restriction block register 1016 if the connected memory devices do not allow do not allow polling in order to determine operating characteristics. Once the SLDRAMs are polled, the scheduler 1006 stores the device specific information which it later uses to develop the appropriate scheduling protocols. In this way, the scheduler 1006 is capable of adaptively providing scheduling services to any number and type of SLDRAMs without resorting to hardwiring or other time consuming and expensive procedures. FIG. 11 is a schematic illustration of a restriction block 1100 in accordance with and embodiment of the invention. It should be noted that the restriction block 1100 is but one possible embodiment of the restriction block 1016 shown in FIG. 10 and as such should not be construed as limiting. The restriction block 1100 includes an address decoder 1102 connected to the system interface 1002 arranged to decode a received new address signal associated with a new memory command generated by the processors 902. The decoded new address signal provides an input to a array tag register 1104 in which is stored the status and other relevant information for all, or in some cases only a subset, of pertinent SLDRAM memory banks. The array tag register 1104 provides an input to a selector 1106 which passes relevant data for the selected virtual bank based upon the decoded new command address to a look up table (LUT) 1108. The restriction block 1100 also includes a region comparator 1110 also connected to the system interface 1002 arranged to use the received new address signal to provide a region identifier indicative of the region of memory for which the new command address is located. In this way, the restriction block 1100 is capable of providing a best case scheduling protocol for the new memory command based at least in part on the memory region specific characterization data. The region comparator 1110 provides the region identifier to the LUT 1108 as an input along with the new command signal. The LUT 1108, in turn, provides a minimum delta issue time and a data offset which is used to convert the new command and associated new address into an SLDRAM command packet. It should be noted that the minimum delta issue time indicates the delta time (in clock cycles) to issue the new command in relation to the just issued old command. The data offset time is indicative of the delta time in clock cycles in order to receive a read data packet associated with the new command after the issuance of the new command. In one embodiment of the invention, the restriction block 1100 includes 16 array tag bank registers and the LUT 1108 is capable of storing four different parameter sets for four timing regions each, in turn, having 16 associated registers. FIG. 12 is a timing diagram 1200 of a SLDRAM bus signals in response to received processor commands in accordance with an embodiment of the invention. It should be noted that TABLE 4 summarizes the scheduling process carried out by the restriction block 1100 by identifying the various generated signals. It should also be noted that a memory command takes the form of {command, address} where "command" represents the instruction to be executed and "address" the associated memory location. Referring now to TABLE 4 and FIG. 12, during a system clock cycle .O slashed..sub.1, a first {OPENPAGE, 1000} command is received at the address decoder 302 and concurrently at the region comparator 1110. For this example, the address decoder 1102 decodes the OPENPAGE command address "1000" as "100" and "400" which the region comparator 1110 determines to be included within memory region 0. Since the OPENPAGE command is the first command to be received, there are no "hits" with any of the Virtual Banks B.sub.0 -13 and a corresponding replacement counter is set to "0". In the described embodiment, the replacement counter is updated based upon a pseudo-random counting scheme whereas in other embodiments random counting or other appropriate schemes can be used. Since the first {OPENPAGE, 1000} command is an open type command, there is no associated minimum delta issue time or data offset, and thus the page at address 1000 is opened on the first command clock cycle .O slashed.C.sub.1. During a next system clock cycle .O slashed..sub.2, a {READ, 1000} command is received at the restriction block 1100 which the address decoder 1102 decodes as 100 and 400 (i.e.; reading the page opened at memory address location 1000 from the previous clock cycle) which again causes the region comparator 1110 to set the region identifier to REGION1. In this case, however, the previous, or otherwise referred to as the "old command" having been stored in a B.sub.0 register results in a "hit" at B.sub.0 which causes the selector to output "READ" as the "old command" input to the LUT 1108. Additional inputs include the region indicator REGION1 generated by the region comparator 1104 and the "new command" input as READ. The LUT 1108 utilizes stored characterization data to generate a minimum delta issue time of 3 command clock cycles .O slashed..sub.3 which indicates that at least 3 command clock cycles must separate the issuance of the {PAGEOPEN, 1000} command and the associated {READ, 1000} command. In this way, each memory command packet received at the restriction block 1100 is processed according to the characterization data stored within the LUT 1108 and at least in part on the just prior issued command. The reordering of commands received from the restriction block according to a specific embodiment of the invention will now be described. FIGS. 13A-13C are timelines 1302 and 1304 which, through a simple command reordering example, serve to illustrate some of the advantages which may be realized by reordering memory commands according to a specific embodiment of the present invention. Each timeline shows four read commands corresponding to two different memory banks. CMD0 and CMD1 are read commands directed to bank 1 of the associated memory. CMD2 and CMD3 are read commands directed to bank 2 of the associated memory. Timeline 1302 shows memory commands arranged on a command bus connecting a memory controller and a memory in the order in which the commands were received by the memory controller from the system processor; CMD0 occupies time slot 0, CMD1 occupies time slot 3, CMD2 occupies time slot 4, and CMD3 occupies time slot 7. Each time slot represents one clock cycle. As discussed above, commands to the same memory bank must have some minimum delay between issuance to accommodate servicing of the previously issued command. This is represented in FIG. 13A by the two time slots between each pair of commands. As can be seen, if the four read commands are sent to the memory in the order shown in FIG. 13A, the command bus will go unused during four available clock cycles, i.e., times slots 1, 2, 5 and 6. As will be discussed at least some of this inefficiency may be ameliorated by reordering the command according to the present invention. Timelines 1304 and 1306 of FIGS. 13B and 13C, respectively, illustrate the reordering of the commands of FIG. 13A according to a specific embodiment of the invention and at least some of the advantages gained thereby. In this example, conflicts on the data bus are not considered for the sake of simplicity. As discussed below, however, attention must be given to such considerations for effective reordering of memory commands. Due to the fact that CMD2 and CMD3 are directed to a different memory bank than CMD0 and CMD1, memory access latencies as between the two pairs of commands are irrelevant and may be ignored. That is, the commands may be rearranged as shown in timeline 1304 to place CMD2 in time slot 1 immediately following CMD0, and CMD3 in time slot 4 immediately following CMD1. This is because there does not need to be any delay between the issuance of CMD0 and CMD2 or between the issuance of CMD1 and CMD3 due to the fact that they are directed to different banks of memory. However, as will be understood and as shown in FIG. 13C, the minimum delay time, e.g., two clock cycles, between the pairs of commands directed to the same bank must be maintained. That is, reordering of commands may not involve attempts to reduce the delay time between successive commands to the same memory bank. The result of reordering the commands is shown in FIG. 13C in which the four commands are issued in five clock cycles with only time slot 2 going unused. It will be understood, of course, that a fifth memory command to yet another memory bank may be inserted in time slot 2 to further maximize the efficiency with which the command bus is used. FIG. 14 is a block diagram of a portion of a memory controller designed according to a specific embodiment of the invention. Reordering circuitry 1400 receives a sequence of incoming memory commands, i.e., 1, 2, 3, from the system processor. According to a specific embodiment, the memory commands are transmitted to reordering circuitry 1400 via restriction circuitry (not shown) which, as described above, imposes issue time constraints on selected commands relative to other commands directed to the same logical bank of the associated memory. The commands are reordered in command queue 1402 from which the commands are issued to the memory. In this example, the commands are reordered into the sequence 1, 3, 2. The original memory command sequence, i.e., 1, 2, 3, is stored in a FIFO memory 1404 in data-read circuitry 1406. The sequence in FIFO 1404 is used for reordering the data received from the memory to correspond to the order in which the commands were originally received by the memory controller. It should be noted, however, that some of the processors expect in-order data while others expect out-of-order data, therefor, by switching the FIFO 1404 on and off as required, any type data order can be supported. This is necessary because the processor "expects" to receive the data in an order corresponding to the order in which it originally transmitted the commands to the memory controller. In addition, because data from the memory may be received by the memory controller in a sequence which does not correspond to the original sequence in which the processor transmits the memory commands, a third sequence is stored in data queue 1408. This sequence (in this example 3, 1, 2) represents the order in which the data corresponding to the command sequence 1, 3, 2, will be received by data-read circuitry 1406. The data queue sequence is computed by reordering circuitry 1400 based on the command queue sequence and known latencies associated with the various logical banks of the memory. When the memory transmits data to the memory controller in the sequence stored in data queue 1408 (i.e., 3, 1, 2), the data are stored in read-data buffer 1410 and reordered based on the information in FIFO 1404 and data queue 1408 such that the data are transmitted to the processor in an order corresponding to the original command sequence order, i.e., 1, 2, 3. FIG. 15 is a block diagram of reordering circuitry 1500 in a memory controller designed according to a specific embodiment of the invention. Reordering circuitry 1500 includes command queue 1502 which stores and reorders commands received from the system processor. Command queue 1502 calculates an issue time for each command, issues the commands, and removes the issued commands from the queue using command issue time constraints associated with commands to the same logical bank in memory as well as data bus usage constraints. Data queue 1504 stores data elements representing data occurrence times corresponding to issued memory commands, calculates new data occurrence times for each new entry in the queue, and removes queue entries when the corresponding memory transaction is completed. Comparator matrix 1506 performs a collision detection function in which the data occurrence time of a command ready to be issued from command queue 1502 (as communicated via multiplexer 1508) is compared to the data occurrence times of previously issued commands as represented in data queue 1504. If a collision is detected, issuance of the command is delayed. FIG. 16 is a more detailed block diagram of reordering circuitry 1500 of FIG. 15. Command queue 1502 comprises six command queue elements 1602 each of which stores 61 bits of information regarding a particular memory command as illustrated by the diagram of FIG. 17. Command field 1702 contains the 40-bit memory command packet which specifies the memory command. Command issue time (C.sub.d) field 1704 is a 6-bit field which indicates a delta time in clock cycles before the command may be issued. The value in field 1704 is determined by the restriction circuitry as described above and relates to the most recent memory command corresponding to the same logical bank in the memory. That is, the value in the C.sub.d field indicates the latency between two commands to the same bank. The information about the required latencies for each bank are stored in the restriction circuitry and are determined largely by the physical characteristics of the memory. Once in the command queue, the C.sub.d field is decremented once for each clock cycle with some exceptions. For example, the latency between successive commands to the same logical bank cannot be changed. Thus, if the C.sub.d field for a command directed to a particular bank reaches zero and is not issued, the C.sub.d fields for all other commands to the same bank cannot be decremented until the first command is issued. Data occurrence time (D.sub.d) field 1706 is a 6-bit field which indicates a delta time in clock cycles between issuance of a memory command from the command queue to transfer of the corresponding data. D.sub.d field 1706 may not be altered in the command queue. Command ID field 1708 is a 5-bit field which uniquely identifies the command in command packet 1702. This information is used with corresponding information in the FIFO and the data queue to keep track of which packets are which and which data correspond to which packets so that reordering of commands and data may be effected. Logical bank (B) field 1710 is a 3-bit field which identifies to which logical bank in the memory the command packet is directed. Finally, burst indicator (D.sub.b) field 1712 is a 1-bit field which indicates whether the data being requested or written occupy one or two clock cycles. Referring back to FIG. 16, the operation of the command queue is controlled by command queue controller 1604. Controller 1604 keeps track of which command queue elements 1602 are available and controls insertion of incoming commands into a particular queue element 1602 via free position indicator 1606. Controller 1604 also facilitates insertion of command queue element information into data queue 1504 once the corresponding command has been issued. According to a specific embodiment, commands are inserted into command queue 1502 without regard to the availability of free time slots on the command or data buses. A command may be issued to the command bus from any one of command queue elements 1602 via multiplexer 1608 if its C.sub.d count is zero and there are no collisions on the data bus indicated. That is, free time slots on the command bus and/or the data bus must be identified. If a command is not a read or a write (and therefore requires no data bus resources) only a command bus time slot is needed. If the command is a read or a write, time slots on both the command and data buses are needed. Zero comparator 1610 in controller 1604 is used to make the first determination, i.e., whether C.sub.d =0. Subtractors 1612 are used to subtract "1" from the C.sub.d count for each command queue element 1602 each clock cycle unless there is an exception as described above, i.e., where C.sub.d =0 for a particular command which cannot be issued. In such a case queue controller 1604, using the C.sub.d and B fields for all queue elements, generates a mask signal (M) which prevents the C.sub.d count for all commands to the same logical bank from being decremented. According to a specific embodiment, if there are two queue elements having C.sub.d =0, the one with the highest priority (e.g., the oldest one) is issued. Address shifter 1614 determines the priority of commands in the queue as will be discussed in greater detail below with reference to FIG. 18. According to another specific embodiment, if a new command arrives at the command queue with its C.sub.d count already at zero, it may be transferred directly to the memory via multiplexer 1608. A new command is stored in a command queue element 1602 if its C.sub.d count is nonzero or there are other commands stored in the command queue with C.sub.d =0 and higher priority. If, however, the command queue is empty, then a new command can be immediately issued (if C.sub.d is equal to zero). For read or write commands, collisions are detected using the D.sub.d and D.sub.b fields of the command queue element 1602 containing the command ready to be issued. The occurrence time and duration of the data corresponding to the command are transmitted to comparator matrix 1506 via multiplexer 1508 which is, in turn, controlled by queue controller 1604. That is, queue controller 1604 controls multiplexer 1508 to transmit the data occurrence time and duration (either one or two clock cycles) of the queue element for which the command issue time, i.e., C.sub.d, is zero. The duration is indicated to be either one or two clock cycles by adding the D.sub.b bit to the data occurrence time D.sub.d with adders 1616 which yields either a "0" for D.sub.d+1 (indicating one clock cycle) or a "1" (indicating two clock cycles). The data occurrence time and duration are then compared in comparator matrix 1506 with the data occurrence times and durations of five previously issued commands stored in data queue 1504. According to a specific embodiment, comparator matrix 1506 comprises a 2*10 parallel comparator matrix. FIG. 18 is a block diagram of a specific embodiment of address shifter 1614 of FIG. 16. As mentioned above, address shifter 1614 determines the priority of commands. Also as discussed above, new commands are inserted into any free command queue element 1602 according to free position indicator 1606. The address of the command queue element 1602 into which a new command is inserted is inserted into the first free position (A0-A5) with the highest priority. The result is that the A0 position in address shifter 1614 stores the queue element address for the oldest command which has not already issued. When a command is issued from the command queue, the corresponding entry in address shifter 1614 is removed and the addresses for lower priority commands are shifted into higher priority positions. As discussed above, when the Cd count for a command in the command queue reaches zero it may be issued. If, however, there are more than one command for which Cd=0, the oldest one, i.e., the command with the highest priority as indicated by the position of its address in address shifter 1614, is issued. Data queue 1504 of FIG. 16 comprises five queue elements 1652 each of which stores 12 bits of information regarding a previously issued memory command as illustrated by the diagram of FIG. 19. Data occurrence time (D.sub.d) field 1902 is a 6-bit field which indicates a delta time in clock cycles between issuance of a command from the command queue and reception of the corresponding data. The D.sub.d count for each data queue element 1652 is decremented every clock cycle using one of subtractors 1654 until its value reaches zero. When D.sub.d =0, the corresponding data are on the data bus. Therefore, it will be understood that only one data queue element 1652 may have D.sub.d =0 at any given time. After the D.sub.d count reaches zero the information in the corresponding data queue element is removed from data queue 1504. Command ID field 1904 is a 5-bit field which uniquely identifies the issued command to which the data correspond. This information is useful for reordering the data to correspond to the order in which the commands were originally transmitted to the memory controller. Finally, burst indicator (D.sub.b) field 1906 is a 1-bit field which indicates whether the data occupy one or two clock cycles. Referring back to FIG. 16 and as described above, the data occurrence time (D.sub.d) and duration for each of data queue elements 1652 are compared in comparator matrix 1506 to the D.sub.d and duration for a command in command queue 1502 which is ready to be issued, i.e., for which C.sub.d =0. The duration is indicated to be either one or two clock cycles by adding the D.sub.b bit to the data occurrence time D.sub.d with adders 1656 which yields either a "0" for D.sub.d+1 (indicating one clock cycle) or a "1" (indicating two clock cycles). If the comparison shows no collisions on the data bus, the command is issued from the command queue. Data queue controller 1658 controls operation of data queue 1504. Free position indicator 1660 along with command queue controller 1604 facilitates insertion of new data queue element information into data queue elements 1652. Free position indicator also facilitates removal of information from data queue elements 1652 when the corresponding memory accesses are complete. Zero comparator 1662 and burst indicator 1664 are used to determine when D.sub.d for any of data queue elements 1652 is zero and when the data transfer no longer occupies the data bus, and thus when the corresponding information may be removed from the data queue. According to another specific embodiment of the invention, collision detection becomes more complex through the use of a two-dimensional array of comparators and multiplexers. This approach is more silicon intensive than the one-dimensional approach described above and looks at all of the elements in the command queue rather than only the one for the command ready to be issued. It schedules commands not only with respect to previously issued commands, but also with respect to the order of data packets on the data bus. In order to insert a new command, each set of two consecutive stages in the to-be-issued portion of the command pipe must be compared to see if a new command can be inserted between them. The comparison actually determines a range that the command can be inserted into. This range is as follows: CLEN.sub.x =command length T.sub.cstart +t.sub.cA =CLEN.sub.A (1) T.sub.cend =t.sub.cB (2) Where t.sub.cA are t.sub.cB are the issue times for consecutive pipeline elements A and B. Pipeline element A is ahead of pipeline element B and thus its issue time is the lower of the two. If there is to be an insertion there must of course be at least one open slot between the A and B elements. Thus: N=T.sub.cend -T.sub.cstart +1 (3) (where N=number of issue slots between elements A and B) LEN<=t.sub.cb -t.sub.ca -CLEN.sub.A (4) In hardware it is easy to simply implement the condition: (t.sub.cB -CLEN.sub.A)-(t.sub.cA +CLEN.sub.A)=>0 (5) The start and end points of the range also specify a possible range of associated data slots. This range must be compared to each set of successive elements in the data pipe to see if there is an overlap and what the new range will be. Five distinct cases exist for this comparison. Case 0 In this case the range described by the data slots t.sub.dA and t.sub.dB is completely outside of the range of the two consecutive elements M and N. In this case then: t.sub.dA +CLEN.sub.A =>t.sub.dN (6) or, where DLENx=DATA LENGTH, t.sub.dB <=t.sub.dM +DLEN.sub.M (7) There is no possible data slot between the pair M and N. Case 1 In this case the range described by the data slots t.sub.dA and t.sub.dB is completely within the range of the two consecutive elements M and N. In this case then: t.sub.dA+CLEN.sub.A =>t.sub.dm +DLEN.sub.M (8) and t.sub.dB -CLEN+DLEN<=t.sub.dN (where CLEN is a new command length and DLEN is new data length in slots) (9) The earliest possible data slot time in this case is t.sub.dA +LEN.sub.A with a corresponding command issue time of t.sub.cA +CLEN.sub.A Case 2 In this case the range described by the data slots tdA and tdB spans the element M. In this case then: t.sub.dA +CLEN.sub.A <t.sub.dM +DLEN.sub.M (10) and t.sub.dB -CLEN+DLEN>t.sub.dM +DLEN.sub.M and t.sub.dB -CLEN+DLEN<t.sub.dM (11) The earliest possible data slot time in this case is t.sub.dM +DLEN.sub.M +1 with a corresponding command issue time of t.sub.dM+CLEN.sub.M -DATA OFFSET where DATA OFFSET is the time between command issue time and data occupancy. Case 3 In this case the range described by the data slots tdA and tdB spans the element N. In this case then: t.sub.dA +CLEN.sub.A >t.sub.dM +DLEN.sub.M (12) and t.sub.dA +CLEN.sub.A +DLEN<t.sub.dN (13) Thus the earliest possible data slot time in this case is t.sub.dA +CLEN.sub.M with a corresponding command issue time of t.sub.cA +CLEN.sub.A +1. It should be noted that the case 1 can also lie within this case. Case 4 In this case the range described by the data slots t.sub.dA and t.sub.dB encapsulates the range defined by the elements M and N. In this case then: t.sub.dA +CLEN.sub.A <t.sub.dM +DLEN.sub.M (14) and t.sub.dB -LEN>Ct.sub.dN (15) Thus the earliest possible data slot time in this case is t.sub.dM +CLEN.sub.M with a corresponding command issue time of t.sub.cM +CLEN.sub.A.+DATA_OFFSET where DATA_OFFSET=t.sub.dA -t.sub.cA. It is clear that Case 1 and Case 3 are identical for the purpose of scheduling as the earliest possible slot is always taken. The combined case therefore is Case 3. Similarly Case 2 and case 4 are identical as the desired result is t.sub.dM +LEN.sub.M. In this case it must simply be shown that t.sub.dM is spanned by the range given by t.sub.dA and t.sub.dB. Additionally the earliest possible issue time (t.sub.c) and data slot (t.sub.d) for the incoming command must be considered. The comparisons that must be made at each data pipe pair for each command pipe pair are:
if(((t.sub.cB - CLEN) => (t.sub.cA + CLEN.sub.A)) && (t.sub.c <=
(t.sub.cA + CLEN.sub.A))){
if(((t.sub.dA + CLEN.sub.A) <= (t.sub.dM + DLEN.sub.M)) &&
((t.sub.dB - DLEN - (t.sub.dM + DLEN.sub.M)) >=
0)){
t.sub.d = t.sub.dM + DLEN.sub.M ;
t.sub.c = t.sub.cA - t.sub.dA + t.sub.dM + DLEN.sub.M ;
}
else if(((t.sub.dN - (t.sub.dA + CLEN.sub.A + DLEN.sub.A)) >= 0) &&
(t.sub.dA + CLEN.sub.A) >= (t.sub.dM +
DLEN.sub.M)){
t.sub.d = t.sub.dA + CLEN.sub.A ;
t.sub.c = t.sub.cA + CLEN.sub.A ;
}
else {
t.sub.d = IMPOSSIBLE;
t.sub.c = IMPOSSIBLE;
}
}
else if(((t.sub.cB - CLEN) => t.sub.c) && (t.sub.c > (t.sub.cA +
CLEN.sub.A))){
if((t.sub.d < (t.sub.dM + DLEN.sub.M)) && ((t.sub.dB - DLEN -
(t.sub.dM + DLEN.sub.M)) >= 0)){
t.sub.d = t.sub.dM + DLEN.sub.M ;
t.sub.c = t.sub.c - t.sub.d + t.sub.dM + DLEN.sub.M ;
}
else if(((t.sub.dN - (t.sub.d + DLEN)) >= 0) && t.sub.d >=
(t.sub.dM + DLEN.sub.M)){
t.sub.d = t.sub.d ;
t.sub.c = t.sub.c ;
}
else {
t.sub.d = IMPOSSIBLE;
t.sub.c = IMPOSSIBLE;
}
}
else {
t.sub.d = IMPOSSIBLE;
t.sub.c = IMPOSSIBLE;
}
Thus for the command pipe the needed operations are: t.sub.cB -CLEN=>t.sub.cA +CLEN.sub.A t.sub.cB -CLEN=>t.sub.c t.sub.c +CLEN<=t.sub.cB t.sub.c >t.sub.cA +CLEN.sub.A t.sub.c <=t.sub.cA +CLEN.sub.A While for the data pipe the needed operations are: t.sub.dA +CLEN.sub.A <=t.sub.dM +DLEN.sub.M t.sub.dA +CLEN.sub.A >=t.sub.dM +DLEN.sub.M t.sub.dB -DLEN>=t.sub.dM +DLEN.sub.M t.sub.dN >=t.sub.dA +CLEN.sub.A +DLEN.sub.A t.sub.d <t.sub.dM +DLEN.sub.M t.sub.dN>=t.sub.d +DLEN t.sub.d >=t.sub.dM +DLEN.sub.M The decision logic therefore consists of a matrix of comparator cells as defined above. The optimum choice is the earliest command issue time and this is determined by a simple priority encoder. The reorder pipe control logic must dynamically determine what operation is to be done on each element of the command and data pipes. In the pending command pipe, each pipe element has 4 possible operations, read from previous element (pipe advances), hold current contents (pipe holds), read from next element (pipe backs up) and read from incoming command bus. A multiple set of conditions may exist at various points in the pipe as defined by four cases. The element from which issues are made to the SLiMAC is defined as element 0 while the element farthest from issue is defined as element M. An insertion to an element N will be made is the reorder determination logic finds that the optimum insertion spot in the current pipeline is between elements N-1 and N. Case 1--Hold The pipe holds as there is no issue to the SLiMAC or insertion of a new command. Case 2--Hold & Insert In this case there is no issue to the SLiMAC, but there is an insertion of a new command into the pipe. If an insertion occurs at the element N, then the pipe will hold from element 0 to element N-1, insert at element N and backs up from element N+1 to element M. Case 3--Issue In this case there is an issue to the SLiMAC from element 0 and the rest of the pipe will advance so that element 0 will contain the contents of element 1, element 1 will contain the contents of element 2 and so on until element M--1 contains the contents of element M. Case 4--Issue & Insert In this case there is an issue to the SLiMAC from element 0 and an insertion at element N. In this case elements 0 to N-2 are given advance operations, element N-1 is given an insert operation while elements N to M will hold. As an advance is given to the element that will store the data from the element behind it, the insertion at element N (the element is to be inserted between element N-1 and element N of the current pipe) actually means that the inserted element will end up in position N-1 of the updated pipe. FIG. 20 illustrates a collision detection system 2000 that is another implementation of the collision detection system 1500 shown in FIG. 15. In this embodiment, the collision detection system 2000 reorders commands to achieve an optimal command sequence based on target response restrictions and determines the optimal slot for data transfer between initiator controller and target subsystem. Because the reordering of the commands can not cause collision of the different data packets on the data bus, a collision detector 2002 that prohibits to the issuance of a particular command if the command data transfer related to this particular command would cause data conflict is required. In the describe embodiment, the collision detection system 2000 includes the collision detector 2002 that is coupled to a command queue 2004. In the described embodiment, the collision detector 2002 detects all possible data collisions between a "to be issued" command (that is stored in a command queue 2004) and "already issued" commands (that are stored in a data queue 2006). In the described embodiment, there are N command queues 2004 each being coupled to a multiplexer 2008. Each of the N command queues 2004 are arranged to store those commands that are to be issued, a time factor "d_time.sub.ND ", indicating when the data transfer will appear on a data bus between the universal controller 104 and the target device (i.e., shared resource) 108 after the command was issued to the target device, a burst-bit (b.sub.ND) indicating data burst transfer, and a read/write bit (rw.sub.ND). In the described embodiment, the data queue 2006 stores a time factor "d_time.sub.D " indicating when the data transfer will appear on the data bus between controller 104 and the target device 108 for an already issued request to the target device. The command queue 2006 also stores the burst-bit (b.sub.ND) and the read/write bit (rw.sub.ND). In a preferred embodiment, the collision detection system 2000 includes a queues and link controller unit 2010 arranged to store and reorder those commands that are to be issued. The queues and controller unit 2010 also calculates the new issue time of commands and a time when the data appears on the data bus. The queues and controller unit 2010 also transfers the issued element from the command queue into the data queue as well as removing it from the command queue after the command was issued. The queues and controller unit 2010 also removes data elements from the data queue after the access to the memory has been completed. Referring to FIG. 21, every read/write command to the target device has related to it a data packet transfer. Before the issue of the command to the target device the new data packet ND (New Data) is checked according to it's timing information to see if it can be inserted into the data queue without collision. In this example shown in FIG. 21, an issued data packet D is already placed in the data queue and a new data packet ND is compared against the issued data packet D. It should be noted that both the issued data packet D and the new data packet ND represent burst accesses. In this example, therefore, there are two possibilities how the new data packet ND can be placed in respect to the issued data packet D without causing a data collision. The new data packet ND can be placed on the left side or on the right side of the issued data packet D. This particular example illustrates collision detection of the memory controller that supports both non-burst and burst data transfer (i.e., 4 data streams). Due to the bi-directional nature of the data bus, one clock cycle must be inserted between consecutive read-write or write-read transfers. It should be noted that there are many possible outcomes, some of which are listed below. 1) There is no collision between D and ND if ND is placed behind or before D. 2) Between consecutive read-write or write-read data transfers one clock cycle has to be inserted. Every element of Command and Data Queues stores a "rw" bit which indicates whether the operation is "read data" (rw=0) or "write data (rw=1). 3) Data packets consist of one data stream (no-burst transfer) or four streams (burst transfer). Every element of Command and Data Queues stores a "burst" bit which indicates whether the operation is "burst transfer" (burst=1) or "no-burst transfer" (burst=0). The comparisons that must be made at each to be issued data packet and issued data packet pair for each to be issued command are: // the initialization of variable collision=NO; // the end of the new packets from Command Queue is determine depends on burst bit if (burst.sub.ND =1) then d_time_end.sub.ND =d_time.sub.ND +3 else d_time_end.sub.ND =d_time.sub.ND for i=1 to last_element_from_Data_Queue begin // the end of the packets from Data Queue is determine depends on burst bit if (burst.sub.D [i]=1) then d_time_end.sub.D [i]=d_time.sub.D [i]+3 else d_time_end.sub.D [i]d_time.sub.D [i] // between two consecutive read/write or write/read one clock has to be implemented if (rw.sub.D [i]=rw.sub.ND) then begin d_time_end.sub.D[i]=d _time_end.sub.D [i]+1 d_time_end.sub.ND =d_time_end.sub.ND +1 end // collision detection if NOT((d_time.sub.ND >d_time_endD[i]) or (d_time.sub.D [i]>d_time_end.sub.ND)) collision=YES; end. In yet another embodiment of the invention, an apparatus and method for predicting the time between two consecutive memory accesses is disclosed that allows for very fast calculation of the earliest "command issue time" for the new command. Referring to FIG. 22, illustrating a predictor system 2200 having N page timers 2202 that store time between last issued command to the particular page and a predicted next access to that memory. The next access to the same page can be "close", "open", "write" or "read". The incoming new command (e.g. read) selects one particular page timer indicating how long a particular page access has to wait before the issue. The same new command then selects appropriate contents of a timing lookup table 2204 which has to be inserted between this command (read) and possible next accesses (close, open, write and read) to the same page. The resolution of timers is one clock cycle. Timing Lookup Table--Data stores time, which indicates how cycles after the issue of the command the data on the data bus will be valid. If the new command is inactive then every cycle the value of all Page Timers is until their value reached "0". Referring now to FIG. 23, in still another embodiment of the invention, a device controller 2300 having a device access prioritizer 2302 in accordance with an embodiment of the invention is shown. In the described embodiment, the prioritizer 2302 includes a requests queue 2303 suitable for receiving and storing any number of device requests coupled to a requests controller unit 2304 that is used to, in part, fetch a particular response from any position in the requests queue 2303 and transmit the fetched response to an appropriate one of the plurality of shared devices 108. In the described embodiment, the prioritizer 2302 also includes a responds queue 2306 arranged to receive and store responses from any of the shared devices 108 coupled to a responds controller unit 2308 used to select particular stored responses to be delivered to the requesting device 102. In a preferred embodiment, each response and request has associated with it the ID number 150 shown in FIG. 1E such that each request and its associated response have the same ID number 150. As discussed previously, the ID number 150 includes 5 data bits, wherein the first and second data bit are the group selector field 152 that identifies the group of requesting devices (such as a group of processors in a multi-processor computing environment) to which that particular response/request belongs. Again, as discussed above, the request number field (RN) 153 represents the number of requests and/or responses associated with the group of requesting devices identified by the group selector field 152 such that consecutive requests from the same requesting device, for example, have consecutive request number fields 153. During operation, both the requests and responds controllers 2304 and 2308, respectively, incorporate the group priority selector register 154, the livelock counter register 156, and a reordering selector 2312. The group priority selector register 154 includes priority information for a particular requests/response group identified by the RN 152, wherein in one embodiment, a value of "3" represents a highest priority whereas a value of "0" represents a lowest priority such that the request with the higher priority can bypass the request with the lower priority. In order to avoid a livelock situation, the livelock counter register 156 contains information about how many consecutive requests (or responses) with the higher priority can bypass requests (or responses) with the lower priority. It should be noted that the livelock counter register 156 is active only in those situations where the request with the higher priority bypasses the request with the lower priority. If, in fact, there is no request (or response) with the lower priority in the appropriate queue, then the livelock counter register 156 is inactive. Although only a few embodiments of the present invention have been described in detail, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope of the appended claims.
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