Dedicated context-cycling computer with timed context

Abstract

A dedicated context cycling microprocessor which features a plurality of input/output circuits for receiving and transmitting information and an individual set of dedicated on-board resources for each plurality of processing contexts. A distinct processing context is provided for each of a plurality of the input/output circuits, and a timed context is also provided for concurrently scheduling multiple processing contexts and enforcing time constraints associated with this schedule. The timed context has a pseudo-queue list which represents an ordered set of data parameters and program memory addresses for scheduling each of the processing contexts. The dedicated on-board resources include a plurality of registers for each of the processing contexts, such as at least one general purpose register and a program counter. A multiplexer circuit is also provided for moving data between the input/output circuits, the dedicated registers of the processing contexts and the computational unit. The input/output circuits include at least one serial and shared memory management unit, a plurality of embedded SCSI interfaces and a plurality of memory mapped registers. The dedicated context cycling microprocessor is also adapted to work in conjunction with, and effectively control another microprocessor, as well as control the access to an external memory system which is shared between these two microprocessors.

Claims

What is claimed is:

1. A dedicated context-cycling microprocessor comprising:

a plurality of input/output circuits for receiving and transmitting information;

a plurality of processing contexts each having an individual set of affiliated registers in which a distinct processing context is provided for each of said plurality of said input/output circuits, said processing contexts also including a time context for concurrently scheduling multiple processing contexts and enforcing time constraints associated with said schedule;

at least one computational unit for performing mathematical and/or logical functions;

a bus structure for transferring instructions and data with external memory devices; and

multiplexer circuit for moving data between said input/output circuits, said dedicated registers and said computational unit, said multiplexer circuit having a move bus coupled to said bus structure,

wherein said processing contexts include an idle state in which the context is waiting to be scheduled, an inactive state in which a scheduled context is waiting for an event to occur, a bidding state in which a scheduled context is competing for service and an active state in which the scheduled context has been granted the highest priority and is now executing a fetched instruction; and

wherein a scheduler latch is provided for each of said processing contexts except for said timed context and a context purpose register is provided for said timed context, with each of said scheduler latches being mapped into said context purpose register for said timed context in order to schedule one or more of said processing contexts for service.

2. The invention according to claim 1 wherein each of said sets of dedicated registers includes at least one general purpose registers and a program counter.

3. The invention according to claim 2 wherein said timed context has access to at least the program counter of said dedicated registers in all of the other of said processing contexts.

4. The invention according to claim 1, wherein said microprocessor further includes a priority encoding circuit which ensures that more than one instruction of an active processing context must be executed before the active processing context is permitted to bid again for service.

5. The invention according to claim 1 wherein said processing contexts have preassigned priority levels and at least some high priority processing contexts are capable of lowering their own priority.

6. The invention according to claim 1 further comprising a local RAM, a program memory and at least said timed context has a pseudo-queue list whose pointers are stored in said local RAM, said pseudo-queue list representing an ordered set of pointers to data and program memory words to be used for scheduling said processing contexts.

7. The invention according to claim 1 wherein said input/output circuits include at least one serial and shared memory management unit comprised of a parallel-to-serial converter and a transmitter circuit which is capable of transmitting a plurality of serial word frames without any spaces between them, said serial and shared memory management unit having its own processing context.

8. The invention according to claim 7 wherein said input/output circuits also include a plurality of SCSI interfaces with each of said SCSI interfaces having its own programming context.

9. A common core computer comprising:

a first microprocessor;

a first private memory system connected to said first microprocessor;

a second microprocessor;

a second private memory system connected to said second microprocessor; and

a shared memory system connected to both said first and second microprocessors;

said second microprocessor including a plurality of input/output circuits for receiving and transmitting information with external communication devices and timing means for controlling the operation of said first microprocessor and access to said shared memory system, wherein said second microprocessor includes:

an individual set of dedicated registers for each of a plurality of processing contexts in which a distinct processing context is provided for each of a plurality of said input/output circuits, said processing contacts also including a timed context for concurrently scheduling multiple processing contexts and enforcing time constraints associated with said schedule;

at least one computational unit for performing mathematical and/or logical functions, said computation unit being coupled to at least one of said input/output circuits;

a bus structure for transferring instructions and data with said shared memory system and said second private memory system; and

multiplexer circuit means for moving data between said input/output circuits said dedicated registers and said computational unit said multiplexer circuit means having a move bus coupled to said bus structure.

10. The invention according to claim 9 wherein said first microprocessor has a Harvard architecture and said second microprocessor has an opcode width corresponding to a data word width of said first microprocessor.

11. The invention according claim 9 wherein at least some of said processing contexts have their own plurality of interrupt signal inputs.

12. The invention according to claim 9 wherein each of said sets of dedicated registers includes at least one general purpose register and a program counter.

13. The invention according to claim 12 wherein said timed context has access to at least the program counter of said dedicated registers in all of the other of said processing contexts.

14. The invention according to claim 9 wherein said processing context include an idle state in which the context is waiting to be scheduled, an inactive state in which a scheduled context is waiting for an event to occur, a bidding state in which a scheduled context is competing for service, and an active state in which the scheduled context has been granted the highest priority and is now executing a fetched instruction.

15. The invention according to claim 14 wherein said second microprocessor further includes a priority encoding circuit which ensures that than one instruction of an active processing context must be executed before the active processing context is permitted to bid again for service.

16. The invention according to claim 14 wherein said processing contexts have preassigned priority levels, which high priority processing contexts being capable of lowering their own priority.

17. The invention according to claim 14 wherein a scheduler latch is provided for each of said processing contexts except for said timed context, and a context purpose register is provided for said timed context, with each of said scheduler latches being mapped into said context purpose register for said timed context in order to schedule one or more of said processing contexts for service.

18. The invention according to claim 9 further comprising a local RAM, a program memory, and at least said timed context has a pseudo-queue list stored in said local RAM which represents an ordered set of pointers to data and program memory words to be used for scheduling said processing contexts.

19. The invention according to claim 9 wherein said input/output circuits include at least one serial and shared memory management unit comprising parallel-to-serial transmitter circuit which is capable of transmitting a plurality of serial word frames without deadtime, said serial and shared memory management unit having its own processing context.

20. The invention according to claim 19 wherein said input/output circuits also include a plurality of SCSI interfaces with each of said SCSI interfaces having its own programming context.

21. A method of processing input/output signals of different types by a computer, comprising:

defining a plurality of functional contexts corresponding to said different types of input/output signals;

configuring an input/output processor to have a dedicated program counter and at least one dedicated general purpose register for each of said functional contexts, said input/output processor being operable in synchronism with a system clock that defines a fundamental clock interval;

operating said input/output processor to cycle from one context to another such that one context is active during a given fundamental clock interval and such that that processing state of a first context is saved in the dedicated program counter and dedicated general purpose register of that first context while switching to process a second context by accessing the program counter of that second context; and

subdividing said fundamental clock interval into a first component and a second component that follows said first component,

wherein the processing state of said first context is saved in the dedicated general purpose register of the first context during the first component of a first fundamental clock interval, and

wherein the program counter of the second context is accessed in preparation to process the second context during the second component of the said first fundamental clock interval.

22. The method of claim 21 further comprising configuring a second processor to have a memory space that is shared with said input/output processor and using said input/output processor to communicate information about to said input/output signals to said second processor by storing said information as data in said shared memory space.

23. The method of claim 21 further comprising configuring a second processor to have a memory space that is shared with said input/output processor and using said input/output processor to supply timing information to said second processor.

24. The method of claim 21 wherein said plurality of contexts includes a timed context that oversees the order in which context switching is performed.

25. The method of claim 21 wherein said functional contexts are assigned different priorities and wherein said step of operating said input/output processor is performed by selecting said second context based on priority bidding.

26. A multi-protocol data processing computer for communicating with multiple processes comprising:

an input/output (I/O) processor for communicating with multiple processes using different protocols;

said I/O processor having context cycling system for defining a plurality of independent operating-state contexts, each context devoted to one of said protocols;

said context cycling system having a plurality of program counter registers and a plurality of general purpose registers each dedicated to said contexts such that each context has its own program counter register and its own general purpose registers;

said context cycling system having priority encoder for selecting one of said contexts as the operative context, such that the program counter register and general purpose registers of the operative context are identified to said I/O processor as the operative program counter register and the operative general purpose registers and the remaining program counter registers and general purpose registers are treated by said I/O processor as inoperative;

said I/O processor communicating with one of said multiple processes by accessing the operative program counter register and the operative general purpose registers, such that communication is effected in accordance with the operative context;

said I/O processor saving the state of the contexts not selected as operative by leaving the contents of the inoperative program counters and general purpose registers unchanged while communication is effected in accordance with the operative context.

27. A multi-protocol multiprocessor data processing system for communicating with and controlling multiple processes comprising:

an input/output (I/O) processor for communicating with multiple processes using different protocols, said I/O processor having first private memory accessed by said I/O processor in communicating with said multiple processes;

a second processor for executing process control instructions to control said multiple processes, said second processor having second private memory accessed by said second processor in executing process control instructions;

a shared memory separate from said first and second private memories and accessed by both said I/O processor and said second processor for establishing communication between said I/O processor and said second processor;

said I/O processor having context cycling system for defining a plurality of independent operating-state contexts, each context devoted to one of said protocols;

said context cycling system having a plurality of program counter registers and a plurality of general purpose registers each dedicated to said contexts such that each context has its own program counter register and its own general purpose registers;

said context cycling system having priority encoder for selecting one of said contexts as the operative context, such that the program counter register and general purpose registers of the operative context are identified to said I/O processor as the operative program counter register and the operative general purpose registers and the remaining program counter registers and general purpose registers are treated by said I/O processor as inoperative;

said I/O processor communicating with one of said multiple processes by accessing the operative program counter register and the operative general purpose registers, such that communication is effected in accordance with the operative context;

said I/O processor saving the state of the contexts not selected as operative by leaving the contents of the inoperative program counters and general purpose registers unchanged while communication is effected in accordance with the operative context.

Description

BACKGROUND OF THE INVENTION

The present invention generally relates to computer architectures and particularly to a dedicated context-cycling microprocessor which is capable of functioning as either a stand-alone processor or as an intelligent interface between one or more external devices and the shared data memory of another computer, such as a Harvard architecture computer.

To achieve high speed, some multiprocessor computers employ specialized dedicated processors for handling specific tasks. For example, it is common to supplement the main central processing unit with a separate math coprocessor, the math coprocessor being specifically designed to perform arithmetic computations at high speed. Although the math coprocessor may perform different computational functions (add, subtract, multiply, divide) these functions are all of the same type or class. A math coprocessor would not be suitable to handle asynchronous data communication in addition to its other arithmetic functions. The math coprocessor is an example of a special purpose processor for a multiprocessor architecture that is dedicated to performing only one task.

As multiprocessor computer systems become more sophisticated, single purpose coprocessors begin to have drawbacks. It would be desirable if multiprocessor systems could be designed to support different classes of tasks by the coprocessor. For example, The Dow Chemical Company has developed a common core computer that employs a Harvard architecture computer as its main central processing unit. The Applicants' assignee has found the Harvard architecture to be highly desirable in process control applications where high speed performance is of utmost importance. The context-cycling microprocessor of the present invention works as an asynchronous data communication handler for this Harvard architecture common core computer.

A computer which includes the following characteristics is generally referred to as having a "Harvard" architecture. Namely, the computer will be designed with separate instruction and data stores and independent buses will be provided to enable the central processing unit (CPU) of the computer to communicate separately with each of these stores. Contrast this architecture with the "von Neumann" or "Princeton" based computer architecture, which generally employs the same physical store for both instructions and data, and a single bus structure for communication with the CPU.

Various approaches have been taken to designing a microcomputer or microprocessor with a Harvard architecture, as represented by the following patents: Yasui et al., U.S. Pat. No. 5,034,887, issued on Jul. 23, 1991, entitled "Microprocessor With Harvard Architecture"; Portanova et al., U.S. Pat. No. 4,992,934, issued on Feb. 12, 1991, entitled "Reduced Instruction Set Computing Apparatus And Methods"; Mehrgardt et al., U.S. Pat. No. 4,964,046, issued on Oct. 16, 1990, entitled "Harvard Architecture Microprocessor With Arithmetic Operations And Control Tasks for Data Transfer Handled Simultaneously"; and Simpson, U.S. Pat. No. 4,494,187, issued on Jan. 15, 1985, entitled "Microcomputer With High Speed Program Memory." Additionally, it should be noted that the Intel i860 64-bit microcomputer has been described as having an on-board Harvard architecture due to the provision of separate instruction and data cache paths. In this regard, a description of the Intel i860 chip design may be found in i860 Microprocessor Architecture, by Neal Margulis, Osborne McGraw-Hill 1990.

The use of separate instruction and data communication paths in a Harvard architecture machine effectively increases the overall speed of the computer by enabling an instruction to be accessed at the same time that data for this or another instruction is accessed. In the context of programmed operations, the instruction is usually referred to as the "opcode" (the operation code), and the data is referred to the "operand." While the benefit in speed of using the Harvard architecture is significant, a significant advance in this design has also been described in commonly assigned Sederlund et al., U.S. patent application Ser. No. 08/319,453, filed on Oct. 6, 1994, entitled "An Extended Harvard Architecture Memory System." This extended memory system employs an address store for containing an ordered sequence of program memory addresses. The address store (referred to as "queue memory") determines the sequence of operations to be implemented through its list of program memory addresses. In this regard each of these program memory addresses identifies the location of the first instruction of a particular subroutine which is contained in the program memory. The address store may also contain the addresses of one or more subroutine arguments which are, in turn, contained in either a value store or in a data memory. Thus, the address store may be utilized as a location server for both the program memory and the data memory of a computer which is based upon the Harvard architecture.

As the preceding suggests, The Dow Chemical Company is committed to the use of highly advanced computer systems that are uniquely suited to process control applications. In this regard, whereas the massively multiplexed CPU design, based on a Harvard architecture, is highly efficient at performing process control instructions at very high speed, another computer architecture is needed to best handle numerous asynchronous events that occur in process control applications. In this regard, although The Dow Chemical Company envisions its massively multiplexed CPU design and the dedicated context-cycling computer of the present invention to be well suited to chemical and manufacturing process applications, the foregoing innovations are equally suited to all other types of process control applications, ranging from power plant to spacecraft.

The present invention provides a dedicated context-cycling microprocessor or computer for handling the input and output tasks on behalf of its associated Harvard architecture central processing unit. As it turns out, providing this functionality is not as easy as it might appear. In a complex process control system there are many widely varying input/output functions and asynchronous events that must be handled. Inasmuch as the main process control computer has been designed to operate at extremely high speeds, the input/output functions must also be handled at comparable high speeds, otherwise the input/output becomes a bottleneck in the system. One approach, consistent with conventional practice, would be to provide a separate coprocessor for each input/output function. However, this would dramatically increase the cost of the system and would unduly complicate the interface between the main processor and the input/output processors.

Another approach would be to employ a single coprocessor that may be programmatically cycled through different functional states. However, such an approach has not heretofore been feasible because of the computational overhead required to save one context state before operating the next.

The present invention solves the problem by providing a dedicated context-cycling microprocessor that has dedicated registers and program counters for each different functional context. As used herein the term "context" (within a processor) refers to a specialized physical circuit having a dedicated program counter to identify the current location in a program instance for fetching an op code for execution in a computational unit--such as the computational unit of a general purpose computer processor. The specialized physical circuit is useful for exchanging data between external entities and the configuration and computational assets of the processor (including the computational unit) according to a predefined protocol, or for performing predefined data manipulation functions. The context may also include an embedded state machine that may operate independently of the computational unit to aid in the exchange of data.

In the preferred configuration, a plurality of contexts share common assets, such as by time division multiple access, each context cycling through active and inactive states according to a context priority scheme. Common assets are assets actively used by only one context at a time (such as, without limitation, external data memory, computational unit, comparator, program counter calculator and local memory). Each context assumes one of a plurality of functional states, including at least one active state and at least one inactive state. In the active state the context may communicate with the computational unit and may also use other common assets. In the inactive state, the embedded state machine of a context may continue to function although the program counter of its context is not being used to identify an op code for the manipulation of configuration and computational assets. Each context has a data store, such as a memory or register, for retaining the process and configuration state of pertinent resources, attributes, or aspects associated with either the interface or the function while another context is active. In the preferred embodiment, each context is configured as an embedded microcontroller associated with a processor for performing mathematical computatations.

The context-cycling microprocessor rapidly cycles from context to context without the usual overhead of saving state; the dedicated registers and program counters automatically save state without wasting processor cycles as in the conventional practice.

Accordingly, it is a principal objective of the present invention to provide a microprocessor design which has special capabilities for handling input/output and asynchronous events.

It is a more specific objective of the present invention to provide a microprocessor design which is capable of dynamically cycling between a number of both device and time handling contexts.

It is another objective of the present invention to provide a context-cycling microprocessor design which may be utilized in either a stand-alone processor or as an intelligent communication interface for another processor which operates as the source and destination of data.

It is a further objective of the present invention to provide a context-cycling microprocessor design which is capable of acting as a time-line enforcer.

It is an additional objective of the present invention to provide a context-cycling microprocessor design which is also capable of acting as a plurality of distinct, but coordinated controllers for processing communication requests with external devices.

It is also an objective of the present invention to provide a context-cycling microprocessor design which is capable of not only rapidly handling external communication requests, but also capable of managing a shared memory system in conjunction with another microprocessor.

SUMMARY OF THE INVENTION

To achieve the foregoing objectives, the present invention provides a dedicated context-cycling microprocessor which features a plurality of input/output circuits for receiving and transmitting information and an individual set of dedicated on-board resources for each of a plurality of processing contexts. A distinct processing context is provided for each of a plurality of the input/output circuits and a timed context is also provided for concurrently scheduling multiple processing contexts and enforcing time constraints associated with this schedule. The timed context has a pseudo-queue list which represents a time-ordered set of data parameters and program memory addresses for scheduling each of the processing contexts. Each of the processing contexts may also employ their own pseudo-queue list of parameters which are needed to accomplish a specific context task. The dedicated on-board resources include a plurality of registers for each of the processing contexts, such as at least one general purpose register and a program counter. Accordingly, each of these processing contexts is capable of operating as a separate controller which is unaware of the other controllers, except for the timed context which has access to the program counters for all of the other processing contexts. In other words, the context-cycling microprocessor according to the present invention is capable of operating as many separate controllers, each with its own set of hardware assets. The cycling between these separate processing contexts is controlled through a scheduling pseudo-queue and priority bidding, such that the context is capable of fire and forget operation. In other words, the context-cycling microprocessor may turn its attention to another processing context before the currently active processing context has completed its task. In one form of the present invention, only one context is active (running an instruction) at any particular time because these contexts do share certain resources, such as an on-board computational unit as well as externally accessible memories.

The dedicated context-cycling microprocessor according to the present invention preferably includes at least one computational unit for performing mathematical and/or logical operations, a bus structure for transferring instructions and data with external memory systems and a multiplexer circuit for moving data between the input/output circuits, the dedicated registers of the processing contexts and the computational unit. In one form of the present invention the bus structure is a multiplexed program/data bus and the multiplexer circuit includes an internal move bus which is connected for output to the multiplexed program/data bus. The input/output circuits include at least one serial and shared memory management unit, which is comprised of parallel-to-serial transmitter and serial-to-parallel receiver circuits that are capable of communicating a plurality of serial word frames without any dead time between them. The input/output circuits also include a plurality of embedded SCSI interfaces and a plurality of internal and/or external memory mapped registers.

The dedicated context-cycling microprocessor is also adapted to work in conjunction with and effectively control another microprocessor, as well as control the access to an external memory system which is shared between these two microprocessors. In this regard the context-cycling microprocessor is capable of immobilizing the other microprocessor through one or more timing signals. In one form of the present invention the context-cycling microprocessor is capable of directly transferring information which has been received at one of its input circuits to the shared memory of this microprocessor. In the event that the shared memory system is currently being used by the other microprocessor, then the data will be maintained in a registered transceiver until the shared memory becomes available.

Additional features and advantages of the present invention will become more fully apparent from a reading of the detailed description of the preferred embodiment and the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a Harvard architecture-based common core computer which employs a context-cycling microprocessor according to the present invention.

FIG. 2 is a simplified block diagram of the context-cycling microprocessor shown in FIG. 1.

FIG. 3 (FIGS. 3A and 3B, collectively) is a detailed block diagram of the context-cycling microprocessor shown in FIG. 1.

FIG. 4A is a detailed block diagram of the timer circuit associated with the timed context.

FIG. 4B is a detailed block diagram of a portion of the context purpose register for the timed-context, which is contained in the context management circuit (1132) generally shown in FIG. 3.

FIGS. 5A and 5B provide diagrammatic views of typical pseudo-queue entries according to the present invention.

FIG. 6 is a detailed block diagram of an interrupt priority encoder circuit as generally shown in FIG. 3.

FIG. 7 is a detailed block diagram of the interrupt selection circuit for the timed context.

FIGS. 8A-8F are a set of detailed block diagrams which illustrate examples of the dedicated registers for the processing contexts.

FIG. 9 is a timing diagram of the clock signals used by the context-cycling microprocessor.

FIG. 10A is a detailed block diagram of the multiplexed program/data bus structure shown in FIG. 3.

FIG. 10B is a detailed block diagram of the bank switch circuit of the preferred embodiment.

FIG. 11 is a detailed block diagram of the move multiplexer circuit contained in mux module circuit 1146 of FIG. 3 and of the external RAM and program data memory RAM.

FIGS. 12A-12D represent a general schematic diagram of the move multiplexer and other multiplexing and data manipulation circuits contained in mux module circuit 1146 of FIG. 3.

FIG. 13 is a block diagram of the opcode decoder shown in FIG. 3 and memory protect functionality.

FIGS. 14A and 14B are charts illustrating the instruction types utilized by the context-cycling microprocessor.

FIGS. 15A-15E provide a set of detailed block diagrams for the serial and shared memory management units shown in FIG. 3.

FIG. 16 is a detailed block diagram for the arbitration circuit shown in FIG. 3.

FIG. 17 is a timing diagram of the clock signals used in connection with the shared memory interface and coprocessing Harvard architecture ASIC.

FIG. 18 is a diagram of the software reference model of the common core computer.

FIG. 19 is a data flow diagram illustrating how the HI/O processor saves state.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Common Core Computer Overview

Referring to FIG. 1, a block diagram of a common core computer 1000 is shown. In particular, the common core computer 1000 features a dedicated context-cycling microprocessor 1012 according to the present invention. The common core computer 1000 further includes a Harvard architecture microprocessor 1014 and a shared memory system 1016. For sake of simplicity, the Harvard architecture microprocessor 1014 is generally referred to herein as the "H2" microprocessor. Similarly, the dedicated context-cycling microprocessor 1012 is also generally referred to herein as the "HI/O." However, it should be noted that the HI/O microprocessor 1012 is sometimes referred to as the "Harvl/O" microprocessor in the drawings.

While the HI/O microprocessor 1012 is designed for use as a stand-alone processor, FIG. 1 specifically serves to illustrate how the HI/O microprocessor 1012 may advantageously be used to work with another microprocessor. In this particular embodiment, the HI/O microprocessor 1012 is used to provide an intelligent interface between the shared memory system 1016 of the H2 microprocessor 1014 and external devices. For example, the H2 microprocessor 1014 may be used in a process control computer which receives input signals from a number of field sensors and determines the output signals needed to drive the physical equipment that governs the process, such as pumps and valves. In such a case, the H2 microprocessor 1014 is the eventual destination of all field input data and source of all field output data. Accordingly, the design of the H2 microprocessor 1014 should focus on rapidly executing the instructions needed to process the various input signals received. Nevertheless, the need exists to transmit both input and output data from the H2 microprocessor 1014 to other external devices, such as a computer network which includes one or more operator stations for supervising the process being controlled. Thus, the HI/O microprocessor 1012 has been designed with exceptional capabilities for rapidly managing asynchronous events, such as communication requests for data from the H2 microprocessor 1014 and other external computer communication and computation entities. The design of the common core computer 1000 capitalizes on the signal transfer capabilities of the HI/O microprocessor 1012 as will be more fully appreciated below.

In the embodiment of the common core computer 1000 illustrated in FIG. 1, the H2 microprocessor 1014 is shown to be of a Harvard architecture design which utilizes an expanded memory system. As generally provided in a Harvard architecture-based design, the H2 microprocessor 1014 includes separate data and program bus structures. Specifically, the H2 microprocessor 1014 includes data bus 1018 (DDATA), a data address bus 1020 (DADDR), a program data bus 1022 (PDATA) and a program address bus 1024 (PADDR). The data bus 1018 and the data address bus 1020 are used to provide read/write communication with an external data memory system 1026 while the program data bus 1022 and the program address bus 1024 are used to provide read/write communication with an external program memory system 1028. The data memory system 1026 includes a private data memory circuit 1030, while the program memory system provides a physically separate program memory circuit 1032.

Preferably, the H2 microprocessor 1014 also includes a queue data bus 1034 (QDATA) and a queue address bus 1036 (QADDR) for communicating with an external queue memory system 1038. The queue memory system 1038 includes a queue memory circuit 1040 which is used to store an ordered list of program memory addresses (as well as subroutine arguments). Each of these program memory addresses generally represents the initial address of a distinct subroutine which has been stored in the program memory circuit 1032. In other words, the H2 microprocessor 1014 is preferably programmed to proceed sequentially down through the "queue list" found in the queue memory circuit 1040 in order to execute the instructions which are contained in the subroutines stored in the program memory circuit 1032. This approach has several advantages, such as significant decrease in the amount of memory required to store an application program for the computer. Additionally, execution speed may be enhanced because normal subroutine overhead is avoided, such as pushing one or more addresses onto a stack. Additional subroutine arguments may be readily changed by a programmer without having to recompile the program. Rather, the argument value may be changed directly in the memory location referenced in queue memory circuit 1040.

The H2 microprocessor 1014 is preferably constructed of a central processing unit design such as that described in the U.S. patent application Ser. No. 08/179,256, entitled "A Massive Multiplexed Super Scalar Harvard Architecture Computer." However, the common core computer 1000 may also employ other types of microprocessor designs in the appropriate application, such as those based upon the Harvard architecture. In this regard, the use of separate data/program bus structures in a Harvard architecture facilitates the use of a data memory that may be shared with at least one other computer entity without unduly complicating the operational constraints on the microprocessor or adversely affecting its processing throughput.

A fundamental departure in Harvard architecture design is described in commonly assigned Dupree et al., U.S. patent application Ser. No. 08/179,256, filed on Jan. 10, 1994, entitled "A Massive Multiplexed Super Scalar Harvard Architecture Computer." This massively multiplexed CPU employs a very wide instruction word format which eliminates the need for microcode decoding or even an instruction register and parallel processing to achieve compound superscalar operations. More specifically, this CPU employs a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers has multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also has an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits is dedicated to at least one unique mathematical function and at least one of the computational circuits includes at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus. The very long instruction word format uses a series of assigned bit locations to represent the selection and operation codes for each of the CPU components. These selection codes are directly transmitted to each of the CPU components by a program control circuit. A separate data control circuit and data bus are further provided to achieve a Harvard architecture design for the CPU.

Shared Memory System and Bus Structure

As illustrated in FIG. 1, the shared memory system 1016 includes a shared data memory circuit 1042 which has the same 40-bit word width as the private data memory circuit 1030 of the H2 microprocessor 1014. In some of the Figures, word width is indicated by brackets ›!. The H2 microprocessor 1014 may either write to or read from the shared data memory circuit 1042 or the private data memory circuit 1030 depending upon the appropriate control signals, such as a memory enable signal and a write/read opcode bit. In the present embodiment, the H2 microprocessor 1014 transmits these memory control signals (for example, the shared active opcode bit) to the HI/O microprocessor 1012, which is responsible for deciding which device will actually be given access to the shared data memory circuit 1042. However, with such a configuration, it is preferred that the H2 microprocessor be given priority to the shared data memory circuit 1042 over the HI/O microprocessor 1012.

The data memory circuit 1030 is characterized as private; it is considered private by the H2 microprocessor 1014. However, other entities may access this memory as well. In other words, as long as access to the data memory circuit 1030 is transparent to the H2 microprocessor 1014, other external computer entities may also have access to this memory.

As with the other memory systems discussed thus far, the shared memory system 1016 includes an address decoder/buffer circuit 1044. Similarly, the shared memory system 1016 also includes a transceiver circuit 1046. The address decoder/buffer circuit 1044 is used to extract an 18-bit address from the 24-but wide data address bus 10 and store this address in a latch. The transceiver circuit 1046 is used to control the direction, destination and source of data transfer to or from the shared data memory circuit 1042 in response to the write/read control signal controlled by the HI/O microprocessor 1012 (namely the H2SharedR/W signal shown in FIG. 2). In one embodiment according to the present invention, the address decoder/buffer circuit 1044 is comprised of three FCT157 muxes and an FCT157 3-to-8 decoder circuit and FCT244 buffers, all from Integrated Device Technology, Santa Clara, Calif. Similarly, the transceiver circuit 1046 may be comprised of five FCT245 transceiver circuits from Integrated Device Technologies. However, as with the other components specifically referenced herein, it should be appreciated that other suitable circuit devices could be employed in the appropriate application.

The HI/O microprocessor 1012 is also shown in FIG. 1 to include its own private memory system 1048 employing private program and data memory circuits 1049. While the HI/O microprocessor 1012 could be constructed to have a Harvard architecture like that of the H2 microprocessor 1014, the presently preferred HI/O microprocessor utilizes a multiplexed program/data bus structure. In this regard, the multiplexed program/data bus structure is comprised of the 40-bit wide program and data bus 1050 and the 20-bit wide program and data address bus 1052. Such a multiplexed bus structure was employed in order to reduce the number of input/output pins needed by the HI/O microprocessor 1012 in light of the significant number of input/output circuits designed into the HI/O microprocessor, as will be discussed more fully below.

The HI/O microprocessor 1012 also includes a separate 24-bit wide H2.sub.-- HI/O address bus 1054 for use in accessing either the shared memory system 1016 or the program memory system 1028 of the H2 microprocessor 1014. The separate address bus is used in the HI/O microprocessor 1012 to enable the HI/O microprocessor to complete a shared memory operation (delayed due to instruction skew and possible access by the H2 microprocessor 1014), and still allow the HI/O microprocessor to execute other instructions. This works as follows. Once the H2 microprocessor 1014 has completed its access to the shared data memory circuit 1042, an H2 opcode bit is cleared, informing the HI/O microprocessor that H2 will not be doing a shared memory operation during the next instruction period, and HI/O is clear to initiate a shared access of its own. The HI/O microprocessor 1012 preferably employs a 40-bit opcode which corresponds to the data word width of the H2 microprocessor 1014, as well as a one-third segment of the 120-bit instruction word format employed in the H2 microprocessor 1014. It should be understood that the design of a context-cycling microprocessor according to the present invention is not limited to any particular data/address bit width combination. While the HI/O microprocessor 1012 could also be provided with a Queue memory system like the Queue memory system 1038 for the H2 microprocessor 1014, a Queue memory system is more advantageous for the H2 microprocessor, due to the regularity in which the H2 microprocessor calls routines on a repeated basis.

In order for the HI/O microprocessor 1012 to access either the shared memory system 1016 or the program memory system 1028 of the H2 microprocessor 1014, a registered transceiver 1056 is also connected to the program and data bus 1050. In one embodiment according to the present invention, the registered transceiver is comprised of five 29FCT52 devices from Integrated Device Technology. This particular transceiver has a pair of internal latches which are interconnected front-to-back for storing and controlling the bidirectional flow of data. The HI/O microprocessor 1012 is capable of loading the program memory circuit 1032 of the H2 microprocessor 1014 with a programmed set of instructions through the circuit created by program and data bus 1050, the registered transceiver 1056, the H2.sub.-- HI/O data bus 1058, the data transceiver 1060 and the program data bus 1022, with the addresses being transmitted on the H2.sub.-- HI/O address bus 1054. Similarly, the HI/O microprocessor 1012 is capable of reading input and output signal data stored in the shared data memory circuit 1042 through the circuit created by program and data bus 1050, the registered transceiver 1056, the H2.sub.-- HI/O data bus 1058, the transceiver circuit 1046 and the shared data bus 1062 with the addresses being transmitted on the H2.sub.-- HI/O address bus 1054 (through address decoder/buffer circuit 1044 to shared address bus 1061).

FIG. 1 also shows that another data transceiver 1064 may be connected to the HI/O program and data bus 1050. The transceiver 1064 is used to facilitate external access to the HI/O's program and data bus 1050, such as through the HI/O external memory mapped data bus 1066. For example, such external access may be used for memory mapped devices, such as a debug panel (for reading a key depressed on the panel or writing to an LCD display).

Before proceeding with a further description of the context-cycling processor, a deeper understanding of the bus structure and memory architecture may be helpful. In FIG. 10A a detailed block diagram of the multiplexed program/data bus structure is shown; and in FIG. 10B, a detailed block diagram is shown of the bank switching functionality whereby memory may be rapidly bank switched by changing the value of bits 23 through 20 of internal memory mapped register at local RAM address FA.

Referring to FIG. 10A, the GP1 register and the program counter are multiplexed to supply the data and PC addresses, respectively, to external RAM. Note how the program counters of different contexts 220 and the GP1 registers 222 are ultimately multiplexed through multiplexer 224. The data read from RAM memory 226 is distributed to the opcode latch 228 and the data read latch 230. In this embodiment when the processor is accessing memory in the internal ROM range of program memory (above FFFEO) a value from onboard ROM 232 is substituted as the opcode. Bank switching is implemented in the presently preferred embodiment. Referring to FIG. 10B the circuitry to accomplish this is illustrated. The bank switching information is supplied as the output of multiplexer 224. Bank switching is used to allow quick switching to a different block of memory within the HI/O processor. This allows parallel programs to be available concurrently inside the HI/O processor. To toggle between these two programs all that must change is the 4 bits (bits 20-23) and these bits are added to the upper 4 bits of the program counter of every instruction that runs. By writing to these 4 bits, the system automatically bank switches, allowing the other parallel program to operate. This enhances the speed of the system in a program load situation.

A program and data memory control circuit 1122 is provided for controlling the HI/O private memory system 1048 (shown in phantom in FIG. 2). Similarly, a shared data and H2 program memory control circuit 1124 is provided for controlling both the shared memory system 1016 and the program memory system 1028 of the H2 microprocessor 1014 (shown together in phantom in FIG. 2). In this regard, each of the memory system control signals generated by the HI/O microprocessor 1012 are identified in FIG. 2. The HI/O microprocessor 1012 also includes several other circuits, which are illustrated in FIG. 2, but are best seen in FIG. 3.

Context-Cycling Processor

Referring to FIG. 2, a simplified block diagram of the HI/O microprocessor 1012 is shown. In this regard, the HI/O microprocessor 1012 includes a substantial number and variety of input and output circuits which are embedded into this single chip central processing unit. While the principles of the present invention are not limited to a single chip implementation, the ability to include all of the I/O functionality of the HI/O microprocessor 1012 into a single integrated circuit chip is considered to be advantageous. In one embodiment according to the present invention, the HI/O microprocessor 1012 may be constructed through the use of a large scale Application Specific Integrated Circuit (ASIC). An ASIC is a type of integrated circuit which includes a significant number of logic gates that may be connected together to perform specific circuit functions. For example, the HI/O microprocessor 1012 may be embodied in a 391 pin package, 100K ASIC device by LSI Logic Corp., Milpitas, Calif. This particular ASIC device contains well over 100,000 gates that may be combined together to form a variety of different circuits. However, it should be appreciated that other suitable integrated circuit technologies may be employed to construct HI/O microprocessor 1012 in the appropriate application, including a fully custom integration.

With respect to its input/output circuit capabilities, the HI/O microprocessor 1012 includes a set of four "small computer system interface" SCSI circuits 1100-1106. A SCSI circuit is a high speed parallel interface that generally conforms to the X3T9.2 standard promulgated by the Committee of the American National Standards Institute (ANSI). Each of these SCSI circuits may be used to connect the HI/O microprocessor 1012 to a number of external peripheral devices, such as magnetic disk drives, optical disk drives and printers. The HI/O microprocessor 1012 also includes a set of ten serial input/output circuits 1108 for 8-bit serial communication with such devices as modems, a mouse, keyboards, printers and even other computers. These serial circuits may also be used to gather input signals from and distribute output signals to a network of remote field computer units, such as the type of multitiered network described in the Glaser et al., U.S. patent application Ser. No. 07/864,931, filed on Mar. 31, 1992, entitled "Process Control Interface System Having Triply Redundant Remote Field Units."

The HI/O microprocessor 1012 further includes a set of six serial and shared memory management unit (SASMMU) circuits 1110. The SASMMU circuits 1110 are parallel-to-serial and serial-to-parallel converters for transmitting and receiving information at a serial baud rate of 28.782 mega baud. At this extremely high baud rate, a 40-bit word will be received every 1.4 microseconds. Separate SASMMU circuits 1110 are used for transmitting and receiving in order to maximize the information transfer capabilities of the HI/O microprocessor 1012. Details of these circuits are shown in FIGS. 15A-15E.

Referring to FIGS. 15A-15E, the SASMMU circuits are seen in more detail. FIG. 15A shows a SASMMU input register 112 and a SASMMU output register 114. The interrupt multiplexers for a SASMMU receiver are shown in FIG. 15B at 116. The interrupt multiplexer for a SASMMU transmitter is shown at 118 in FIG. 15C. Note that program data bits 37 and 38 of a COMBO instruction type are used (for both transmitter and receiver) to select what the interrupt source will be until changed again. (A COMBO instruction is one of several different types of opcode instructions described below.)

The context cycling processor assigns priorities to different contexts to determine which context should be run next. The different priorities ensure that no data are lost. The SASMMU contexts are ordinarily assigned a very high priority because of the very high serial baud rate. However, the SASMMU contexts can programmatically reduce their effective priority to allow other lower priority contexts to utilize processor cycles.

FIG. 15D shows how SASMMU contexts can effectively lower their priority by choosing an interrupt source referred to as "no high priority." Normally, SASMMUs are considered very high priority (due to the very high data transfer rates). By running SASMMU contexts, other contexts of lower priority can be effectively blocked from performing any operations. To handle this, the SASMMU circuits are capable of selecting a lower priority operation when low data rate operations are being performed. The logic circuitry of FIG. 15D shows how this no high priority signal is generated. FIG. 15E shows how one of the CP bits (context purpose bits) of the SASMMU context is generated. In this case CP bit 19 is illustrated. This is the end-of-message bit. Two successive stop bits generates this EOM signal. The end-of-message signal can be used as an interrupt, or as a CP bit. The CP bits of a context are generally used for configuration of hardware assets associated with that particular context.

Active Redundancy and Arbitration

When the common core computer 1000 is used in a process control computer, it is preferred that the process control computer actually comprise a set of three actively redundant common core computers, which make independent process control decisions on mutually exchanged input information from the field. In such process control computers, the SASMMU circuits 1110 may advantageously be used to provide communication between each of the redundant common core computers. To support redundancy, a substantial number of input signals may need to be mutually exchanged between the redundant common core computers in a very limited amount of time during a precise time interval in an overall process control cycle. For example, in one preferred method of process control, a 1 second cycle is provided, during which all of the following must occur: receiving and mutually exchanging over 1,000 input signals, arbitrating between these input signals, making process control decisions based upon the arbitrated input signal values, mutually exchanging the output signal values which represent these process control decisions and transmitting all of the necessary output signals to the field. While the H2 microprocessor 1014 is preferably used to make the needed process control decisions, the HI/O microprocessor 1012 is also capable of being programmed to execute the instructions for these types of decisions. For example, while the H2 microprocessor could be programmed to arbitrate between input signals received from sensors in the field, it is preferred that the HI/O microprocessor 1012 be utilized for this purpose, as its hardware-based arbitration is capable of faster execution. The arbitration circuitry to accomplish this is shown in FIG. 16.

Referring to FIG. 16, the arbitration circuitry arbitrates data from triply redundant computers, each supplying a separate data word. In FIG. 16 these are depicted as word 1, word 2 and word 3, as shown at 120. Ideally, all three word values should be the same, if all three computers and data sources are performing properly. If all three word values are not the same, then the arbitration selector circuitry 122 determines which computer and/or data source is out of tolerance. A process control system will generally operate on both analog and digital signals. The analog signals are first converted to digital signals through appropriate analog to digital conversion circuitry. Nevertheless, the converted values still represent analog values. In FIG. 16 there is a separate analog path 124 and digital path 126. Analog values (digitally represented) are fed to processor block 128 whereas digital values are fed to processor block 130. Processor block 128 compares each of the word 1, word 2 and word 3 values with one another. Processor block 130 performs a similar function using AND gates and OR gates to determine the lowest signal of each bit position on line 132 and the digitally triple arbitrated value of each bit position on line 134. A bit by bit compare is performed by the arbitration circuitry and the selector circuitry 122 arbitrates based on 2 out of 3 wins. Selector circuitry 122 can also be set to arbitrate to take the lowest digital or analog value. In some cases the lowest digital value is considered the best default value to select (as it typically will represent a valve in the open or closed state that is preferred when there has been a system malfunction). The analog/digital mode of the incoming data is set on line 136. Because analog values can be expressed as either 40 bit words or 16 bit words, a bit compensation circuit 138 is provided to fill out 16 bit words into their 40 bit equivalent.

The data Table I lists the result for each different possible input combination to selector circuitry 122. The result is used by the system to indicate when the arbitration circuitry has detected a disagreement.

                                      TABLE I
    __________________________________________________________________________
         Word1
             Word2
                 Word3
         &   &   &   Word1
                         Word2
                             Word3
         Word2
             Word3
                 Word1
                     >   >   >   Own/
    3/2/1/10
         Agree
             Agree
                 Agree
                     Word2
                         Word3
                             Word1
                                 Lowest/
    In-Service
         ?   ?   ?   ?   ?   ?   Highest
                                     Answer
    __________________________________________________________________________
    0    x   x   x   x   x   x   x   word1
    1    x   x   x   x   x   x   x   word1
    2    0   x   x   0   x   x   own word1
    2    0   x   x   0   x   x   lowest
                                     word1
    2    0   x   x   0   x   x   high
                                     word2
    2    0   x   x   1   x   x   own word1
    2    0   x   x   1   x   x   lowest
                                     word2
    2    0   x   x   1   x   x   high
                                     word1
    2    1   x   x   x   x   x   x   word1
    3    0   0   0   x   x   x   own word1
    3    0   0   0   0   0   1   lowest
                                     word1
    3    0   0   0   0   0   1   highest
                                     word3
    3    0   0   0   0   1   0   lowest
                                     word3
    3    0   0   0   0   1   0   highest
                                     word2
    3    0   0   0   0   1   1   lowest
                                     word1
    3    0   0   0   0   1   1   highest
                                     word2
    3    0   0   0   1   1   0   lowest
                                     word2
    3    0   0   0   1   0   0   highest
                                     word1
    3    0   0   0   1   0   1   lowest
                                     word2
    3    0   0   0   1   0   1   highest
                                     word3
    3    0   0   0   1   1   0   lowest
                                     word3
    3    0   0   0   1   1   0   highest
                                     word1
    3    0   0   1   x   x   x   x   word1
    3    0   1   x   x   x   x   x   word2
    3    1   x   x   x   x   x   x   word1
    __________________________________________________________________________

                  TABLE
    ______________________________________
    COMBO instruction type:
    b39     INST TYPE Instruction Type. "0" indicates the
    b38 . . . 37
            INT CND   instruction type is COMBO Interrupt
                      Condition. Selects, via context's interrupt
                      mux, the 1 (of 4) interrupt condition requisite
                      for context to execute next instruction.
                      Number of conditions (up to 4) along with
                      type of conditions, vary with context type.
                      Selections are:
                      CD0 (condition0 of interrupt mux "Always"
                      for all 24 contexts)
                      CD1 (condition1 of interrupt mux; condition
                      varies based on context)
                      CD2 (condition2 of interrupt mux; condition
                      varies based on context)
                      CD3 (condition3 of interrupt mux; condition
                      varies based on context)
    b36 . . . 35
            JMP TGT   Jump Target. Value with which context's PC
                      will be updated at end of instruction period
                      in which this opcode is executed. Selections
                      are:
                      PC + 1 (PC of current instruction + 1)
                      PC + 1 + IM (same as previous + PIMMED
                      value, located at b7 . . . 0 of the opcode,
                      PIMMED to be interpreted as 1 bit sign, 7
                      bits magnitude)
                      GP3 (bits 34 . . . 15 of value in context's
                      GP3 register RAM location)
                      0 (Zero)
    b34 . . . 33
            COMP S2   Comparitor Source2 operand. Selections are:
                      GP2 (value in context's GP2 register RAM
                      location)
                      IMG1 (value of PIMMED/GP1 bus - the
                      value on this 20-bit bus is equal to the
                      right-justified value of the PIMMED field, as
                      8 bits integer, unless PIMMED = FFh, where
                      the bus assumes the value of GP1)
                      GP3 (value in context's GP3 register RAM
                      location)
                      0 (Zero)
    b32 . . 30
            COMP OP   Comparitor Operation, in form (COMP
                      S1.COMP OP.COMP S2, like
                      GP2.GTE.LRR). Selections are:
                      EQ (equal)
                      NEQ (not equal)
                      GT (greater than)
                      GTE (greater than or equal)
                      LT (less than)
                      LTE (less than or equal)
                      S1@S2T (bit of comparitor source1 operand,
                      at bit position equivalent to comparitor
                      source2 operand integer value, is TRUE)
                      S1@S2F (bit of comparitor source1 operand,
                      at bit position equivalent to comparitor
                      source2 operand integer value, is FALSE)
    b29 . . . 28
            COMP S1   Comparitor Source1 operand. Selections are:
                      GP2 (value in context's GP2 register RAM
                      location)
                      LRR (value on multiplexed Local RAM/
                      (mmed) Registers bus)
                      MVB (value on Move Bus)
                      MMO (value on Main Math Output bus)
    b27 . . . 25
            MMU S2    Main Math Unit Source2 operand. Selections
                      are:
                      GP1 (value in context's GP1 register RAM
                      location)
                      GP2 (value in context's GP2 register RAM
                      location)
                      GP3 (value in context's GP3 register RAM
                      location)
                      LRR (value on multiplexed Local RAM/
                      (mmed) Registers bus)
                      +1 (integer value of +1)
                      1's (all 40 bits of operand forced to 1's)
                      PIMMED (8-bit Program Immediate field of
                      the present opcode, used as integer)
                      0 (Zero)
    b24 . . . 21
            MMU OP    Main Math Unit Operation, in form (MMU
                      S1.MMU OP.MMU S2, like
                      GP1.EXOR.1's). Selections are:
                      AND (logical AND)
                      OR (logical OR)
                      EXOR (logical EXOR)
                      + (addition)
                      - (subtraction)
                      * (integer 20-bit by 20-bit multiply; result
                      MSB .fwdarw. LSB will be in bit positions
                      14 . . . 0, 39 . . . 15.)
                      / (software assisted, successive approxima-
                      tion divide - 40-bit numerator, 20-bit
                      denominator, 20 bit quotient; numerator
                      operand selected as COMP S2, denominator
                      operand as MMU S2, and interim quotient as
                      MMU S1. The PIMMED value, interpreted
                      as an 8-bit, positive integer, will be used to
                      point to each bit position of the temporary
                      quotient to be calculated)
                      S1 IF CO ELSE S2 (MMU Source1 operand
                      will be the MMU output IF the output of the
                      comparitor is TRUE, else the value of the
                      MMU Source2 operand will be the output)
                      S1 BSET@S2 (value of MMU Source1
                      operand with bit set at position pointed to by
                      integer value of MMU Source2 operand
                      value)
                      S1 BCLR@52 (value of MMU Source1
                      operand with bit cleared at position pointed
                      to by integer value of MMU Source2
                      operand value)
                      S1 BSUB@S2 (value of MMU Source1
                      operand with bit substituted with at position
                      pointed to by integer value of MMU Source2
                      operand value)
                      ROTATE/MERGE 8 (value of rotated
                      Source1 operand merged with Source2
                      operand on byte boundaries. Bits 7 . . . 5
                      of the PIMMED field furnish the code for 1
                      of 8 discrete rotation amounts. Bits 4 . . . 0
                      of the PIMMED field are the byte select bits,
                      a "1" translated as "from rotated Source1
                      operand", "0" as "from Source2 operand")
                      CHKSUM (new checksum calculation with
                      the Source1 operand as the input data value
                      and the Source2 operand as the previous
                      checksum value)
                      ENCR/DECR (encrypt/decrypt data with the
                      Source1 operand as the data to be encrypted/
                      decrypted, and the Source2 operand as the
                      encryption/decryption dynamic key to use,
                      with the static key provided by a Local
                      RAM/(mmed) register)
                      DYNAMIC KEY (hardware permute the
                      Dynamic Key value, provided as the Source1
                      operand)
                      PARITY (using Source1 operand only, exor
                      bits 8 . . . 0, and substitute this 1 bit value
                      for bit 7 of the Source1 operand, passing all
                      other 39 bits of the Source1 operand un-
                      altered)
    b20 . . . 18
            MMU S1    Main Math Unit Source1 operand. Selections
                      are:
                      GP1 (value in context's GP1 register RAM
                      location)
                      GP2 (value in context's GP2 register RAM
                      location)
                      GP3 (value in context's GP3 register RAM
                      location)
                      LRR (value on multiplexed Local RAM/
                      (mmed) Registers bus)
                      CP (value in context's "Context Purpose",
                      CP, register)
                      MVBUS (value on the Move Bus)
                      PC + 1 (PC of current instruction + 1)
                      RAWIN (raw, un-autodecrypted data from
                      context's input register)
    b17     GP3       GP3 update value. Selections are:
                      NO/-E (no change to context's GP3 value)
                      MMO (update context's GP3 value to that on
                      Main Math Output bus)
    b16 . . . 15
            GP2       GP2 update value. Selections are:
                      NO/-E (no change to context's GP2 value)
                      MMO (update context's GP2 value with bits
                      34 . . . 15 of the value on the Main Math
                      Output bus)
                      -1 (decrement context's current GP2 value
                      by 1)
                      MVB (update context's GP2 value with bits
                      34 . . . 15 of the value on the Move Bus)
    b14 . . . 13
            GP1       GP1 update value. Selections are:
                      NO/-E (no change to context's GP1 value)
                      MMO (update context's GP1 value with bits
                      34 . . . 15 of the value on the Main Math
                      Output bus)
                      +1 (increment context's current GP1 value
                      by 1)
                      LRR (update context's GP1 value with bits
                      34 . . . 15 of the value on the multiplexed
                      Local RAM/(mmed) Registers bus)
    b12 . . . 8
            MOVE OPT. Move Bus Option. This portion of the
                      opcode handles 4 functions simultaneously,
                      in the form W.X.Y.Z, where W is the source
                      operand to be placed on the Move Bus, X is
                      the destination of the Move Bus value, Y is
                      the Local RAM/(mmed) Register update
                      source, and Z is the CP register update
                      source. Abbreviations are: DM - Data
                      Memory, DI - Context's Default Input
                      Register, DO - Context's Default Output
                      Register, LR - multiplexed Local RAM/
                      (mmed) Registers bus, G3 - Context's GP3
                      value, MB - Move Bus, NC - No Change,
                      and MM - Main Math Output bus. The 32
                      selections are as follows:
                       0. DM.MB.NC.NC
                       1. DM.MB.MM.NC
                       2. DM.MB.MB.NC
                       3. 


DM.DO.NC.NC
                       4. DM.DO.MM.NC
                       5. DM.DO.MB.NC
                       6. DM.MB.NC.MM
                       7. DM.DO.NC.MM
                       8. DI.DM.NC.MM
                       9. DI.MB.NC.NC
                      10. DI.MB.MM.NC
                      11. DI.MB.MB.NC
                      12. DI.DM.NC.NC
                      13. DI.DM.MM.NC
                      14. DI.DM.MB.NC
                      15. LR.MB.NC.NC
                      16. LR.MB.MM.NC
                      17. LR.DM.NC.NC
                      18. LR.DM.MM.NC
                      19. LR.DO.NC.NC
                      20. LR.DO.MM.NC
                      21. MM.DO.NC.NC
                      22. MM.DO.MM.NC
                      23. DI.MB.NC.MM
                      24. G3.DM.NC.MM
                      25. G3.DM.NC.NC
                      26. G3.DM.MM.NC
                      27. G3.MB.MB.NC
                      28. G3.DO.NC.NC
                      29. G3.DO.MM.NC
                      30. G3.DO.MB.NC
                      31. G3.DO.NC.MM
    b7 . . . 0
            PIMMED    Program Immediate field. 8 bits used in a
                      variety of ways, as explained above.
    Long Immediate Math (LIM) instruction type:
    b39 . . . 38
            INST TYPE Instruction Type. "10" (binary) indicates the
                      instruction type is Long Immediate Math.
    b37     JMP TGT   Jump Target. Value with which context's PC
                      will be updated at end of instruction period
                      in which this opcode is executed. Selections
                      are:
                      PC + 1 (PC of current instruction + 1)
                      MMO (bits 34 . . . 15 of the value on the
                      Main Math Output bus)
    b36 . . . 34
            MMU S2    Main Math Unit Source2 operand. Selections
                      are:
                      GP1 (value in context's GP1 register RAM
                      location)
                      GP2 (value in context's GP2 register RAM
                      location)
                      GP3 (value in context's GP3 register RAM
                      location)
                      LINT0 (20 bits of Long Immediate field
                      placed into bit positions 34 . . . 15, and
                      padded with zeros)
                      LINT1 (20 bits of Long Immediate field
                      placed into bit positions 34 . . . 15, and
                      padded with ones)
                      LFRC0 (20 bits of Long Immediate field
                      placed into bit positions 39 . . . 35 and
                      14 . . . 0, and padded with zeros)
                      LFRC1 (20 bits of Long Immediate field
                      placed into bit positions 39 . . . 35 and
                      14 . . . 0, and padded with ones)
                      0 (Zero)
    b33 . . . 31
            MMU OP    Main Math Unit Operation, in form (MMU
                      S1.MMU OP.MMU S2, like
                      GP1.OR.LFRC0). Selections are:
                      AND (logical AND)
                      OR (logical OR)
                      EXOR (logical EXOR)
                      + (addition)
                      - (subtraction)
                      * (integer 20-bit by 20-bit multiply; result
                      MSB .fwdarw. LSB will be in bit positions
                      14 . . . 0, 39 . . . 15.)
                      ROTATE/MERGE 40 (value of rotated
                      Source1 operand merged with Source2
                      operand on 4-bit, nibble boundaries, with
                      LS nibble defined as bit positions 2 . . . 0
                      including bit 39 as the LS bit. Bits 15 . . . 10
                      of the Long Immediate field, LIMMED,
                      furnish the continuous, right-rotation amount
                      (rotated right 0 to 63 times). Bits 9 . . . 0 of
                      the LIMMED field are the nibble select bits,
                      a "1" translated as "from rotated Source1
                      operand", a "0" as "from Source2 operand")
                      S2 (the value of the Source2 operand is out-
                      put)
    b30 . . . 28
            MMU S1    Main Math Unit Source1 operand. Selections
                      are:
                      GP1 (value in context's GP1 register RAM
                      location)
                      GP2 (value in context's GP2 register RAM
                      location)
                      GP3 (value in context's GP3 register RAM
                      location)
                      LINT0 (20 bits of Long Immediate field
                      placed into bit positions 34 . . . 15, and
                      padded with zeros)
                      CP (value in context's "Context Purpose",
                      CP, register)
                      MVBUS (value on the Move Bus)
                      PC + 1 (PC of current instruction + 1)
                      RAWIN (raw, un-autodecrypted data from
                      context's input register)
    b27 . . . 26
            GP3       GP3 update value. Selections are:
                      NO/-E (no change to context's GP3 value)
                      MMO (update context's GP3 value to that on
                      Main Math Output bus)
                      PC + 1 (PC of current instruction + 1)
                      MVBUS (value on the Move Bus)
    b25     GP2       GP2 update value. Selections are:
                      NO/-E (no change to context's GP2 value)
                      MMO (update context's GP2 value with bits
                      34 . . . 15 of the value on the Main Math
                      Output bus)
    b24     GP1       GP1 update value. Selections are:
                      NO/-E (no change to context's GP1 value)
                      MMO (update context's GP1 value with bits
                      34 . . . 15 of the value on the Main Math
                      Output bus)
    b23 . . . 20
            MOVE OPT. Move Bus Option. This portion of the
                      opcode handles 3 functions simultaneously,
                      in the form P.Q.R, where P is the source
                      operand to be placed on the Move Bus, Q is
                      the destination of the Move Bus value, and R
                      is the CP register update source. Abbrevia-
                      tions are: DM - Data Memory, DI -
                      Context's Default Input Register, DO -
                      Context's Default Output Register, G3 -
                      Context's GP3 value, MB - Move Bus, NC -
                      No Change, and MM - Main Math Output
                      bus. The 16 selections are as follows:
                       0. DM.MB.NC
                       1. DM.DO.NC
                       2. DI.MB.NC
                       3. DI.DM.NC
                       4. DI.DO.NC
                       5. MM.DO.NC
                       6. G3.DM.NC
                       7. G3.DO.NC
                       8. DM.MB.MM
                       9. DM.DO.MM
                      10. DI.MB.MM
                      11. DI.DM.MM
                      12. DI.DO.MM
                      13. MM.DO.MM
                      14. G3.DM.MM
                      15. G3.DO.MM
    b19 . . . 0
            LIMMED    Long Immediate field. 20 bits used in a
                      variety of ways, as explained above.
    Long Immediate Compare (LIC) instruction type:
    b39 . . . 38
            INST TYPE Instruction Type. "11" (binary) indicates
                      the instruction type is Long Immediate
                      Compare.
    b37 . . . 36
            JMP TGT   Jump Target. Value with which context's PC
                      will be updated at end of instruction
                      period in which this opcode is executed.
                      Selections are:



                      PC + 1 (PC of current instruction + 1)
                      PC + 1 + IM (same as previous + PIMMED
                      value, located at b27 . . . 20 of the opcode,
                      PIMMED to be interpreted as 1 bit sign, 7
                      bits magnitude)
                      GP3 (bits 34 . . . 15 of value in context's
                      GP3 register RAM location)
                      LI (value of 20-bit Long Immediate field)
    b35 . . . 34
            COMP S2   Comparitor Source2 operand. Selections are:
                      GP2 (value in context's GP2 register RAM
                      location)
                      IMG1 (value of PIMMED/GP1 bus - the
                      value on this 20-bit bus is equal to the value
                      of the PIMMED field, as 8 bits integer,
                      unless PIMMED = FFh, where the bus
                      assumes the value of GP1)
                      GP3 (value in context's GP3 register RAM
                      location)
                      0 (Zero)
    b33 . . . 31
            COMP OP   Comparitor Operation, in form (COMP
                      S1.COMP OP.COMP S2, like
                      GP2.GTE.LRR). Selections are:
                      EQ (equal)
                      NEQ (not equal)
                      GT (greater than)
                      GTE (greater than or equal)
                      LT (less than)
                      LTE (less than or equal)
                      S1@S2T (bit of comparitor source1 operand,
                      at bit position equivalent to comparitor
                      source2 operand integer value1 is TRUE)
                      S1@52F (bit of comparitor source1 operand,
                      at bit position equivalent to comparitor
                      source2 operand integer value, is FALSE)
    b30 . . . 29
            COMP S1   Comparitor Source1 operand. Selections are:
                      GP2 (value in context's GP2 register RAM
                      location)
                      LRR (value on multiplexed Local RAM/
                      (mmed) Registers bus)
                      CP (value in context's "Context Purpose",
                      CP, register)
                      LINT0 (20 bits of Long Immediate field
                      placed into bit positions 34 . . . 15, and
                      padded with zeros)
    b28     LRR       Local RAM/(mmed) Registers update value.
                      Selections are:
                      NO/-E (no change to addressed Local RAM/
                      (mmed) Register's value)
                      LINT0 (20 bits of Long Immediate field
                      placed into bit positions 34 . . . 15, and
                      padded with zeros)
    b27 . . . 20
            PIMMED    Program Immediate field. 8 bits used in a
                      variety of ways, as explained above.
    b19 . . . 0
            LIMMED    Long Immediate field. 20 bits used in a
                      variety of ways, as explained above.
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