Hardware-configured operating system kernel having a parallel-searchable event queue for a multitasking processor5465335Abstract A multitasking data processing system is provided with a hardware-configured operating system kernel. The system includes a processor queue that includes a plurality of word stores, each word store storing a task name, in execution priority order, that is ready for processing. An event queue in the kernel includes a plurality of word stores for storing task names that await the occurrence of an event to be placed in the processor queue. When an associated processor signals the occurrence of an event, matching logic searches all word stores in the event queue, in parallel, to find a task associated with the signalled event and then transfers the task to the processor queue. Shift logic is also provided for simultaneously transferring a plurality of task names, in parallel, in the processor queue to make room for a task name transferred from the event queue. Claims I claim: Description FIELD OF THE INVENTION
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Inputs to EXEC Module 12
CS - chip select
R/W - read/not (write) line
uPAddr (0-7) - address lines
SCLK - EXEC system clock (not shown)
NRST - External Reset line
NTST - Test line (for test mode operation)
Bidirectional lines to EXEC Module 12
uP Data (0-15) - data lines
Outputs from EXEC Module 12
NDTACK - data transfer acknowledge
(asynchronous acknowledge)
NINT - interrupt line to CPU
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The following signals go between Queue State Machine 16 and each of queues 20, 22 AND 24 via bus 32 (but are not specifically illustrated in FIG. 1). D (0-7 )--EXEC Internal Data Bus ADDR (0-15)--EXEC Internal Address Bus CMD (0-3)--Command Lines to Queue system 18 QEN (0-3)--Queue Command Enables (one for each queue and array) There are 256 queue elements in each queue. Each queue element stores two, 8-bit words. Therefore, 8 data lines and 9 address lines are required to access any word in any queue. The ninth address line is the CMD(3) signal line. CMD(0-2) are used to specify which of 8 different commands will be performed. CMD(3) determines which of two queue element words the operation will be performed on. QEN(0-3) lines are used to enable only one of the queues. Commands can be sent to a particular queue to execute arithmetic comparisons. These arithmetic comparisons are done on all queue elements in parallel. The result of such comparisons is used to make parallel shifts in the queue in order to insert or delete items. This yields a significant speed improvement over manipulating these data as is typically done with pointers into a list. The following additional signals run from Queue State Machine 16 to the Event Count Registers 26 over Bus 32 (not specifically shown in FIG. 1) ECOP (0-1)--Event Counter Operations ECOC--Event Counter Output Control ECCLK--Event Counter Clock ECLR--Event Register Array Clear EOC--Event Register Output Control These signals are used to control 256 8-bit registers in Event count registers 26 and a counter therein which can be loaded with any of these values and incremented or decremented. Each register location in Event Count registers 26 is associated with a correspondingly numbered event. When a "Signal of a particular event occurs, the appropriate register value is read, incremented, and re-written. Likewise, when a Wait is executed on a particular event, the appropriate register's value is read, decremented, and re-written. QUEUE STRUCTURES Turning now to FIG. 2, the basic structure of CPU queue 20 is illustrated. It will be recalled, that the hardware structure of each queue is identical. TCB names are stored in CPU queue 20 in priority order. Rather than a assigning a separate priority value to a TCB name, it has been determined that substantial storage area can be conserved by assigning as a TCB name, the actual priority value assigned to the TCB. Thus, a TCB having the name 0 has the highest priority value and is referred to by an address indication in EXEC module 12 by an all-0s address. Other TCBs of lower priority are similarly denoted. CPU queue 20 contains a plurality of queue elements 35. For illustration purposes, CPU queue 20 is shown with only four queue elements, instead of the 256 which can be used with an eight bit address. The structure of a queue element is shown in FIG. 3 and will be described in detail below. Data lines D(0-7) carry data into and out of data ports in each of queue elements 35 (see FIG. 2). CMD(0-3) are address lines that are used to specify which of eight different commands will be performed by each queue element 35. The CMD(3) line provides a level which determines which of two words in a queue element 35 the operation will be performed upon. QEN(0) is an enable line and enables one of the three queues (20, 22, 24). An address bus ADDR (0-7) is decoded by address decoder 36 and is used to select an individual queue element 35 (via an output on cable 38 which contains 256 separate word lines). Each of the word lines in word bus 38 is connected to an individual queue element 35 so as to enable logical operations in any one chosen queue element in accordance with a received address into address decoder 36. Such connections are not shown in FIG. 2 to avoid over-complication of the diagram. Address bus ADDR (0-7) also carries address information back to queue state machine 16 during comparison operations. During such an operation, the address of a queue element 35 that meets a comparison criteria is returned on address bus ADDR (0-7). A resolver/encoder 40 resolves the case where more than one queue element 35 meets a comparison criteria. For instance, if a command is issued to return an address of a queue element that contains "numeral 0" and all queue elements contain "0", then resolver encoder 40 causes address bus ADDR 0-7 to return the lowest numbered queue location to queue state machine 16. In the example given, resolver encoder 40 would return location 1 on address bus ADDR (0-7). Each queue element 35 contains two words of information pertaining to a task. In general, queue element 35 at position 1 in CPU queue 20 will contain two words pertaining to the highest-priority task awaiting action. Those words are the TCB name having the lowest numerical value (priority) and the name of the event that caused the TCB name to be moved into CPU queue 20. Queue elements at position 3, 4 etc. will contain TCB names with lower priority (and higher numerical value). There are two local buses 42 and 44 that connect each queue element 35 to its next higher-numbered neighbor queue element and are used when inserting or deleting items from a queue. Each queue element 35 has two comparison operations incorporated into its structure, the results of which are manifest at GT output 46 and M output 48. The signals "GT" and "M" stand for "greater than" and "match", respectively. In brief, when data is applied to data bus D(0-7), each queue element 35 determines whether a data word contained within it matches in value or is greater in value in relation to the applied data word. If it finds that its stored word value is greater than the data bus value, then an output is impressed on output GT line 46. If a match is found between the values, M output 48 is energized. A multiplexer 50 is connected to all queue elements 35 and is controlled to select either all "greater than" outputs 46 from queue elements 35 or all "match" outputs 48 from queue elements 35. In the example shown in FIG. 2, multiplexer 50 provides four outputs from the selected greater than or match outputs from the four queue elements 35 shown. Which group of signals is selected is dependent on whether it is desired to know the lowest-numbered queue element 35 that matches the input data or the lowest-numbered queue element 35 that holds a value greater than the input data. QUEUE ELEMENT STRUCTURE Turning now to FIG. 3, the structure of a queue element 35 is illustrated. In each queue element 35, a pair of word stores 52 and 54 hold two 8-bit values, i.e., word A and word B. In addition, each word store contains the necessary logic to enable a comparison to be made between an incoming data word and the word contained therein. Details of that logic structure are shown in FIG. 4 and will be further considered below. A queue element 35 holds the following information:
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Queue Name Word A Word B
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CPU Queue Task Name/Priority
Event Case
Event Queue Task Name/Priority
Event Name
Delay Queue Delay Value Event Name
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The Task name/priority is manifest by a TCB name whose value is directly related to its priority (as above described). An "Event Case" is the event name value that occurred that caused the task denoted by a TCB in word A, to be moved into CPU queue 20. An "Event Name" is a name or value given to a specific action within microprocessor 10. For instance, an event name may be a value assigned to a hardware interrupt, an I/O interrupt, etc. A "Delay Value" is a value assigned to a time before an event is to occur. Each word store 52, 54 has a GT and M output that is applied, respectively, to multiplexers 56 and 58. The CMD (3) line is applied to multiplexers 56 and 58 and its level selects which word (word A or word B) is compared to provide the desired output on either GT line 46 or M line 48. LAST busses 42 and 44 and NEXT busses 42' and 44' are used to shift words between queue elements 35. Each word store 52, 54 has its own LAST and NEXT bus that allows the contents of an entire queue element 35 to be shifted in one parallel operation. The contents of a word store 52 and a word store 54 always occupy the same queue element 35 together. WORD STORE STRUCTURE In FIG. 4, the details of a word store 52 is illustrated. A multiplexer 70 receives four sources of input data for word store 52 (word A). Those sources are as follows: LAST A(0-7)--Contents of next lower Queue Element Word D(0-7)--EXEC Internal Data Bus NEXT A(0-7)--Contents of next higher Queue element Word A VDD--used to precharge BIT and nBIT (complement) lines during a comparison in a content-addressable memory 72. Content addressable memory (CAM) 72 contains eight, parallel connected bit cells for word A. Each bit cell provides both true and complement outputs for its respective bit. A pair of multiplexers 74 and 76 enable a comparison operation to be carried out with respect to the 8-bit word held in CAM 72. The details of a one-bit CAM cell are shown in FIG. 5. Bit lines 82 and 84 are separate, but the word lines 81 and 83 of all eight one-bit CAM cells are tied together (not shown) to form a common 8-bit word line. The basic memory cell is a CMOS flip-flop 85 of known structure. To write into cell 85, data is placed on bit line 82 and complement data is placed on complement bit line 84. Then, word lines 81, 83 are asserted causing cell 80 to switch in accordance with the applied inputs. A read operation commences by precharging bit and bit complement lines 82 and 84. Word lines 81, 83 are then asserted and bit line 82 manifests the value of the cell. For a comparison operation, true data against which comparison is to be made is applied to complementary bit line 84 and complement data is placed on bit line 82. If the applied data matches that in cell 85, then a match transistor 86 remains in a nonconductive state, thereby enabling match line 88 to be unaffected by the state in cell 80. There is one match line 88 in each memory cell. Returning to FIG. 4, a queue element logic module 73 receives a plurality of commands over CMD(0-2) lines decodes each command using wired logic and accordingly energizes one or more of its output lines S1-S5, E and W. The output lines from queue element logic module 73 are applied to multiplexers 70, 74, 75, content addressable word memory 72 and a de-multiplexer 76 to enable a received command to be performed. A comparator 77 examines the Match line outputs from CAM 72 and data inputs appearing on data bus D(0-7) to determine if received data has a greater value than that stored in word store 72. Comparator 77 includes an exclusive NOR input stage (not shown) which reconstructs the stored data word from the Match line outputs and enables a subsequent magnitude comparison of the input values. If the input data is less in value than the stored word, the GT output from comparator 77 is asserted. If the input data is equal in value to the stored word, AND gate 78 asserts its M output. QUEUE COMMANDS Each word store 52/54 responds to the following commands: Match=--return highest-numbered location containing the compared word Match>--return highest-numbered location containing the next higher value than the compared word SR--shift contents of queue right (to next higher-numbered location) SL--shift contents of queue left (to next lower-numbered location) RD--read contents of addressed Word Store onto D(0-7) LD--load D(0-7) into addressed Word Store Init--initialize all queue element words to value=all 1's. The "Match" commands are comparison commands and are executed in every queue element in a queue with respect to a selected word store (word A or word B). The RD and LD commands are only executed on one addressed word in a queue. The SR and SL commands both contain addresses which indicate a queue element word store from which data shifting is to occur. Thus, SR and SL shift commands only execute within queue elements whose address location is equal to or greater than the specified address. The selective shift operation is enabled by feeding the specified address from Queue State machine 16 to address decoder 36 (FIG. 2) in the respective queue. Address decoder 36 responds to the address by activating the required word lines on bus 38 which feed into each queue element (e.g., Word (0) which feeds into queue element logic module 73 in FIG. 4). The Init command is used to initialize all word stores in a queue to the 1 state. This value indicates that a queue element is empty. Returning to FIG. 4, the operations of Word store 52 in response to the Match =, RD, LD and SR commands will be considered. The Match =command is initiated by appropriate values being emplaced on CMD(0-2) and QEN(0) lines flowing into queue element logic module 77. Those values indicate a Match =command for the specific queue in which word store 52 is present. The data value to be matched is presented to word store 52 on the D(0-7) lines from the data bus. Queue element logic module 73 activates output signals S1 and S2 to cause multiplexers 70 to pass the D(0-7) inputs to multiplexers 74, 75. Signal S3 from queue element logic module 73 is asserted and selects D(0-7) to flow to NBIT(0-7) input to word store 72. Signal S3 further causes the complement of D(0-7) to flow to the BIT(0-7) input to word store 72. If D(0-7) matches the value held in word store 72, resulting outputs on the Match lines cause AND gate 78 to assert Match output M. Assume now that a Read Contents (RD) instruction appears over the CMD(0-2) lines accompanied by a QEN(0) enable signal. Queue element logic module 73 interprets these levels as an RD-A (read) word A command. An applied level to word(O) input to queue element logic module 73 indicates that this particular queue element's word A will be read onto data bus D(0-7). The read operation is initiated by pre-charging (raising to the logical 1 state) the bit lines to each bit cell in word store 72. This is accomplished by tri-stating outputs from multiplexers 74 and 76 with an assertion of the E line from queue element logic module 73. The word line to each bit cell in word store 72 is then asserted and the 8-bit values stored therein are read onto data bus D(0-7) through demultiplexer 76 under control of signals S4 and S5 from queue element logic module 73. A Load (LD) command is commenced by command values applied onto CMD(0-2) inputs to queue element logic module 73, accompanied by a QEN(0) enable signal. An assertion of the word(O) input to queue element logic module 73 indicates that this particular queue element word A will be loaded from data bus D(0-7). In response to the LD command, queue element logic module 73 asserts signals S1 and S2 to multiplexer 70 which, in turn, causes the D(0-7) inputs to be connected to the input of multiplexers 74 and 75. Levels asserted on the S3 and S4 outputs from queue element logic module 73 then select the data values D(0-7) and their complements to be connected to bit (0-7) and NBIT (0-7) inputs to word store 72, respectively. Word line W from queue element logic module 73 is then asserted and causes storage of the data values into word store 72. To accomplish a Shift Right command (SR), the CMD(0-2) lines are asserted with the proper command values accompanied by an enable signal on QEN(0). Word line word (0) is asserted indicating that this particular queue element word A will be part of a partial or total queue position shift. An SR (or SL) command is a concatenation of the above described RD and LD commands. The only differences are logic signals S4 and S5 from queue element logic module 73 select NEXTA(0-7) as outputs of the read function and the S1 and S2 outputs select LASTA(0-7) as inputs for the load (for the SR command). A parallel operation Shift Right is achieved by reading all queue element words simultaneously onto the separate NEXTA buses, and then simultaneously loading all queue element words from their separate LASTA buses. While not expressly shown, each queue elements NEXTA bus is connected to the next higher-position queue element's LASTA bus. From the above, it can thus be seen that shifts of data between queue elements occur in parallel and simultaneously and may occur between selected queue elements or between all queue elements in a queue. EVENT COUNT REGISTERS EXEC module 12 includes 256 event count registers 26, one for each possible event (as limited by an 8-bit address). In FIG. 6, an 8-bit event counter 100 and the first three event count registers 102, 104 and 106 are shown. Event counter 100 is programmable and responds to either an event count being loaded via data bus D(0-7) or to an event count from one of registers 102, 104 or 106. Each event count register has an assigned value indicative of one of 256 events which can occur in the system. If a register indicates a plus count, that is an indication that multiple tasks are waiting for the event to occur. If the event count register indicates a negative value, the indication is that the event has been signalled (occurred) more times than there are tasks waiting for the event's occurrence. Upon the occurrence of an event, the event count register corresponding to that event is examined to see the state of its count. If the count is seen to be positive, then queue state machine 16 knows that a task is present in event queue 24 and is awaiting the occurrence of the specific event. In such a case, event queue 24 is searched, in parallel, to find all TCBs that specify the specific event. The highest priority TCB that specifies the event is then chosen for execution. Queue state machine 16 transfers the chosen TCB from event queue 24 to CPU queue 20, where it is placed in priority order. When the task is removed from event queue 24, the value in the event count register is decremented through the action of counter 100. When an event occurs, the Signal utility causes the value of the corresponding event count register to be read and used to program counter 100. Then, counter 100 decrements the value, which decremented value is then written back into an appropriate register. A Wait utility causes the same sequence to occur with the exception that the value is decremented. The value of any event count register (102,104, 106, etc.) is available to be read by queue state machines 16 via data bus D(0-7). The following command lines from queue state machine 16 are applied to counter 100. ECOP(0-1) are used to specify whether counter 100 should increment, decrement, load, or clear. ECOC is used to enable the output from counter 100 onto the data lines D(0-7) ECCLK is the clock used to cause an operation on counter 100. ECLR is used to initialize all event count registers 102, 104, 106, etc. to 0. DELAY TIMER In FIG. 7, the details of delay timer 28 in FIG. 1 are shown. Delay timer 28 counts system clock cycles and causes queue state machine 16 to signal any event whose delay is up. The number of clock cycles in a delay unit (i.e. a unit of delay time) is programmable and is held in a timer interval register within command and status registers 14. The delay unit value comes into an 8-bit counter 110 in delay timer 28 on TIR(0-7) lines from the timer interval register. 8-bit counter 112 counts the number of delay units by accumulating the number of clock cycles in each delay unit and then incrementing to a next delay unit count. 8-bit counter 112 counts up to 255 and then rolls over to 0. The Delay utility delays events by a relative time, not an absolute time. COMMAND AND STATUS REGISTERS With reference to FIG. 1, command and status registers comprise a number of microprocessor-accessible registers which receive 16 bit data (and commands) from microprocessor 10 and 8-bit data from various of the elements within EXEC module 12. All registers are 16 bits in width and each register is either readable or writeable, but not both. For instance, in FIG. 8, examples of a write register 120 and read register 122 are shown along with their interconnections and control circuitry. Register 122 is a read register and receives data from EXEC module data bus D(0-7). Such data may subsequently be read out to microprocessor 10 upon application of enable signal ROEN(5). Similarly, write register 120 receives data from microprocessor 10 and upon application of an enable signal RIEN(0), provides such data as an output on data bus D(0-7). The following is a list of microprocessor accessible registers (not shown) within command and status registers 14 and a description of the respective register's operation during execution of an associated utility operation. Schedule Register (a Write Register): When a Task TCB is written to this register, the TCB is placed in CPU Queue 20 according to its priority (TCB value). Suspend Register (a Write Register): When a Task TCB is written to this register, the TCB is removed from CPU Queue 20, if it is indeed in CPU Queue 20. If the TCB is not in CPU Queue 20, an interrupt condition is generated to microprocessor 10. Status indicating this condition is set in a Status Register. Signal Register (a Write Register): When an Event control block is written to this register from microprocessor 10, this event is signalled. If no task is waiting for this event, the only action taken is to decrement the Event Count for this event. If tasks are waiting for this event, then the TCB with the highest priority (lowest TCB value) is removed from Event Queue 24 and placed in CPU Queue 20. Wait Register (a Write Register): When an Event control block is written to this register from microprocessor 10, the running task's TCB is placed in Event Queue 24 to wait for the named event. The running task's TCB is found at the first queue position in CPU Queue 20 (position 0). This TCB is removed from CPU Queue 20 and placed in Event Queue 24 according to its priority (TCB value). Delay Register (a Write Register): When an Event control block and an 8-bit delay value is written to this register from microprocessor 10, the Event control block name is placed into Delay Queue 22, prioritized by its delay value. The lower the delay, the closer to the head of the queue this block name is placed. Status Register (a Read Register): The Status register contains information on any abnormal conditions that occur within the EXEC chip. Timer Interval Register (a Write Register): The user writes a 16-bit value to this register which represents the number of system clocks that make up each delay value. CPUQ Register, Event Q Register, Delay Q Register (Read Registers): These registers, when read by microprocessor 10, will sequentially give the contents of all the Queue Element Words in the appropriate queue. These are Diagnostic Registers. Diagnostic Pointer Register (a Write Register): When written to with a value, the diagnostic registers above when read will be set to read from this location within the queues. Active TCB Register (a Read Register): When read, the TCBName of the current task that has highest priority in the CPU Queue is returned. Event Case Register (a Read Register): When read, the Event control block Name of the event that caused a task to resume execution is returned. This value only has meaning if this task has executed a Wait utility call. QUEUE STATE MACHINE Queue state machine 16 controls the workings of EXEC Module 12. Queue state machine 16 is, in turn, controlled by internal hardware that responds to commands written to command and status registers 14, to sequentially energize control lines to cause system operations in accordance with a specified command. In all respects queue state machine 16 is conventional and its arrangement is known to those skilled in the art. EXEC MODULE OPERATION-SCHEDULE UTILITY Assume that microprocessor 10 writes a TCB of a task that it wishes to schedule, to the Schedule Register within command and status registers 14 in EXEC module 12. The TCB value is thereby latched within the Schedule register. In response, queue state machine 16 performs a parallel search of CPU queue 20 to find a stored next lower priority TCB from the TCB being scheduled. Once found, the TCBs within CPU 20 are shifted one position to the right, starting from the incoming TCB's queue position. The position within CPU 20 vacated by this rightward shift is loaded with the TCB of the task to be scheduled. EXEC module 12 now asserts a handshake signal NDTACK from Port control 30 to indicate that the transaction may now be terminated. In response, microprocessor 10 de-asserts its CS signal to Port control 30, which signal precedes every transaction with EXEC module 12. CPU queue 20 has now been modified so that the TCB name of the task to be scheduled is present in CPU queue 20 in its proper priority position. Microprocessor 10, to determine what is now the highest-priority task awaiting execution, reads the Active TCB register from command and status registers 14. Microprocessor 10 may also read the Event case register. The access by microprocessor 10 to the Active TCB register causes queue state machine 16 to read the TCB name from the first queue element (highest priority) in CPU queue 20 and to place this value onto microprocessor data lines DATA (0-15). Port control 30 then asserts the NDTACK line to indicate that the value of the active TCB register is available to microprocessor 10. It will be recalled that the Event case is the name of the event that caused a name of a task to be moved into CPU queue 20. Microprocessor 10 can access the Event case register to determine the event value within CPU queue 20. This access causes the event name to be read from the first queue element in CPU queue 20 into the Event case register and thence to be placed on microprocessor 10's data bus DATA(0-15). The signal NDTACK is asserted indicating to microprocessor 10 that the value of this register is available on the output data bus. QUEUE STATE MACHINE OPERATION--SCHEDULE UTILITY The following are states that occur during a Schedule utility. Inputs to Queue state machine 16 are in lower case and outputs are uppercase. All events are synchronized to the system clock. For each state that is not exited until a particular event occurs, the event is indicated. If no event is specified for a given state, the state is exited upon the next state machine clock. 1. IDLE--EXEC chip select (cs) is not asserted, ntst is not asserted, nrst is not asserted, timer carry out (tco) is not asserted. Event--Chip select (cs) is asserted, CPU wishes to make an operating system call. 2. CMD RCVD--an EXEC command is received. Actions--The schedule Register latches the value the CPU provides on the uP Address lines. This value is the TCBName of the task that is to be scheduled for execution. 3. SETUP MATCH CMD--Begin the Schedule utility. Setup for a "Match>." command. Actions--CMD(0-3) lines set up with the command "Match>A." D(0-7) lines get the value in the Schedule Register. QEN(0-3) is set to the CPUQ value to indicate that this action takes place on the CPU Queue. 4. FINISH MATCH CMD--Assert the "MATCH" line. Actions--De-assert last state's actions and assert the MATCH line. 5. READ MATCH>ADD--Read address lines for highest priority match>address. Actions--Store the value on ADDR(0-7) in a temporary register, and de-assert the MATCH line. 6. SETUP SR CMD--Setup for a shift right command. Actions--Put value in temporary register out on ADDR(0-7) lines. Set CMD(0-3) lines to "SR" (Shift Right) command, and set QEN(0-3) lines equal to CPUQ value (to indicate action on CPU Queue) . 7. FINISH SR CMD--Finish the Shift Right command. Actions--De-assert last actions. 8. SETUP LD CMD--Setup for a "LD" (load) command. Actions--CMD(0-3) lines gets the "LDA" command value. D(0-7) lines gets the contents of the Schedule Register. ADDR(0-7) lines get the value in the temporary register. QEN(0-3) lines are set equal to the CPUQ value (to indicate action on the CPU Queue). 8. FINISH LD CMD--Finish the load command. Actions--De-assert the actions of the last state. 10. SETUP END uP XACTION (Setup to end transaction with CPU. Actions--DTACK (data transfer acknowledge) is asserted. Event--cs is de-asserted. 11. END uP XACTION--End transaction with CPU. Actions--DTACK (data transfer acknowledge) is de-asserted. 12. IDLE--GO to state 1 above. At this time, the task's TCB has been placed in the CPU Queue. In order to use the updated queue information, microprocessor 10 must execute a "READ.sub.13 ACTIVETCB" command. In addition, microprocessor 10 may execute a "READ.sub.13 EVENTCASE" in order to determine the event that caused this task to resume execution. These actions are performed for any utility call including Schedule, Suspend, Signal, Wait, and Delay. READ.sub.13 ACTIVETCB Command 1. IDLE--EXEC chip select (cs), ntst, nrst, and tco (timer carry out) all are de-asserted. 2. SETUP RD CMD--Setup for a "RD" (read) command. Actions--CMD(0-3) lines get the command "RDA" (read word A). The QEN(0-3) lines get the CPUQ value. ADDR(0-7) lines are set equal to 0 (for the first location in the CPU Queue--the Queue Head). 3. WRITE ACTIVETCB REG--Write the Active TCB Register with the TCBName at the head of the CPU Queue. Actions--The Active TCB Register is written with the value now appearing on the D(0-7) lines. This is the TCBName of the next task to have use of the CPU resource by virtue of its priority. 4. SETUP END uP XACTION--Setup to end transaction with CPU. Actions--DTACK (data transfer acknowledge) is asserted. Event--cs is de-asserted. 5. END uP XACTION--End transaction with CPU. Actions--DTACK (data transfer acknowledge) is de-asserted. 6. IDLE (state 1 above) READ.sub.-- EVENTCASE Command 1. IDLE--EXEC chip select (cs), ntst, nrst, and tco (timer carry out) all are de-asserted. 2. SETUP RD CMD--Setup a "RD" (read) command. Actions--CMD(0-3) is set to the "RDB" (read word B) value. QEN(0-3) is set to the CPUQ value. ADDR(0-7) lines are set to 0. We wish to read word B of the first element in the CPU Queue 3. WRITE EVENTCASE REG--Write the EventCase Register with the EventCase value of the next task to execute on the CPU. Actions--The EventCase Register is set equal to the value of the lines D(0-7). Actions of last state are de-asserted. 4. SETUP END uP XACTION--Setup to end transaction with CPU. Actions--DTACK (data transfer acknowledge) is asserted. Event--cs is de-asserted. 5. END uP XACTION--End transaction with CPU. Actions--DTACK (data transfer acknowledge) is de-asserted. 6. IDLE (state 1 above) It should be understood that the foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variances which fall within the scope of the appended claims.
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