Multi-task execution control system

Abstract

In a microcomputer system, having independently programmed tasks and a master control processing unit (CPU), tasks can be switched independent of the master CPU through the use of a multi-task support processor which may, for example, be connected to the microcomputer system via an input/output (I/O) port. The multi-task support processor includes a memory for storing task control programs, a data memory and task control memory, a timer, a controller for controlling multi-task operations, and a master CPU interface element. Tasks including task control commands are stored in a memory for execution by the master CPU. The master CPU, upon encountering a task control command, sends that command to the multi-task support processor which becomes activated to control the switching and communications between the tasks under the direction of the received task control command, so that tasking control may be performed independent of the master CPU.

Claims

What is claimed is:

1. A multi-task execution control system for a microcomputer having only a single central processor unit comprising:

memory means for storing a plurality of independently programmed tasks, said plurality of independently programmed tasks including a plurality of task control commands;

said single central processor unit (CPU) executing said plurality of tasks; and

multi-task support processor means, external from and operatively connected to said central processor means and responsive to said task control commands, for controlling the switching and communication of said plurality of tasks for execution by said central processing unit;

said central processor unit, upon execution of an activation task control command included in an independently programmed task, sending said activation task control command to said multi-task support processor means;

said multi-task support processor means controlling the switching of and the communication between said plurality of tasks under the direction of said activation task control command independently of the architecture of said central processor unit.

2. A system, as recited in claim 1, wherein said multi-task support processor means includes,

first memory means for storing control programs for controlling the switching and communication between said plurality of tasks,

interface-means, operatively connected to said central processor unit for sending data to and receiving data from said central processor means,

second memory means, connected to said interface means for storing system configuration data received from said central processing unit, and

control means, responsive to said control programs and said task control command received from said central processor unit, for controlling the switching and communication between said plurality of tasks.

3. A system, as recited in claim 2, wherein said second memory means stores priority data corresponding to said plurality of tasks, and

said control means controls the switching between said plurality of tasks in accordance with said priority data.

4. A system, as recited in claim 2, further comprising, input/output means, external from and operatively connected to said central processor means, for inputting data to said central processor unit from an external device and outputting data from said central processor means to said external device.

5. A system, as recited in claim 2, wherein said control means initiates switching between said plurality of tasks by causing said interface means to receive or transmit said plurality of tasks to said central processor unit.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a method of controlling the execution of multiple tasks in a microcomputer system.

Conventionally, when a CPU unit simultaneously executes a plurality of tasks in a microcomputer system, each program is obliged to deal with complex and massive contents. In addition, timing mechanisms needed for the task switching operation cannot be designed easily. To compensate for this, a microcomputer system uses the operating system (OS) to properly control the execution of multiple tasks. In other words, the microcomputer system is obliged to perform the switching operation (OS) for correctly executing a plurality of tasks. Conventionally, either a floppy disk or ROM containing the software operation system is made available for controlling the execution of multiple tasks. However, since such a software operating system is provided in a position above the program memory space controlled by the master CPU, the master CPU itself must execute the task switching operation, thus eventually restraining the user's program addresses to some extent. Although the concept of task control is basically free from the architecture of the CPU, if the task control is built into the operating system, the task control operation will become largely dependent on the CPU. As a result, if the needed operating system software is transferred to another CPU, it becomes necessary to also convert the operating system software so that it can be suited for use in the designated CPU, thus requiring an excessive handling operation to implement the needed conversion.

OBJECT AND SUMMARY OF THE INVENTION

The present invention aims at providing a method of controlling the execution of multiple tasks, being perfectly compatible with any CPU of a microcomputer system, since the preferred embodiment effectively switches tasks independent of the master CPU without applying any restraint on memory space availability and also without depending on the architecture of the CPU.

The preferred embodiment of the present invention provides a method of controlling the execution of multiple tasks comprising means for controlling the execution of multiple tasks by first entering a plurality of tasks into programs before these tasks are executed by the main CPU, followed by reception of a specific command by a multi-task support processor located external of the master CPU which activates switching and communication between tasks so that the switching and communication between the multiple tasks can be controlled by the command.

Although there are several methods employed for controlling the execution of multiple tasks, the preferred embodiment of the present invention is definitely unique, since the control of the execution of multiple tasks is assigned to the independently operating processes. The preferred embodiment can be usefully applied to a variety of microcomputer systems and effectively improves the operational efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified block diagram of a multi-task execution control system incorporating the preferred embodiment of the present invention;

FIG. 2 shows the internal configuration of the main elements of the multi-task execution control system shown in FIG. 1; and

FIG. 3 shows the flowchart describing the stepwise operations of the main elements shown in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

In reference to the attached drawings, the preferred embodiment of the present invention is described below. FIG. 1 shows a simplified block diagram of a multi-task execution control system embodied by the present invention. Reference number 1 indicates the main elements making up an independent multi-task support processor (hereinafter called MTSP element) that controls the execution of multiple tasks by switching a number of tasks in the microcomputer system. Like other peripheral devices, the MTSP element 1 is provided at one of the I/O ports. Also, like the other peripheral input terminal 4, the MTSP element 1 is connected to a master CPU 2 via an internal bus 3. Program memory 5 independently stores the initialized programs of the MTSP element 1 and a plurality of tasks, while the program memory 5 is connected to a data memory RAM 6 which is to be used by respective tasks, thus making up a system. The MTSP element 1 executes the scheduling of tasks in order to realize the multi-task system (by performing the switching of tasks to be executed according to the precedence of the time-sharing), while it also executes the synchronization and communication between tasks (by either transmitting or receiving data between tasks and by determining whether the task execution should be discontinued or resumed). The MTSP element 1 is provided with a function to control memory (by inhibiting the duplicated use of the memory area available for each task) and a clock function as well. In other words, the MTSP element 1 removes the necessity for performing the multi-task control function as a function of the operating system of the computer system, by acting as a peripheral device which itself executes the multiple task control function.

FIG. 2 shows the internal configuration of the MTSP element 1. The software that executes multiple tasking control, contained in the MTSP element 1 is stored in a ROM of a program memory 11. Register file 12 provides the data memory necessary for executing the function of the MTSP element 1 and contains a task control block (which is the area in which information needed for switching tasks is registered), a mail box (which is the relay point for data used to synchronize and communicate between tasks), a memory map (which is the area that registers data needed for controlling memory and indentifying whether the memory area is busy or not), a working area, and an exclusive data area, respectively. A timer 13 executes the time-sharing process (which causes tasks holding the same precedence to be executed at specific intervals) and a clock function as well. An operation controller 14, containing an ALU and other arithmetic units, executes programs stored in the program memory 11, which is connected to other units via an internal bus 15. In addition, the MTSP element 1 is also provided with a master CPU interface 16 for executing data input and output to and from the master CPU 2 and for realizing the interruption into the master CPU 2. Access from the master CPU 2 to the MTSP element 1 is executed by an activated command, whereas access from the MTSP element 1 to the master CPU 2 is executed by an interruption. The MTSP element 1 has a basic specification, for example, as shown below.

    ______________________________________
    Items      Specifications
    ______________________________________
    Tasks to be
               8 max.Task numbers 1 through 8
    registered:
    Priority   8 max. Priority: l through 8
    level:
    Mail box:  8 max. Mail box numbers 1 through 8
    Clock unit:
               10 microseconds
    Scheduling:
               Either by the precedence or by the
               time-sharing. Switches tasks by applying
               an interruption from the MTSP element 1.
    Number of  14 commands
    commands:
    Task regist-
               When the system is activated, task infor-
    ration:    mation is registered into the MTSP element 1.
    Memory     When the system is activated, the initial
    control:   and last RAM addresses available for users
               are registered into the MTSP element 1.
               Control of the MTSP element 1:
               Any desired address can be chosen from
               addresses 0 through FFFFH at 100H intervals.
    Clock:     Clock sets hour, minute, and second, which
               can be read as required.
    ______________________________________

    ______________________________________
    Names     Functions
    ______________________________________
    TSPD      Stops the task execution to eliminate the
              task from the control of the MTSP element 1.
    TRSM      Activates the task execution from either the
              standby or stop mode.
    TPRI      Changes the priority of the tasks to be
              executed.
    TSLI      Designates the time-sharing process.
    TIMR      Designates the timer operation for setting
              the time-out time or for keeping the timer
              to stand by for a specific period of time.
    CSET      Sets the clock.
    CGET      Reads the clock.
    MALC      Monopolizes memory.
    MREL      Releases memory.
    POST      Transmits messages.
    PEND      Receives messages. Keeps standby until
              receiving any message.
    ______________________________________

• Inventors
  Nakade, Toshimitsu; Kuki, Masaru; Uno, Takaaki;
• Assignee
  Sharp Kabushiki Kaisha (Osaka, JP)
• Published
  Jul-11-1989
• Current US Classes:
  718/107
  719/310
• Application #
  059192
• International Classes
  G06F 009/38; G06F 009/46
• Field of Search
  364/200
• Examiner
  Harkcom; Gary V.
• Agent
  Birch, Stewart, Kolasch, & Birch
• US Patent References:
  4152761
  4384324
  4493020
  4543630
  4553202
  4591976
  4604694