Subclass 107	Subclass 108
Context switching

Microphone/speaker system with context switching in processor

6986142

Abstract

A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Claims

What is claimed is:

1. A system comprising:

A. a microphone having output leads;

B. a speaker having input leads: and

C. a processor including:

i. a semiconductor chip having microphone input leads connected to the microphone output leads and having speaker output leads connected to the speaker input leads;

ii. a processor formed on the chip and coupled to the microphone input leads and the speaker output leads, the processor including an ALU and selected registers that are associated with the ALU, each selected register being formed of a pair of first and second registers, the ALU storing program data in one of the first and second registers for each selected register;

iii. a context change signal lead formed on the semiconductor chip, the context change signal lead carrying a signal having a first state indicating a context of a first set of program instructions operating on first data stored in the selected registers and a second state indicating a context of a second set of program instructions operating on second data stored in the selected registers; and

iv. context switching circuitry formed on the semiconductor chip, the context switching circuitry being connected to the selected registers and the context change signal lead, the context change switching circuitry connecting one of the pair of first and second registers, for each selected register, to hold the first data in response to the first state of the context change signal and connecting the other of the pair of first and second registers, for each selected register, to hold the second data in response to the second state of the context change signal.

2. The system of claim 1 in which the selected registers include an accumulator, an accumulator buffer, an auxiliary register, a compare register, an index register, a processor mode status register, a product register, a status register 0, a status register 1, a temporary register for multiplier, a temporary register for shift count and a temporary register for bit test.

3. The system of claim 1 in which the context change signal lead receives a hardware interrupt signal forming the context change signal.

4. The system of claim 1 in which the context change signal lead receives a signal indicating one of an interrupt, a software trap, and a subroutine.

5. The system of claim 1 in which the processor includes a hardwired multiplier coupled to the ALU.

6. The system of claim 1 in which each selected register includes the first register having an output connected to the input of the second register and the second register having an output connected to the input of the first register and the context switching circuitry moving the first data from the first register to the second register for each selected register.

7. The system of claim 1 in which each selected register includes the first and second register both having an input coupled to receive data from the ALU and the context switching circuitry changes the flow of data being received by a selected register from the first register to the second register.

8. The system of claim 1, in which the context switching circuitry includes a multiplexer selectively switching data from the ALU to the first and second registers of each selected register.

9. The system of claim 1, in which the context switching circuitry includes a clock signal connected to each first and second register of each selected register selectively to clock data from the ALU into one and the other of the first and second registers.

10. The system of claim 1 in which the selected registers include an accumulator and a product register.

11. The system of claim 1 including an analog to digital converter connected between the microphone and the processor and a digital to analog converter connected between the processor and the speaker.

Description

This invention relates to data processing devices, electronic processing and control systems and methods of their manufacture and operation.

BACKGROUND OF THE INVENTION

A microprocessor device is a central processing unit or CPU for a digital processor which is usually contained in a single semiconductor integrated circuit or "chip" fabricated by MOS/LSI technology, as shown in U.S. Pat. No. 3,757,206, issued to Gary W. Boone and assigned to Texas Instruments Incorporated. The Boone patent shows a single-chip 8-bit CPU including a parallel ALU, registers for data and addresses, an instruction register and a control decoder, all interconnected using the von Neumann architecture and employing a bidirectional parallel bus for data, address and instructions. U.S. Pat. No. 4,074,351, issued to Gary W. Boone and Michael J. Cochran, assigned to Texas Instruments Incorporated, shows a single-chip "microcomputer" type device which contains a 4-bit parallel ALU and its control circuitry, with on-chip ROM for program storage and on-chip RAM for data storage, constructed in the Harvard architecture. The term microprocessor usually refers to a device employing external memory for program and data storage, while the term microcomputer refers to a device with on-chip ROM and RAM for program and data storage. In describing the instant invention, the term "microcomputer" will be used to include both types of devices, and the term "microprocessor" will be primarily used to refer to microcomputers without on-chip ROM. Since the terms are often used interchangeably in the art, however, it should be understood that the use of one of the other of these terms in this description should not be considered as restrictive as to the features of this invention.

Modern microcomputers can be grouped into two general classes, namely general-purpose microprocessors and special-purpose microcomputers/microprocessors. General purpose microprocessors, such as the M68020 manufactured by Motorola, Inc. are designed to be programmable by the user to perform any of a wide range of tasks, and are therefore often used as the central Processing unit in equipment such as personal computers. Such general-purpose microprocessors, while having good performance for a wide range of arithmetic and logical functions, are of course not specifically designed for or adapted to any particular one of such functions. In contrast, special-purpose microcomputers are designed to provide performance improvement for specific predetermined arithmetic and logical functions for which the user intends to use the microcomputer. By knowing the primary function of the microcomputer, the designer can structure the microcomputer in such a manner that the performance of the specific function by the special-purpose microcomputer greatly exceeds the performance of the same function by the general-purpose microprocessor regardless of the program created by the user.

One such function which can be performed by a special-purpose microcomputer at a greatly improved rate is digital signal processing, specifically the computations required for the implementation of digital filters and for performing Fast Fourier Transforms. Because such computations consist to a large degree of repetitive operations such as integer multiply, multiple-bit shift, and multiply-and-add, a special-purpose microcomputer can be constructed specifically adapted to these repetitive functions. Such a special-purpose microcomputer is described in U.S. Pat. No. 4,577,282, assigned to Texas Instruments Incorporated and incorporated herein by reference. The specific design of a microcomputer for these computations has resulted in sufficient performance improvement over general purpose microprocessors to allow the use of such special-purpose microcomputers in real-time applications, such as speech and image processing.

Digital signal processing applications, because of their computation intensive nature, also are rather intensive in memory access operations. Accordingly, the overall performance of the microcomputer in performing a digital signal processing function is not only determined by the number of specific computations performed per unit time, but also by the speed at which the microcomputer can retrieve data from, and store data to, system memory. Prior special-purpose microcomputers, such as the one described in said U.S. Pat. No. 4,577,282, have utilized modified versions of a Harvard architecture, so that the access to data memory may be made independent from, and simultaneous with, the access of program memory. Such architecture has, of course provided for additional performance improvement.

The increasing demands of technology and the marketplace make desirable even further structural and process improvements in processing devices, application systems and methods of operation and manufacture.

Among the objects of the present invention are to provide improved data processing devices, systems and methods that reduce competition of compare functions and arithmetic computation functions for processor resources; to provide improved data processing devices, systems and methods that simplify operations and provide architectural solutions that increase processing efficiency where intensive computation and comparison operations coexist; to provide improved data processing devices, systems and methods with applications to improved gain and to provide improved data processing devices, systems and methods to better adapt computers to pattern recognition, complex information processing and control generally.

SUMMARY OF THE INVENTION

In general, one form of the invention is a data processing device including an instruction decoder and an arithmetic logic unit having first and second inputs and an output. An accumulator is connected between the output and first input of the arithmetic logic unit. A further register is connected between the accumulator and the second input of the arithmetic logic unit. The arithmetic logic unit includes circuitry for computing a digital value to the accumulator as wall as an additional circuit. The additional circuit thereupon compares the value at the second input from said register with the digital value in the accumulator in response to a command from the instruction decoder and then stores to the register the lesser or the greater in value of the contents of the register and the digital value in the accumulator depending on the command.

Other device, system and method forms of the invention are also disclosed and claimed herein. Other objects of the invention are disclosed and still other objects will be apparent from the disclosure herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are set fourth in the appended claims. The preferred embodiments of the invention as well as other features and advantages thereof will be best understood by reference to the detailed description which follows, read in conjunction with the accompanying drawings, wherein:

FIGS. 1A and 1B are two halves of an electrical diagram in block form of an improved microcomputer device including a CPU or central processor unit formed on a single semiconductor chip;

FIG. 2 is a block diagram of an improved industrial process and protective control system;

FIG. 3 is a partially pictorial, partially block electrical diagram of an improved automotive vehicle system;

FIG. 4 is an electrical block diagram of an improved motor control system:

FIG. 5 is an electrical block diagram of another improved motor control system;

FIG. 6 is an electrical block diagram of yet another improved motor control system;

FIG. 7 is an electrical block diagram of an improved robotic control system;

FIG. 8 is an electrical block diagram of an improved satellite telecommunications system;

FIG. 9 is an electrical block diagram of an improved echo cancelling system for the system of FIG. 8;

FIG. 10 is an electrical block diagram of an improved modem transmitter;

FIG. 11 is an electrical block diagram equally representative of hardware blocks or process blocks for the improved modem transmitter of FIG. 10;

FIG. 12 is an electrical block diagram equally representative of hardware blocks or process blocks for an improved modem receiver;

FIG. 13 is an electrical block diagram of an improved system including a host computer and a digital signal processor connected for PCM (pulse code modulations communications;

FIG. 14 is an electrical block diagram of an improved video imaging system with multidimensional array processing;

FIG. 15 is an electrical block diagram equally representative of hardware blocks or process blocks for improved graphics, image and video processing;

FIG. 16 is an electrical block diagram of a system for improved graphics, image and video processing;

FIG. 17 is an electrical block diagram of an improved automatic speech recognition system;

FIG. 18 is an electrical block diagram of an improved vocoder-modem system with encryption;

FIG. 19 is a series of seven representations of an electronic register holding bits of information and illustrating bit manipulation operations of a parallel logic unit improvement of FIG. 1B;

FIG. 20 is an electrical block diagram of an improved system for high-sample rate digital signal processing;

FIG. 21 is an electrical block diagram of architecture for an improved data processing device including the CPU of FIGS. 1A and 1B;

FIG. 22 a schematic diagram of a circuit for zero-overhead interrupt context switching;

FIG. 23 is a schematic diagram of an alternative circuit for zero-overhead interrupt context switching;

FIG. 24 is a schematic diagram of another alternative circuit for zero-overhead interrupt context switching;

FIG. 25 is a flow diagram of a method of operating the circuit of FIG. 24;

FIG. 26 is a block diagram of an improved system including memory and I/O peripheral devices interconnected without glue logic to a data processing device of FIGS. 1A and 1B having software wait states on address boundaries;

FIG. 27 is a partially block, partially schematic diagram of a circuit for providing software wait states on address boundaries;

FIG. 28 is a process flow diagram illustrating instructions for automatically computing a maximum or a minimum in the data processing device of FIGS. 1A and 1B;

FIG. 29 is a partially graphical, partially tabular diagram of instructions versus instruction cycles for illustrating a pipeline organization of the data processing device of FIGS. 1A and 1B;

FIG. 30 is a further diagram of a pipeline of FIG. 29 comparing advantageous operation of a conditional instruction to the operation of a conventional instruction;

FIG. 31 is an electrical block diagram of an improved video system with a digital signal processor performing multiple-precision arithmetic using conditional instructions having the advantageous operation illustrated in FIG. 30;

FIG. 32 is a block diagram of status bits and mask bits of a conditional instruction such as a conditional branch instruction;

FIG. 33 is a block diagram of an instruction register and an instruction decoder lacking provision for status and mask bits;

FIG. 34 is a block diagram detailing part of the improved data processing device of FIG. 1A having an instruction register and decoder with provision for conditional instructions with status and mask bits:

FIG. 35 is a partially schematic, partially block diagram of circuitry for implementing the status and mask bits of FIGS. 32 and 34;

FIG. 36 is a pictorial of an improved pin-out or bond-out configuration for a chip carrier for the data processing device of FIGS. 1A and 1B illustrating improvements applicable to configurations for electronic parts generally;

FIG. 37 is a pictorial view of four orientations of the chip carrier of FIG. 36 on a printed circuit in manufacture;

FIG. 38 is a pictorial of an automatic chip socketing machine and test area for rejecting and accepting printed circuits of FIG. 37 in manufacture;

FIG. 39 is a processing method of manufacture utilizing the system of FIG. 38;

FIG. 40 is a version of the improved pin-out configuration in a single in-line type of chip;

FIG. 41 is another version of the improved pin-out configuration;

FIG. 42 is a pictorial of a dual in-line construction wherein the improved pin-out configuration is applicable and showing translation arrows; and

FIG. 43 is a pictorial of some pins of a pin grid array construction wherein the improved pin-out configuration is acceptable.

Corresponding numerals and other symbols refer to corresponding parts in the various figures of drawing except where the context indicates otherwise.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

An architectural overview first describes a preferred embodiment digital signal processing device 11.

The preferred embodiment digital signal processing device 11 of FIGS. 1A and 1B implements a Harvard-type architecture that maximizes processing power by maintaining two separate memory bus structures, program and data, for full-speed execution. Instructions are included to provide data transfers between the two spaces.

The device 11 has a program addressing circuit 13 and an electronic computation circuit 15 comprising a processor. Computation circuit 15 performs two's-complement arithmetic using a 32 bit ALU 21 and accumulator 23. The ALU 21 is a general-purpose arithmetic logic unit that operates using 16-bit words taken from a data memory 25 of FIG. 1B or derived from immediate instructions or using the 32-bit result of a multiplier 27. In addition to executing arithmetic instructions, the ALU 21 can perform Boolean operations. The accumulator 23 stores the output from the ALU 21 and provides a second input to the ALU 21 via a path 29. The accumulator 23 is illustratively 32 bits in length and is divided into a high-order word (bits 31 through 16) and a low-order word (bits 15 through 0). Instructions are provided for storing the high and low order accumulator words in data memory 25. For fast, temporary storage of the accumulator 23 there is a 32-bit accumulator buffer ACCB 31.

In addition to the main ALU 21 there is a Peripheral Logic Unit (PLU) 41 in FIG. 1B that provides logic operations on memory locations without affecting the contents of the accumulator 23. The PLU 41 provides extensive bit manipulation ability for high-speed control purposes and simplifies bit setting, clearing, and testing associated with control and status register operations.

The multiplier 27 of FIG. 1A performs a 16×16 bit two's complement multiplication with a 32-bit result in a single instruction cycle. The multiplier consists of three elements: a temporary TREG0 register 49, product register PREG 51 and multiplier array 53. The 16-bit TREG0 register 49 temporarily stores the multiplicand; the PREG register 51 stores the 32-bit product. Multiplier values either come from data memory 25, from a program memory 61 when using the MAC/MACD instructions, or are derived immediately from the MPYK (multiply immediate) instruction word.

Program memory 61 is connected at addressing inputs to a program address bus 101A. Memory 61 is connected at its read/write input/output to a program data bus 101D. The fast on-chip multiplier 27 allows the device 11 to efficiently perform fundamental DSP operations such as convolution, correlation, and filtering.

A processor scaling shifter 65 has a 16-bit input connected to a data bus 111D via a multiplexer (MUX) 73, and a 32-bit output connected to the ALU 21 via a multiplexer 77. The scaling shifter 65 produces a left-shift of 0 to 16 bits on the input data, as programmed by instruction or defined in a shift count register (TREG1) 81. The LSBs (least significant bits) of the output are filled with zeros, and the MSBs (most significant bits) may be either filled with zeros or sign-extended, depending upon the state of the sign-extension mode bit SXM of the status register ST1 in a set of registers 85 of FIG. 13. Additional shift capabilities enable the processor 11 to perform numerical scaling, bit extraction, extended arithmetic, and overflow prevention.

Up to eight levels of a hardware stack 91 are provided for saving the contents of a program counter 93 during interrupts and subroutine calls. Program counter 93 is selectively loaded upon a context change via a MUX 95 from program address bus 101A or program data bus 101D. The PC 93 is written to address bus 101A or pushed onto stack 91. On interrupts, certain strategic registers (accumulator 23, product register 51, TREG049, TREG1, TREG2, and in register 113: ST0, ST1, PMST, ARCR, INDX and CMPR) are pushed onto a one deep stack and popped upon interrupt return: thus providing a zero-overhead, interrupt context switch. The interrupts operative to save the contents of these registers are maskable.

The functional block diagram shown in FIGS. 1A and 1B outlines the principal blocks and data paths within the processor. Further details of the functional blocks are provided hereinbelow. Refer to Table A-1, the internal hardware summary, for definitions of the symbols used in FIGS. 1A and 1B.

The processor architecture is built around two major buses (couples): the program bus 101A and 101D and the data bus 111A and 111D. The program bus carries the instruction code and immediate operands from program memory on program data bus 101D. Addresses to program memory 61 are supplied on program address bus 101A. The data bus includes data address bus 111A and data bus 111D. The latter bus 111D interconnects various elements, such as the Central Arithmetic Logic Unit (CALU) 15 and an auxiliary register file 115 and registers 85, to the data memory 25. Together, the program and data buses 101 and 111 can carry data from on-chip data memory 25 and internal or external program memory 61 to the multiplier 27 in a single cycle for multiply/accumulate operations. Data memory 25 and registers 85 are addressed via data address bus 111A. A core register address decoder 121 is connected to data address bus 111A for addressing registers 85 and all other addressable CPU core registers.

The processor 13, 15 has a high degree of parallelism; e.g., while the data is being operated upon by the CALU 15, arithmetic operations are advantageously implemented in an Auxiliary Register Arithmetic Unit (ARAU) 123. Such parallelism results in a powerful set of arithmetic logic, and bit manipulation operations that may all be performed in a single machine cycle.

The processor internal hardware contains hardware for single-cycle 16×16-bit multiplication, data shifting and address manipulation.

Table A-1 presents a summary of the internal hardware. This summary table, which includes the internal processing elements, registers, and buses, is alphabetized within each functional grouping.

TABLE A-1

Internal Hardware

UNIT	SYMBOL	FUNCTION

Accumulator	ACC(32)	A 32-bit accumulator
	ACCH(16	accessible in two halves:
	ACCL(16)	ACCH (accumulator high) and
		ACCL (accumulator low). Used
		to store the output of the ALU.
Accumulator	ACCB(32)	A register used to temporarily
Buffer		store the 32-bit contents of
		the accumulator. This
		register has a direct path
		back to the ALU and therefore
		can be arithmetically or
		logically operated with the
		ACC.
Arithmetic	ALU	A 32-bit two's complement
Logic Unit		arithmetic logic unit having
		two 32-bit input ports and one
		32-bit output port feeding the
		accumulator.
Auxiliary	ARAU	A 16-bit unsigned arithmetic
Arithmetic Unit		unit used to calculate
		indirect addresses using the
		auxiliary, index, and compare
		registers as inputs.
Auxiliary	ARCR	A 16-bit register used in use
Register		as a limit to compare indirect
Compare		address against.
Auxiliary	AUXREGS	A register file containing
Register File		eight 16-bit auxiliary
		registers (AR0-AR7), used for
		indirect data address
		pointers, temporary storage,
		or integer arithmetic
		processing through the ARAU.
Auxiliary	ARP	A 3-bit register used as a
Register		pointer to the currently
Pointer		selected auxiliary register.
Block Repeat	BRCR	A 16-bit memory-mapped
Counter Register		counter register used as a
		limit to the number of times
		the block is to be repeated.
Block Repeat	PAER	A 16-bit memory-mapped
Counter Register		register containing the end
		address of the segment of code
		being repeated.
Block Repeat	PASR	A 16-bit memory-mapped
Address Start		register containing the start
Register		address of the segment of code
		being repeated.
Bus Interface	BIM	A buffered interface used to
Module		pass data between the data and
		program buses.
Central	CALU	The grouping of the ALU,
Arithmetic		multiplier, accumulator, and
Logic Unit		scaling shifters.
Circular	CBCR	An 8-bit register used to
Buffer Control		enable/disable the circular
Register		buffers and define which
		auxiliary registers are mapped
		to the circular buffers.
Circular	CBER1	Two 16-bit registers
Buffer End		indicating circular buffer
Address		end addresses. CBER1 and
		CBER2 are associated with
		circular buffers one and two
		respectively.
Circular Buffer	CBSR1	Two 16-bit registers
Start Address	CBSR2	indicating circular buffer
		start addresses. CBSR1/CBSR2
		are associated with circular
		buffers one and two
		respectively.
Data Bus	DATA	A 16-bit bus used to route
		data.
Data Memory	DATA	This block refers to data
	MEMORY	memory used with the core and
		defined in specific device
		descriptions. It refers to
		both on and off-chip memory
		blocks accessed in data memory
		space.
Data Memory	DMA	A 7-bit register containing
Address		the immediate relative address
Immediate		within a data page.
Register
Data Memory	DP(9)	A 9-bit register containing
Page Pointer		the address of the current
		page. Data pages are 128
		words each, resulting in 512
		pages of addressable data
		memory space (some locations
		are reserved).
Direct Data	DATA	A 16-bit bus that carries the
Memory Address	ADDRESS	direct address for the data
Bus		memory, which is the
		concatenation of the DP
		register and the seven LSBs of
		the instruction (DMA).
Dynamic Bit	DEMR	A 16-bit memory-mapped
Manipulation		register used as an input to
Register		PLU.
Dynamic	TREG2	A 4-bit register that holds a
Bit Pointer		dynamic bit pointer for the
		BITT instruction.
Dynamic	TREG1	A 5-bit register that holds a
Shift Count		dynamic prescaling shift count
		for data inputs to the ALU.
Global Memory	GREG(8)	An 8-bit memory-mapped
Allocation		register for allocating the
Register		size of the global memory
		space.
Interrupt Flag	IFR(16)	A 16-bit flag register used to
Register		latch the active-low
		interrupts. The IFR is a
		memory mapped register.
Interrupt Mask	IMR(16)	A 16-bit memory mapped
Register		register used to mask
		interrupts.
Multiplexer	MUX	A bus multiplexer used to
		select the source of operands
		for a bus or execution unit.
		The MUXs are connected via
		instructions.
Multiplier	MULTI-	A 16 × 16 bit parallel
	PLIER	multiplier.
Peripheral	PLU	A 16-bit logic unit that
Logic Unit		executes logic operations from
		either long immediate operands
		or the contents of the DBMR
		directly upon data locations
		without interfering with the
		contents of the CALU
		registers.
Prescaler	COUNT	A 4-bit register that contains
Count Register		the count value for the
		prescaling operation. This
		register is loaded from either
		the instruction or the dynamic
		shift count when used in
		prescaling data. In
		conjunction with the BIT and
		BITT instructions, it is
		loaded from the dynamic bit
		pointer of the instruction.
Product	PREG(32)	A 32-bit product register used
Register		to hold the multiplier
		product. The high and low
		words of the PREG can also be
		accessed individually using
		the SPH/SPL (store P register
		high/low) instructions.
Product	BPR(32)	A 32-bit register used for
Register Buffer		temporary storage of the
		product register. This
		register can also be a direct
		input to the ALU.
Program Bus	PROG DATA	A 16-bit bus used to route
		instructions (and data for the
		MAC and MACD instructions).
Program Counter	PC(16)	A 16-bit program counter used
		to address program memory
		sequentially. The PC always
		contains the address of the
		next instruction to be
		executed. The PC contents are
		updated following each
		instruction decode operation.
Program	PROGRAM	This block refers to program
Memory	MEMORY	memory used with the core and
		defined in specific device
		descriptions. It refers to
		both on and off-chip memory
		block accessed in program
		memory space.
Program Memory	PROG AD-	A 16-bit bus that carries the
Address Bus	DRESS	program memory address.
Prescaling	PRESCALER	A 0 to 16-bit left barrel
Shifter		shifter used to prescale data
		coming into the ALU. Also
		used to align data for
		multi-precision operations.
		This shifter is also used as a
		0-16 bit right barrel shifter
		of the ACC.
Postscaling	POST-	A 0-7 bit left barrel shifter
Shifter	SCALER	used to post scale data coming
		out of the CALU.
Product	P-SCALER	A 0, 1, 4-bit left shifter
Shifter		used to remove extra sign bits
		(gained in the multiply
		operation) when using fixed
		point arithmetic. A 6-bit
		right shifter used to scale
		the products down to avoid
		overflow in the accumulation
		process.
Repeat	RPTC(16)	An 8-bit counter to control
Counter		the repeated execution of a
		single instruction.
Stack	STACK	A 8 × 16 hardware stack used
		to store the PC during
		interrupts and calls. The
		ACCL and data memory values
		may also be pushed onto the
		popped from the stack.
Status	ST0,ST1,	Three 16-bit status registers
Registers	PMST, CBCR	that contain status and
		control bits.
Temporary	TREG0	A 16-bit register that
Multiplicand		temporarily holds an operand
		for the multiplier.
Block Move	BMAR	A 16-bit register that holds
Address Register		an address value for use with
		block moves or multiply
		accumulates.

There are 28 core processor registers mapped into the data memory space by decoder 121. These are listed in Table A-2. There are an additional 64 data memory space registers reserved in page zero of data space. These data memory locations are reserved for peripheral control registers.

TABLE A-2

Memory Mapped Registers

ADDRESS

NAME	DEC	HEX	DESCRIPTION

	0-3	0-3	RESERVED
IMR	4	4	INTERRUPT MASK REGISTER
GREG	5	5	GLOBAL MEMORY ALLOCATION
			REGISTER
IFR	6	6	INTERRUPT FLAG REGISTER
PMST	7	7	PROCESSOR MODE STATUS REGISTER
RPTC	8	8	REPEAT COUNTER REGISTER
BRCR	9	9	BLOCK REPEAT COUNTER RGISTER
PASR	10	A	BLOCK REPEAT PROGRAM ADDRESS
			START REGISTER
PAER	11	B	BLOCK REPEAT PROGRAM ADDRESS END
			REGISTER
TREG0	12	C	TEMPORARY REGISTER USED FOR
			MULTIPLICAND
TREG1	13	D	TEMPORARY REGISTER USED FOR
			DYNAMIC SHIFT COUNT
TREG2	14	E	TEMPORARY REGISTER USED AS BIT
			POINTER IN DYNAMIC BIT TEST
DBMR	15	F	DYNAMIC BIT MANIPULATION REGISTER
AR0	16	10	AUXILIARY REGISTER ZERO
AR1	17	11	AUXILIARY REGISTER ONE
AR2	18	12	AUXILIARY REGISTER TWO
AR3	19	13	AUXILIARY REGISTER THREE
AR4	20	14	AUXILIARY REGISTER FOUR
AR5	21	15	AUXILIARY REGISTER FIVE
AR6	22	16	AUXILIARY REGISTER SIX
AR7	23	17	AUXILIARY REGISTER SEVEN
INDX	24	18	INDEX REGISTER
ARCR	25	19	AUXILIARY REGISTER COMPARE
			REGISTER
CBSR1	26	1A	CIRCULAR BUFFER 1 START ADDRESS
			REGISTER
CBER1	27	1B	CIRCULAR BUFFER 1 END ADDRESS
			REGISTER
CBSR2	28	1C	CIRCULAR BUFFER 2 START ADDRESS
			REGISTER
CBER2	29	1D	CIRCULAR BUFFER 2 END ADDRESS
			REGISTER
CBCR	30	1E	CIRCULAR BUFFER CONTROL REGISTER
BMAR	31	1F	BLOCK MOVE ADDRESS REGISTER

The processor 13, 15 addresses a total of 64K words of data memory 25. The data memory 25 is mapped into the 96K data memory space and the on-chip program memory is mapped into a 64K program memory space.

The 16-bit data address bus 111A addresses data memory 25 in one of the following two ways:

1) By a direct address bus (DAB) using the direct addressing mode (e.g. ADD 010 h), or
2) By an auxiliary register file bus (AFB) using the indirect addressing mode (e.g. ADD+)
3) Operands are also addressed by the contents of the program counter in an immediate addressing mode.

In the direct addressing mode, a 9-bit data memory page pointer (DP) 125 points to one of 512 (128-word) pages. A MUX 126 selects on command either bus 101D or 111D for DP pointer register portion 125. The data memory address (dma) specified from program data bus 101D by seven LSBs 127 of the instruction, points to the desired word within the page. The address on the DAB is formed by concatenating the 9-bit DP with the 7-bit dma. A MUX 129 selectively supplies on command either the ARAU 123 output or the concatenated (DP, dma) output to data address bus 111A.

In the indirect addressing mode, the currently selected 16-bit auxiliary register AR(ARP) in registers 115 addresses the data memory through the AFB. While the selected auxiliary register provides the data memory address and the data is being manipulated by the CALU 15, the contents of the auxiliary register may be manipulated through the ARAU 123.

The data memory address map can be extended beyond the 64K-word address reach of the 16-bit address bus by paging in an additional 32K words via the global memory interface. By loading the GREG register with the appropriate value, additional memory can be overlaid over the local data memory starting at the highest address and moving down. This additional memory is differentiated from the local memory by the BR- pin being active low.

When an immediate operand is used, it is either contained within the instruction word itself or, in the case of 16-bit immediate operands, the word following the instruction word.

Eight auxiliary registers (AR0-AR7) in the auxiliary registers 115 are used for indirect addressing of the data memory 25 or for temporary data storage. Indirect auxiliary register addressing allows placement of the data memory address of an instruction operand into one of the auxiliary registers. These registers are pointed to by a three-bit auxiliary register pointer (ARP) 141 that is loaded with a value from 0 through 7, designating AR0 through AR7, respectively. A MUX 144 has inputs connected to data bus 111D and program data bus 101D. MUX 144 is operated by instruction to obtain a value for ARP 141 from one of the two buses 111D and 101D. The auxiliary registers 115 and the ARP 141 may be loaded either from data memory 25, the accumulator 23, the product register 51, or by an immediate operand defined in the instruction. The contents of these registers may also be stored in data memory 25 or used as inputs to the main CPU.

The auxiliary register file (AR0-AR7) 115 is connected to the Auxiliary Register Arithmetic Unit (ARAU) 123 shown in FIG. 1B. The ARAU 123 may autoindex the current auxiliary register in registers 115 while the data memory location is being addressed. Indexing by either +/-1 or by the contents of an index register 143 or AR0 may be performed. As a result, accessing tables of information by rows or columns does not require the central Arithmetic Logic Unit (CALU) 15 for address manipulation, thus freeing it for other operations.

The index register 143 or the eight LSBs of an instruction register IR are selectively connected to one of the inputs of the ARAU 123 via a MUX 145. The other input of ARAU 123 is fed by a MUX 147 from the current auxiliary register AR (being pointed to by ARP). AR(ARP) refers to the contents of the current AR 115 pointed to by ARP. The ARAU 123 performs the following functions.


AR(ARP) + INDX -- AR(ARP)	Index the current AR by
	adding a 16-bit integer
	contained in INDX.
AR(ARP) - INDX -- AR (ARP)	Index the current AR by
	subtracting a 16-bit
	integer contained in INDX.
AR(ARP) + 1-- AR(ARP)	Increment the current AR
	by one.
AR(ARP) - 1 -- AR(ARP)	Decrement the current AR
	by one.
AR(ARP) -- AR(ARP)	Do not modify the current
	AR.
AR(ARP) + IR(7 - 0) -- AR(ARP)	ADD an 8-bit immediate
	value to current AR.
AR(ARP) - IR(7 - 0) -- AR(ARP)	Subtract an 8-bit immediate
	value from current AR.
AR(ARP) + rc(INDX) -- AR(ARP)	Bit-reversed indexing, add
	INDX with reverse carry
	(rc) propagation.
AR(ARP) - rc(INDX) -- AR(ARP)	Bit-reversed indexing,
	subtract INDX with
	reverse-carry (rc)
	propagation.
if (AR(ARP) = ARCR) then TC = 1	Compare current AR with
if (AR(ARP)gt ARCR) then TC = 1	ARCR and if comparison
if (AR(ARP)lt ARCR) then TC = 1	is true then set TC bit of
if (AR(ARP)neq ARCR) then TC = 1	the status register (ST1)
	to one. If false then
	clear TC.
if(AR(ARP) = CBER)then AR(ARP) =	If at end of circular
CBSR	buffer reload start
	address

("--" means "loaded into")

The index register (INDX) can be added to or subtracted from AR(ARP) on any AR update cycle. This 16-bit register is one of the memory-mapped registers. This 16-bit register is used to step the address in steps larger than one and is used in operatios such as addressing down a column of a matrix. The auxiliary register compare register (ARCR) is used as a limit to blocks of data and in conjunction with the CMPR instruction supports logical comparisons between AR(ARP) and ARCR.

Because the auxiliary registers 115 are memory-mapped, they can be acted upon directly by the CALU 15 to provide for more advanced indirect addressing techniques. For example, the multiplier 27 can be used to calculate the addresses of three dimensional matrices. There is a two machine cycle delay after a CALU load of the auxiliary register until auxiliary registers can be used for address generation.

Although the ARAU 123 is useful for address manipulation in parallel with other operations, it suitably also serves as an additional general-purpose arithmetic unit since the auxiliary register file can directly communicate with data memory. The ARAU implements 16-bit unsigned arithmetic, whereas the CALU implements 32-bit two's complement arithmetic. BANZ and BANZD instructions permit the auxiliary registers to also be used as loop counters.

A 3-bit auxiliary register pointer buffer (ARB) 148 provides storage for the ARP on subroutine calls.

The processor supports two circular buffers operating at a given time. These two circular buffers are controlled via the Circular Buffer Control Register (CBCR) in registers 85. The CBCR is defined as follows:


BIT	NAME	FUNCTION

0-2	CAR1	Identifies which auxiliary register is
		mapped to circular buffer 1.
3	CENB1	Circular buffer 1 enable = 1/disable = 0.
		Set 0 upon reset.
4-6	CAR2	Identifies which auxiliary register is
		mapped to circular buffer 2.
7	CENB2	Circular buffer 2 enable = 1/disable = 0.
		Set 0 upon reset.

Upon reset (RS-risinq edge) both circular buffers are disabled. To define each circular buffer first load the CBSR1 and CBSR2 with the respective start addresses of the buffers and CBER1 and CBER2 with the end addresses. Then load respective auxiliary registers AR(i1) and AR(i2) in registers 115 to be used with each circular buffer with an address between the start and end. Finally load CBCR with the appropriate auxiliary register number i1 or i2 for ARP and set the enable bit. As the address is stepping through the circular buffer, the update is compared by ARAU 123 against the value contained in CBER 155. When equal, the value contained in CBSR 157 is automatically loaded into the AR auxiliary register AR(i1) or AR(i2) for the respective circular buffer.

Circular buffers can be used with either incremented or decremented type updates. If using increment, then the value in CBER is greater than the value in CBSR. When using decrement, the greater value is in the CBSR. The other indirect addressing modes also can be used wherein the ARAU 123 tests for equality of the AR and CBER values. The ARAU does not detect an AR update that steps over the value contained in CBER 155.

As shown in FIG. 1B, the data bus 111D is connected to supply data to MUXes 144 and 126, auxiliary registers 115 and registers CBER 155, INDX 143, CBSR 157 and an address register compare register ARCR 159. MUX 145 has inputs connected to registers CBER, INDX and ARCR and instruction register IR for supplying ARAU 123.

The preferred embodiment provides instructions for data and program block moves and for data move functions that efficiently utilize the memory spaces of the device. A BLDD instruction moves a block within data memory, and a BLPD instruction moves a block from program memory to data memory. One of the addresses of these instructions comes from a data address generator, and the other comes from either a long mediate constant or a Block Move Address Register (BMAR) 160. When used with the repeat instructions (RPT/RPTK/RPTR/RPTZ), the BLDD/BLPD instructions efficiently perform block moves from on-chip or off-chip memory.

A data move instruction DMOV allows a word to be copied from the currently addressed data memory location in on-chip RAM to the next higher location while the data from the addressed location is being operated upon in the same cycle (e.g. by the CALU). An ARAU operation may also be performed in the same cycle when using the indirect addressing mode. The DMOV function is useful for implementing algorithms that use the Z^-1delay operation, such as convolutions and digital filtering where data is being passed through a time window. The data move function can be used anywhere within predetermined blocks. The MACD (multiply and accumulate with data move) and the LTD (load TREG0 with data move and accumulate product) instructions use the data move function.

TBLR/TBLW (table read/write) instructions allow words to be transferred between program and data spaces. TBLR is used to read words from program memory into data memory. TBLW is used to write words from data memory to program memory.

As described above, the Central Arithmetic Logic Unit (CALU) 15 contains a 16-bit prescaler scaling shifter 65, a 16×16-bit parallel multiplier 27, a 32-bit Arithmetic Logic Unit (ALU) 21, a 32-bit accumulator (ACC) 23, and additional shifters 169 and 181 at the outputs of both the accumulator 23 and the multiplier 27. This section describes the CALU components and their functions.

The following steps occur in the implementation of a typical ALU instruction:

1) Data is fetched from the RAM 25 on the data bus.
2) Data is passed through the scaling shifter 65 and the ALU 21 where the arithmetic is performed, and
3) The result is moved into the accumulator 23.

One input to the ALU 21 is provided from the accumulator 23, and the other input is selected from the Product Register (PREG) 51 of the multiplier 27, a Product Register Buffer (BPR) 185, the Accumulator Buffer (ACCB) 31 or from the scaling shifters 65 and 181 that are loaded from data memory 25 or the accumulator 23.

Scaling shifter 65 advantageously has a 16-bit input connected to the data bus 111D via MUX 73 and a 32-bit output connected to the ALU 21 via MUX 77. The scaling shifter prescaler 65 produces a left shift of 0 to 16 bits on the input data, as programmed by loading a COUNT register 199. The shift count is specified by a constant embedded in the instruction word, or by a value in register TREG1. The LSBs of the output of prescaler 65 are filled with zeros, and the MSBs may be either filled with zeros or sign-extended, depending upon the status programmed into the SXM (sign-extension mode) bit of status register ST1.

The same shifter 65 has another input path from the accumulator 23 via MUX 73. When using this path the shifter 65 acts as a 0 to 16 bit right shifter. This allows the contents of the ACC to be shifted 0 to 16 bits right in a single cycle. The bits shifted out are lost and the bits shifted in are either zeros or copies of the original sign bit depending on the value of the SXM status bit.

The various shifters 65, 169 and 181 allow numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention.

The 32-bit ALU 21 and accumulator 23 implement a wide range of arithmetic and logical functions, the majority of which execute in a single clock cycle in the preferred embodiment. Once an operation is performed in the ALU 21, the result is transferred to the accumulator 23 where additional operations such as shifting may occur. Data that is input to the ALU may be scaled by the scaling shifter 181.

The ALU 21 is a general-purpose arithmetic unit that operates on 16-bit words taken from data RAM or derived from immediate instructions. In addition to the usual arithmetic instructions, the ALU can even perform Boolean operations. As mentioned hereinabove, one input to the ALU is provided from the accumulator 23, and the other input is selectively fed by MUX 77. MUX 77 selects the Accumulator Buffer (ACCB) 31 or secondly the output of the scaling shifter 65 (that has been read from data RAM or from the ACC), or thirdly, the output of product scaler 169. Product scaler 169 is fed by a MUX 191. MUX 191 selects either the Product Register PREG 51 or the Product Register Buffer 185 for scaler 169.

The 32-bit accumulator 23 is split into two 16-bit segments for storage via data bus 111D to data memory 25. Shifter 181 at the output of the accumulator provides a left shift of 0 to 7 places. This shift is performed while the data is being transferred to the data bus 111D for storage. The contents of the accumulator 23 remain unchanged. When the post-scaling shifter 181 is used on the high word of the accumulator 23 (bits 16-31), the MSBs are lost and the LSBs are filled with bits shifted in from the low word (bits 0-15). When the post-scaling shifter 181 is used on the low word, the LSB's are zero filled.

Floating-point operations are provided for applications requiring a large dynamic range. The NORM (normalization) instruction is used to normalize fixed point numbers contained in the accumulator 21 by performing left shifts. The four bits of temporary register TREG181 define a variable shift through the scaling shifter 65 for the LACT/ADDT/SUBT (load/add-to/subtract from accumulator with shift specified by TREG1) instructions. These instructions are useful in floating-point arithmetic where a number needs to be denormalized, i.e., floating-point to fixed-point conversion. They are also useful in applications such as execution of an Automatic Gain Control (AGC) going into a filter. The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value contained in the four LSBs of a temporary register TREG2195.

Registers TREG1 and TREG2 are fed by data bus 111D. A MUX 197 selects values from TREG1, TREG2 or from program data bus 101D and feeds one of them to a COUNT register 199. COUNT register 199 is connected to scaling shifter 65 to determine the amount of shift.

The single-cycle 0-to-16-bit right shift of the accumulator 23 allows efficient alignment of the accumulator for multiprecision arithmetic. This coupled with the 32-bit temporary buffers ACCB on the accumulator and BPR on the product register enhance the effectiveness of the CALU in multiprecision arithmetic. The accumulator buffer register (ACCB) provides a temporary storage place for a fast save of the accumulator. ACCB can be also used as an input to the ALU. ACC and ACCB can be stored into each other. The contents of the ACCB can be compared by the ALU against the ACC with the larger/smaller value stored in the ACCB (or in both ACC and ACCB) for use in pattern recognition algorithms. For instance, the maximum or minimum value in a string of numbers is advantageously found by comparing the contents of the ACCB and ACC, and if the condition is met then putting the minimum or maximum into one or both registers. The product register buffer (BPR) provides a temporary storage place for a fast save of the product register. The value stored in the BPR can also be added to/subtracted from the accumulator with the shift specified for the provided shifter 169.

An accumulator overflow saturation mode may be programmed through the SOVM and ROVM (set/reset overflow mode) instructions. When the accumulator 73 is in the overflow saturation mode and an overflow occurs, the overflow flag (OVM bit of register ST0) is set and the accumulator is loaded with either the most positive or the most negative number depending upon the direction of the overflow. The value of the accumulator upon saturation is 07FFFFFFFh (positive) or 0800000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the overflowed results are loaded into the accumulator with modification. (Note that logical operations do not result in overflow.)

A variety of branch instructions depend on the status conditions of the ALU and accumulator. These status conditions include the V (branch on overflow) and Z (branch on accumulator equal to zero), L (branch on less than zero) and C (branch on carry). In addition, the BACC (branch to address in accumulator) instruction provides the ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.

The accumulator has an associated carry bit C in register ST1 that is set or reset depending on various operations within the device. The carry bit allows more efficient computation of extended-precision products and additions or subtractions. It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the single bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other such nonarithmetic are control instructions. Examples of carry bit operation are shown in Table A-3.

TABLE A-3

Examples of Carry Bit Operation

C	MSB	LSB	C	MSB	LSB

X	FFFF	FFFF	ACC	X	0000	0000	ACC
	+	1			-	1
1	0000	0000		0	FFFF	FFFF
X	7FFF	FFFF	ACC	X	8000	0001	ACC

1 (OVM = 0)

2 (OVM = 0)

0	8000	0000		1	7FFFF	FFFF
1	0000	0000	ACC	X	FFFF	FFFF	ACC

0 (ADDC)

1 (SUBB)

0	0000	0001	1	FFFF	FFFE

The value added to or subtracted from the accumulator, shown in the example of Table A-3 may come from either the input scaling shifter, ACCR, PREG or BPR. The carry bit is set if the result of an addition or accumulation process generates a carry, or reset to zero if the result of a subtraction generates a borrow. Otherwise, it is reset after an addition or set after a subtraction.

The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions provided use the previous value of carry in their addition/subtraction operation. The ADCR (add ACCB to accumulator with carry) and the SBBR (subtract ACCR from accumulator with borrow) also use the previous value of carry C.

An exception to operation of the carry bit is the use of ADD with a shift count of 16 (add to high accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. The case of the ADD instruction sets the carry bit if a carry is generated, and this case of the SUB instruction resets the carry bit if a borrow is generated. Otherwise, neither instruction affects it.

Two branch instructions, BC and BNC, are provided for branching on the status of the carry bit. The SETC, CLRC and LST1 instructions can also be used to load the carry bit. The carry bit is set to one on a hardware reset.

The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM-1, SFR performs an arithmetic right shift, maintaining the sign of the accumulator data. When SXM=0, SFR performs a logical shift, shifting out the LSBs and shifting in a zero for the MSB. The SFL (shift accumulator left instruction is not affected by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT, RPTK, RPTR or RPTZ) instructions may be used with the shift and rotate instructions for multiple-bit shifts.

The 65-bit combination of the accumulator, ACCB, and carry bit can be shifted or rotated as described above using the SFLR, SFRR, RORR and ROLR instructions.

The accumulator can also be right-shifted 0-31 bits in two instruction cycles or 0-16 bits in one cycle. The BSAR instruction shifts the accumulator 1-16 bits based upon the four bit value in the instruction word. The SATL instruction shifts the accumulator to the right based upon the 4-LSBs of TREG1. The SATH instruction shifts the accumulator 16-bits if bit 5 of TREG1 is a one.

The 16×16-bit hardware multiplier 27 computes a signed or unsigned 32-bit product in a single machine cycle. All multiply instructions, except MPYU (multiply unsigned) instruction preform a signed multiply operation in the multiplier. That is, two numbers being multiplied are treated as two's-complement numbers, and the result is a 32-bit two's-complement number. The following three registers are associated with the multiplier.

The 16-bit temporary register (TREG0) 49 connected to the data bus that holds one of the operands for the multiplier.

The 32-bit product register (PREG) 51 that holds the product, and

The 32-bit product buffer (BPR) 185 that is used to temporarily store the PREG 51.

The output of the product register 51 and product buffer 185 can be left-shifted according to four product shift modes (PM), which are useful for implementing multiply/accumulate operations, fractional arithmetic or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode. The product is shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit two's-complement numbers (MPY). A four bit shift is used in conjunction with an MPYK instruction to eliminate the four extra sign bits gained in multiplying a 16-bit number times a 13-bit number. The output of PREG and BPR can instead be right-shifted 6 bits to enable the execution of up to 128 consecutive multiply/accumulates without the possibility of overflow. When right shift is specified, the product is sign-extended, regardless of the value of SXM.

An LT (load TREG0) instruction normally loads the TREG049 to provide one operand (from the data bus), and the MPY (multiply) instruction provides the second operand (also from the data bus). A multiplication can also be performed with an immediate operand using the MPYK instruction. In either case, a product can be obtained every two cycles.

Four multiply/accumulate instructions (MAC and MACD, MADS and MADD) fully utilize the computational bandwidth of the multiplier 27, allowing both operands to be processed simultaneously. A MUX 211 selects either data bus 111D or program data bus 101D to feed a second input of multiplier array 53. The data for these operations can be thus transferred to the multiplier each cycle via the program and data buses. This provides for single-cycle multiply/accumulates when used with repeat (RPT, RPTK, RTPR, RPTZ) instructions. The SQRA (square/add) and SQRS (square/subtract) instructions pass the same value to both inputs of the multiplier for squaring a data memory value.

The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended precision arithmetic operations. The unsigned contents of TREG0 are multiplied by the unsigned contents of the addressed data memory location, with the result placed in PREG. This allows operands of greater than 16 bits to be broken down into 16-bit words and processed separately to generate products of greater than 32-bits.

After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit Product Register (PREG) 51. The product from the PREG may be transferred to the ALU, to the Product Buffer (BPR) or to data memory 25 via the SPH (Store Product High) and SPL (Store Product Low). Temporarily storing the product in BPR for example is vital to efficient execution of algorithms such as the transposed form of the IIR (infinite impulse response) digital filter. Use of BPR avoids unnecessary subsequent recomputation of the product of the same two operands.

As discussed above, four product shift modes (PM) are available at the PREG and BPR outputs, which are useful when performing multiply/accumulate operations, fractional arithmetic, or justifying fractional products. The PM field of status register ST1 specifies the PM shift mode, as shown below:


PM	RESULTING SHIFT

00	NO SHIFT
01	LEFT SHIFT OF 1 BIT
10	LEFT SHIFT OF 4 BITS
11	RIGHT SHIFT OF 6 BITS

Left shirts specified by the PM value are useful for implementing fractional arithmetic or justifying fractional products, for example, the product of either two normalized, 16-bit, two's-complement numbers or two Q15 numbers contains two sign bits, one of which is redundant. Q15 format, one of the various types of Q format, is a number representation commonly used when performing operations on non-integer numbers. The single-bit-left-shift eliminates this extra sign bit from the product when it is transferred to the accumulator. This results in the accumulator contents being formatted in the same manner as the multiplicands. Similarly, the product of either a normalized, 16-bit, two's-complement or Q15 number and a 13-bit, two's-complement constant (MPYK) contains five sign bits, four of which are redundant. Here the four-bit shift property aligns the result as it is transferred to the accumulator.

Use of the right-shift PM value allows the execution of up to 128 consecutive multiply/accumulate operations without the threat of an arithmetic overflow, thereby avoiding the overhead of overflow management. The shifter can be disabled to cause no shift in the product when working with integer or 32-bit precision operations. Note that the PM right shift is always sign-extended regardless of the state of SXM.

System control is provided by the program counter 93, hardware stack 91, PC-related hardware, the external reset signal RS-, interrupts to an interrupt control 231, the status registers, and the repeat counters. The following sections describe the function of each of these components in system control and pipeline operation.

The processor has 16-bit Program Counter (PC) 93, and an eight deep hardware stack 91 provides PC storage. The program counter 93 addresses internal and external program memory 61 in fetching instructions. The stack 91 is used during interrupts and subroutines.

The program counter 93 addresses program memory 61, either on-chip or off-chip, via the Program Address Bus (PAB) 101A. Through the PAB, an instruction is addressed in program memory 61 and loaded via program data bus 101D into the Instruction Register (IR) for a decoder PLA 221. When the IR is loaded, the PC 93 is ready to start the next instruction fetch cycle. Decoder PLA (programmable logic array) 221 has numerous outputs for controlling the MUXes and all processor elements in order to execute the instructions in the processor instruction set. For example, decoder PLA 221 feeds command signals to a pipeline controller 225 which also has various outputs for implementing the pipelined processing operations so that the processor elements are coordinated in time. The outputs of pipeline controller 225 also include CALL, RET (RETURN), IAQ (interrupt acquisition) and IACK (interrupt acknowledge).

Data memory 25 is addressed by the program counter 93 during a BLKD instruction, which moves data blocks from one section of data memory to another. The contents of the accumulator 23 may be loaded into the PC 93 in order to implement "computed GOTO" operations. This can be accomplished using the BACC (branch to address in accumulator) or CALA (call subroutine indirect) instructions.

To start a new fetch cycle, the PC 93 is loaded either with PC+1 or with a branch address (for instructions such as branches, calls, or interrupts). In the case of special conditional branches where the branch is not taken, the PC is incremented once more beyond the location of the branch immediate. In addition to the conditional branches, the processor has a full complement of conditional calls and returns.

The processor 13, 15 operates with a four deep pipeline. This means any discontinuity in the PC 93 (i.e., branch call or interrupt) forces the device to flush two instructions from the pipeline. To avoid these extra cycles, the processor has a full set of delayed branches, calls and returns. In the delayed operation of the branches, calls or returns, the two instructions following the delayed instruction are executed while the instructions at the branch address are being fetched, therefore, not flushing the pipeline and giving an effective two cycle branch. If the instruction following the delayed branch is a two word instruction, then only it will be executed.

A further feature allows the execution of the next single instruction N+1 times. N is defined by loading a 16-bit RPTC (repeat counter) in registers 85. When this repeat feature is used, the instruction is executed, and the RPTC is decremented until the RPTC goes to zero. This feature is useful with many instructions, such as NORM (normalize contents of accumulator), MACD (multiply and accumulate with data move), and SUBC (conditional subtract). When repeating instructions, the program address and data buses are freed to fetch a second operand in parallel with the data address and data buses. This allows instructions such as MACD and BLKP to effectively execute in a single cycle when repeated.

The PC stack 91 is 16-bits wide and eight levels deep. The PC stack 91 is accessible through the use of the push and pop instructions. Whenever the contents of the PC 93 are pushed onto the top of the stack 91, the previous contents of each level are pushed down, and the bottom (eighth) location of the stack is lost. Therefore, data is lost if more than eight successive pushes occur before a pop. The reverse happens on pop operations. Any pop after seven sequential pops yields the value of the bottom stack level. All of the stack levels then contain the same value. The two instructions, PSHD and POPD, push a data memory value onto the stack or pop a value from the stack to or from data memory via data bus 111D. These instructions allow a stack to be built in data memory for the nesting of subroutines/interrupts beyond eight levels.

Instruction pipelining involves the sequence of bus operations that occurs during instruction execution. The instruction—fetch, decode, operand—fetch, execute pipeline is essentially visible to the user, except in some cases where the pipeline must be broken (such as for branch instructions). In the operation of the pipeline the instruction fetch, decode, operand fetch, and execute operations are independent which allow instruction executions to overlap. Thus, during any given cycle, one to four different instructions can be active, each at a different stage of completion, resulting in a four deep pipeline.

Reset (RS-) is a non-maskable external interrupt that can be used at any time to put the processor 13, 15 into a known state. Reset is typically applied after powerup when the machine is in an unknown state.

Driving the RS-signal low causes the processor to terminate execution and forces the program counter 93 to zero. RS- affects various registers and status bits. At powerup, the state of the processor 13, 15 is undefined. For correct system operation after powerup, a reset signal is asserted low for five clock cycles to reset the device 11. Processor execution begins at location 0, which normally contains a B (BRANCH) statement to direct program execution to the system initialization routine.

Upon receiving an RS- signal, the following actions take place:

1) A logic 0 is loaded into the CNF. (configuration control) bit in status register ST1, mapping all on-chip data RAM into data address space.
2) The Program Counter (PC) is set to 0, and the address bus A15-A0 is driven with all zeros while RS- is low.
3) All interrupts are disabled by setting the INTM (interrupt mode) bit to 1. (Note that RS- is non-maskable). The interrupt flag register (IFR) is cleared.
4) Status bits: ("--" means "loaded into")
0--OV, 1--XF, 1--SXM, 0--PM, 1--HM, 0--BRAF, 0--TRM, 0--NDX, 0--CENB1, 0--CENB2, Inverse of TxM--MP/MX- and RAM, 0--OVLY, 0--IPTR, and 1--C. 0--OVLY, 0—IPTR, and 1--C.
(The remaining status bits remain undefined and should be initialized appropriately).
5) The global memory allocation register (GREG) is cleared to make all memory local.
6) The RPTC (repeat counter) is cleared.
7) The IACK—(interrupt acknowledge) signal is generated in the same manner as a maskable interrupt.
8) A synchronized reset signal SRESET—is sent to the peripheral circuits to initialize them.

Execution starts from location 0 of program memory when the RS- signal is taken high. Note that if RS- is asserted while in the hold mode, normal reset operation occurs internally, but all buses and control lines remain in the high-impedance state. Upon release of HOLD- and RS-, execution starts from location zero.

There are four key status and control registers for the processor core. ST0 and ST1 contain the status of various conditions while PMST and CBCR contain extra status and control information for control of the enhanced features or the processor core. These registers can be stored into data memory and loaded from data memory, thus allowing the status of the machine to be saved and restored for subroutines. Each of these registers has an associated one-deep stack for automatic context saves when an interrupt trap is taken. The stack is automatically popped upon a return from interrupt.

The PMST and CBCR registers reside in the memory/mapped register 85 space in page zero of data memory space. Therefore they can be acted upon directly by the CALU and the PLU. They can be saved the same as any other data memory location.

ST0 and ST1 are written to using the LST and LST1 instructions respectively and read from using the SST and SST1 instructions (with the exception of the INTM bit that is not affected by the LST instruction).

Unlike the PMST and CBCR registers, the ST0 and ST1 registers do not reside in the memory map and therefore are not handled using the PLU instructions. The individual bits of these registers can be set or cleared using the SETC and CLRC instructions. For example, the sign-extension mode is set with SETC SXM or cleared with CLRC SXM.

Table A-4 defines all the status/control bits.

TABLE A-4

Status Register Field Definitions

FIELD	FUNCTION

ARB	Auxiliary Register Pointer Buffer. ST1 bits
	15-13. Whenever the ARP is loaded, the old
	ARP value is copied to the ARB except during an
	LST instruction. When the ARB is loaded via a
	LST1 instruction, the same value is also copied
	to the ARP.
ARP	Auxiliary Register Pointer. ST0 bits 15-13.
	This three-bit field selects the AR to be used
	in indirect addressing. When ARP is loaded, the
	old ARP value is copied to the ARB register.
	ARP may be modified by memory-reference
	instructions when using indirect addressing, and
	by the LARP, MAR, and LST instructions. ARP is
	also loaded with the same value as ARB when an
	LST1 instruction is executed.
BRAF	Block Repeat Active Flag. PMST bit 0. This
	bit indicates whether (BRAF = 1) or not (BRAF =
	0) block repeat is currently active. Writing a
	zero to this bit deactivates block repeat. BRAF
	is set to zero upon reset.
C	Carry Bit. ST1 bit 9. This bit is set to 1 if
	the result of an addition generates a carry, or
	reset to 0 if the result of a subtraction
	generates a borrow. Otherwise, it is reset
	after an addition or set after a subtraction,
	except if the instruction is ADD or SUB. ADD
	can only set and SUBH only reset the carry bit,
	but does not affect it otherwise. The single
	bit shift and rotate instructions also affect
	this bit, as well as the SETC, CLRC, LST1
	instructions. Branch instructions are provided
	to branch on the status of C. C is set to 1 on
	a reset.
CAR1	Circular Buffer 1 Auxiliary Register. CBCR
	bits 2-0. These three bits identify which
	auxiliary register is assigned to circular
	buffer 1.
CAR2	Circular Buffer 2 Auxiliary Register. CBCR
	bits 6-4. These three bits identify which
	auxiliary register is assigned to circular
	buffer 2.
CENB1	Circular Buffer 1 Enable. CBCR bit 3. This bit,
	when set to 1, enables circular buffer 1. When
	set to zero, disables circular buffer 1. Set to
	zero upon reset.
CENB2	Circular Buffer 2 Enable. CBCR bit 7. This bit,
	when set to 1, enables circular buffer 2. When
	set to zero circular buffer 2 is disabled.
	CBEN2 is set to zero upon reset.
CNF	On-chip RAM Configuration Control bit. ST1 bit
	12. If set to 0, the reconfigurable data RAM
	blocks are mapped to data space; otherwise, they
	are mapped to program space. The CNF may be
	modified by the CNFD, CNFP, and LST1
	instructions. RE- resets the CNF to 0.
DP	Data Memory Page Pointer. ST0 bits 8-0. The
	9-bit DP register is concatenated with the 7
	LSBs of an instruction word to form a direct
	memory address of 16 bits. DP may be modified
	by the LST, LDP, and LDPK instructions.
FO	Format bit. ST1 bit 3. This bit is used to
	configure the serial port format.
FSM	Frame Synchronous Mode bit. ST1 bit 5. This bit
	is used in configuration of the framing mode of
	the serial port.
HM	Hold Mode bit. ST1 bit 6. When HM = 1, the
	processor halts internal execution when
	acknowledging an active HOLD-. When HM = 0, the
	processor may continue execution out of internal
	program memory but puts its external interface
	in a high-impedance state. This bit is set to 1
	by reset.
INTM	Interrupt Mode bit. ST0 bit 9. When set to 0,
	all unmasked interrupts are enabled. When set
	to 1, all maskable interrupts are disabled.
	INTM is set and reset by the DINT and
	EINT instructions. RS- and LACK- also set INTM.
	INTM has no effect on the unmaskable RS- and
	NM1- interrupts. INTM is unaffected by the LST
	instruction.
IPTR	Interrupt vector pointer PMST bits 15-11. These
	five bits point to the 2K page where the
	interrupt vectors reside. This allows the user
	to remap interrupt vectors to RAM for boot
	loaded operations. At reset these bits are all
	set to zero. Therefore the reset vector always
	resides at zero in the program memory space.
MP/	MicroProcessor/MicroComputer bit, PMST bit 3.
MC-	When set to zero the on-chip ROM is enabled.
	When set to one the on-chip ROM is not
	addressable. This bit is set to the inverse of
	TXM at reset.
NDX	Enable Extra Index Register. PMST bit 2. When
	set to 0, the ARAU uses ARO for indexing and
	address compare. When set to 1, the ARAU uses
	INDX for indexing and ARCR for address compare.
	Upon reset, this bit is set to zero.
OV	Overflow Flag bit. ST0 bit 12. As a latched
	overflow signal, OV is set to 1 when overflow
	occurs in the ALU. Once an overflow occurs, the
	OV remains set until a reset, BV, BNV, or LST
	instructions clears OV.
OVLY	OVerLAY the on-chip program memory in data
	memory space. PMST bit 5. If set to zero the
	memory is addressable in program space only. If
	set to one it is addressable in both program and
	data space. Set to zero at reset.
OVM	Overflow Mode bit. ST0 bit 11. When set to 0,
	overflowed results overflow normally in the
	accumulator. When set to 1, the accumulator is
	set to either its most positive or negative
	value upon encountering an overflow. The SOVM
	and ROVM instructions set and reset this bit,
	respectively. LST may also be used to modify
	the OVM.
PM	Product Shift Mode. ST1 bits 1-0. If these two
	bits are 00, the multiplier's 32-bit product or
	buffer is loaded into the ALU with no shift. If
	PM = 01, the PREG or BPR output is left-shifted
	one place and loaded into the ALU, with the LSB
	zero-filled. If PM = 10, the PREG or BFR output
	is left-shifted by four bits and loaded into
	the ALU, with the LSBs zero-filled. PM = 11
	produces a right shift of six bits,
	sign-extended. Note that the PREG or BPR
	contents remain unchanged. The shift takes
	place when transferring the contents of the PREG
	or BPR to the ALU. PM is loaded by the SPM and
	LST1 instructions. The PM bits are cleared by
	RS-.
RAM	Enable/Disable on-chip RAM. PMST bit 4. Set to
	inverse of TXM at reset. If set to zero the
	on-chip program RAM is disabled. If set to one
	the on-chip program RAM is enabled.
SXM	Sign-Extension Mode bit. ST1 bit 10. SXM = 1
	produces sign extension on data as it is passed
	into the accumulator through the scaling
	shifter. SXM = 0 suppresses sign extension.
	SXM does not affect the definition or certain
	instructions; e.g., the ADDS instruction
	suppresses sign extension regardless of SXM.
	This bit is set and reset by the SSXM and RSXM
	instructions, and may also be loaded by LST1.
	SXM is set to 1 by reset.
TC	Test/Control Flag bit. ST1 bit 11. The TC bit
	is affected by the BIT, BITT, CMPR, LST1, NORM,
	CPLK, XPLK, OPLK, APLK, XPL, OPL, and APL
	instructions. The TC bit is set to a 1 if a bit
	tested by BIT or BITT is a 1, if a compare
	condition tested by CMPR exists between ARCR and
	another AR pointed to by ARP, if the
	exclusive-OR function of the two MSBs of the
	accumulator is true when tested by a NORM
	instruction, if the long immediate value is
	equal to the data value on the CPLK instruction,
	or if the result of the logical function (XPLK,
	OPLK, APLK, XPL, OPL or APL) is zero. Fourteen
	conditional branch, call and return instructions
	provide operations based upon the value of TC:
	BBZ, BBZD, BBNZ, BBNZD, CBZ, CBZD, CBNZ, CBNZD,
	RBZ, RJBZD, RBNZ, RBNZD, CEBZ, and CEBNZ.
TRM	Enable Multiple TREG's. PMST bit 1. When TRM
	is set to zero, any write to any of TREG0, TREG1
	or TREG2 writes to all three. When TRM
	is set to one, TREG0, TREG1, and TREG2 are
	individually selectable. TRM is set to zero at
	reset.
TXM	Transmit Mode Bit. ST1 bit 2. This bit is
	used in configuration of the transmit clock pin
	of the serial port.
XF	XF pin status bit. ST1 bit 4. This bit
	indicates the current level of the external
	flag.

The repeat counter (RPTC) in registers 85 is a 16-bit counter, which when loaded with a number N, causes the next single instruction to be executed N+1 times. The RPTC can be loaded with a number from 0 to 255 using the RPTK instruction or a number from 0 to 65535 using the RPT, RPTR, or RPTZ instructions. This results in a maximum of 65536 executions of a given instruction. RPTC is cleared by reset. Both the RPTR and the RPTZ instructions load a long immediate value into RPTC and the RPTZ also clears the PREG and ACC.

The repeat feature can be used with instructions such as multiply/accumulates (MAC/MACD), block moves (BLXD/BLKP), I/O transfers (IN/CUT), and table read/writes (TBLR/TBLW). These instructions, although normally multi-cycle, are pipelined when using the repeat feature, and effectively become single-cycle instructions. For example, the table read instruction may take three or more cycles to execute, but when repeated, a table location can be read every cycle.

A block repeat feature provides zero overhead looping for implementation of FOR or DO loops. The function is controlled by three registers (PASR, PAER and BRCR) in registers 85 and the BRAF bit in the PMST. The Block Repeat Counter Register (BRCR) is loaded with a loop count or 0 to 65535. Then the RPTB (repeat block) instructions is executed, thus loading the Program Address Start Register (PASR) with the address of the instruction following the RPTB instruction and loading the Program Address End Register (PAER) with its long immediate operand. The long immediate operand is the address of the last instruction in the loop. The BRAF bit is automatically set active by the execution of the RPTB instruction so the loop starts. With each PC update, the PAER is compared to the PC. If they are equal the BRCR is decremented. If the BRCR is greater than or equal to zero, the PASR is loaded into the PC thus starting the loop over.

The equivalent to a WHILE loop can be implemented by setting the BRAF bit to zero if the exit condition is met. If this is done, the program completes the current pass through the loop but not go back to the top. The bit must be set at least three instructions before the end of the loop to exit the current loop. Block repeat loops can be exited and returned to without stopping and restarting the loop. Subroutine calls and branches and interrupts do not necessarily affect the loop. When program control is returned to the loop, the loop execution is resumed.

Loops can be nested by saving the three registers PASR, PAER and BRCR prior to entry of an internal loop and restoring them upon completion of the internal loop and resetting of the BRAF bit. Since it takes a total of 12 cycles to save (6 cycles) and restore (6 cycles) the block repeat registers, smaller internal loops can be processed with the BANZD looping method that take two extra cycles per loop (i.e., if the loop count is less than 6 it may be more efficient to use the BANZD technique).

When operating in the powerdown mode, the processor core enters a dormant state and dissipates considerably less power than the power normally dissipated by the device. Powerdown mode is invoked either by executing an IDLE instruction or by driving the HOLD- input low while the HM status bit is set to one.

While in powerdown mode, all of the internal contents of processor 13, 15 are maintained to allow operation to continue unaltered when powerdown mode is terminated. Powerdown mode, when initiated by an IDLE instruction, is terminated upon receipt of an interrupt. When powerdown mode is initiated via the HOLD- signal it is terminated when the HOLD- goes inactive.

The power requirements can be further lowered to the sub-milliamp range by slowing down or even stopping the input clock. RS- is suitably activated before stopping the clock and held active until the clock is stabilized when restarting the system. This brings the device back to a known state. The contents of most registers and all on-chip RAM remain unchanged. The exceptions include the registers modified by a device reset.

The Peripheral Logic Unit (PLU) 41 of FIG. 1B is used to directly set, clear, toggle or test multiple bits in a control/status register or any data memory location. The PLU provides a direct logic operation path to data memory values without affecting the contents of the accumulator or product register. It is used to set or clear multiple control bits in a register or to test multiple bits in a flag register.

The PLU 41 operates by fetching one operand via data bus 111D from data Memory space, fetching the second from either long immediate on the program bus 101D or a DBMR (Dynamic Bit Manipulation Register) 223 via a MUX 225. The DBMR is previously loaded from data bus 111D. Then the PLU executes its logic operation, defined by the instruction on the two operands. Finally, the result is written via data bus 111D to the same data location that the first operand was fetched from.

The PLU allows the direct manipulation of bits in any location in data memory space. This direct bit-manipulation is done with by ANDing, ORing, XORing or loading a 16-bit long immediate value to a data location. For example, to initialize the CBCR (Circular Buffer Control Register) to use AR1 for circular buffer 1 and AR2 for circular buffer 2 but not enable the circular buffers, execute:

SPLK 021h, CBCR Store Peripheral Long Immediate
To later enable circular buffers 1 and 2 execute:
OPLK 088h, CBCR Set bit 7 and bit 3 in CBCR

Testing for individual bits in a specific register or data word is still done via the BIT instruction, however, a data word can be tested against a particular pattern with the CPLK (Compare Peripheral Long Immediate) instruction. If the data value is equal to the long immediate value, then the TC bit is set to one. If the result of any PLU instruction is zero then the TC bit is set.

The bit set, clear, and toggle functions can also be executed with a 16-bit dynamic register DBMR value instead of the long immediate value. This is done with the following three instructions: XPL (XOR DBMR register to data); OPL (OR DBMR register to data); and APL (AND DBMR Register to data).

The processor has sixteen external maskable user interrupts (INT16-INT1) available for external devices that interrupt the processor. Internal interrupts are generated by the serial port (RINT and XINT), by the timer (TINT), by parity checkers (PNTL and PNTH), and by the software interrupt (TRAP) instruction. Interrupts are prioritized with reset (RS-) having the highest priority and INT15 having the lowest priority.

An interrupt control block 231 feeds program data bus 101D. Vector locations and priorities for all internal and external interrupts are shown in Table A-5. The TRAP instruction, used for software interrupts, is not prioritized but is included here since it has its own vector location. Each interrupt address has been spaced apart by two locations so that branch instructions can be accomodated in those locations.

TABLE A-5

Interrupt Locations and Priorities

LOCATION

PRIOR-

NAME	DEC	HEX	ITY	FUNCTION

RS-	0	0	1	EXTERNAL RESET SIGNAL
			(high-
			est)
INT1-	2	2	3	EXTERNAL USER INTERRUPT #1
INT2-	4	4	4	EXTERNAL USER INTERRUPT #2
INT3-	6	6	5	EXTERNAL USER INTERRUPT #3
INT4-	8	8	6	EXTERNAL USER INTERRUPT #4
INT5-	10	A	7	EXTERNAL USER INTERRUPT #5
INT6-	12	C	8	EXTERNAL USER INTERRUPT #6
INT7-	14	E	9	EXTERNAL USER INTERRUPT #7
INT8-	16	10	10	EXTERNAL USER INTERRUPT #8
INT9-	18	12	11	EXTERNAL USER INTERRUPT #9
INT10-	20	14	12	EXTERNAL USER INTERRUPT #10
INT11-	22	16	13	EXTERNAL USER INTERRUPT #11
INT12-	24	18	14	EXTERNAL USER INTERRUPT #12
INT13-	26	1A	15	EXTERNAL USER INTERRUPT #13
INT14-	28	1C	16	EXTERNAL USER INTERRUPT #14
INT15-	30	1E	17	EXTERNAL USER INTERRUPT #13
INT16-	32	20	18	EXTERNAL USER INTERRUPT #14
TRAP	34	22	N/A	TRAP INSTRUCTION VECTOR
NMI	36	24	2	NON-MASKABLE INTERRUPT

In FIG. 1B, a Bus Interface Module BIM 241 is connected between data bus 111D and program data bus 101D. BIM 241 on command permits data transfers between buses 101D and 111D and increases the architectural flexibility of the system compared to either the classic Harvard architecture or Von Neumann architecture.

Inventive systems including processing arrangements and component circuitry made possible by improvements to the processor 13, 15 are discussed next. For general purpose digital signal processing applications, these systems advantageously perform convolution, correlation, Hilbert transforms, Fast Fourier Transforms, adaptive filtering, windowing, and waveform generation. Further applications involving in some cases the general algorithms just listed are voice mail, speech vocoding, speech recognition, speaker verification, speech enhancement, speech synthesis and text-to-speech systems.

Instrumentation according to the invention provides improved spectrum analyzers, function generators, pattern matching systems, seismic processing systems, transient analysis systems, digital filters and phase lock loops for applications in which the invention is suitably utilized.

Automotive controls and systems according to the invention suitably provide engine control, vibration analysis, anti-skid braking control, adaptive ride control, voice commands, and automotive transmission control.

In the naval, aviation and military field, inventive systems are provided and improved according to the invention to provide global positioning systems, processor supported navigation systems, radar tracking systems, platform stabilizing systems, missile guidance systems, secure communications systems, radar processing and other processing systems.

Further systems according to the invention include computer disk drive motor controllers, printers, plotters, optical disk controllers, servomechanical control systems, robot control systems, laser printer controls and motor controls generally. Some of these control systems are applicable in the industrial environment as robotics controllers, auto assembly apparatus and inspection equipment, industrial drives, numeric controllers, computerized power tools, security access systems and power line monitors.

Telecommunications inventions contemplated according to the teachings and principles herein disclosed include echo cancellers, ADPCM transcoders, digital PBXs, line repeaters, channel multiplexers, modems, adaptive equalizers, DTMF encoders and DTMF decoders, data encryption apparatus, digital radio, cellular telephones, fax machines, loudspeaker telephones, digital speech interpolation (DSI) systems, packet switching systems, video conferencing systems and spread-spectrum communication systems.

In the graphic imaging area, further inventions based on the principles and devices and systems disclosed herein include optical character recognition apparatus, 2-D rotation apparatus, robot vision systems, image transmission and compression apparatus, pattern recognition systems, image enhancement equipment, homomorphic processing systems, workstations and animation systems and digital mapping systems.

Medical inventions further contemplated according to the present invention include hearing aids, patient monitoring apparatus, ultrasound equipment, diagnostic tools, automated prosthetics and fatal monitors, for example. Consumer products according to the invention include high definition television systems such as high definition television receivers and transmission equipment used at studios and television stations. Further consumer inventions include music synthesizers, solid state answering machines, radar detectors, power tools and toys and games.

It is emphasized that the system aspects of the invention contemplated herein provide advantages of improved system architecture, system performance, system reliability and economy.

For example, in FIG. 2, an inventive industrial process and protective control system 300 according to the invention includes industrial sensors 301 and 303 for sensing physical variables pertinent to a particular industrial environment. Signals from the sensors 301 and 303 are provided to a signal processor device 11 of FIGS. 1A and 1B which include the PLU (parallel logic unit) improvement 41 of FIG. 1B. An interface 305 includes register locations A, B, C; D, E, F, G and H and drivers (not shown). The register locations are connected via the drivers and respective lines 307 to an industrial process device driven by a motor 311, relay operated apparatus controlled by relays 313 and various valves including a solenoid valve 315.

In the industrial process and protective control environment, various engineering and economic considerations operate at cross purposes. If the speed or throughput of the industrial process is to be high, heavy burdens are placed on the processing capacity of device 11 to interpret the significance of relatively rapid changes occurring in real time as sensed by sensors 301 and 303. On the other hand, the control functions required to respond to the real-world conditions sensed by sensors 301 and 303 must also be accomplished swiftly. Advantageously, the addition of PLU 41 resolves conflicting demands on device 11, with negligible additional costs when device 11 is fabricated to a single semiconductor chip. In this way, the industrial processing rate, the swiftness of protective control and the precision of control are considerably enhanced.

In FIG. 3, an inventive automotive vehicle 321 includes a chassis 323 on which is mounted wheels and axles, an engine 325, suspension 327, and brakes 329. An automotive body 331 defines a passenger compartment which is advantageously provided with suspension relative to chassis 323.

An active suspension 335 augments spring and absorber suspension technique and is controlled via an interface 341 having locations for bits A, B, C, D, E, F, G, H, I, J, K, L, M and N. A parallel computation processor 343 utilizes computation units of the type disclosed in FIGS. 1A and 1B and includes at least one parallel logic unit 41 connected to data bus 351D and program data bus 361D. Numerous sensors include sensors 371, 373 and 375 which monitor the function of suspension 335, engine operation, and anti-skid braking respectively.

An engine control system 381 is connected to several of the locations of interface 341. Also an anti-skid braking control system 383 is connected to further bits of interface 341. Numerous considerations of automotive reliability, safety, passenger comfort, and economy place heavy demands on prior automotive vehicle systems.

In the invention of FIG. 3, automotive vehicle 321 is improved in any or all of these areas by virtue of the extremely flexible parallelism and control advantages of the invention.

The devices such as device 11 which are utilized in the systems of FIGS. 2 and 3 and further systems described herein not only address issues of increased device performance, but also solve industrial system problems which determine the user's overall system performance and cost.

A preferred embodiment device 11 executes an instruction in 50 nanoseconds and further improvements in semiconductor manufacture make possible even higher instruction rates. The on-chip program memory is RAM based and facilitates boot loading of a program from inexpensive external memory. Other versions are suitably ROM based for further cost reduction.

An inventive digitally controlled motor system 400 of FIG. 4 includes a digital controller 401 having a device 11 of FIGS. 1A and 1B. Digital controller 401 supplies an output u(n) to a zero order hold circuit ZOH 403. ZOH 403 supplies control output u(t) to a DC servomotor 405 in industrial machinery, home appliances, military equipment or other application systems environment. Connection of motor 405 to a disk drive 406 is shown in FIG. 4.

The operational response of servomotor 405 to the input u(t) is designated y(t). A sensor 407 is a transducer for the motor output y(t) and feeds a sampler 409 which in its turn supplies a sampled digitized output y(n) to a subtractor 411. Sampler 409 also signals digital controller 401 via an interrupt line INT-. A reference input r(n) from human or automated supervisory control is externally supplied as a further input to the subtracter 411. An error difference e(n) is then fed to the digital controller 401 to close the loop. Device 11 endows controller 401 with high loop bandwidth and multiple functionality for processing and control of other elements besides servomotors as in FIG. 2. Zero-overhead interrupt context switching in device 11 additionally enhances the bandwidth and provides an attractive alternative to polling architecture.

In FIG. 5, a multi-variable state controller 421 executes advanced algorithms utilizing the device 11 processor. State controller 421 receives a reference input r(n) and supplies an output u(n) to a motor 423. Multiple electrical variables (position x1, speed x2, current x3 and torque x4) are fed back to the state controller 421. Any one or more of the four variables x1-x4 (in linear combination for example) are suitably controlled for various operational purposes. The system can operate controlled velocity or controlled torque applications, and run stepper motors and reversible motors.

In FIG. 6, a motor 431 has its operation sensed and sampled by a sampler 433. A processor 435 including device 11 is interrupt driven by sampler 433. Velocity information determined by unit 433 is fed back to processor 435 improved as described in connection with FIGS. 1A and 1B. Software in program memory 61 of FIG. 1A is executed as estimation algorithm process 437. Process 437 provides velocity, position and current information to state controller process 439 of processor 435. A digital output u(n) is supplied as output from state controller 439 to a zero order hold circuit 441 that in turn drives motor 431.

The motor is suitably a brushless DC motor with solid state electronic switches associated with core, coils and rotor in block 431. The systems of FIGS. 4-6 accommodate shaft encoders, optical and Hall effect rotor position sensing and back emf (counter electromotive force) sensing of position from windings.

In FIG. 7, robot control system 451 has a motor-driven grasping mechanism 453 at the end of a robot arm 455. Robot arm 455 has a structure with axes of rotation 457.1, 457.2, 457.3 and 457.4. Sensors and high response accurately controllable motors are located on arm 455 at articulation points 459.1, 459.2, 459.3 and 459.4.

Numerous such motors and sensors are desirably provided for accurate positioning and utilization of robot arm mechanism 455. However, the numerous sensors and motors place conflicting demands on the system as a whole and on a controller 461. Controller 461 resolves these system demands by inclusion of device 11 of FIGS. 1A and 1B and interrupt-driven architecture of system 451. Controller 461 intercommunicates with an I/O interface 463 which provides analog-to-digital and digital-to-analoq conversion as well as bit manipulation by parallel logic unit 41 for the robot arm 455. The interface 463 receives position and pressure responses from the navigation motors 467 and sensors associated with robot arm 455 and grasping mechanism 453. Interface 463 also supplies control commands through servo amplifiers 465 to the respective motors 467 of robot arm 455.

Controller 461 has associated memory 467 with static RAM (SRAM) and programmable read only memory (PROM). Slower peripherals 469 are associated with controller 471 and they are efficiently accommodated by the page boundary sensitive wait state features of controller 461. The controller 461 is also responsive to higher level commands supplied to it by a system manager CPU 473 which is responsive to safety control apparatus 475. System manager 473 communicates with controller 461 via I/O and RS 232 drivers 475.

The digital control systems according to the invention make possible performance advantages of precision, speed and economy of control not previously available. For another example, disk drives include information storage disks spun at high speed by spindle motor units. Additional controls called actuators align read and write head elements relative to the information storage disks.

The preferred embodiment can even provide a single chip solution for both actuator control and spindle motor control as well as system processing and diagnostic operations. Sophisticated functions are accommodated without excessively burdening controller 461. A digital notch filter can be implemented in controller 461 to cancel mechanical resonances. A state estimator can estimate velocity and current. A Kalman filter reduces sensor noise. Adaptive control compensates for temperature variations and mechanical variations. Device 11 also provides on-chip PWM pulse width modulation outputs for spindle motor speed control. Analogous functions in tape drives, printers, plotters and optical disk systems are readily accommodated. The inventive digital controls provide higher speed, more precise speed control, and faster data access generally in I/O technology at comparable costs, thus advancing the state of the art.

In missile guidance systems, the enhanced operational capabilities of the invention provide more accurate guidance of missile systems, thereby reducing the number of expensive missiles required to achieve operational objectives. Furthermore, equivalent performance can be attained with fewer processor chips, thus reducing weight and allowing augmented features and payload enhancements.

In FIG. 8, a satellite telecommunication system according to the invention has first stations 501 and 503 communicating by a satellite transmission path having a delay of 250 milliseconds. A far end telephone 505 and a near end telephone 507 are respectively connected to earth stations 501 and 503 by hybrids 509 and 511. Hybrids 509 and 511 are delayed eight milliseconds relative to the respective earth stations 501 and 503. Accordingly, echo cancellation is necessary to provide satisfactory telecommunications between far end telephone 505 and near end telephone 507. Moreover, the capability to service numerous telephone conversation circuits at once is necessary. This places an extreme processing burden on telecommunications equipment.

In FIG. 9, a preferred embodiment echo canceller 515 is associated with each hybrid such as 511 to improve the transmission of the communications circuit. Not only does device 11 execute echo cancelling algorithms at high speed, but it also economically services more satellite communications circuits per chip.

Another system embodiment is an improved modem. In FIG. 10, a process diagram of operations in device 11 programmed as a modem transmitter includes a scrambling step 525 followed by an encoding step 527 which provides quadrature digital signals I[nT_b] and Q[nT_b] to interpolation procedures 529 and 531 respectively. Digital modulator computations 533 and 535 multiply the interpolated quadrature signals with prestored constants from read only memory (ROM) that provide trigonometric cosine and sine values respectively. The modulated signals are then summed in a summing step 537. A D/A converter connected to device 11 converts the modulated signals from digital to analog form in a step 539. Gain control by a factor G1 is then performed in modem transmission and sent to a DAA.

In FIG. 11, a modem receiver using another device 11 receives analog communications signals from the DAA. An analog-to-digital converter A/D 521 digitizes the information for a digital signal processor employing device 11. High rates or digital conversion place heavy burdens on input processing of prior processors. Advantageously, DSP 11 provides zero-overhead interrupt context switching for extremely efficient servicing of interrupts from digitizing elements such as A/D 521 and at the same time has powerful digital signal processing coputational facility for executing modem algorithms. The output of device 11 is supplied to a universal synchronous asynchronous receiver transmitter (USART) 523 which supplies an output D[nT].

In FIG. 12, a process diagram of modem reception by the system of FIG. 11 involves automatic gain control by factor G2 upon reception from the DAA supplying a signal s(t) for analog-to-digital conversion at a sampling frequency fs. The digitized signal is s[nTs] and is supplied for digital processing involving first and second bandpass filters implemented by digital filtering steps BPF1 and BPF2 followed by individualized automatic gain control. A demodulation algorithm produces two demodulated signals I′[nTs] and Q′[nTs]. These two signals I′ and Q′ used for carrier recovery fed back to the demodulation algorithm. Also I′ and Q′ are supplied to a decision algorithm and operated in response to clock recovery. A decoding process 551 follows the decision algorithm. Decoding 551 is followed by a descrambling algorithm 555 that involves intensive bit manipulation by PLU 41 to recover the input signal d[nT].

As shown in FIG. 12, the numerous steps of the modem reception algorithm are advantageously accomplished by a single digital signal processor device 11 by virtue of the intensive numerical computation capabilities and the bit manipulation provided by PLU 41.

In FIG. 13, computing apparatus 561 incorporating device 11 cooperates with a host computer 563 via an interface 565. High capacity outboard memory 567 is interfaced to computer 561 by interface 569. The computer 561 advantageously supports two-way pulse code modulated (PCM) communication via peripheral latches 571 and 573. Latch 571 is coupled to a serial to parallel converter 575 for reception of PCM communications from external apparatus 577. Computer 561 communicates via latch 573 and a parallel to serial unit 579 to supply a serial PCM data stream to the external apparatus 577.

In FIG. 14, a video imaging system 601 includes device 11 supported by ROM 603 and RAM 605. Data gathering sensors 607.1 through 607.n feed inputs to a converter 509 which then supplies voluminous digital data to device 11. FIG. 14 highlights ALU 21 accumulator 23, multiplier array 53, product register 51 and has an addressing unit including ARAU 123. A control element 615 generally represents decoder PLA 221 and pipeline controller 225 of FIG. 1A. On-chip I/O peripherals (not shown) communicate with a bus 617 supplying extraordinarily high quality output to a video display unit 619. Supervisory input and output I/O 621 is also provided to device 11.

Owing to the advanced addressing capabilities in device 11, control 615 is operable on command for transferring the product from product register 51 directly to the addressing circuit 123 and bypassing any memory locations during the transfer. Because of the memory mapping, any pair of the computational core-registers of FIGS. 1A and 1B are advantageously accessed to accomplish memory-bypass transfers therebetween via data bus 111D, regardless of arrow directions to registers on those Figures. Because the multiplication capabilities of device 11 are utilized in the addressing function, the circuitry establishes an array in the electronic memory 605 wherein the array has entries accessible in the memory with a dimensionality of at least three. The video display 619 displays the output resulting from multi-dimensional array processing by device 11. It is to be understood, of course, that the memory 605 is not in and of itself necessarily multi-dimensional, but that the addressing is rapidly performed by device 11 so that information is accessible on demand as if it were directly accessible by variables respectively representing multiple array dimensions. For example, a three dimensional cubic array having address dimensions A1, A2 and A3 can suitably be addressed according to the equation N²×A3+N×A2+A1. In a two dimensional array, simple repeated addition according to an index count from register 199 of FIG. 1A is sufficient for addressing purposes. However, to accommodate the third and higher dimensions, the process is considerably expedited by introducing the product capabilities of the multiplier 53.

FIGS. 15 and 16 respectively show function-oriented and hardware block-oriented diagrams of video processing systems according to the invention. Applications for these inventive systems provide new workstations, computer interfaces, television products and high definition television (HDTV) products.

In FIG. 15, a host computer 631 provides data input to numeric processing by device 11. Video pixel processing operations 633 are followed by memory control operations 635. CRT control functions 637 for the video display are coordinated with the numeric processing 639, pixel processing 633 and memory control 635. The output from memory control 635 operations supplies frame buffer memory 641 and then a shift register 643. Frame buffer memory and shift register 641 and 643 are suitably implemented by a Texas Instruments device TMS 4161. A further shift register 645 supplies video information from shift register 643 to a color palette 647. Color palette 647 drives a display 649 which is controlled by CRT control 637. The color palette 647 is suitably a TMS 34070.

In FIG. 16, the host 631 supplies signals to a first device 11 operating as a DSP microprocessor 653. DSP 653 is supported by memory 651 including PROM, EPROM and SRAM static memory. Control, address and data information are supplied by two-way communication paths between DSP 653 and a second device 11 operating as a GSP (graphics signal processor) 655. GSP 655 drives both color palette 647 and display interface 657. Interface 657 is further driven by color palette 647. Display CRT 659 is driven by display interface 657. It is to be understood that the devices 11 and the system of FIG. 16 in general is operated at an appropriate clock rate suitable to the functions required. Device 11 is fabricated in micron level and sub-micron embodiments to support processing speeds needed for particular applicat