Method and apparatus for providing fast switching between floating point and multimedia instructions using any combination of a first register file set and a second register file set

Abstract

A system and method is provided that adds another floating point register set in the floating point execution unit of a microprocessor. Thus, when the floating point state, or environment is stored as an image into memory, it is also stored as a copy in the additional internal registers. When the state, or environment, is to be restored the necessary information (data and/or instructions) is normally present in the additional registers, thus saving CPU cycles by avoiding reloading the image from memory. The present invention allows for either of the two register sets (or a combination thereof) to be, at a given point in time, the working set, with the other being a shadow register set. All of the memory write cycles are monitored (snooped) to determine if the information in the on-chip image has been altered, since the last store operation. The shadowed register file will allow the state of the floating point register file to be kept "as is" on the occurrence of a task switch.

Claims

What is claimed is:

1. A data processing unit, comprising:

means for designating a working register set and a shadow register set from any combination of a first register set including first environment registers and a first register file and a second register set including second environment registers and a second register file after decoding of an instruction;

means for performing a first task using said working register set;

means for storing said working register set corresponding to said first task in said shadow register set upon a switch to a second task;

means for determining whether said shadow register set is modified; and

means for restoring said shadow register set upon a switch from said second task to said first task when said shadow register set is unmodified.

2. A data processing unit according to claim 1 wherein said means for determining comprises means for indicating that information included in any one of said first environment registers, said second environment registers, said first register file and said second register file has been modified.

3. A data processing unit according to claim 2 wherein said means for designating further comprises:

an environment pointer register for storing an environment pointer bit that designates whether said first environment registers or said second environment registers are included in said working set; and

a register file pointer register for storing a register pointer bit that designates whether said first register file or said second register file is included in said working set.

4. A data processing unit according to claim 3 wherein said means for determining further comprises:

an environment dirty bit register for storing an environment dirty bit that indicates whether one of said first environment registers or said second environment registers have been modified; and

a register file dirty bit register for storing a register dirty bit that indicates whether one of said first register file or said second register file has been modified.

5. A data processing unit according to claim 4 wherein said means for maintaining further comprises:

means for storing said working resister set corresponding to said first task in a memory.

6. A data processing unit according to claim 5 wherein said means for restoring comprises means for loading said working register set from said memory when said shadow register set has been modified upon a switch from said second task back to said first task.

7. A data processing unit according to claim 6 wherein said first task includes floating point operations and said second task includes multimedia operations.

8. A method for switching between a first task and a second task which are implemented on a data processing unit, comprising the steps of:

designating one of a first register set comprising a first environmental register and a first register file, a second register set comprising a second environmental register and a second register file, or a combination of said first register set and said second register set as a working register set after decoding of an instruction;

performing said first task using said working register set;

storing said working register set corresponding to said first task, in a shadow register set, upon a switch to said second task;

determining whether said first state information stored in said shadow register set is modified; and

restoring said first state information from said shadow register set upon a switch from said second task to said first task when said first state information is unmodified.

9. A method according to claim 8 wherein said step of determining comprises the step of indicating that information included in any one of said first environment registers, said second environment registers, said first register file and said second register file has been modified.

10. A method according to claim 9 wherein said step of designating further comprises the steps of:

storing an environment pointer bit, in an environment pointer register, that designates whether said first environment registers or said second environment registers are included in said working set; and

storing a register pointer bit, in a register file pointer register, that designates whether said first register file or said second register file is included in said working set.

11. A method according to claim 10 wherein said step of determining further comprises the steps of:

storing an environment dirty bit, in an environment dirty bit register, that indicates whether one of said first environment registers or said second environment registers have been modified; and

storing a register dirty bit, in a register file dirty bit register, that indicates whether one of said first register file or said second register file has been modified.

12. A method according to claim 11 wherein said first task includes floating point operations and said second task includes multimedia operations.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method and apparatus for saving and restoring the state of various registers in a microprocessor. More particularly, a system is provided which allows the state of a floating point execution unit to be restored without requiring all of the data to be restored from memory.

2. Description of Related Art

Based upon consumer demands for increased multimedia capabilities and functionality, the computer industry has responded with enhancements and new technology that will aid in the processing of multimedia computer software applications. One example is the multimedia extensions (MMX) to the Intel microprocessor architecture. These MMX instructions provide capabilities that will allow software vendors to create applications with enhanced multimedia functions.

The architecture of Intel microprocessors is such that MMX instructions use the floating point unit (FPU) registers for instruction computation. An MMX instructions once executed shall write over the previous floating point state. Thus, the previous floating point state cannot be preserved without first saving such FP state to memory. The previous floating point state can be restored by loading the FP information from memory, and the floating point instructions can continue execution from the FP state that is remaining. The Intel MMX architecture requires empty out (by executing an EMMS instruction) the state that the MMX instructions accumulate before the floating point instructions are allowed to be executed. Otherwise, a floating point exception will be generated. In other words, the MMX state must be erased and the floating point state must re reset before the floating point instructions can be executed without causing a floating point exception. Thus, the MMX state cannot be preserved without first being saved into memory, before execution of the EMMS instruction. The previous MMX state can be restored by loading the information from memory, and the MMX instruction can continue execution from the MMX state that is remaining. However, state restoration from memory will take a large number of CPU cycles and is very costly in terms of system performance.

The term "context switch" as used herein will refer to the state saving and restoring process. It should be noted that the floating point/MMX state does not have to be saved and then restored for certain types of instructions to execute. The present invention may have less utility in these cases where the loss of the state information does not affect the correctness of the execution of the code. The present invention is a technique that rapidly saves and restores the state of the floating point/MMX unit if it is determined by the programmer that the floating point/MMX state must be preserved.

The FPU circuitry within Intel x86 architecture microprocessors provide the user with an FPU data register file, having eight, 80 bit FPU data registers, which are accessed in a stack-like manner. The floating point registers are visible, and available for use by the programmer. The Intel architecture also provides a 16 bit control register and 16 bit status register. A data register tag word is also provided that contains eight, 2 bit fields, each associated with one of the eight data registers. The tag word is used to improve context switching and stack performance by maintaining empty/non-empty status for each of the eight data registers.

Further, the Intel architecture contains an instruction pointer to the memory location containing the instruction word and a data pointer to the memory location containing the operand associated with the current instruction (if any). Also, the last instruction opcode is stored in an eleven bit register. The aforementioned control register, status register, tag word, instruction pointer, data pointer and opcode define the floating point environment (ENV). This environment in combination with the floating point registers (REG) constitute the floating point state.

As noted above, when Intel architecture microprocessors execute MMX instructions the FPU registers are utilized for instruction computation. Thus, 64 bits of the 80 bit FPU registers will be utilized by MMX instructions. When a task switch from floating point operation to MMX, the environment and register state is saved using a floating point save (FNSAVE or FSAVE) instruction. A floating point store environment instruction (FNSTENV or FSTENV) will save the environment to memory. The FNSAVE instruction stores the floating point register state to main memory. The FNSTENV instruction stores the floating point environment to main memory. The floating point load environment (FLDENV) or floating point restore (FRSTOR) instructions are then executed to load the environment, or environment and registers, respectively, from main memory when floating point operations are to be resumed from the remaining state information. This context switching, due to the FLDENV and FRSTOR instructions, can cost as much as 32 to 95 CPU cycles, while the switching time due to instructions FNSTENV and FNSAVE can cost as much as 48 to 151 cycles. Thus, it can be seen that conventional techniques of saving and restoring the floating point context may take from 80 to 246 clock cycles to save the floating point state to main memory, and then restore the registers to their previous state, when switching between floating point and multimedia operations.

Usually, the FNSAVE and FRSTOR instructions are used in conjunction with one another, as are the FNSTENV and FLDENV instructions. It should be noted that FNSAVE, FRSTOR, FNSTENV and FLDENV instructions have been used by the Intel instruction set long before the introduction of MMX to the computer industry in 1996. These instructions become important to the execution of MMX instructions, since the MMX code shares floating point register usage with the Intel floating point instructions.

Therefore, a need exists for a technique that can quickly and efficiently save and restore the state of the floating point register file, when switching between floating point and multimedia operations, using a minimum number of clock cycles.

SUMMARY OF THE INVENTION

In contrast to the prior art, the present invention provides a system and method that reduces the latency associated with execution of save and load instructions, such as FNSAVE and FRSTOR, when switching tasks between floating point and multimedia operations.

Broadly, the present invention provides an additional floating point register set in the CPU. In this manner, when the CPU stores the floating point state, or environment as an image into memory, it also stores the state, or environment, as a copy in the additional internal registers. When the CPU needs to restore the state, or environment, the necessary information (data and/or instructions) in the additional registers, thus saving CPU cycles by avoiding reloading the image from main memory. As used herein, "on-chip image" will be used to refer to the state information as stored in the additional internal register set, and, "memory image" will be used as a reference to the state information as stored in main memory.

The present invention allows for either of the two register sets (or a combination thereof) to be, at a given point in time, the working set, with the other being a shadow register set. All of the memory write cycles are monitored (snooped) to determine if the information in the on-chip image has been altered, since the last store operation. If so, the memory image is loaded when a context switch occurs.

Generally, in single CPU systems an on chip memory write operation refers to the memory write which is generated from the CPU. It should be noted that, it is also possible for a bus master devices to generate a memory write operation in a single CPU system. However, the memory write operation generated from a bus master, other than the CPU, is note referred to as an on chip memory write.

The shadowed register file will allow the state of the floating point register file to be kept "as is" on the occurrence of a task switch to MMX, or another context. The present invention also provides environment and register pointer bits, along with environment and register dirty bits. These bits are stored in four, 1 bit registers.

There are two sets of registers in the architecture of the present invention, register set 0 and register set 1. Each set has its own floating point environment (ENV) registers and eight, 80 bit registers (REG) for floating point and/or multimedia instructions, i.e. MMX. A working register set constitutes the environment registers (control, status, tag, instruction/data pointers) and floating point registers from either set, which are being accessed by the processor. To the programmer, the working set is the visible floating point or MMX states. The shadowed register set constitutes environment registers and the floating point data registers which are not in the working set. The entire, or a portion of, the shadowed set is used to store the on-chip image, in response to the most recent FNSAVE or FSTENV instruction. In other words, the on-chip image is a subset of the shadowed set.

A snoop address register is provided which holds the address of the memory image from the most recent FNSAVE or FSTENV instruction. The environment pointer always points to the ENV registers of the working set, i.e. the bit is set=1 for environment register set 1 and set=0 for environment register set 0. The register pointer bit always points to the REG registers of the working set, i.e. floating point registers R0-R8. The environment dirty bit tracks the status of the environment registers of the shadowed set, while the register dirty bit tracks the status of the register of the shadowed set.

The pointer and dirty bits are used to facilitate the algorithm for the dual register set of the present invention. A new working set if formed by selectively picking the environment registers and floating point registers from both the working set and the shadowed set when one of the instructions FNSAVE, FRSTOR, FNSTENV of FLDENV are executed.

The present invention selectively picks the environment and registers using an algorithm which forms a new working set in a single CPU cycle. The present invention also maintains compatibility with the Intel x86 instruction set. It should be noted that the present invention allows for the dynamic creation of the working set from the environment of either register set 0 or 1 in combination with the register file from either register set 0 or 1. For example, the working set can include: the environment register from set 0 and the register file from set 0; the environment from set 1 and the register file from set 1; the environment from set 0 and the register file from set 1; or the environment from set 1 and the register file from register set 0.

Therefore, in accordance with the previous summary, objects, features and advantages of the present invention will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary microprocessor capable of implementing the preferred embodiments of the present invention;

FIG. 2 is a block diagram of the floating point unit of the microprocessor of FIG. 1;

FIG. 3 is a block diagram of the floating point state including the floating point register and floating point environment;

FIG. 4 shows the dual register sets of the present invention including the FPR, environment, snoop address register, dirty and pointer bit registers;

FIG. 5 is a block diagram showing the relationship between the working set registers, shadowed set and memory when an FSTENV instruction has been processed;

FIG. 6 is another block diagram of the relationship between the working set, shadowed set and memory when an FNSAVE instruction has been executed;

FIG. 7 is a block diagram showing one preferred embodiment of the present invention wherein the working set can include an environment from either register set 0 or 1 and a register file from the other register set 1 or 0, respectively;

FIG. 8 is a state machine table that defines a state machine for controlling the pointer bits;

FIG. 9 is another state machine table which provides a mechanism for controlling the dirty bits;

FIG. 10 is a state diagram of the mechanism for controlling the pointer bits; and

FIG. 11 is another state diagram that shows how the state of the dirty bits is controlled.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As noted previously, for microprocessors compatible with the Intel architecture, MMX instructions use the floating point unit (FPU) registers for instruction computation. Thus, a task switch may occur when the processor changes from executing FP instructions to MMX instructions, or vice versa. A task switch can also occur between various floating point tasks, where the state of the previous task must be saved by executing the FNSAVE instruction and restored by the FRSTOR instruction, or the like. For the purposes of clarity the present invention will be described using the example of a task switch between FP operations and MMX operations. However, the present invention contemplates task switches within the same context, e.g. floating point, and is useful in minimizing the number of clock cycles needed to save the previous state information when switching to another task, and restoring the first state when the operating system switches back to the first task.

It should be noted that context, or task switching can also be controlled by the operating system (OS), such as Windows 95, Windows NT, OS/2, or the like. When a context switch is desired, the operating system generates a trap which will be received by a trap handler. The trap handler then saves the state of the previous context by causing an FNSAVE instructions, FSTENV instructions, or the like to be executed. It should also be noted that task switching can occur within a single context. For example, a switch can occur between different tasks in the floating point context. Similarly, task switching can also occur entirely within the MMX context.

Referring to FIG. 1, a block diagram of an exemplary microprocessor capable of executing the Intel instruction set and implementing the present invention is shown generally by reference numeral 10. Those skilled in the art will understand that many other differently configured microprocessors can also be utilized to implement the present invention.

Bus interface unit (BIU) 11 interfaces the microprocessor components with a system bus 12. Main memory 13 and various input/output devices 23 are also connected to bus 12. I/O devices may include a diskette drive, keyboard, mouse, parallel port, and the like. Control, address and data information is transmitted from microprocessor 10 onto bus 12 via BIU 11. Further, control, address and data signals from memory 13 and I/O devices 23 are received by BIU 11 for use by microprocessor 10. It should be noted that the control, address and data information will include microprocessor instructions, as well as operand data which will be manipulated by the instructions.

Memory management is provided by determining the physical address using an addressing mode which calculates an offset address often referred to as an effective address. Depending on the operating mode of the CPU, the offset is then combined using memory management mechanisms to create a physical address that actually addresses the physical memory device(s). A memory management unit (MMU) (not shown) typically includes a translation lookaside buffer (TLB) which is a cache for the paging mechanism. In a typical microprocessor, similar to the one shown in FIG. 1, the TLB is a page table cache that automatically keeps the most commonly used page table entries in the processor. An address calculation unit is also provided for memory management operations and is used to calculate the physical address by computing an offset address (effective address). Generally, the effective address is calculated by adding together up to three values: a base, an index and a displacement. The base, if present, is the value in one of the 32 bit general registers at the time of the execution of the instruction. The index is also a value contained in one of the 32 bit general purpose registers. The index differs from the base in that the index is first multiplied by a scale factor of 1, 2, 4 or 8 before the summation is made. The third component added to the memory address calculation is the displacement which is a value of up to 32 bits which is supplied as part of the instruction.

Load/store functions are implemented by load/store unit 22 which executes load and store instructions on an arithmetic logic unit (ALU). Load and store instructions include load string (LODS), load task register (LTR), move data (MOV), and the like. Store instructions include store task register (STR), store string (STOS), and the like. Generally, load instructions retrieve data and/or instructions from cache/memory and place the information in one of the microprocessor registers, while store instructions place data and/or instructions into a cache/memory location from the microprocessor registers. Integer unit 21 may perform address calculations for the load and store instructions.

It should be noted that microprocessor 10 of FIG. 1 includes a hierarchical memory subsystem. The memory subsystem includes a level one (L1) instruction cache 15 and data cache 16 which provide the instructions and data to the execution units (FPU 20, Integer Unit 21 and Load/Store unit 22). An off chip level two (L2) cache (not shown) is usually provided. While the L2 cache is smaller than main memory 13, retrieving information likely to be used by the processor from the L2 cache is much faster than loading the information from main memory. Main memory 13 is the last level of storage in the memory subsystem. Memory 13 is the largest storage area, but also requires the greatest number of cycles to be accessed by the microprocessor.

More particularly, level one (L1) instruction cache 15 is included in microprocessor 10, as shown in FIG. 1. Cache 15 can be configured to run in write-through mode, or in a higher performance write-back mode. The write-back mode optimizes performance of the CPU core by eliminating bus bottlenecks caused by unnecessary external write cycles. Write-through cache architectures require that all writes to the cache also update external memory simultaneously. These unnecessary write cycles create bottle necks which can result in CPU stall and adversely impact performance. In contrast, a write-back architecture allows data to be written to the cache without updating external memory. With a write-back cache external write cycles are only required when a cache miss occurs, a modified line is replaced in the cache, or when an external bus master requires access to data. Cache 15 stores instructions only in order to provide faster and less complex retrieval of instructions. Four-way set associative architecture and a least recently used (LRU) algorithm are used in cache 15. Of course, cache 15 can be operated in write-through mode when desired. The line size of cache 15 may be 16 bytes and new lines are only allocated during memory read cycles. Valid status is then maintained on a 16 byte cache line basis, but modified or "dirty" status for write-back mode is maintained on a 4-byte (double word) status. Therefore, only the double words that have been modified are written back to external memory when a line is replaced in the cache. The CPU can access the cache in a single internal clock cycle for both reads and writes.

Level one (L1) data cache 16 is also provided, as shown in FIG. 1. As noted above, instructions and data are stored separately in the L1 cache in order to increase performance. Cache 16 is also a four way set associative cache having, for example, a 16 byte line size and uses a least recently used (LRU) replacement algorithm.

Instruction cache 15 is connected to an instruction prefetch buffer 19 which is provided to store microprocessor instructions prior to their being fetched by instruction fetch/decode unit 18. Instructions are loaded into the buffer by being "prefetched" from the instruction stream. As instructions are fetched by unit 18, new instructions are loaded into the buffer. This ensures that the executions units will always have a continuous supply of instructions and prevents any "bubbles" from occurring in the pipeline. A branch target buffer 17 is used to predict the target address of a "branch" or "jump" instruction. That is, the target address is precalculated (predicted) and stored in buffer 17. Thus, when an unconditional branch is taken, or a conditional branch instruction is encountered, the address for the next (non-sequential) instruction is already known and available for use by the corresponding execution unit (floating point or integer).

In addition to being fetched by unit 18, the instructions are also decoded and issued, or dispatched. For example, load/store instructions are issued to load/store unit 22 for execution, the integer unit 21 for memory address calculation, and to a memory control unit, or the like, for scheduling. Additional integer instructions, such as add (ADD), multiply (IMUL), move (MOV) and the like are also issued by fetch/decode/issue unit 18 to integer unit 21. Floating point unit 20 receives the issued floating point instructions from unit 18 for execution thereon. The floating point unit 20 includes an execution unit 27 (FIG. 2). FPU 20 includes eight 80 bit registers with a 64 bit interface and is capable of parallel execution. The exemplary Intel architecture floating point unit 20 uses the x87 instruction set and is compatible with IEEE standard 754. Load/store unit 22 includes a snooping mechanism that ensures coherency of data throughout the memory subsystem. The present invention utilizes this snooping mechanism, as described in more detail below.

Referring to FIG. 2, a block diagram of floating point unit 20 of microprocessor 10 is shown. As can be seen from FIG. 2, floating point and MMX instructions will both be executed by FPU 20. Floating point/MMX instructions are issued from fetch/decode/issue unit 18, where they have been pre-decoded to determine that they are either floating point or MMX instructions. Additional circuitry is provided in this stage to designate the use of floating point register set 0, 110 and/or register set 1, 100. The Floating Point/MMX instructions are then associated with their corresponding operand data in FP register set 100, 110, as the case may be.

FP/MMX decode unit 51 receives the predecoded instructions from fetch/decode/issue unit 18, as discussed above. Floating point/MMX instructions are then fully decoded in Floating Point/MMX decode unit 51. The instruction is then stored in floating point/MMX instruction queue 55 prior to being dispatched for processing on execution unit 27. Dispatch unit 24 will determine when instructions from FP instruction queue 55 are to be provided to execution unit 27. The instructions are then provided to execution unit 27 for execution. The instructions (floating point or MMX) are then executed by floating point execution unit 27. Execution unit 27 performs typical floating point operations, such as Add Multiply, Shift, absolute value, negative number operations, and the like. The output of FP execution unit 27 is provided to a result queue 25 where the execution result will be buffered. The result data from result queue 25 will be written back to the register files 100, 110, in a manner as designated by the fetch/decode/issues stage 18. Additionally, intermediate result data can be provided directly from execution unit 27, result queue 25 or register sets 100, 110 to dispatch unit 24, when further processing is needed. The microprocessor will typically be initialized with the floating point or MMX instructions updating the FP register file 110. Floating point or MMX store instructions will write the completed result from the register files 100, 110 back to main memory through load/store unit 22.

Referring to FIG. 3, the FPU circuitry within Intel x86 architecture microprocessors provide the user with an FPU data register file 1, having eight, 80 bit FPU data registers R0-R7, which are accessed in a stack-like manner. A sixteen bit control register 2 and sixteen bit status register 3 are also provided. Data register tag word 4 contains eight, 2 bit fields, each associated with one of the eight data registers R0-R7. The tag word is used to designate status, such as empty/non-empty, or the like for each of the eight data registers.

Also shown in FIG. 3, is an instruction pointer 5 to the memory location containing the current instruction word and a data pointer 6 to the memory location containing the operand associated with the current instruction (if any). An eleven bit opcode register 8 is also shown that contains the opcode of the last executed instruction. As seen in FIG. 3, control register 2, status register 3, tag word register 4, instruction pointer 5, data pointer 6 and opcode register 8 are the environment. The combination of register file 1 with the above noted environment registers comprise the floating point state.

Referring more specifically to FIG. 3, a tag field (not shown) is used to associate each of the eight 2-bit fields in the tag word with one of the physical data registers in FPU data register file 1. Tag word register 4 is comprised of two bits for each physical data register. Tag word fields (0-7 of the tag field) assume one of four values depending on the contents of their associated register (R0-R7), i.e. Valid (00), Zero (01), Special (10), and Empty (11). Special values include Denormal, Infinity, QNaN, SNaN and unsupported formats. Tag values are maintained transparently by the Intel microprocessors and are only available to the programmer indirectly through the FSTENV and FSAVE instructions.

The FPU circuitry communicates information about its status and the results of operations to other functional units in the microprocessor via status register 3. The FPU status register is comprised of bit fields that reflect exception status, operation execution status, register status, operand class and comparison results. This register is continuously accessible to the microprocessor CPU, i.e. integer unit, regardless of the state of the control or execution units.

FPU mode control register 2 is used by the CPU to specify the operating mode of the FPU. Control register 2 contains bit fields which specify the rounding mode to be used, the precision (single or double) by which to calculate results and the exception condition which should be reported to the CPU via traps. The user controls precision, rounding and exception reporting by setting or clearing the appropriate bits in control register 2. For additional information see the ST486DX/DX2 Databook, published by SGS-THOMSON Microelectronics, Inc. and the Pentium Processor Family Developer's Manual, published by Intel Corporation, both hereby incorporated by reference.

The dual register set of the present invention is shown in FIG. 4. Register Set 0 is shown by reference numeral 110 and register set 1 is designated by reference numeral 100. Register set 110 includes a register file 111 having eight, 80 bit registers and a set of environment registers 112 (control, status, tag, opcode, instruction pointer, data pointer), which function in the manner described previously in conjunction with FIG. 3. Register set 100 includes environment registers 102 and register file 101 which are functionally identical to the environment registers 112 and register file 111 of register set 110. Those skilled in the art will understand how decoding the FNSAVE, FRSTOR, FSTENV, FLDENV instructions will drive a state machine, or the like, to set the pointer bit(s) that will determine whether register set 0 or 1 (or some combination thereof) is the working set, and the dirty bit(s) that determine if the state information associated with the previous task must be loaded from memory. Further, an additional translation step is included in the present invention which determines, for each instruction being executed in the floating point unit, the value of the pointer bits and, therefore, which register set (0 or 1) to access.

The present invention also includes a snoop address register 120 which stores a memory address corresponding the FP state (register file and environment) and/or the FP environment which is saved as the result of an FNSAVE or FSTENV instruction, respectively. The address in register 120 is snooped to determine whether the saved information has been modified. In accordance with the present invention, the state of a previous task can be restored from an "on-chip" image, unless the information in memory is modified. When the saved memory information is modified the floating point state, must be restored from memory.

Referring more specifically to FIG. 4, a block diagram of register set 0, 110 is shown having environment registers 112 and register file 111. Register set 1, 100 is also shown with environment registers 102 and register file 101. Floating point instructions, FNSTENV/FLDENV correspond to environment registers 102 and 112 only, since they respectively store and load the environment. The FNSAVE and FRSTOR, instructions are associated with both the environment registers 102, 112 and register files 101, 111, because these instructions respectively save and restore the environment registers and register file.

A snoop address register 120 is also illustrated by FIG. 4 and will include the address of the shadowed register set (invisible to the programmer) such that any modification of the information corresponding to this address will cause the information to be considered "dirty" and necessitate a memory load to restore the previous context.

Environment pointer bit register 121 indicates which environment register 102 or 112 in register set 0 or register set 1 is the working environment and which is the shadowed environment. A logical 0 in register 121 means that ENV 112 is the working environment register, while a logical 1 indicates that ENV 102 is the working environment. Similarly, pointer bit register 123 indicates which register file 101 or 111 in register set 0 or register set 1 is the working register file and which is the shadowed register file. Again, a logical 0 in register 123 indicates the REG 111 is the working file and a logical 1 will mean that REG 101 is the working file.

Environment register dirty bit register 122 and register file dirty bit 122 are both are set=1 when the CPU is reset. Then, dirty bits are then turned off, set=0, for a newly created on-chip image for a corresponding register file. That is, when an on-chip image is created (ENV 102 or 112 is saved as the shadowed ENV) then the ENV dirty bit register is set=0. Similarly, the REG dirty bit register is also set=0 for the corresponding register file, REG 101 or 111 saved as the shadowed register file. If another instruction or operation then modifies the shadowed ENV or REG, the corresponding bit is flipped to a logical 1, thereby indicating that the saved information has been modified and the state must be restored from main memory upon a context switch. In this manner, the ENV and REG dirty bits track the status of the shadowed ENV and REG, respectively.

For example, when the shadowed register set is saved as an on-chip image, ENV dirty bit register 122 and REG dirty bit register 124 are then set=0 and the memory address of the shadowed register set is stored in snoop address register 120. Upon the occurrence of a snoop hit, the dirty bits in registers 122 and/or 124 are set=1 indicating that the on-chip image has been modified and must be loaded from memory when a task switch occurs.

The pointer bits and dirty bits are used to facilitate the algorithm for the dual register set of the present invention. A new working set is formed by selectively picking ENV and REG registers from both the working set and/or shadowed set when one of the FNSAVE, FSTENV, FRSTOR, FLDENV instructions are executed. The algorithm of the present invention forms a new working set in a single CPU cycle while maintaining instruction compatibility.

Generally, the algorithm flips the bits in the pointer registers 121, 123 when either an FNSAVE instruction (saves the environment registers and register file) or an FSTENV instruction (stores the environment registers) is executed. Further, if the instruction is either an FRSTOR (restores the environment registers and register file) or an FLDENV (loads the environment registers), and a match occurs with the snoop address register (stored information has not been modified), and the dirty bits are off (set=0). It should be noted that for an FRSTOR both the ENV and REG dirty bits in registers 121, 123, must be off, and for an FLDENV only the ENV dirty bit in register 121 needs to be off.

The algorithm of the present invention controls the dirty bits by turning them on (set=1) or off (set=0). For a newly created on-chip image, the corresponding dirty bit(s) in registers 122, 124 are turned off. Dirty bits, for an on-chip image, turn on when the corresponding memory image is modified. Both the ENV dirty bit in register 122 and REG dirty bit in register 124 are turned on when the CPU is reset.

The operation of the present invention will now be described in conjunction with the actual execution of the FNSAVE, FNSTENV, FRSTOR and FLDENV instructions on the microprocessor 10.

For the purposes of describing the present invention it will be assumed that initially the working register set={ENV[env.sub.-- ptr], REG[reg.sub.-- ptr]}. FNSAVE is then processed and the CPU prepares switching over to the shadowed register set by initializing the environment pointer, ENV[.about.env.sub.-- ptr] and copying the current working set REG pointer, REG[reg.sub.-- ptr] over to REG[.about.reg.sub.-- ptr], i.e. setting register pointer bit 123 equal to the value (0 or 1) corresponding to the working register set. This initialization and copying is a requirement for the FNSAVE instruction at the instruction level and is necessary to maintain compatibility with the instruction set architecture. The CPU then overwrites the snoop address register 120 with the store address from the FNSAVE instruction. The ENV pointer bit in register 121 and REG pointer bit in register 123 are then flipped to form a new working set ={ENV[env.sub.-- ptr], REG[reg.sub.-- ptr]}is formed. The ENV and REG dirty bits in registers 122, 124 are then turned off and a new on-chip image={ENV[.about.env.sub.-- ptr], REG[.about.reg.sub.-- ptr]} is created. All of the previously described operations occur in one CPU cycle.

Pseudo-code for FNSAVE:

    ______________________________________
    ENV[.about.env.sub.-- ptr] = INIT.sub.-- ENVIRONMENT
    REG[.about.reg.sub.-- ptr] = REG[reg.sub.-- ptr]
    SNOOP.sub.-- REG.address = FNSAVE.sub.-- address
    env.sub.-- tr = .about.env.sub.-- ptr
    reg.sub.-- tr = .about.reg.sub.-- ptr
    env.sub.-- dirty = 0
    reg.sub.-- dirty = 0
    ______________________________________

    ______________________________________
            ENV[.about.env.sub.-- ptr] = ENV[env.sub.-- ptr]
            SNOOP.sub.-- REG.address = FNSTENV.sub.-- address
            env.sub.-- ptr = .about.env.sub.-- ptr
            env.sub.-- dirty = 0
            reg.sub.-- dirty = 1
    ______________________________________

    ______________________________________
    if((SNOOP.sub.-- REG.address == FRSTOR.sub.-- address) &&!(env.sub.--
    dirty
    .parallel. reg.sub.-- dirty)) then
    env.sub.-- ptr = .about.env.sub.-- ptr
    reg.sub.-- ptr = .about.reg.sub.-- ptr
    env.sub.-- dirty = 1
    reg.sub.-- dirty = 1
    else
    ENV[env.sub.-- ptr] = MEMOR[FRSTOR.sub.-- address].ENV
    REG[reg.sub.-- ptr] = MEMORY[FRSTOR.sub.-- address].REG
    endif
    ______________________________________

    ______________________________________
    if((SNOOP.sub.-- REG.address == FLDENV.sub.-- adress) &&!env.sub.--
    dirty)) then
    env.sub.-- ptr = .about.env.sub.-- ptr
    env.sub.-- dirty = 1
    reg.sub.-- dirty = 1
    else
    ENV[env.sub.-- ptr] = MEMORY[FLDENV.sub.-- adress}.ENV
    endif
    ______________________________________

    ______________________________________
           ENV[0] = RESET.sub.-- ENVIRONMENT
           REG[0] = RESET.sub.-- REGISTERS
           env.sub.-- dirty = 1
           reg.sub.-- dirty = 1
           SNOOP.sub.-- REG.address = XXXXXXXX
           env.sub.-- ptr = 0
           reg.sub.-- ptr = 0
    ______________________________________

    ______________________________________
    Snoop Reg                       What    Load from
    ENV ptr ENV drt  REG ptr REG drt
                                    Happened
                                            Memory
    ______________________________________
    X       0        1       0      1 reset
    A       1        0       1      0 fnsave[A]
    A       0        1       0      1 frstor[A]
                                            No
    B       1        0       1      0 fnsave[B]
    B       1        0       1      1 Store to
                                    REG
                                    memory
                                    image
    B       1        0       1      1 frstor[B]
                                            Yes
    ______________________________________

    ______________________________________
    Snoop Reg                       What    Load from
    ENV ptr ENV drt  REG ptr REG drt
                                    Happened
                                            Memory
    ______________________________________
    X       0        1       0      1 reset
    A       1        0       0      1 fnstenv[A]
    A       0        1       0      1 fldenv[A]
                                            No
    B       1        0       0      1 fnstenv[B]
    B       0        1       0      1 fldenv[B]
                                            No
    ______________________________________

    ______________________________________
    Snoop Reg                       What    Load from
    ENV ptr ENV drt  REG ptr REG drt
                                    Happened
                                            Memory
    ______________________________________
    X       0        1       0      1 reset
    B       1        0       0      1 fnsave[B]
    A       0        0       0      0 fnsave[A]
    B       1        0       0      1 fnstenv[B]
    B       0        1       0      1 frstor[B]
                                            Yes,
                                            re-load
                                            from
                                            memory
                                            image
    ______________________________________

    ______________________________________
    Snoop Reg                       What    Load from
    ENV ptr ENV drt  REG ptr REG drt
                                    Happened
                                            Memory
    ______________________________________
    X       0        1       0      1 reset
    A       1        0       1      0 fnsave[A]
    A       0        1       1      0 fldenv[A]
                                            No
    A       0        1       1      0 frstor[A]
                                            Yes
    ______________________________________

• Inventors
  Wong, David;
• Assignee
  STMicroelectronics, Inc. (Carrollton, TX)
• Published
  Nov-7-2000
• Current US Classes:
  710/267
  712/228
  718/108
• Application #
  999206
• International Classes
  G06F 009/48
• Field of Search
  709/108 710/267 712/228
• Examiner
  Kim; Kenneth S.
• Agent
  Galanthay; Theodore E., Jorgenson; Lisa K.
• US Patent References:
  4945510
  5050067
  5142677
  5222241
  5535397
  5713038
  5742791
  5928356