Thread switch tuning tool for optimal performance in a computer processor6018759Abstract A method, apparatus, and article of manufacture for performing thread switch tuning for optimal performance of a program executed by a computer data processing system having a multithreaded processor. The system includes a performance monitor facility; a thread switch controller enabling thread switching for the target program while the target program is executed and disabling thread switching after completing execution of the target program; a thread switch control register including at least one thread switching event for the target program; a monitor for monitoring performance of the target program by the performance monitor facility to measure and record the performance, setting a different value for the thread switch control register whereby the target program is executed for the plurality of times, each time with a different value for the thread switch control register, choosing one of the values of the thread switch control register, after completing execution of the target program for the plurality of times, as an optimal value of the thread switch control register for the target program, based on a highest performance recorded by the performance monitor facility. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
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Bit Allocation of the Thread State Register
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(0) Instruction/Data
0 = Instruction
1 = Data
(1:2) Miss type sequencer
00 = None
01 = Translation lookaside buffer miss (check bit 0 for I/D)
10 = L1 cache miss
11 = L2 cache miss
(3) Transition
0 = Transition to current state does not result in thread switch
1 = Transition to current state results in thread switch
(4:7) Reserved
(8) 0 = Load
1 = Store
(9:14)
Reserved
(15:17)
Forward progress count sequencer
111 = Reset (instruction has completed during this thread)
000 = 1st execution of this thread w/o instruction complete
001 = 2nd execution of this thread w/o instruction complete
010 = 3rd execution of this thread w/o instruction complete
011 = 4th execution of this thread w/o instruction complete
100 = 5th execution of this thread w/o instruction complete
(18:19)
Priority (could be set by software)
00 = Medium
01 = Low
10 = High
11 = <Illegal>
(20:31)
Reserved
(32:63)
Reserved if 64 bit implementation
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In the embodiment described herein, bit 0 identifies whether the miss or the reason the processor stalled execution is a result of a request for an instruction or for data. Bits 1 and 2 indicate if the requested information was not available and if so, from what hardware, i.e., whether the translated address of the data or instruction was not in the translation lookaside buffer 250, or the data or instruction itself was not in the L1 D-cache 120 or the L2 cache 130, as further explained in the description of FIG. 5. Bit 3 indicates whether the change of state of a thread results in a thread switch. A thread may change state without resulting in a thread switch. For instance, if a thread switch occurs when thread T1 experiences an L1 cache miss, then if thread T1 experiences a L2 cache miss, there will be no thread switch because the thread already switched on a L1 cache miss. The state of T1, however, still changes. Alternatively, if by choice, the thread switch logic 400 is configured or programmed not to switch on a L1cache miss, then when a thread does experience an L1 cache miss, there will be no thread switch even though the thread changes state. Bit 8 of the thread state registers 442 and 444 is assigned to whether the information requested by a particular thread is to be loaded into the processor core or stored from the processor core into cache or main memory. Bits 15 through 17 are allocated to prevent thrashing, as discussed later with reference to the forward progress count register 420. Bits 18 and 19 can be set in the hardware or could be set by software to indicate the priority of the thread. FIG. 5 represents four states in the present embodiment of a thread processed by the data processing system 10 and these states are stored in the thread state registers 440, bit positions 1:2. State 00 represents the "ready" state, i.e., the thread is ready for processing because all data and instructions required are available; state 10 represents the thread state wherein the execution of the thread within the processor is stalled because the thread is waiting for return of data into either the L1 D-cache 120 or the return of an instruction into the L1 I-cache 150; state 11 represents that the thread is waiting for return of data into the L2 cache 130; and the state 01 indicates that there is a miss on the translation lookaside buffer 250, i.e., the virtual address was in error or wasn't available, called a table walk. Also shown in FIG. 5 is the hierarchy of thread states wherein state 00, which indicates the thread is ready for execution, has the highest priority. Short latency events are preferably assigned a higher priority. FIG. 5 also illustrates the change of states when data is retrieved from various sources. The normal uninterrupted execution of a thread T0 is represented in block 510 as state 00. If a L1 D-cache or I-cache miss occurs, the thread state changes to state 10, as represented in block 512, pursuant to a signal sent on line 474 (FIG. 4) from the storage control unit 200 or line 470 (FIG. 4) from the instruction unit 220, respectively. If the required data or instruction is in the L2 cache 130 and is retrieved, then normal execution of T0 resumes at block 510. Similarly block 514 of FIG. 5 represents a L2 cache miss which changes the state of thread of either T0 or T1 to state 11 when storage control unit 200 signals the miss on lines 476 or 478 (FIG. 4). When the instructions or data in the L2 cache are retrieved from main memory 140 and loaded into the processor core 100 as indicated on lines 480 and 482 (FIG. 4), the state again changes back to state 00 at block 510. The storage control unit 200 communicates to the thread registers 440 on line 484 (FIG. 4) when the virtual address for requested information is not available in the translation lookaside buffer 250, indicated as block 516, as a TLB miss or state 01. When the address does become available or if there is a data storage interrupt instruction as signaled by the storage control unit 200 on line 486 (FIG. 4), the state of the thread then returns to state 00, meaning ready for execution. The number of states, and what each state represents is freely selectable by the computer architect. For instance, if a thread has multiple L1 cache misses, such as both a L1 I-cache miss and L1 D-cache miss, a separate state can be assigned to each type of cache miss. Alternatively, a single thread state could be assigned to represent more than one event or occurrence. An example of a thread switch algorithm for two threads of equal priority which determines whether to switch threads is given. The algorithm can be expanded and modified accordingly for more threads and thread switch conditions according to the teachings of the invention. The interactions between the state of each thread stored in the thread state registers 440 (FIG. 4) and the priority of each thread by the thread switching algorithm is dynamically interrogated each cycle. If the active thread T0 has a L1 miss, the algorithm will cause a thread switch to the dormant thread T1 unless the dormant thread T1 is waiting for resolution of a L2 miss. If a switch did not occur and the L1 cache miss of active thread T0 turns into a L2 cache miss, the algorithm then directs the processor to switch to the dorman thread T1 regardless of the T1 's state. If both threads are waiting for resolution of a L2 cache miss, the thread first having the L2 miss being resolved becomes the active thread. At every switch decision time, the action taken is optimized for the most likely case, resulting in the best performance. Note that thread switches resulting from a L2 cache miss are conditional on the state of the other thread, if not extra thread switches would occur resulting in loss of performance. Thread Switch Control Register In a multithreaded processor, there are latency and performance penalties associated with switching threads. This latency includes the time required to complete execution of the current thread to a point where it can be interrupted and correctly restarted when it is next invoked, the time required to switch the thread- specific hardware facilities from the current thread's state to the new thread's state, and the time required to restart the new thread and begin its execution. In order to achieve optimal performance in a coarse grained multithreaded data processing system, the latency of an event which generates a thread switch must be greater than the performance cost associated with switching threads in a multithreaded mode, as opposed to the normal single-threaded mode. The latency of an event used to generate a thread switch is dependent upon both hardware and software. For example, specific hardware considerations in a multithreaded processor include the speed of external SRAMs used to implement an L2 cache external to the processor chip. Fast SRAMs in the L2 cache reduce the average latency of an L1 miss while slower SRAMS increase the average latency of an L1 miss. Thus, performance is gained if one thread switch event is defined as a L1 cache miss in hardware having an external L2 cache data access latency greater than the thread switch penalty. As an example of how specific software code characteristics affect the latency of thread switch events, consider the L2 cache hit-to-miss ratio of the code, i.e., the number of times data is actually available in the L2 cache compared to the number of times data must be retrieved from main memory because data is not in the L2 cache. A high L2 hit to miss ratio reduces the average latency of an L1 cache miss because the L1 cache miss seldom results in a longer latency L2 miss. A low L2 hit to miss ratio increases the average latency of an L1 miss because more L1 misses result in longer latency L2 misses. Thus, a L 1 cache miss could be disabled as a thread switch event if the executing code has a high L2 hit to miss ratio because the L2 cache data access latency is less than the thread switch penalty. A L1 cache miss would be enabled as a thread switch event when executing software code with a low L2 hit to miss ratio because the L1 cache miss is likely to turn into a longer latency L2 cache miss. Some types of latency events are not readily detectable. For instance, in some systems the L2 cache outputs a signal to the instruction unit when a cache miss occurs. Other L2 caches, however, do not output such a signal, as in for example, if the L2 cache controller were on a separate chip from the processor and accordingly, the processor cannot readily determine a state change. In these architectures, the processor can include a cycle counter for each outstanding L1 cache miss. If the miss data has not been returned from the L2 cache after a predetermined number of cycles, the processor acts as if there had been a L2 cache miss and changes the thread's state accordingly. This algorithm is also applicable to other cases where there are more than one distinct type of latency. As an example only, for a L2 cache miss in a multiprocessor, the latency of data from main memory may be significantly different than the latency of data from another processor. These two events may be assigned different states in the thread state register. If no signal exists to distinguish the states, a counter may be used to estimate which state the thread should be in after it encounters a L2 cache miss. The thread switch control register 410 is a software programmable register which selects the events to generate thread switching and has a separate enable bit for each defined thread switch event. Although the embodiment described herein does not implement a separate thread switch control register 410 for each thread, separate thread switch control registers 410 for each thread could be implemented to provide more flexibility and performance at the cost of more hardware and complexity. The thread switch control register 410 can be written by a service processor with software such as a dynamic scan communications interface disclosed in U.S. Pat. No. 5,079,725 entitled Chip Identification Method for Use with Scan Design Systems and Scan Testing Techniques or by the processor itself with software system code. The contents of the thread switch control register 410 is used by the thread switch controller 450 to enable or disable the generation of a thread switch. A value of one in the register 410 enables the event associated with that bit to generate a thread switch. A value of zero in the thread switch control register 410 disables the event associated with that bit from generating a thread switch. The following table shows the association between thread switch events and their enable bits in the register 410.
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Thread Switch Controi Register Bit Assignment
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(0) Switch on L1 data cache fetch miss
(1) Switch on L1 data cache store miss
(2) Switch on L1 instruction cache miss
(3) Switch on instruction TLB miss
(4) Switch on L2 cache fetch miss
(5) Switch on L2 cache store miss
(6) Switch on L2 instruction cache miss
(7) Switch on data TLB/segment lookaside buffer miss
(8) Switch on L2 cache miss and dormant thread not L2 cache miss
(9) Switch when thread switch time-out value reached
(10) Switch when L2 cache data returned
(11) Switch on IO external accesses
(12) Switch on double-X store: miss on first of two*
(13) Switch on double-X store: miss on second of two*
(14) Switch on store multiple/string: miss on any access
(15) Switch on load multiple/string: miss on any access
(16) Reserved
(17) Switch on double-X load: miss on first of two*
(18) Switch on double-X load: miss on second of two*
(19) Switch on or 1,1,1 instruction if machine state register (problem
state) bit, msr(pr)=1. Allows software priority change
independent of msr(pr). If bit 19 is one, or 1,1,1 instruction
sets
low priority. If bit 19 is zero, priority is set to low only if
msr(pr)=0 when the or 1,1,1 instruction is executed. See
changing priority with software, to be discussed later.
(20) Reserved
(21) Thread switch priority enable
(22:29)
Reserved
(30:31)
Forward progress count
(32:63)
Reserved in 64 bit register implementation
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*A doubleX load/store refers to loading or storing an elementary halfword
a word, or a double word, that crosses a doubleword boundary. A doubleX
load/store in this context is not a load or store of multiple words or a
string of words.
Thread Switch Time-out Register As discussed above, coarse grained multithreaded processors rely on long latency events to trigger thread switching. Sometimes during execution, a processor in a multiprocessor environment or a background thread in a multithreaded architecture, has ownership of a resource that can have only a single owner and another processor or active thread requires access to the resource before it can make forward progress. Examples include updating a memory page table or obtaining a task from a task dispatcher. The inability of the active thread to obtain ownership of the resource does not result in a thread switch event, nonetheless, the thread is spinning in a loop unable to do useful work. In this case, the background thread that holds the resource does not obtain access to the processor so that it can free up the resource because it never encountered a thread switch event and does not become the active thread. Allocating processing cycles among the threads is another concern; if software code running on a thread seldom encounters long latency switch events compared to software code running on the other threads in the same processor, that thread will get more than it's fair share of processing cycles. Yet another excessive delay that may exceed the maximum acceptable time is the latency of an inactive thread waiting to service an external interrupt within a limited period of time or some other event external to the processor. Thus, it becomes preferable to force a thread switch to the dormant thread after some time if no useful processing is being accomplished to prevent the system from hanging. The logic to force a thread switch after a period of time is a thread switch time-out register 430 (FIG. 4), a decrementer, and a decrementer register to hold the decremented value. The thread switch time-out register 430 holds a thread switch time-out value. The thread switch time-out register 430 implementation used in this embodiment is shown in the following table:
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Thread Switch Time-out Register Bits
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(0:21)
Reserved
(22:31)
Thread switch time-out value
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The embodiment of the invention described herein does not implement a separate thread switch time-out register 430 for each thread, although that could be done to provide more flexibility. Similarly, if there are multiple threads, each thread need not have the same thread switch time-out value. Each time a thread switch occurs, the thread switch time-out value from the thread switch time-out register 430 is loaded by hardware into the decrement register. The decrement register is decremented once each cycle until the decrement register value equals zero, then a signal is sent to the thread switch controller 450 which forces a thread switch unless no other thread is ready to process instructions. For example, if all other threads in the system are waiting on a cache miss and are not ready to execute instructions, the thread switch controller 450 does not force a thread switch. If no other thread is ready to process instructions when the value in the decrement register reaches zero, the decremented value is frozen at zero until another thread is ready to process instructions, at which point a thread switch occurs and the decrement register is reloaded with a thread switch time-out value for that thread. The thread switch time-out register 430 can be written by a service processor as described above or by the processor itself with software code. The thread switch time-out value loaded into the thread switch time-out register 430 can be customized according to specific hardware configuration and/or specific software code to minimize wasted cycles resulting from unnecessary thread switching. Too high of a value in the thread switch time-out register 430 can result in reduced performance when the active thread is waiting for a resource held by another thread or if response latency for an external interrupt or some other event external to the processor is too long. Too high of a value can also prevent fairness if one thread experiences a high number of thread switch events and the other does not. A thread switch time-out value twice to several times longer than the most frequent longest latency event that causes a thread switch is recommended, e.g., access to main memory. Forcing a thread switch after waiting the number of cycles specified in the thread switch time-out register 430 prevents system hangs due to shared resource contention, enforces fairness of processor cycle allocation between threads, and limits the maximum response latency to external interrupts and other events external to the processor. Forward Progress Guarantee That at least one instruction must be executed each time a thread switch occurs and becomes active is too restrictive in certain circumstances, such as when a single instruction generates multiple cache accesses and/or multiple cache misses. For example, a fetch instruction may cause an L1 I-cache 150 miss if the instruction requested is not in the cache; but when the instruction returns, required data may not be available in the L1 D-cache 120. Likewise, a miss in translation lookaside buffer 250 can also result in a data cache miss. So, if forward progress is strictly enforced, misses on subsequent accesses do not result in thread switches. A second problem is that some cache misses may require a large number of cycles to complete, during which time another thread may experience a cache miss at the same cache level which can be completed in much less time. If, when returning to the first thread, the strict forward progress is enforced, the processor is unable to switch to the thread with the shorter cache miss. To remedy the problem of thrashing wherein each thread is locked in a repetitive cycle of switching threads without any instructions executing, there exists a forward progress count register 420 (FIG. 4) which allows up to a programmable maximum number of thread switches called the forward progress threshold value. After that maximum number of thread switches, an instruction must be completed before switching can occur again. In this way, thrashing is prevented. Forward progress count register 420 may actually be bits 30:31 in the thread switch control register 410 or a software programmable forward progress threshold register for the processor. The forward progress count logic uses bits 15:17 of the thread state registers 442, 444 that indicate the state of the threads and are allocated for the number of thread switches a thread has experienced without an instruction executing. When a thread changes state invoking the thread switch algorithm, if at least one instruction has completed in the active thread, the forward-progress counter for the active thread is zeroed and the thread switch algorithm continues to compare thread states between the threads in the processor. If no instruction has completed, the forward-progress counter value of the active thread is compared to the forward progress threshold value. If the counter value is less than the threshold value, the thread switch algorithm continues to evaluate the thread states of the threads in the processor. Then if a thread switch occurs, the forward-progress counter is incremented. If, however, the counter value is equal to the threshold value, no thread switch will occur until an instruction can execute, i.e., until forward progress occurs. Note that if the threshold register has value zero, at least one instruction must complete within the active thread before switching to another thread. If each thread switch requires three processor cycles and if there are two threads and if the thread switch logic is programmed to stop trying to switch threads after five tries; then the maximum number of cycles that the processor will thrash is thirty cycles. One of skill in the art can appreciate that there a potential conflict exists between prohibiting a thread switch because no forward progress will be made on one hand and, on the other hand, forcing a thread switch because the time-out count has been exceeded. Such a conflict can easily be resolved according to architecture and software. FIG. 6 is a flowchart of the forward progress count feature of thread switch logic 400 which prevents thrashing. At block 610, bits 15:17 in thread state register 442 pertaining to thread T0 are reset to state 111. Execution of this thread is attempted in block 620 and the state changes to 000. If an instruction successfully executes on thread T0, the state of thread T0 returns to 111 and remains so. If, however, thread T0 cannot execute an instruction, a thread switch occurs to thread T1, or another background thread if more than two threads are permitted in the processor architecture. When a thread switch occurs away from T1 or the other background thread and execution returns to thread T0, a second attempt to execute thread T0 occurs and the state of thread T0 becomes 001 as in block 630. Again, if thread T0 encounters a thread switch event, control of the processor is switched away from thread T0 to another thread. Similarly, whenever a thread switch occurs from the other thread, e.g., T1, back to thread T0, the state of T0 changes to 010 on this third attempt to execute T0 (block 640); to 011 on the fourth attempt to execute T0 (block 650), and to state 100 on the fifth attempt to execute T0 (block 660). In this implementation, there are five attempts to switch to thread T0. After the fifth attempt or whenever the value of bits 15:17 in the thread state register (TSR) 442 is equal to the value of bits 30:31 plus one in the thread switch control register (TSC) 410, i.e., whenever TSC(30:31)+1 =TSR (15:17), no thread switch away from thread T0 occurs. It will be appreciated that five attempts is an arbitrary number; the maximum number of allowable switches with unsuccessful execution is programmable and it may be realized in certain architectures that five is too many switches, and in other architectures, five is too few. In any event, the relationship between the number of times that an attempt to switch to a thread with no instructions executing must be compared with a maximum value and once that maximum value has been reached, no thread switch occurs away from that thread and the processor waits until the latency associated with that thread is resolved. In the embodiment described herein, the state of the thread represented by bits 15:17 of the thread state register 442 is compared with bits 30:31 in the thread switch control register 410. Special handling for particular events that have extremely long latency, such as interaction with input/output devices, to prevent prematurely blocking thread switching with forward progress logic improves processor performance. One way to handle these extremely long latency events is to block the incrementing of the forward progress counter if data has not returned. Another way to handle extremely long latency events is to use a separate larger forward progress count for these particular events. Thread Switch Manager The thread state for all software threads dispatched to the processor is preferably maintained in the thread state registers 442 and 444 of FIG. 4 as described. In a single processor one thread executes its instructions at a time and all other threads are dormant. Execution is switched from the active thread to a dormant thread when the active thread encounters a long-latency event as discussed above with respect to the forward progress register 420, the thread switch control register 410, or the thread switch time-out register 430. Independent of which thread is active, these hardware registers use conditions that do not dynamically change during the course of execution. Flexibility to change thread switch conditions by a thread switch manager improves overall system performance. A software thread switch manager can alter the frequency of thread switching, increase execution cycles available for a critical task, and decrease the overall cycles lost because of thread switch latency. The thread switch manager can be programmed either at compile time or during execution by the operating system, e.g., a locking loop can change the frequency of thread switches; or an operating system task can be dispatched because a dormant thread in a lower priority state is waiting for an external interrupt or is otherwise ready. It may be advantageous to disallow or decrease the frequency of thread switches away from an active thread so that performance of the current instruction stream does not suffer the latencies resulting from switching into and out of it. Alternatively, a thread can forgo some or all of its execution cycles by essentially lowering its priority, and as a result, decrease the frequency of switches into it or increase the frequency of switches out of the thread to enhance overall system performance. The thread switch manager may also unconditionally force or inhibit a thread switch, or influence which thread is next selected for execution. A multiple-priority thread switching scheme assigns a priority value to each thread to qualify the conditions that cause a switch. It may also be desirable in some cases to have the hardware alter thread priority. For instance, a low-priority thread may be waiting on some event, which when it occurs, the hardware can raise the priority of the thread to influence the response time of the thread to the event. Relative priorities between threads or the priority of a certain thread will influence the handling of such an event. The priorities of the threads can be adjusted by the thread switch manager software through the use of one or more instructions, or by hardware in response to an event. The thread switch manager alters the actions performed by the hardware thread switch logic to effectively change the relative priority of the threads. Three priorities are used with the embodiment described herein of two threads and provides sufficient distinction between threads to allow tuning of performance without adversely affecting system performance. With three priorities, two threads can have an equal status of medium priority. The choice of three priorities for two threads is not intended to be limiting. In some architectures a "normal" state may be that one thread always has a higher priority than the other threads. It is intended to be within the scope of the invention to cover more than two threads of execution having one or multiple priorities that can be set in hardware or programmed by software. The three priorities of each thread are high, medium, and low. When the priority of thread T0 is the same as thread T1, there is no effect on the thread switching logic. Both threads have equal priority so neither is given an execution time advantage. When the priority of thread T0 is greater than the priority of thread T1, thread switching from T0 to T1 is disabled for all L1 cache misses, i.e., data load, data store, and instruction fetch, because L1 cache misses are resolved much faster than other conditions such as L2 misses and translates. Thread T0 is given a better chance of receiving more execution cycles than thread T1 which allows thread T0 to continue execution so long as it does not waste an excessive number of execution cycles. The processor, however, will still relinquish control to thread T1 if thread T0 experiences a relatively long execution latency. Thread switching from T1 to T0 is unaffected, except that a switch occurs when dormant thread T0 is ready in which case thread T0 preempts thread T1. This case would be expected to occur when thread T0 switches away because of an L2 cache miss or translation request, and the condition is resolved in the background while thread T0 is executing. The case of thread T0 having a priority less than thread T1 is analogous to the case above, with the thread designation reversed. There are different possible approaches to implementing management of thread switching by changing thread priority. New instructions can be added to the processor architecture. Existing processor instructions having side effects that have the desired actions can also be used. Several factors influence the choice among the methods of allowing software control: (a) the ease of redefining architecture to include new instructions and the effect of architecture changes on existing processors; (b) the desirability of running identical software on different versions of processors; (c) the performance tradeoffs between using new, special purpose instructions versus reusing existing instructions and defining resultant side effects; (d) the desired level of control by the software, e.g., whether the effect can be caused by every execution of some existing instruction, such as a specific load or store, or whether more control is needed, by adding an instruction to the stream to specifically cause the effect. The architecture described herein preferably takes advantage of an unused instruction whose values do not change the architected general purpose registers of the processor; this feature is critical for retrofitting multithreading capabilities into a processor architecture. Otherwise special instructions can be coded. The instruction is a "preferred nop" or 0,0,0; other instructions, however, can effectively act as a nop. By using different versions of the or instruction, or 0,0,0 or 1,1,1 etc. to alter thread priority, the same instruction stream may execute on a processor without adverse effects such as illegal instruction interrupts. An extension uses the state of the machine state register to alter the meaning of these instructions. For example, it may be undesirable to allow a user to code some or all of these thread priority instructions and access the functions they provide. The special functions they provide may be defined to occur only in certain modes of execution, they will have no effect in other modes and will be executed normally, as a nop. One possible implementation, using a dual-thread multithreaded processor, uses three instructions which become part of the executing software itself to change the priority of itself:
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tsop 1 or 1,1,1 - Switch to dormant thread
tsop 2 or 1,1,1 - Set active thread to LOW priority
Switch to dormant thread
NOTE: Only valid in privileged mode unless TSC[19]=1
tsop 3 or 2,2,2 - Set active thread to MEDIUM priority
tsop 4 or 3,3,3 - Set active thread to HIGH priority
NOTE: Only valid in privileged mode
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Instructions tsop 1 and tsop 2 can be the same instruction as embodied herein as or 1,1,1 but they can also be separate instructions. These instructions interact with bits 19 and 21 of the thread switch control register 410 and the problem/privilege bit of the machine state register as described herein. If bit 21 of the thread switch control register 410 has a value of one, the thread switch manager can set the priority of its thread to one of three priorities represented in the thread state register at bits 18:19. If bit 19 of the thread switch control register 410 has a value zero, then the instruction tsop 2 thread switch and thread priority setting is controlled by the problem/privilege bit of the machine state register. On the other hand, if bit 19 of the thread switch control register 410 has a value one, or if the problem/privilege bit of the machine state register has a value zero and the instruction or 1,1,1 is present in the code, the priority for the active thread is set to low and execution is immediately switched to the dormant or background thread if the dormant thread is enabled. The instruction or 2,2,2 sets the priority of the active thread to medium regardless of the value of the problem/privilege bit of the machine state register. And the instruction or 3,3,3, when the problem/privilege bit of the machine state register bit has a value of zero, sets the priority of the active thread to high. If bit 21 of the thread switch control register 410 is zero, the priority for both threads is set to medium and the effect of the or x,x,x instructions on the priority is blocked. If an external interrupt request is active, and if the corresponding thread's priority is low, that thread's priority is set to medium. The events altered by the thread priorities are: (1) switch on L1 D-cache miss to load data; (2) switch on L1 D-cache miss for storing data; (3) switch on L1 I-cache miss on an instruction fetch; and (4) switch if the dormant thread in ready state. In addition, external interrupt activation may alter the corresponding thread's priority. The following table shows the effect of priority on conditions that cause a thread switch. A simple TSC entry in columns three and four means to use the conditions set forth in the thread switch control (TSC) register 410 to initiate a thread switch. An entry of TSC[0:2] treated as 0 means that bits 0:2 of the thread switch control register 410 are treated as if the value of those bits are zero for that thread and the other bits in the thread switch control register 410 are used as is for defining the conditions that cause thread switches. The phrase when thread T0 ready in column four means that a switch to thread T0 occurs as soon as thread T0 is no longer waiting on the miss event that caused it to be switched out. The phrase when thread T1 ready in column 3 means that a switch to thread T1 occurs as soon as thread T1 is no longer waiting on the miss event that caused it to be switched out. If the miss event is a thread switch time-out, there is no guarantee that the lower priority thread completes an instruction 2:0 before the higher priority thread switches back in.
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T0 T1 T0 Thread T2 Thread
Priority
Priority Switch Conditions
Switch Conditions
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High High TSC TSC
High Medium TSC[0:2] treated as 0
TSC or if T0 ready
High Low TSC[0:2] treated as 0
TSC or if T0 ready
Medium High TSC or if T1 ready
TSC[0:2] treated as 0
Medium Medium TSC TSC
Medium Low TSC[0:2] treated as 0
TSC or if T0 ready
Low High TSC or if T1 ready
TSC[0:2] treated as 0
Low Medium TSC or if T1 ready
TSC[0:2] treated as 0
Low Low TSC TSC
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It is recommended that a thread doing no productive work be given low priority to avoid a loss in performance even if every instruction in the idle loop causes a thread switch. Yet, it is still important to allow hardware to alter thread priority if an external interrupt is requested to a thread set at low priority. In this case the thread is raised to medium priority, to allow a quicker response to the interrupt. This allows a thread waiting on an external event to set itself at low priority, where it will stay until the event is signalled. Thread Switch Tuning Monitor FIG. 7 illustrates a block diagram of a thread switch tuning tool implemented in one embodiment of the data processing system 10 according to the present invention. A monitor 700 is coupled to a thread switch controller 702. The thread switch controller 702 is arranged and configured to enable or disable thread switching for a target program to be monitored. The thread switch controller 702 allows thread switching once a condition for thread switching occurs. The monitor 700 is coupled to a thread switch time-out (tst) control register 704. As previously described, the thread switch time-out (tst) control register 704 forces a thread switch after a period of time held by the thread switch time-out (tst) control register 704. The monitor 700 is also coupled to a thread switch condition (tsc) control register 712. As previously described, the thread switch condition (tsc) control register 712 provides a plurality of conditions from which thread switching will occur. The value of the thread switch time-out (tst) control register 704, i.e., the period of time held by the register, can be changed by the monitor 700. The value of the thread switch condition (tsc) control register 712, i.e., the logic combinations of "1s" and "0s" of the register 712, can be changed by the monitor 700. The target program is executed by the processor and is to be "tuned" by the monitor 700. A processor performance monitor facility 705 as shown in dash line of FIG. 7 is used to evaluate the performance of the target program. In one embodiment, this facility 705 may include two registers namely performance monitor counters PMCs 708, 716 and two incrementers 706, 714 which are used to increment the value in PMCs 708, 716 if a selected event occurs. The event selection and counter activation are controlled by a machine monitor control register (MMCR) 710. The MMCR 710 can select many possible events in the machine to be counted such as machine cycles, instructions executed, Instruction cache (a-cache) misses, Data cache (D-cache) misses, etc. The MMCR 710 and two PMCs 708, 716 can also be read or written by monitor code represented by line 711. Further in FIG. 7, to determine the relative performance of the target program for each execution, the MMCR 710 is set up so that the PMC 708 counts machine cycles, and the PMC 716 counts instructions executed. Accordingly, the cycles per instruction (CPI) for each execution or called "pass" can be calculated by reading the values of the PMC 708 and the PMC 716 after the target program completes the pass. Further shown in FIG. 7, the monitor 700 writes to the machine monitor control register MMCR 710 to activate/deactivate the incremental counters 706, 714 for each execution of the target program so as to set/reset the performance monitor counter PMCs 708, 716 at the beginning of execution of the target program. The monitor 700 records the value of the performance monitor counter PMC 716 after completion of execution one pass of the target program. It will be appreciated that other recording methods can be used without departure from the scope and spirit of the present invention. For example, in one alternative embodiment, the monitor 700 may record the performance monitor counter PMCs 708, 716 both at the beginning and at the end of the execution pass. Also in FIG. 7, the thread switch controller 702, similar to the thread switch controller 450 of FIG. 4A, triggers a thread switch based on the events communicated (identified by circled "A") on lines 470, 472, 474, 476, 478, 480, 482, 484, and 486 shown in FIG. 4B. The lines 470-484 are only representative events. It will be appreciated to a person skilled in the art that other thread switch triggering events can be implemented without departing from the principles of the present invention. In one embodiment, there are twenty-two (22) conditions or events are implemented in the system 10. Thread Switch Tuning Flow Chart FIG. 8 is a flow chart of the thread switch tuning operation according to the present invention. Box 800 represents the start of the operation. The monitor 700 loads initial values for the thread switch time-out (tst) control register 704 and the thread switch condition (tsc) control register 712 in box 802. The monitor 700 then sets up the performance monitor counters PMCs 708, 716 by writing to the machine monitor control register (MCR) 710 in box 804. The counters PMCs 708, 716 count cycles and the executed instructions during execution of the target program. It will be appreciated that other types of target program performances can be monitored by performance monitor facility 705 according to the principles of the present invention. In box 806, the monitor 700 enables thread switching for the target program so that the thread switching events of the target program can be detected, and the performance of the program, such as the machine cycles and instructions executed can be counted. The monitor 700 then transfers control to the target program and executes the target program in box 808. After completion of the execution of the target program, control is returned from the target program to the monitor 700 as shown in box 810. In box 812, the monitor 700 instructs the thread switch controller 702 to disable the thread switching for the target program. The monitor 700 then deactivates the performance monitor counters PMCs 708, 716 by writing to the machine monitor control register (MMCR) 710 as shown in box 814. Next, the monitor 700 records the values of the performance monitor counters PMCs 708, 716 along with the corresponding values of the thread switch time-out (tst) control register 704 and the thread switch condition (tsc) control register 712 as shown in box 816. In box 818, the monitor 700 determines whether it has tried all the values of the tst control register 704 and the tsc control register 712. If not, the monitor 700 changes the value of the tst/tsc control registers 704, 712 in box 820, and the monitor re-starts the operation from box 804. The changes of tst/tsc control registers' values can be based on the last set value of the tst/tsc control registers 704, 712. It will be appreciated that the value change can be based on other predetermined set of values. If all the values of the tst/tsc control registers 704,712 have been tried by the monitor 700 in executing the target program from box 818, the monitor 700 then chooses the values of the tst/tsc control registers as optimal values, based on the best performance such as the lowest value of cycles per instruction recorded as shown in box 822. The tst/tsc control registers with the chosen (tuned) values can then be loaded prior to executing the target program for end applications. Accordingly, the target program is able to execute the end applications with its optimal performance. The operation ends in box 824. It will be appreciated that other types of performance, other than cycles per instructions (CPI), can be monitored within the principles of the present invention. In alternative embodiments of the present invention, other types and configurations of computers could be used. For example, the invention need not be restricted to the hardware and software configuration illustrated herein. For example, mainframes, minicomputers, or personal computers could be used with the present invention. In another example, peripherals other than tape drives could benefit from the present invention. In alternative embodiments of the present invention, the amount of different values of the tst/tsc control registers used to execute a target program, in order to obtain the optimal performance of the target program, can be adjusted or predetermined. In alternative embodiments of the present invention, the logic described herein could be performed by other types of hardware. For example, the invention need not be restricted to programs or logic executed by the processor as illustrated herein. Instead, the logic of the invention could be performed by embedded processors or specialized electronic circuitry. While the invention has been described in connection with what is presently considered the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
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