Graphical automatic programming4315315Abstract Invention involves a process for automatically producing a computer program in machine assembly language directly from a two-dimensional network representing the flow of data and control logic which it is desired to accomplish on a specified general purpose digital computer. The network used to represent the desired data processing to be programmed involves a fundamentally new type of graphical representation, herein referred to as "data flow circuits". A specially defined "vocabulary" of some 50 basic data processing "data circuit elements" constitute the building blocks of data flow circuits. These elements on the one hand are functionally equivalent to hardware digital processing operations, and on the other hand are exactly defined as a set of computer instructions. The automatic preparation of a computer program by this method is especially advantageous when used with a computer-driven graphics terminal which provides for rapid and interactive configuration of the data flow circuit, on-line testing and immediate output of the final computer program. Claims I claim: Description BACKGROUND OF THE INVENTION
TABLE 1
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DATA FLOW CIRCUIT ELEMENTS
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SENSE ELEMENTS TRANSFER ELEMENTS
BRANCH ON ZERO READ WORD
BRANCH ON PLUS WRITE WORD
BRANCH ON MINUS READ FILE
BRANCH ON CONSTANT
WRITE FILE
FUNCTION TABLE
OPERATOR ELEMENTS
INPUT DATA
ADD OUTPUT DATA
AVERAGE
MULTIPLY ROUTING ELEMENTS
SUBTRACT LINKAGE DATA
DIVIDE PASSIVE SPLIT
EXPONENTIATE DATA SPLIT
AND CONTROL SPLIT
INCLUSIVE OR LINKAGE EXIT
EXCLUSIVE OR PASSIVE JUNCTION
MINIMUM DATA JUNCTION
MAXIMUM CONTROL JUNCTION
LINKAGE STORE
COMPARISON ELEMENTS
DATA GATE
BRANCH ON COMPARE
DATA PACK
BRANCH ON GREATER
LINKAGE ENTRY
BRANCH ON UNEQUAL
DATA LOOP
CORRELATE CONTROL LOOP
THRESHOLD
RANGE GATE SWITCHING ELEMENTS
STORE BRANCH
READ BRANCH
INDEX DATA
INTEGRATING ELEMENTS
SUM ADD
SUM MULITPLY
SUM DIVIDE
SUM EXPONENTIATE
PRODUCT ADD
PRODUCT EXPONENTIATE
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FIG. 3 illustrates the symbolic representation of typical circuit elements. The top rows picture one element of each of the four main functional groups, while the bottom rows illustrate four ROUTING elements. As noted previously, solid lines are used for data signals and dashed lines for control signals. In FIG. 3 the sample elements are seen to have the following types and numbers of connections:
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Data
Control
Data Control
Element Type
Name Inputs
Inputs
Outputs
Outputs
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SENSE BRANCH ON ZERO
1-2 1-0 0-2 2-0
OPERATOR ADD 2 1 1 0
COMPARISON
BRANCH ON COMPARE
2-3 1-0 0-3 3-0
TRANSFER READ FILE 2 2 1 1
SWITCHING
DATA SPLIT 1 0 2 0
INTEGRATING
CONTROL JUNCTION
0 2 0 1
ROUTING STORE BRANCH 0 3 1 0
SUM MULTIPLY 2 1 1 0
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OPERATOR, COMPARISON, and TRANSFER elements are provided with an optional control input to serve as a gate for delaying the functioning of the element until the receipt of a control signal from elsewhere in the circuit. The READ FILE and DATA LOOP elements have a control input which serves a different purpose, namely to initiate the next cycle of the loop. The maximum number of connections for any element is eight, and for SENSE and OPERATOR elements it is four. Connections are numbered clockwise with #1 at 12 o'clock. The characteristics of Data Circuit Elements can best be described by examples. Three of these elements will be used in a simple circuit to illustrate the automatic translation of a data circuit into a computer program. The detailed operation and equivalent code of four of the elements in FIG. 3, are described below. The function of the BRANCH ON COMPARE element is to emit a control signal from one of its three output termimals in accordance with the relative magnitude of the two data inputs at terminals 2 and 3. As the signals in a data circuit flow from an output of one element to an input of another, one link at a time, the step when a given data element performs its function and generates an output occurs when the final input necessary for its operation arrives. In the case of the BRANCH ON COMPARE element in its basic ungated form, only the above two data inputs are required. When the first arrives it is put in a temporary memory location; when the second arrives, usually several steps in the transformation program later, the element functions and generates the appropriate output, which in this instance is a control output from terminal 4, 5 or 6 of the numbered connections of said COMPARE element. In translating the functioning of the element into computer assembly code, the conditions at the time of functioning must be noted. In Appendix A is listed the assembly code equivalent to each of the commonly used data circuit elements in the assembly language of the Honeywell DDP-516 computer. The code labels used hereinbelow are entirely arbitrary. However, it will be convenient to relate them to the notation of the corresponding element input or output connections. When the BRANCH ON COMPARE element is activated by the arrival of the input at terminal 2, the corresponding data word is in a general register, designated AR, while the other data input is in a temporary memory location, labeled M3. The resulting code would have the form listed below for computers having a specific "Compare" instruction. The instructions in word form are listed in the left column and the equivalent instructions in assembly code for the conventional simple computer mentioned in connection with FIG. 1 are listed at the right.
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1. Compare AR with M3 CAS BC3
2. Jump to M4 (if AR > M3)
JMP BC4
3. Jump to M5 (if AR = M3)
JMP BC5
4. Jump to M6 (if AR < M3)
JMP BC6
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Like most SENSE and COMPARISON elements, the BRANCH ON COMPARE element has a terminal 1 that can be used to switch a control or data signal to the particular output conditional on the relative magnitude of the data inputs at terminals 2 and 3. This connection saves the addition of several routing elements which would accomplish the same result. The BRANCH ON COMPARE element also has another form in which there is a data input at terminal 1 while either terminal 2 or 3 is "shorted" to terminal 1. The element will behave as if the input at terminal 1 were also present at the shorted terminal, and hence switch the input accordingly. Since such simple variants of an element are distinguishable in the diagram by a simple notation at the shorted terminal, the same basic element can be used for several closely related functions without ambiguity. The READ FILE element has the function of extracting one or a series of data words from an array or file in memory. In its fully connected form it is designed to operate in a circuit "loop", extracting one word of a sequence at each turn until the file is empty. If the stepping control input at terminal 5 is designated as unconnected, the READ FILE element will extract a single data word from the core location designated by the sum of the inputs at terminals 2 and 3. In the READ FILE element, the input required to generate the code is the control input at terminal 1. When this input arrives, the element reads out the data word located at the address indicated by the initial value of the index, i.e. the number of items in the file to be read out, which has been stored previously at the data input at terminal 2. After the extracted word has been processed, a "stepping" control pulse is received at terminal 5. This input causes the index to step to the next word on the list. If the incremented value of the index shows that no words remain, a control output appears at terminal 6. If not, the next word is read out at terminal 4, initiating the next cycle of the loop. The translation of the READ FILE element into assembly language is written in a single sequence of instructions as soon as the first word is read out. The differentiation between the initial and stepping modes is done by the use of labels which indicate the entry points for the two modes. The code for the READ FILE element is shown below in its generalized form on the left and in conventional computer code on the right. The "IRS" instruction in the conventional code stands for "increment, replace, and skip" and has the function of incrementing the contents of the indicated memory location by one and skipping the next instruction if the result is zero. "SKP" is an unconditional skip instruction. The significance of the other instructions is obvious.
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1. M5:Increment M2 RF5:IRS RF2
SKP
2. Jump to M6 if M2 = 0
JMP RF6
3. M1:Load M2 into XR RF1:LDX RF2
4. Load M3, X into AR
LDA RF3,1
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M5 is the label of the jump instruction which provides the gating input to terminal 5. M1 is the label corresponding to the readout of the first word on the list. Thus, an instruction calling for a jump to M1 would result in the execution of instructions 3 and 4, and eventual return to the loop at instruction 1. M3, X stands for the X'th entry in the file whose base address is in M3, and where X is the contents of the index register. The DATA SPLIT element stores a data input temporarily, and routes it to two other circuit elements. The data input is temporarily stored by the code: 1. Store AR in M1 STA DS1 The CONTROL JUNCTION routes several different control signals to a single element input. While it does not in general produce code, it does change the labels of jump instructions on the connected elements. Data Preparation The word length in most general-purpose computers varies between 12 and 36 bits. The accuracy with which a given variable is known is seldom greater than one part in 2000, which requires 11 bits plus 1 bit to designate sign. Often the accuracy of the data requires 8 bits or less. Since memory capacity is often a limiting factor in the performance of a computer as a system element, it is frequently necessary to combine or "pack" two or more variables into a single data word to economize on memory storage and access time. When an operation must be performed on a given variable, the latter must first be extracted from the data word and manipulated to adjust its sign bit and location to put it into proper form for the ensuing operation. The data preparation usually involves several mask, shift, and complement instructions. In the Data Flow Circuit notation, such preparation is specified as a preliminary to the operation performed by each element. The format of each variable is also specified as part of the circuit definition. The manipulations involved in data preparation, which represent a major portion of the "housekeeping" labor in programming, are thereafter accomplished automatically along with the translation of the functional operations of the elements in the Data Circuit. Application Of Computer Graphics To The Design of Data Flow Circuits The second key element in the technique of Graphical Automatic Programming is the utilization of the newly available computer-driven displays to help the designer lay out a satisfactory Data Flow Circuit, and at the same time store in the computer a complete description of the circuit as drawn. This latter step lays the necessary foundation for automating the transformation of the Data Circuit directly into computer code. The net result is an enormous saving in time in the overall process of Data Flow circuit design, checkout, and translation. The development of computer graphics terminals enables the engineer to use the computer without writing a computer program. An example of a modern graphics terminal is the IBM 2250, which can be driven by most of the IBM 360 computers. The display has a 10-in..times.10-in. cathode-ray-tube screen, a typewriter keyboard, a set of special control keys, and a light pen for direct interaction between the display and the operator. The operator uses the light pen to indicate the point at which he wishes a line or other symbol to appear, or the symbol which he wishes to select, erase, or otherwise operate on as he may direct by the keyboard. Graphics terminals have greatly broadened the utility of computers as direct aids to many human tasks. By enabling the operator to "talk" with pointers and English words rather than through an elaborate code, they are revolutionizing many tasks. For example, a computer program called "ECAP", together with a graphics terminal, enables an engineer to "draw" an electronic circuit on the face of the display, punch in the component values he wishes to try, and in a few moments it gives him the salient characteristics of the circuit. If these characteristics are outside the desired limits, the engineer can adjust component values, alter connections, insert or delete components, and get essentially instantaneous feedback of the effects on performance. This technique promises to shorten the time for circuit design drastically. In the graphic display program for the design of electronic circuits, the available components are first displayed at the bottom of the screen. They are then located in the circuit by pointing in turn to the desired component and then to the desired location on the screen with the light pen. The scanning beam in the display recognizes the location of the light pen, associates it with the component, and positions it accordingly. Elements are connected by simply pointing the pen at each of the terminals to be joined. The successful development of such a powerful technique for the design of electronic circuits suggested that computer graphics might equally help accomplish direct and real-time transformation of Data Circuits into computer routines. The programming of the computer to accomplish this is, of course, quite different from "ECAP," but the property of communication between the engineer and computer by means of symbols and light pen is the same. The display of a Data Circuit is accomplished in the same general manner as that described above for conventional electronic circuits. The symbols used are those defined in FIG. 3 for the Data Circuit elements, with the appropriate character code specifying the member of the element class. The GAP graphic display program is designed to fulfill the following functions: 1. To display the element symbols located by the designer, storing the location of all element connections. 2. To display the data and control connections between the elements, and any special notation entered by the designer, including data preparation. 3. To associate the linked elements into an "Interconnection Matrix." 4. To check for any obvious errors in the diagram and to signal them to the designer. 5. To interact with the designer in the later stages of program generation by displaying anomalies or altering the circuit as directed. Example Of The Graphical Design Of A Data Flow Circuit The following elementary process illustrates how a simple Data Flow Circuit would be designed. Data Inputs: 1. A number of potential target returns or "hits" have been received by a radar during several dwells. 2. The Amplitude, A, and Range, R, of each hit have been encoded into a single word A, R. 3. The hits have been listed sequentially in a file. Data Processing: 1. All hits whose amplitude equals or exceeds a certain threshold are to be retained and stored in another file for further processing. 2. Other hits are to be rejected. The representation of this process in a conventional programmer's Logic Flow Diagram is shown in FIG. 4. In the figure, a potential target return is called a "HIT," and a return exceeding the threshold is called a "TRK," a mnemonic for "track." The diagram shows the steps required in indexing and the three decision branch points which occur when the amplitude is below the threshold or when either file is exhausted. The representation of this data process in Data Flow Circuit language can be accomplished by the use of three functional elements. 1. READ FILE, to extract each hit from the hit entry file. 2. BRANCH ON GREATER, to select hits whose amplitude equals or exceeds the threshold. 3. WRITE FILE, to enter the selected hits into another file for retention. The designer selects the READ FILE (RF) and WRITE FILE (WF) from the TRANSFER elements and positions them on the screen with the aid of a 1/4 in. grid used during circuit assembly. If he wishes to use the basic form of the BRANCH ON GREATER (BG) element, he positions it to one side to provide the path for the hit selection logic. He then selects and locates the signal ROUTING elements and connects the element inputs and outputs with data (solid) or control (dashed) lines. The ROUTING elements required are a DATA SPLIT (DS) to route the extracted hit to both the BRANCH ON GREATER element and the WRITE FILE element, and a DATA GATE (DG) to pass the hit for entry only if the comparison shows that its amplitude passes the threshold. the partially completed circuit diagram is shown in FIG. 5a. The next step is to enter the arrows marking the input end of each connection, as well as other auxiliary labels and symbols (FIG. 5b). Where data inputs are to be stored in permanent memory locations, the input is indicated by a diamond with a symbol denoting the variable. Where a data input requires preparation, such as extracting the amplitude A from the hit word (R,A), the input arrow is closed into a triangle. In order to help him remember the data and control inputs to the different elements, the designer may type in appropriate symbols on the keyboard and place them on the diagram by means of the light pen. In FIG. 5b the file names "HIT" and "TRK" are indicated on the RF and WF elements, as well as the number of his "NHT" and the number of empty spaces in the TRK file "JTK". The threshold and amplitude connections on the BG element are indicated by the symbols "THR" and "A," respectively. In representing the BRANCH ON GREATER element, which is a derivative of BRANCH ON COMPARE, the difference is depicted in the figure by locating a character `4` opposite terminal 5. This notation denotes that the output normally present at this terminal is "shorted" (combined) with the output of terminal 4. FIG. 5b includes a passive CONTROL JUNCTION (CJ) element and a connecting link from it to the WF element that are not shown in FIG. 5a. FIG. 5b also shows terminals marked "EXH" and "EXT" (Exit) to the RF and WF elements. The appearance of these features illustrates how the GAP graphics program would discover formal errors or omissions by the designer in connecting the circuit elements. The computer examines each connection to see whether it has been assigned its proper function, i.e., data or control, input or output, and indicates omissions or incompatibilities by flashing or otherwise marking the connections involved. The designer would correct such errors before initiating the transformation of the circuit into computer code. The data tables stored in the computer to generate the above circuit design on a terminal such as the IBM 2250 would then be converted by an automatic program into a table of logical connections represented by the circuit. Element Interconnection Matrix The information concerning the configuration of the data flow circuit entered by the designer is organized by the computer into a table which will be called the Element Interconnection Matrix. The matrix for the circuit described in FIG. 5a and 5b is shown in Table 2.
TABLE 2
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ELEMENT INTERCONNECTION MATRIX
ELEMENTS LINKAGES TERMINALS
Ref.
NAME No.
Label
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
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LINKAGE 0 LD RF2
RF3
BG2
WF2
WF3
LE1
C Y Y Y Y Y J
DATA
LINKAGE 1 LE LD7
RF1 C J
ENTRY
READ 2 RF LE2
LD2
LD3
DS1
CJ3
LX1 C X X Y C J
FILE
BRANCH 3 BG U LD4
DS3
DG3
`4`
CJ1 U X X J 4 J
ON GREATER
WRITE 4 WF DG2
LD5
LD6
U CJ2
LX2 X X X U J J
FILE
DATA 5 DS RF4
DG1
BG3 X Y Y
SPLIT
DATA 6 DG DS2
WF1
BG4 X C Y
GATE
COLTROL 7 CJ BG6
WF5
RF5 C C J
JUNCTION
LINKAGE 8 LX RF6
WF6 C C
EXIT
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The first three columns contain the element name, reference number in the circuit, and label. The next six numbered columns are the labels of the connections of each respective terminal. Each terminal which is linked to another element in the circuit is labeled with the code and terminal number of that element. For example, the entry "DS1" in column 4 of row 3 means that terminal 4 of RF is linked to terminal 1 of DS. Since there may be several elements of a given type in a single circuit, in actual practice the labels would use the reference numbers instead of the element label. In the above example, the reference number "5" of the DS element would be used instead of the characters "DS". It will be seen from Table 2 that three elements not shown in FIG. 5 appear in the element Interconnection Matrix. These are the three of the four Linkage routing elements, LINKAGE DATA (LD), LINKAGE ENTRY (LE), and LINKAGE EXIT (LX). Linkage elements are generally not displayed on a graphics terminal, since they represent non-functional interface terminals of the data flow circuit to other parts of the overall program. However, they are a necessary part of the circuit description and hence must be defined by the designer and incorporated into the Interconnection Matrix and thence transformed into computer code. In addition to the entry of element interconnections, a separate list is entered of all "Data Prepare" operations. Also each output of a Linkage Data element, representing a file location, index, or reference word, must be defined in the Dictionary. In the above example, NHT, HIT, THR, JTK and TRK are so defined. In addition, connections of control inputs and outputs at LE and LX must be labeled to correspond to the designations of the corresponding linkages to other portions of the program. The Dictionary is used in the translation of the data flow circuit into computer code. The last column of the matrix designated "Connections" indicates the type of each connection, namely: X: Data Input Y: Data Output C: Control Input J: Control Output U: Unconnected The data in this column enable the program to make sure that an output always goes to an input and that each element has the appropriate type of connections. Transformation Of Graphical Into Logical Form The third key feature of Graphical Automatic Programming is the automatic transformation of the Element Interconnection Matrix, generated by the graphics terminal from the Data Flow Circuit, into the desired computer program. This requires the translation of the designated process represented by a two-dimensional circuit diagram into a one-dimensional sequence of computer instructions. The noteworthy facts are that this transformation can be done entirely automatically and that the resulting program is highly efficient in execution time and Core usage. It will be recalled that in a Data Flow Circuit, as opposed to an ordinary digital circuit, signals flow in a succession of steps, each representing the transfer of a signal from an output of one element to an input of an adjoining element. The transformation of a Data Flow Circuit into an operational sequence involves putting these steps into an order which can be performed efficiently by a general-purpose computer. A set of rules produces a program that has high efficiency and is logically consistent. The transformation procedure begins by initializing the data inputs entered from external memory locations specified in the Linkage Data element. It then proceeds to stack all but one of the external control entry inputs of the Linkage Entry element and examine the element to which this input is connected. The next and subsequent steps in the transformation program proceed in accordance with specific procedures for each element "Transformation Type". The different Transformation Types fall into four primary classes, as described in the first column of Table 3. Of these, the Branching and Joining types are seen from column two of Table 3 to be involved in switching or combining branches of different logical content. The Operating and Splitting types are involved in operation and distribution of data with the same logical content. The Joining and Splitting types involve only routing elements.
TABLE 3
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ELEMENT TRANSFORMATION RULES
TRANSFORMATION
ELEMENT TRANSFORMATION PROCEDURE
TYPE FUNCTION FIRST INPUT FINAL INPUT
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BRANCHING BRANCH SIGNAL PATH
STORE DATA INPUT(S)
WRITE ELEMENT CODE
ACCORDING TO INPUT
LINK NEXT SPLIT
DEFER JUMP OUPUT(S)
CONDITION(S) LINK TO IMMEDIATE OUTPUT
JOINING JOIN TWO JUMP FORWARD TO
WRITE ELEMENT CODE
BRANCHES ADDRESS OF OUTPUT
LABEL ADDRESS OF OUTPUT
LINK NEXT BRANCH
LINK TO OUTPUT
OPERATING OPERATE ON TWO OR
STORE DATA INPUT(S)
WRITE ELEMENT CODE
MORE INPUTS TO FORM
LINK NEXT SPLIT
LINK TO OUTPUT
AN OUTPUT
SPLITTING DISTRIBUTE SIGNAL
(ONLY ONE INPUT)
WRITE ELEMENT CODE
TO TWO ELEMENTS DEFER ONE OUTPUT
LINK TO OTHER OUTPUT
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In transforming the first two types of elements rules have been established to insure correct logical behavior. In transforming the second two, the rules insure efficient ordering of the operations to conserve execution time and memory usage. The last two columns of Table 3 gives the Transformation procedures for two different input conditions of the element types. The first occurs with the arrival of an initial input preceding the arrival of the last one. The second occurs with the arrival of the final input necessary for the element to function. The writing of a general element code is seen to occur in the second step. The other steps result in signal routing operations. The above rules apply to all elements except those members of the first two types which have a recycle mode. Examples of such elements are the READ FILE discussed previously and the DATA LOOP routing element. For these elements the procedure listed in the last column of Table 3 is used when the final input of the first cycle arrives. When the final input for the recycle mode arrives the procedure is to jump back to the labeled location of the feedback input and then to link the next branch. In the table the term "next branch" refers to the last deferred jump output from a previously completed branching element. This order insures against jumping out of an incomplete loop. The "next split" refers to the last deferred output from a previously completed split element. The term "Link" specifies the element which is examined in the next step of the transformation. The logic behind the Transformation Rules is the following: 1. Branching Elements These elements serve to switch the sequence of operations into one of two or more alternative paths, each of a different logical content, depending on the conditions which determine this decision for the particular element. In terms of a computer program, which can process only one signal at a time, the branching must be accomplished by selecting one of the branches as the continuation of the main sequence, deferring the processing of the alternative branches until a suitable stopping point is reached in the main sequence. This is accomplished by writing a "Jump" instruction for each deferred branch with a designation to be specified later when the processing of that branch can resume. 2. Joining Elements These elements serve to join two sequences of operation, or branches, with different logical content into a single sequence. The first sequence to arrive at a joining element must await further processing until the other sequence has reached the same point. This is accomplished by an unconditional "Jump" instruction at the end of the first sequence (input) to arrive. Following this point the sequence must shift to process the last branch output to be deferred. This order is necessary to insure against endless loops and other logical traps. When the last input arrives at the joining element, the operational sequence continues and the address of the junction is inserted as the destination of the jump instructions of the branch(es) which rejoin the main sequence. 3. Operating Elements These elements serve to perform an operation on two or more data inputs to produce a single data output. The initial inputs are stored for later use, as in incomplete branching elements. The final input causes the operation characteristic of the element to be performed and the sequence of operations to continue to the element linked to the output. No change in logical content is involved. 4. Splitting Elements These elements serve to split off a data or control signal from the main signal flow for later reference. This is done in the computer program in the case of data by storing the data in a temporary memory location which is accessed at a later time. In the case of a control signal this is done by storing a "flag" or jump location in a temporary memory store, which later directs the processing into a particular branch in the sequence of operations. In the transformation program the main operational sequence is deferred until the data or control flag is stored for later reference (as the input to the appropriate element). Provision is made against branching or joining the operational sequence while any deferred split outputs remain unprocessed, since the logical content must remain the same for all split outputs. A detailed set of rules for transforming links to each different member or subclass of the form main transformation types is given in Appendix B. Transformation Of A Data Flow Circuit The applications of most of the above rules to the translation of a data circuit into computer instructions can be illustrated by proceeding step-by-step through the process on the very simple circuit described hereinabove. By referring to FIG. 6a the first step of the transformation process will be seen. The process begins by tabulating and labeling the inputs and outputs connecting a circuit block to other blocks in the overall program. The external data inputs come from the LINKAGE DATA element, not shown. They are: two connections to files--HIT and TRK, and three data word inputs--the file indices NHT and JTK, and the threshold THR. There are three external control inputs and outputs, i.e., one enter, ENT, and two exits, EXH and EXT, located in the LINKAGE ENTRY and LINKAGE EXIT elements, not shown. A section of the computer program is assigned to the definition of the labels used in the instruction code. This section, called the "Linkage" area, defines the labels used in referring to each external connection. The resulting assembly code, in the language of the Honeywell DDP-516 computer, is given in the top block at the right side of FIG. 6a. The instruction "DAC" stands for "Declare Address Constant" and serves to define the labels used in the assembly code for the circuit in terms of labels for variables and files defined for the overall program. The labels used for all memory locations are defined in terms of the elements connections, as used in the Element Interconnection Matrix (Table 2). The linkage section will later be used to connect the circuit block to others in the program. Other circuit blocks may be in a different section of the computer memory, and in the prior art computer have to be addressed by the "indirect" memory address mode. An asterisk is used to indicate indirect addressing. The listing of the external connections in the Linkage section produces one control output, namely from the ENT (enter) symbol to RF6. This and other outputs are listed in FIG. 6a at the right of the instruction block. The first link to be made in the circuit is the connection of the above output to the READ FILE element. Since the index data input is already available in the Linkage, the RF element functions when the control input RF6 arrives. This step results in the following set of operations which transforms the circuit into computer code: 1. Write code for RF element in its gated form. defer branch output RF6. Proceed to output RF4. In accordance with the transformation rules, the undeferred output, RF4, is chosen as link 2, the next step in the transformation. This, and the subsequent five steps in the transformation of the circuit are illustrated in FIG. 6b. The number of each output selected, the corresponding link formed in the circuit, and the resulting block of code are shown by a circled number. The Linkage section of code is not repeated, for the sake of brevity. The arrival of the data input to the DATA SPLIT element in Step 2 causes it to function. This stores the input temporarily and produces two data outputs. The transformation results in the following operations: 2. Write code for DS element. Defer split output DS3. Proceed to output DS2. The element connected to DS2, the DATA GATE element (DG), requires the presence of the control input as well as the data input in order to function. Since the former has not yet arrived and the latter is already stored in a temporary location, DS1, the completion of link 3 does not result in any code but merely the entry of the temporary store label DS1 into the input of the DG element, and hence the operation: 3. Change label on DG1 to DS1. According to the transformation rules, the step following the input of a data signal into an incomplete Operator element is to operate on the deferred split output, DS3. This goes to the input of the BRANCH ON GREATER element in Step 2 in the transformation. This completes the inputs required for the BG element to function, and results in the operations: 4. Prepare input BG2. Write code for BG element. Defer branch output BG6. Proceed to output BG4. The data input, BG2, has to be prepared by extracting the amplitude, A. This is accomplished by a logical "and" (ANA) masking operation, which is included in the first instruction of the block of code written for the BG element. The next output to be transformed is the last deferred control output, BG6. In Step 5 this output provides one of the two necessary inputs to the CONTROL JUNCTION element, but results in no additional code since the jump instruction was written during the coding of the RF element in Step 2. Output BG6, Step 6, completes the required inputs to the DATA GATE. This step results in the operations: 6. Write code for DG element. Proceed to output DG2. Step 7 is to link data output DG2 to WF1, which causes the WF element to function. This results in the operations shown in the last block in FIG. 6b: 7. Write code for WF element. Defer control output WF6. Proceed to output WF5. The final figure of the series, 6c, shows the completion of the last four links in the circuit. Output WF5 causes the CJ element to function. The functioning of the CJ element completes the link to RF and simply changes the labels on the control. Element Operational Sequence--In FIG. 6 the Data Circuit was transformed directly into computer assembly code. In actual practice it is useful to divide this process into two steps. 1. Transformation of the Element Interconnection Matrix into an Operational Sequence. 2. Compilation of the Operational Sequence into Computer Code. The first step is the really fundamental one, since it converts the two-dimensional matrix into a one-dimensional sequence. This is done by following the priority order of the circuit transformation rules. During this process some of the signal routing elements effectively disappear after establishing the sequence of operation of the functional elements and making direct interconnections among the functional elements themselves. The result of this first step for the example discussed above is shown in Table 4.
TABLE 4
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ELEMENT OPERATIONAL SEQUENCE
Sequence
Reference Element Input Input
Number Number Label Form Terminal
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1 0 LD C 1
2 2 RF C 1
3 5 DS X 1
4 3 BG X 3
5 6 DG C 2
6 4 WF X 1
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When Table 4 is compared with Table 2 it will be seen that the LE, CJ and LX elements have disappeared since their operation produces no new code. In addition to producing the Element Operational Sequence the Transformation program lists any changes to be made in the input and output linkage entries of the functional elements as indicated by the transformation of the routing elements. For example, the output linkage of WF5 to CJ1 is altered to link directly to RF5 after the CJ element is transformed. Similarly, the program notes that the address of the data stored in DG1 is DS1. Compilation Of Computer Code The information generated by the transformation program, combined with that entered previously, together with equivalent element computer code as defined for each computer to be programmed, are sufficient to generate optimum assembly code. This may be done conveniently in two steps: The first is to assemble all of the information derived in the transformation program for each element in the operational sequence, and the second is to generate computer code for each element in turn by reference to the element code equivalents. The assembly of information for each element is derived by collecting the pertinent data from the following lists: 1. Data Prepare List, with definition of each variable by reference to the Dictionary 2. Link Label List, which notes labels of inputs and outputs altered during the transformation program, as well as certain load, store or jump labels. The compilation of code for each entry in the operational sequence then proceeds, by reference to equivalent code definition and to the interconnection matrix, by listing the code instructions equivalent to each of the following steps. 1. Preparation of input signals as directed by the Prepare List and Link Label List. 2. Operation of the element itself, including any prepare operations on stored inputs. 3. Preparation of output signals as in Item 1 above. At the same time a list may be made of core usage and operating time for each entry in the operational sequence. This process is seen to involve a mechanical substitution of the code for each element in the operational sequence, with due regard for the mechanics of storing and retrieving data from temporary stores as indicated by the notation in the connection field, and the conversion of label notation to suit the format of the specific computer code being written. The compact and universal form of the Element Operational Sequence and associated data means that this intermediate step in program design can be used to check the program logic using any computer code, including the one which drives the interactive terminal, such as an IBM 360. Thus, compilation of the IBM 360 version of the code enables the immediate on-line test of the entire logical design of the circuit and of its transformation into the sequence of operations. If this is successful, the program logic can be considered "debugged" for all practical purposes, inasmuch as the conversion to the code for another computer involves no change in operational logic. This on-line debugging capability is an enormous advantage inherent in the use of the graphics or other interactive terminal to effect direct interaction with the computer. The program can then be automatically recompiled in the code of the specific computer for which it was designed. Integration And Testing Of Complex Programs A data-processing program for a large-scale system can be represented as a Data Flow Block Diagram, in which each block is an individual Data Flow Circuit. Each Circuit Block can be regarded as a special "Macro" Circuit element, with data and control signal inputs and outputs connecting it to other blocks which comprise the total program. The integration of Data Flow Circuits is readily accomplished by the use of the graphics terminal and a special Integration Program in a manner similar to that used in constructing the Data Flow Circuits. This program serves the purpose of a "Linkage Editor" in computer terminology. The representation of a Data Flow Circuit as a Program Block is shown in FIG. 7, using the Hit Sorting Program as a simple example. It is seen that the block has 8 connections, namely 4 data inputs, 1 data output, 1 control input, and 2 control outputs. By reference to FIG. 6a it can also be seen that all of these connections are embodied in the Linkage Section of the code for the block. This section is equivalent to a terminal strip in a piece of electronic equipment. The integration of program blocks into the total program may be simply done by drawing the program Block Diagram on the graphics display and making proper connections between the individual blocks. In such a diagram, it is important to keep all files external to the processing circuits. An example of such a diagram is shown in FIG. 8, which represents the Track Prediction module of the 3D Radar Automatic Tracking Program. The program blocks are represented by rectangles and the data files by squares. The block illustrated in FIG. 2 is near the center of the diagram. The very important function of synchronizing the operations of the program with the real-time schedule of radar transmission, elevation scanning, and rotation is accomplished by three "Executive" blocks supervised by a master Executive block. The Data Flow representation is ideally suited to visualize the detailed interactions between the high-priority, real-time functions and the supporting functions which may be accomplished with loose scheduling. The transformation of the Block Diagram into computer assembly code involves only the proper correlation of the block linkage labels, where all inputs and outputs are listed. Since the module is itself a "block," as seen in FIG. 9, the next higher level of program integration is done in terms of entire modules rather than blocks. In this way an orderly and flexible format for the total program can be achieved. Program Dictionary--The efficient management of the process of program design requires careful definition, organization, and maintenance of all terms used in the program. The list of these properties has to be assembled during the design process and, when complete, constitutes a basis for fully documenting the program and facilitating future changes. The data required for this list include the code names, definitions, format, constituent parts, and cross-references of all of the following in a Program Dictionary: 1. Variables and constants 2. Data Files 3. Circuit Blocks 4. Modules In addition, areas of memory must be allotted to store each of the above. Once the above terms have been defined, their subsequent use requires only reference by code name. The computer automatically looks up the necessary characteristics in the Program Dictionary. This saves a great deal of housekeeping by the system designer, and should eliminate a major source of error. Program Checkout--The most laborious and time-consuming part of programing is the elimination of errors, or "debugging". In this area Graphical Automatic Programming is likely to produce one of its greatest benefits in program design. The power of this technique to facilitate the production of a correct program stems from the following sources: 1. The Data Flow Circuit representation renders the pattern of data and logic flow highly visible and hence eliminates many errors at the source. 2. The entry of the Data Flow Circuit into the computer enables a virtually instantaneous check of any inconsistencies in the design by checking the Element Interconnection Matrix and monitoring its transformation into computer code. 3. The display of the circuit by a graphics terminal enables the designer to correct errors immediately by altering the circuit and verifying that the errors have been eliminated. 4. The GAP technique is ideally suited to rapid and thorough testing of the program at any desired level of realism. Thus, upon completion of a constituent circuit, the designer can test it by entering sample inputs and reading out the resulting outputs. He can also quickly design a test program in the form of another Data Circuit which would perform a realistic simulation of the program input and automatically compare the results with requirements. A particularly important type of test that may be performed automatically is that of compatibility with real-time operation. Since the functioning of each element corresponds to a definite execution time in the computer to be employed, it is readily possible to have the test program simulate the execution time and monitor it against specified events. Documentary Configuration of Data Flow Circuits As described hereinabove, it is convenient in the design of GAP circuits on a graphics terminal to configure the Data Flow Circuit in a compact form to fit on the roughly square face of the display. This is also the form in which alternative parallel branches can best be represented, just as in conventional engineering circuit diagrams. There are circumstances, however, in which the compact form of circuit representation is not the most advantageous. An important case is that of program documentation. For this purpose it is desirable to represent not only all of the data and control flow paths, but also the sequence in which the transformation program has arranged the functional branches of the circuit. It is also desirable to configure the circuit in a highly orderly and standardized manner, with maximum visibility of the course of each individual conditional branch and of each individual data variable. A modified representation satisfying the above requirements is shown in FIG. 10. It will be referred to as the "documentary" form, as opposed to the "compact" form. The circuit is identical in all respects to the left hand portion of FIG. 2. Its salient characteristics are as follows: 1. All functional elements are arranged in a central vertical column, in the operational sequence in which they are ordered by the transformation program. 2. Each data signal which is temporarily stored by a Data Split for distribution to two or more elements is routed along a vertical line on one side (to the right) of the central operational sequence. 3. Each branching signal is routed along a vertical line on the other side (to the left) of the operational sequence. Since the same signal path can carry both data and control logic, the lines on this side may be either solid or dotted. 4. Identification of linkage connections, prepare operations, branch numbers and other notation is carried in the margins and alongside the operational sequence. Reference to FIG. 10 shows that there are several different types of branches represented on the left of the figure. B1 is a Linkage Entry branch. B2 and B6 are Linkage Exit branches. B4, B8 and B9 are deferred conditional branches. B11 is a deferred junctions. B12 is a loop feedback. It may, be seen that branches 4, 8, 9 and 10 are stored in the Store Branch (SB) element, and the identity of the stored branch carried by 11 to the Read Branch (RB) element which produces three corresponding branches after the Write Word Element functions. The notation on the margin documents all Linkage inputs and outputs, and lists the assigned labels. In addition, the Prepare operations are identified. The ones shown perform the operations AD1 (add one), MSK (mask) and DPK (pack). It is seen that this alternative form of the circuit lends itself to providing a more complete and formal description of all salient features of the circuit in a manner particularly easy to follow if changes (program patches) are made. It is also possible to inspect the logical consistency of the circuit at a glance. It is seen that no deferred branches cross one another or the loop feedback. It is also seen that all branches stored in the Store Branch element are joined in the Data Function preceding the Write Word element and are properly read out in the Read Branch element. In addition this form is especially convenient for listing the running times through the circuit. The documentary form of the Data Flow Circuit may also be simulated on an alphanumeric terminal for purposes of documentation. This may be done in any one of a number of convenient ways, as for example where the elements may be indicated by their labels and terminal forms, and the connections only outlined. With this notation an ordinary typewriter terminal may be used to output a Data Flow Circuit for documentation purposes. This more formalized notation may also be employed for designing programs on a common remote terminal. This process is more laborious than that employing a full graphics terminal with light pen, but is more widely available and considerably less expensive. For users not requiring a high program output, this type of terminal may well prove the most practical. The transformation program is accommodated in well under 4000 words (IBM CPS format), using disk files for reference data. The documentary notation is also more similar to the logic diagram form familiar to programmers, and hence may be preferred by some users. The representation is of course also fully compatible with a graphics terminal. Design Of Data Flow Circuits The representation of data-processing operations in the Data Flow Circuit form has turned out to have all of the characteristics which were sought for in a basic language for the programming of real-time systems. For those interested in how a given program is translated by the designer into a Data Flow Circuit, the paragraphs below illustrate how one might design the circuit illustrated in FIG. 2. The design of a particular Data Flow Circuit is best approached by constructing a "cause-effect table"--similar to a "truth table" or "decision matrix" in mathematical logic. This lists the possible combinations of input conditions and the corresponding outputs. For its application to the Target Coordinate Computation Circuit illustrated in the figure, the logic is as follows: 1. if no prior hit exists in the target data file (TD4), set number of hits =1 and store coordinates of new hit in target data files (TD4, TD5). 2. If previous hit exists, but does not coincide in range with new hit, exit to multiple target routine. 3. If previous hit correlates in range, increment number of hits, store target coordinates of strongest hit. This leads to the following cause-effect table in which A is amplitude, .DELTA.R is range increment within the gate, B is bearing, E is elevation.
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Conditions (Cause)
Previous entry in TD4,
(A, .DELTA.R)
None Yes Yes Yes Yes
.DELTA.R of hit correlates with
previous entry
-- No Yes Yes Yes
Amplitude of hit compared
-- -- Greater
Equal
Less
to previous entry
Actions (Effect)
Number of hits
Set = 1
-- Add 1
Add 1
Add 1
Store in file TD4,
(N,A,.DELTA.R)
New hit
-- New Hit
Previous
Previous
hit hit
Store in file TD5,
New hit
-- New hit
Average
--
(B,E)
Other -- Exit
-- -- --
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From the cause-effect table it is evident that the following functional elements will be required. 1. READ FILE (RF) and WRITE FILE (WF) elements to read out data on new hits, previous entry, and to store updated coordinates. 2. CORRELATE (CR) element to check range correlation. 3. BRANCH ON COMPARE (BC) element to compare amplitude of new and previous hit. 4. AVERAGE (AV) elements to combine bearing and elevation for hits of equal amplitude. The table also helps to arrange these operations in an efficient order in the circuit. It is evident, for example, that the range correlation check should be made before amplitude comparison. With the aid of this type of logical organization, the layout of a Data Circuit such as the one shown in FIG. 2 folllows quite readily. The representation is intuitively easy to use by engineers, and makes it relatively simple to configure the routing elements to minimize the total number of instructions. For example, convergence of the data paths before storage of the updated coordinates is an obvious saving in code. This type of optiminization is made much more visible by the Data Circuit representation than by the conventional sequential logic approach. The Data Circuit language thus makes it possible for an engineer to design the data flow process, in a form with which he is intuitively familiar, to achieve the best balance between operational requirements on accuracy, capacity, and timing within the limitations of available computer speed and size. The language is also directly interpretable by a programmer, so that even without the automatic features it bridges the communication gap which currently represents one of the greatest impediments to the economical design of system "software." APPENDIX A EQUIVALENT CODE FOR DATA CIRCUIT ELEMENTS INSTRUCTION FORMAT FOR HONEYWELL DDP-516 The tables in this Appendix give for the Data Circuit Elements the equivalent code in the assembly language of the Honeywell DDP-516 computer, as used in the text. Where an element has several forms in which it can be connected so as to vary its function in convenient ways but in a well defined and formal fashion, the code for each is listed at the right. Under input conditions, the first entry is the last input to arrive. The second entry indicates where a given input is to be prepared before processing by the characters "pr" followed by the terminal number. For each such entry the instruction directly at the right is inserted in the code; otherwise the code skips the instruction. The characters "pr" in the code column stand for whatever DDP-516 code corresponds to the GAP prepare instruction. The code is not repeated for similar members of the class, where the difference is so indicated.
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SENSE ELEMENTS
Input
Element Name Label
Form
Conditions
Code
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BRANCH ON ZERO
BZ CXJJ
C1 1.
LDA BZ2
pr2 2.
pr2
3.
SNZ
4.
JMP BZ4
XXYY
X1 1.
STA BZ1
2.
LDA BZ2
pr2 3.
pr2
4.
SNZ
5.
RCB
6.
LDA BZ1
7.
SSC
8.
JMP BZ4
X1YY
X1 pr2 1.
STA BZ1
2.
Go to 3 above
X1 1.
SNZ
2.
JMP BZ4
X1JJ
X1 pr1 1.
pr1
2.
SNZ
3.
JMP BZ4
BRANCH ON PLUS
BP Same except SMI for SNZ
BRANCH ON MINUS
BM Same except SPL for SNZ
BRANCH ON CONSTANT
BK Same except pr is SUB
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