Method and apparatus for generating multiple processor-specific code segments in a single executable6473897Abstract A computer-implemented method analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object code that can be executed by one of the processor types compared with generating a non-customized version. If a performance advantage would be achieved, the method generates at least one customized object code version and a non-customized version for the source code segment, and it generates a control section that causes one of the object code versions to be called during execution of the object code in accordance with an executing processor's processor type. If no performance advantage would be achieved, the method generates a non-customized version of the object code that can be executed by any of the different processor types. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE I
cpu_specifier Processor Type
pentium_iii Pentium .RTM. III processor
pentium_ii Pentium .RTM. II processor
pentium_pro Pentium .RTM. Pro processor
pentium_mmx Pentium .RTM. processor with MMX .TM. technology
pentium Pentium .RTM. processor
generic A "generic" processor, other than one of the Pentium .RTM.
processor family or Pentium .RTM. Pro processor family
The second construct is a "dispatch" construct which is used during compilation to identify the processor-specific constructs and the different processor types to which they correspond. The syntax of this dispatch construct is: cpu_dispatch (cpu_specifier [, cpu_specifier [ . . . ]]) empty_function_definition The "empty_function_definition" is an empty function (no code) having the same name as the function_definition. Multiple cpu_specifier identifiers may be included in the cpu_dispatch construct, one for each cpu_specific construct for the function_definition. According to one embodiment of the present invention, the cpu_specific and cpu_dispatch constructs are implemented as an "extension" to the C and C++ programming languages. Although these extension constructs are not part of the original programming language, they can be added to the language and used as if they were a part of the original language, such as by using the Microsoft.TM. "_declspec" keyword. The"_declspec" keyword can be used to identify a function as an extension to the language. According implementation, the syntax for doing so is as follows: _declspec (cpu_specific (cpu_specifier))function definition _declspec (cpu_dispatch (cpu_specifier [, cpu_specifier [ . . . ]]) empty_function_definition The cpu_specifier, function_definition, and empty_function_definition are the same as discussed above. FIG. 2 illustrates multiple code segments written in the C++ programming language incorporating the cpu_specific and cpu_dispatch constructs. As illustrated, software program 200 includes a first cpu_specific construct 201 which identifies a print_cpu function 205 customized to the Pentium.RTM. III processor (as indicated by cpu_specifier identifier 208). Similarly, program 200 also includes a second cpu_specific construct 211 which identifies a print_cpu function 215 customized to a Pentium.RTM. II processor, a third CPU-specific construct 221 which identifies a print_cpu function 225 customized to the Pentium.RTM. Pro processor, a fourth cpu_specific construct 241 which identifies a print_cpu function 245 customized to the Pentium.RTM. processor with MMX.TM. technology, and a fifth print_cpu construct 261 which identifies a print_cpu function 265 customized to the Pentium.RTM. processor. As illustrated, each of the five print_cpu functions has the same function name but different instructions which are customized to particular processor types. Software program 200 also includes a cpu_dispatch construct 281. The cpu_dispatch construct 281 includes a list of identifiers which includes each of the processor types listed in the cpu_specific constructs 201, 211, 221, 241, and 261. The cpu_dispatch construct 281 identifies a print_cpu function 287, the name of which is the same as the function in the cpu_specific constructs 201, 211, 221, 211, and 261 The cpu_specific constructs and the cpu_dispatch constructs allow the present invention to be used multiple times within the same program on different function names. Thus, other processor-specific functions (not shown) can be included along with constructs 201, 211, 221, 241, 261, and 281 in program 200. It should be noted that the cpu_specific functions 201, 211, 221, 241, and 261 of FIG. 2 may be located adjacent one another as illustrated in program 200, or alternatively may be distributed throughout different locations of program 200. FIG. 3 is a flowchart illustrating the steps followed in compiling the high-level language according to one embodiment of the present invention. During compilation, a dispatch construct is first identified, step 305. In the illustrated embodiment, this is the cpu_dispatch construct 281 of FIG. 2. Processor-specific constructs corresponding to the dispatch construct are then identified, step 310. In the illustrated embodiment, the empty_function_definition of the cpu_dispatch construct is the same name as the function_definition of the cpu_specific construct. Thus, the compiler is able to search through the high-level program to identify each of the different processor-specific constructs which correspond to the dispatch construct, which are constructs 201, 211, 221, 241, and 261 of FIG. 2. The compiler then modifies the names of each of the processor-specific functions, step 315. This is done in order for the assembler to distinguish between each of the different functions. However, this step is done by the compiler and is not visible to the high-level language programmer, who views each of the functions as having the same name. In one embodiment, this is accomplished by a "name mangling" algorithm, which modifies function names as necessary during compilation. In this embodiment, the compiler is pre-programmed with possible processor types and an appropriate modification for each function name based on processor type. By way of example, the characters "$B" can be added to the end of a function name for a Pentium.RTM. processor type, while the characters "$F" can be added to the end of a function name for a Pentium.RTM. III processor type. In the illustrated embodiment, at least one character which is an invalid character for a function name in the high-level language is added to the function name in the object code. This use of an invalid high-level language character in the object code ensures that the compiler does not modify the name to be the same as another function name created by the programmer. The compiler then generates multiple assembly code processor tests corresponding to the dispatch construct, step 390. These multiple tests access an intel_cpu_indicator variable to identify the processor type. According to one embodiment of the present invention, the intel_cpu_indicator is a bit vector which encodes the processor type. The bit vectors and their corresponding processor types according to one embodiment of the present invention are illustrated in Table II below. Alternate embodiments can include a lesser or greater number of bits.
TABLE II
Bit Vector Processor Type
00000000000000000000000000000001 generic
00000000000000000000000000000010 Pentium .RTM. processor
00000000000000000000000000000100 Pentium .RTM. Pro processor
00000000000000000000000000001000 Pentium .RTM. processor with
MMX .TM. technology
00000000000000000000000000010000 Pentium .RTM. II processor
00000000000000000000000000100000 Pentium .RTM. III processor
The compiler then adds a "call to dispatch fail function" instruction to the assembly code, step 325. This dispatch fail instruction identifies a course of action to take when the processor type is not identifiable. In the illustrated embodiment, the dispatch fail instruction is a jump instruction to a dispatch fail function which is a library function that is programmer-replaceable. Thus, the programmer is able to display, for example, an error message indicating the program cannot be executed by the current processor, or alternatively provide a "bare minimum" amount of code which will allow the program to continue running. The compiler then adds a "call to processor identification function" instruction to the assembly code, step 330. The processor identification instruction identifies a course of action to take when the processor type has not yet been identified. In the illustrated embodiment, the processor identification instruction is a call to a cpu_indicator initialization function which loads the processor type information into the intel_cpu_indicator variable. Thus, once the processor type is loaded into the intel_cpu_indicator variable, the code will be able to access and identify the processor type. The cpu_indicator initialization function obtains the processor type information using the CPUID instruction, supported by many Intel processors. The CPUID instruction identifies the processor family (e.g., Pentium.RTM. processor family or Pentium.RTM. Pro processor family), as well as whether the processor is enabled with MMX.TM. technology (e.g., the Pentium.RTM. processor with MMX.TM. technology, the Pentium.RTM. II processor, or Pentium.RTM. III processor), thereby indicating whether the processor type is a Pentium.RTM. processor, Pentium.RTM. II processor, Pentium.RTM. III processor, Pentium.RTM. Pro processor, or Pentium.RTM. processor with MMX.TM. technology. Additional information may also be returned by the CPUID instruction, such as the stepping of the processor. This additional information can be used in alternate embodiments of the present invention to distinguish between different processor types. By way of example, a particular stepping of a processor may have a "bug" which is not present in subsequent steppings, and thus different code segments can be written customized to the different steppings. During initialization of the program, the intel_cpu_indicator variable is initialized to zero. The processor type is then stored in the intel_cpu_indicator variable when the cpu_indicator initialization function is called. Thus, in the illustrated embodiment the cpu_indicator initialization function need not be called more than once during program execution. FIG. 4 illustrates sample assembly code generated according to one embodiment of the present invention by a compiler from the program code 200 of FIG. 2. The assembly code provides a series of tests for processor types. The tests are performed during execution by checking a value stored at the memory location identified by intel_cpu_indicator (i.e., the intel_cpu_indicator variable). If the test succeeds, then the code jumps to the appropriate address for the beginning of the function for the identified processor type. However, if a test fails, then the code checks for another processor type. As illustrated, the code initially checks with test 402 whether the processor type is a Pentium.RTM.III processor. If the processor type is a Pentium.RTM. III processor, then the jump instruction 404 transfers program execution to the memory location indicated by _print_cpu$F, which is the memory address of the section of code for the _print_cpu function customized to the Pentium.RTM. III processor (function 205 of FIG. 2). The assembly code contains similar tests for the Pentium.RTM. II processor, Pentium.RTM. Pro processor, Pentium.RTM. processor with MMX.TM. technology, and the Pentium.RTM. processor. The final test 412 checks whether there is a non-zero value stored in the intel_cpu_indicator variable. If there is a non-zero value, then jump instruction 414 jumps program execution to a dispatch fail function located at the address intel_cpu_dispatch_fail. However, if there is not a non-zero value stored in the intel_cpu_indicator variable, then a call 416 to the cpu_indicator initialization function located at the address intel_cpu_indicator is made. Upon return from the cpu_indicator initialization function, the program execution continues in a jump to test instruction 402, thereby repeating the process. However, now that the intel_cpu_indicator variable has been initialized, one of the tests for processor type will be successful, indicating either a particular processor type or a dispatch fail. In the illustrated embodiment, the compiler orders the test instructions so that the program execution jumps to the most "advanced" function (that is, the function customized to the most advanced processor architecture) which can be executed by the processor executing the program. By way of example, if two customized functions are generated, one for a Pentium.RTM. processor and one for a Pentium.RTM. processor with MMX.TM. technology, and if the process processor executing the program is a Pentium.RTM. II processor, then the test for the Pentium.RTM. processor with MMX.TM. technology is successful, thereby causing program execution to jump to the function customized for the Pentium.RTM. processor with MMX.TM. technology. Also in the illustrated embodiment, the compiler orders the test instructions in the assembly code such that the highest performance processor is tested for first. This reduces the overhead (the additional tests) of the present invention for higher performance processors. However, alternate embodiments can use different orderings. In one such alternate embodiment, the test instructions are ordered so that the most likely processor to be executing the program is tested for first. The assembly code illustrated in FIG. 4 is a sample of assembly code which is generated according to one embodiment of the present invention. Alternate embodiments can generate different assembly code. By way of example, the ordering of the test instructions can be changed, the test values (-32, -16, -8, -12, and -2) can be changed, different types of testing or comparing instructions can be used, etc. For ease of explanation, the present invention has been described in terms of the assembly code generated by the compiler. Those skilled in the art will appreciate that this assembly code is subsequently converted to object code which is executed by the processor. FIG. 5 illustrates an example hardware system suitable for use with one embodiment of the present invention. Hardware system 500 includes processor 502 and cache memory 504 coupled to each other as shown. Additionally, hardware system 500 includes high performance input/output (I/O) bus 506 and standard I/O bus 508. Host bridge 510 couples processor 502 to high performance I/O bus 506, whereas I/O bus bridge 512 couples the two buses 506 and 508 to each other. Coupled to bus 506 are network network/communication interface 524, system memory 514, and video memory 516. In turn, display device 518 is coupled to video memory 516. Coupled to bus 508 are mass storage 520, keyboard and pointing device 522, and I/O ports 526. Collectively, these elements are intended to represent a broad category of hardware systems, including but not limited to general purpose computer systems based on the Pentium.RTM. processor, Pentium.RTM. Pro processor, Pentium.RTM. II processor, Pentium.RTM. III processor, or Pentium.RTM. processor with MMX.TM. technology, available from Intel Corporation of Santa Clara, Calif. These elements 502-524 perform their conventional functions known in the art. In particular, network/communication interface 524 is used to provide communication between system 500 and any of a wide range of conventional networks, such as an Ethernet, token ring, the Internet, etc. It is to be appreciated that the circuitry of interface 524 is dependent on the type of network the system 500 is being coupled to. Mass storage 520 is used to provide permanent storage for the data and programming instructions to implement the above described functions, whereas system memory 514 is used to provide temporary storage for the data and programming instructions when executed by processor 502. I/O ports 526 are one or more serial and/or parallel communication ports used to provide communication between additional peripheral devices which may be coupled to hardware system 500. It is to be appreciated that various components of hardware system 500 may be rearranged. For example, cache 504 may be on-chip with processor 502. Alternatively, cache 504 and processor 502 may be packed together as a "processor module", with processor 502 being referred to as the "processor core". Furthermore, certain implementations of the present invention may not require nor include all of the above components. For example, mass storage 520, keyboard and pointing device 522, and/or display device 518 and video memory 516 may not be included in system 500. Additionally, the peripheral devices shown to standard I/O bus 508 may be coupled to high performance I/O bus 506; in addition, in some implementations only a single bus may exist with the components of hardware system 500 being coupled to the single bus. Furthermore, additional components may be included in system 500, such as additional processors, storage devices, or memories. In one embodiment, the compiling and assembling of instructions according to the present invention is implemented as a series of software routines run by hardware system 500 of FIG. 5. In this embodiment, compiler 110 and assembler 120 of FIG. 1 are each implemented as a series of software routines. These software routines comprise a plurality or series of instructions to be executed by a processor in a hardware system, such as processor 502 of FIG. 5. Initially, the series of instructions are stored on a storage device, such as mass storage 520. It is to be appreciated that the series of instructions can be stored using any conventional storage medium, such as a diskette, CD-ROM, magnetic tape, DVD, laser disk, ROM, Flash memory, etc. It is also to be appreciated that the series of instructions need not be stored locally, and could be received from a remote storage device, such as a server on a network, via network/communication interface 524. The instructions are copied from the storage device, such as mass storage 520, into memory 514 and then accessed and executed by processor 502. In one implementation, these software routines are written in the C++ programming language. It is to be appreciated, however, that these routines may be implemented in any of a wide variety of programming languages. FIG. 6 is a block diagram illustrating a device on which one embodiment of the present invention can be implemented. The device 600 is meant to represent a wide variety of devices in which the present invention can be implemented, including conventional storage media (such as a floppy disk, hard disk, or a random access memory), as well as discrete hardware or firmware. The device 600 includes a compiler portion 602 and an assembler portion 604. Compiler portion 602 includes the instructions, to be executed by a processor, for carrying out the process of compiling a high-level language into assembly code, whereas assembler portion 604 includes the instructions, to be executed by a processor, for carrying out the process of converting the assembly code into object code. According to an alternate embodiment, referred to as "automatic CPU dispatch", the compiler automatically and dynamically analyzes the source code and customizes the object code for particular processor types. In this embodiment, the compiler analyzes the source code on a code segment by code segment basis to determine whether a performance advantage can be obtained over the non-customized version of the function by customizing the function to a particular processor type. If greater than a threshold performance advantage can be obtained, then the compiler compiles the source code customized for particular processor types in addition to compiling the source code for a "generic" processor. Otherwise, only a "generic", non-processor-specific compilation is performed. This alternate embodiment will now be described with reference to FIGS. 7 through 13. FIG. 7 is a flowchart illustrating the steps followed in compiling high-level language when a compiler switch for automatic CPU dispatch is turned off, according to an alternate embodiment of the invention. The automatic CPU dispatch embodiment is implemented by a compiler that analyzes source code written for any of a set of N potential CPU types and, depending upon whether a particular compiler switch is set or turned off, either looks for opportunities to optimize the compiled code to any or all of the set of N potential CPU types, or simply compiles in the normal way, generating generic compiled code that will execute on each CPU of the set of N CPU types. If the compiler switch is turned off, as shown in block 700 of FIG. 7, the compiler analyzes each source code file function-by-function (block 710), compiling a generic version of each function (block 720) with no CPU-specific optimization. When all functions in the particular source code file have been analyzed (block 730), the method returns to block 710 and analyzes another source code file, until all source code files have been analyzed (block 740), and the compiling method ends. FIG. 8 is a flowchart illustrating the steps followed in compiling high-level language when a compiler switch for automatic CPU dispatch is set, according to an alternate embodiment of the invention. If the compiler switch is set, as shown in block 800 of FIG. 8, the compiler analyzes each source code file function-by-function (block 805), and the compiler determines whether there is a performance advantage in customizing a particular source code function to a particular processor type (block 810). If so, the method generates a dispatch function (block 815) that indicates which processor type(s) will execute one or more object code optimizations of the function. For example, if the compiler determines that the function could be performed faster by optimizing object code for the Pentium.RTM. III processor and Pentium.RTM. II processor than by merely compiling generic object code, the compiler will embed a construct in the compiled code indicating which processors types to test for and which specific compiled code to call for each of those processor types. In block 820, the compiler compiles one or more CPU-specific optimized versions of the function, depending upon how many opportunities for optimization it determined in block 810. The method then proceeds to block 825. If, in block 810, the compiler found no opportunities for customization, the method proceeds directly to block 825. In block 825, the compiler compiles a generic version of the function that will execute on any processor type in the set of N processor types. In the context of the CPU's described herein, this means that the compiled function can be executed by any CPU from a Pentium.RTM. processor to a Pentium.RTM. III processor. When all functions in the particular source code file have been analyzed (block 830), the method returns to block 805 and analyzes another source code file, until all source code files have been analyzed (block 835), and the compiling method ends. FIG. 9 illustrates sample source code segments that can be compiled by an automatic CPU dispatch construct according to an alternate embodiment of the invention. The sample source code segments in FIG. 9 comprise a plurality of source code files, i.e. File_A, File_B, File_C, through File_N, identified by 900, 930, 940, and 950 respectively. Each of files 900, 930, 940, and 950 can comprise one or more functions. For example, File_A (900) can comprise Function_A.sub.-- 1 (910), Function_FOO (915), and Function_A_M (920). FIG. 10 illustrates sample assembly code for CPU-dispatch testing that is generated using automatic CPU dispatch according to an alternate embodiment of the invention. As in FIG. 4, the assembly code provides a series of tests for processor types. The tests are performed during execution by checking a value stored at the memory location identified by intel_cpu_indicator (i.e., the intel_cpu_indicator variable). If the test succeeds, then the code jumps to the appropriate address for the beginning of the function for the identified processor type. However, if a test fails, then the code checks for another processor type. The operation of the sample assembly code shown in FIG. 10 will be explained below with reference to FIGS. 11-13, each of which will first be briefly described FIG. 11 illustrates sample assembly code (1105, 1110) optimized for a high performance CPU that is generated using automatic CPU dispatch according to an alternate embodiment of the invention. FIG. 12 illustrates sample assembly code (1205, 1210) optimized for a medium performance CPU that is generated using automatic CPU dispatch according to an alternate embodiment of the invention. FIG. 13 illustrates sample assembly code (1305, 1310) with no CPU-specific optimizations that is generated using automatic CPU dispatch according to an alternate embodiment of the invention. With reference once again to FIG. 10, the code initially checks with test 1000 to see whether the processor type is a Pentium.RTM. III processor. If the processor type is a Pentium.RTM. III processor, then the jump instruction 1005 transfers program execution to the memory location indicated by Function_FOO_$F (1100), which is the memory address of the section of assembly code for the Function_FOO function customized to the Pentium.RTM. III processor (function 915 of FIG. 9). The assembly code for Function_FOO_$F comprises code which has been specifically optimized for, and requires execution on, the Pentium.RTM. III processor and indicated generally for illustration purposes by 1105 and 1110. This assembly code can also be executed on future, higher performance processors, provided that they are backward-compatible with the Pentium.RTM. III processor, i.e. they can execute any code that the Pentium.RTM. III processor can execute. If the processor type is not a Pentium.RTM. III processor, the code next checks with test 1010 to see whether the processor type is a Pentium.RTM. II processor. If the processor type is a Pentium.RTM. II processor, then the jump instruction 1015 transfers program execution to the memory location indicated by Function_Foo_$E (1200), which is the memory address of the section of assembly code for the Function_FOO function customized to the Pentium.RTM. II processor (function 915 of FIG. 9). The assembly code for Function_FOO_$E comprises code which has been specifically optimized for, and requires execution on, the Pentium.RTM. II processor and indicated generally for illustration purposes by 1205 and 1210. This optimized code can also be executed by CPU types, including future CPU types, which are more advanced than the Pentium.RTM. II processor, such as the Pentium.RTM. III processor, provided that they are backward-compatible with the Pentium.RTM. II processor. The final test 1020 checks whether the processor type has already been determined. If so, then jump instruction 1025 jumps program execution to the memory location indicated by Function_FOO_$B (1300), which is the memory address of the section of assembly code for the non-customized or generic version of Function_FOO, indicated generally for illustration purposes by 1305 and 1310. This generic code can also be executed by all CPU types, including future CPU types, provided that they are backward-compatible. If the processor type is not yet set in the intel_cpu_indicator variable, then a call 1030 to the intel_cpu_indicator initialization function located at the address intel_cpu_indicator_init is made. Upon return from the intel cpu_indicator initialization function, the program execution continues in a jump to test instruction 1000, thereby repeating the process. However, now that the intel_cpu_indicator variable has been initialized, one of the tests for processor type will be successful, and the appropriate version of the object code will be executed, depending upon the processor type. As mentioned earlier, the compiler orders the test instructions so that the program execution jumps to the most "advanced" function (that is, the function customized to the most advanced processor architecture) which can be executed by the processor executing the program. Also in the illustrated embodiment, the compiler orders the test instructions in the assembly code such that the highest performance processor is tested for first. This reduces the overhead (the additional tests) of the present invention for higher performance processors. However, alternate embodiments can use different orderings. In one such alternate embodiment, the test instructions are ordered so that the most likely processor to be executing the program is tested for first. The present invention can be implemented by a computer-readable medium containing instructions for instructing a processor. The instructions can include analyzing a source code segment, and determining whether generating a customized version of object code for the source code segment to execute on one of several types of processors would provide a performance advantage over generating a non-customized version of object code. If so, the customized version of object code is generated; otherwise, the non-customized version of object code is generated. The computer-readable medium further includes computer instructions that generate a control section that causes one of the versions of object code to be called during execution in accordance with an executing processor's type. The computer-readable medium can also include instructions that determine whether generating two or more customized versions of object code to execute on two or more types of processors would provide performance advantages over a non-customized version of object code. If so, the two or more customized versions of object code are generated; otherwise, the non-customized version of object code is generated. A control section is generated that causes a first customized version of object code to be called during execution if the executing processor is a first type, and that causes a second customized version of object code to be called during execution if the executing processor is a second type. The control section causes a non-customized version of object code to be called during execution if the executing processor is neither the first or second type. If the first customized version of object code is more advanced than the second customized version of object code, the control section causes the first customized version to be executed if the control section examines the processor type variable and it corresponds to a processor type that can execute either the first or second customized versions of object code. It should be noted that, although specific syntax for the present invention is discussed above, alternate embodiments can use variations on this syntax. According to one such alternate embodiment, the empty_function_definition of the cpu_dispatch construct is not empty, rather, it contains the code the user wishes for the compiler to make processor-specific. The compiler generates a different piece of object code for each of the different processors, based on the code of the cpu_dispatch construct. Each of these different pieces of code is optimized by the compiler for the particular processor types (e.g., by setting of specific compiler switches). Various examples of processor types are given in the discussions above. Although different Intel-architecture processors are discussed, the present invention may also be used to customize code different manufacturers or different processor types of another manufacturer. Additionally, the present invention is discussed above with reference to the C or C++ programming language. In alternate embodiments, the processor-specific and dispatch constructs are provided in other programming languages, such as PASCAL, Fortran, Java, etc. Furthermore, other modifications can be made by compiler 110 to further enhance the processor-specific customization of the present invention. In an alternate embodiment, one such customization is the setting and clearing of particular processor optimization switches. In this embodiment, when compiling the cpu_dispatch and cpu_specific constructs, additional switches or compiler options are set by the compiler which correspond to the processor type of the function being compiled (as identified by the cpu_specific construct). These additional switches and/or compiler options cause the compiler to further customize the source code generated for the particular processor type. In addition, the invention can be implemented by any suitable processor or other type of computational circuit, such as but not limited to a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLW) microprocessor, a graphics processor, a digital signal processor, an application-specific integrated circuit (ASIC), or any other type of processor or processing circuit, or combination thereof. Thus, the present invention supports multiple processor-specific code segments in a single executable. In one embodiment, the present invention allows a programmer to write multiple different code segments, each customized to a particular type of processor, yet each advantageously having the same identifier. During program execution, the proper customized code segment is advantageously selected based on the type of processor that is executing the program. Additionally, in another embodiment, the present invention allows a programmer to write a single code segment and advantageously have that single code segment analyzed and customized to different object code versions, executable by different processor types, automatically by the compiler. Again, during program execution, the proper customized code segment is advantageously selected based on the type of processor that is executing the program. When a new processor type is released that has new and/or different instructions, source code programs do not have to be rewritten. Instead, a simple re-compilation is all that is necessary, assuming that a new compiler supports the desired instructions. One significant advantage of the present invention is that it enables independent software vendors (ISVs) to take advantage of different high performance instructions available on different types of processors while simultaneously allowing them to generate applications that can be executed on several types of processors. ISVs are more likely to take advantage of new instructions, because their application code is readily portable. Thus, a method and apparatus for supporting and/or generating multiple processor-specific code segments in a single executable have been described. Whereas many alterations and modifications of the present invention will be comprehended by a person skilled in the art after having read the foregoing description, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. References to details of particular embodiments are not intended to limit the scope of the claims.
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