Debug interface including data steering between a processor, an input/output port, and a trace logic6142683Abstract A system for debugging a processor includes a data steering circuit for steering commands and data from a debug port and a parallel input/output port. The data steering circuit also directs commands and data to from the debug port and the parallel input/output port to the same set of debug registers. The data steering circuit also selectively directs trace information indicative of execution of instructions in the processor to either a trace buffer or directly out to a port, such as the debug port or the parallel input/output port. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
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select.sub.-- IR = (tap.sub.-- state = SEL.sub.-- IR.sub.-- SCAN).vertline
.tap.sub.-- state = CAPTURE.sub.-- IR.vertline.tap.sub.-- state =
SHIFT.sub.-- IR.vertline.tap.sub.-- state = EXIT1.sub.-- IR.vertline.tap.s
ub.-- state = PAUSE.sub.-- IR.vertline.tap.sub.-- state =
EXIT2.sub.-- IR.vertline.tap.sub.-- state = UPDATE.sub.-- IR).
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The transmit data output (TDO) signal is determined, as follows: TDO=!(select.sub.-- IR & JTAG.sub.-- debug.sub.-- inst & debug.sub.-- shfout). where debug.sub.-- shfout is bit 0 shifted output of the 38-bit serial port register 1604. Commands and data are loaded into and read from the 38-bit serial-port register/shifter using the capture.sub.-- DR--Update.sub.-- DR sequence in the JTAG TAP controller state machine. JTAG.sub.-- debug.sub.-- inst Register is enabled after DEBUG inst is written into the JTAG.sub.-- TAP.sub.-- IR Register. A signal definition includes two sections, a standard section and a bond-out section. Standard signals are shown in TABLE I and are available for usage on all embedded processor device 102 integrated circuits. Bond-out signals are shown in TABLE II and are available only on specially-packaged parts, typically for usage by in-circuit emulation (CE) vendors. A TBUS[18:0] is shared between the parallel port 214 and the trace pad interface 220. The remaining bond-out signals are dedicated to either the parallel port or the trace pad interface 220.
TABLE I
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Sync
Name I/O Res
Clock
Description
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TCK Input
PU
Clock for TAP controller and debug serial/parallel
interface
TDI Input PU TCK Input test data and instructions
TD0 Output
TCK Output data
TMS Input PU TCK Test functions and sequence of test
changes
TRST Input PU Async Test reset
BRTC Input PD Async Request entry to debug mode/On-Off
switch for instruction
trace capture. Function selected by BRKMODE bit in
DCSR (optional)
CMDACK Output
TCK Acknowledge command (optional)
STOPTX Output
Async Asserted high on entry to DEBUG mode. Set high
in
NORMAL mode when data is to be transmitted to the
host
during OS/Application communication.
TRIG/TRACE Output
Async Trigger event to logic analyzer
(optional)/TRACE-ON/OFF
ON/OFF STATUS when bit 14 in the ITCR register is
set.
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Referring to FIG. 4, a state diagram illustrates a high-level flowchart of the host/serial port interface of the JTAG TAP controller 204 when using standard JTAG communication. The host system 111 writes a DEBUG instruction to the Instruction Register in the JTAG TAP controller 204 in operation 402. After the DEBUG instruction has been written the 38-bit serial port register is connected between TDI and TDO pins. Now the host begins to shift a 38-bit serial value into the 38-bit serial port register using the capture DR--Update DR sequence in the JTAG TAP controller state machine with the Command Pending Flag (P) asserted and data (if applicable, otherwise zero) in the data field in operation 404. Upon completing the command, which typically involves transferring a value between the data field of the 38-bit serial register and a predetermined processor register or memory/IO location in the processor core 104, the debug-port state machine clears the Pending flag (P=0) and asserts the Finished flag (F=1), simultaneously storing a value in the data field, if applicable. The entire 38-bit register is scanned out to monitor the Finished (F) and Pending (P) flags. If the Pending flag P is reset to zero and the Finished flag F is set to one, the previous command is finished. The status of the flags is captured during the Capture-DR TAP controller state shown in FIG. 3. A slave copy of the flag status is saved internal to the JTAG TAP controller 204 and checked in operation 406 to determine in logic state 408 whether the next instruction is to be loaded in the Update-DR TAP controller state. If the Finished flag (F) is set, a new 38-bit command is scanned in operation 406, otherwise the previous data scan is repeated in operation 410. A slave copy is maintained due to the possibility of the status changing between the Capture-DR and Update-DR TAP controller states. The processor saves the slave copy to determine the status the user will detect at the time the status capture is performed to prevent the loading of the next instruction if the user sees that the previous instruction has not finished. Referring again to FIG. 2, the processor interface state machine 202 performs asynchronous control operations for adding the signals CMDACK, BRTC, STOP/TX, and TRIG/TRACE-ON/OFF to the standard JTAG interface. The CMDACK, BRTC, STOP/TX, and TRIG/TRACE-ON/OFF signals are enabled when the DEBUG instruction is written to the JTAG instruction register in the JTAG TAP controller 204, but forced to a logic zero when disabled. The BRTC signal pin is supplied with an internal pull-down resistor (not shown). Referring to FIG. 5, a flow diagram illustrates state operation of the enhanced JTAG interface. The host system 111 writes a DEBUG instruction to the JTAG TAP controller 204 in operation 502 then optionally monitors the output signal CMDACK to determine command completion status in a logic operation 504. The CMDACK signal is asserted high simultaneous with assertion of the Finished flag (F) and remains high until the next command is shifted. When using the CMDACK pin, the Finished flag (F) status is captured without shifting out the serial port register in the serial debug port shifter block 227 since the CMDACK pin transitions high on the next rising edge of TCK after the real-time status of the Finished flag (F) changes from 0 to 1. The CMDACK signal is not delayed from the state saved during the previous Capture-DR state entry of the TAP controller state machine. Accordingly, in the enhanced JTAG mode a new shift sequence is not started in operation 506 until the CMDACK pin is asserted high. The CMDACK pin asserts high when the serial port is ready to receive instructions after the DEBUG instruction is loaded into the JTAG instruction register. The CMDACK signal is synchronous with the TCK signal. TCK is generally not be clocked at all times, but is clocked continuously when waiting for a CMDACK response. The BRTC input signal functions either as a break request signal or a trace capture enable signal depending on the BRKMODE bit in the DCSR The BRTC signal, when set to function as a break request signal, is pulsed to cause the target system 101 to enter debug mode. If the BRTC signal is set to function as a trace capture enable signal, asserting the signal high activates the trace capture. Deasserting the BRTC signal deactivates the trace capture. The BRTC signal takes effect on the next instruction boundary after detection and is internally synchronized with the internal processor clock. The BRTC signal can be asserted at any time. The TRIG/TRACE-ON/OFF output signal is optionally enabled to pulse whenever an internal breakpoint in the processor core 104 is asserted and if the corresponding enable bit is set in the ITCR register. The TRIG signal event is typically used to trigger an external capturing device such as a logic analyzer. When the processor core 104 generates a breakpoint, the TRIG output signal event is pulsed for two CPUCLK periods. When bit-14 in the ITCR register is set the TRIG/TRACE-ON/OFF pin is used to indicate the internal status of TRACE-ON/OFF. The STOPTX output signal is asserted high when the target system 101 enters debug mode and is ready for register interrogation and modification, or memory or I/O reads and writes through the serial/parallel command interface. In a normal (nondebug) mode, the STOPTX signal is asserted high when the target system 101 is ready to transmit data during Operating System (OS) or Application communication. The STOPTX signal reflects the state of bit 7 or bit 11 in the debug control/status register (DCSR). The STOPTX signal is synchronous with JTAG TCK clock. When external instruction tracing through the bond-out DEBUG trace port is enabled, assertion of STOPTX is delayed until all data in the instruction trace buffer 200 is transferred out. Referring again to FIG. 2, the parallel port 214 is a high-performance interface that is typically available in the bond-out version of the target system 101. The parallel port 214 supplies a 16 -bit data path is intended to perform fast downloads and uploads between the host system 111 and the target system memory. The parallel port 214 is optionally used for all debug communication with the target system 101 whenever the processor core 104 is stopped. The serial port interface, either standard or enhanced, is used for debug access to the target system 101 when the processor core 104 is executing instructions or when the processor core 104 is stopped. The parallel port 214 includes a 16-bit wide bi-directional data bus PDATA[15:0], a 3-bit address bus PADR[2:0], a read/write strobe PRW, and a request-grant pair PBREQ-PBGNT. The interface uses TCK (see Table 1) for synchronization of all transactions. TCK is continually clocked while the parallel debug interface is enabled. The parallel port 214 is enabled by setting DCSR:3 to logic 1 via the serial port of the JTAG TAP controller 204. The serial port interface is not disabled when the parallel port is enabled and has mandatory usage for access while the processor core 104 is executing instructions. Any transaction started on the parallel port 214 completes on the parallel parallel port 214. Similarly, any transaction begun on the serial port of the JTAG TAP controller 204 also completes on the serial port. All input signals to the parallel port 214 are sampled on the rising edge of TCK. All output signals are changed on the falling edge of TCK. Referring to FIG. 6, a timing diagram illustrates three complete bus cycles of signal behavior for acquisition and release of a parallel debug bus PDATA[15:0] and PADR[2:0]. Because pins are shared between the parallel port 214 and the DEBUG trace port 220, parallel port transmission commands are initiated only while the processor core 104 is stopped and the DEBUG trace port 220 is disconnected from the shared bus. A request-grant handshake pair of signals PB REQ/PB GNT are supplied to expedite turnaround of the shared bus signals between the DEBUG trace port 220 and the parallel port 214. When the host system 111 interface to the parallel port 214 determines that PBREQ is asserted high, the host system 111 is to begin driving the parallel port 214 signals and assert PBGNT. When PBREQ is deasserted, the host system 111 interface to the parallel port 214 responds by tri-stating host system 111 interface signals and deasserting PBGNT to indicate that the host system 111 interface is isolated from the bus. To prevent bus contention, devices driving the parallel port 214 are tri-stated whenever PBGNT is deasserted. The PBREQ signal is asserted immediately after the debug mode entry when the parallel port is enabled and is deasserted after exiting the debug mode. When PBREQ is deasserted the CMDACK is not yet asserted until the PBGNT is deasserted. The parallel port 214 host interface responds to the PBREQ deassertion by tri-stating the parallel port 214 drivers and deasserting the PBGNT signal. The parallel port 214 controller then activates the DEBUG trace port pin drivers in the debug trace port 220, asserts the CMDACK signal and returns control of the debug trace port 220 interface to the trace control circuit 218. In FIG. 6, the abbreviations are as follows: WDATA=Write Data; READ=Read Data; WCMD=Write Command; RCMD=Read Command; and Trace=Instruction Trace Record. Host.sub.-- lat.sub.-- data is an illustrative signal showing when the host system latches read data. Tar.sub.-- lat.sub.-- data is an illustrative signal showing when the parallel port controller latches host data/commands and processor data. PDATA, PADR, PRW and PBGNT must meet set up/hold times from the rising edge of TCK. Host.sub.-- sample.sub.-- CMDACK is an illustrative signal showing when the host system samples CMDACK. Cycle.sub.-- type is an illustrative signal showing the types of parallel bus cycles occurring in the diagram. PRW and PADR[1:0] must be driven stable on any rising TCK edge on which PBGNT is asserted. If PBGNT is asserted and PRW is low, PDATA[15:0] must also be driven stable on all rising edges of TCK. For the Register Read command the register address is supplied in the debug.sub.-- data register. The command should be preceded by the register address. These cycles are not shown in the timing diagram. These cycles are similar to the WDATA cycles shown for low 16-bits and high 16-bits for the WCMD. For memory Read operation the command is preceded by only low 16-bit WDATA cycles. Referring to FIG. 7, a flow chart depicts a parallel debug port interface protocol followed by the host system 111 during communications via the parallel port 214. Address pins PADR[2:0] select the field of the 38-bit internal debug register that is mapped to the 16-bit data bus PDATA[15:0]. The field is selected from among a null selection, the right 16 bits of debug data, the left 16 bits of debug data, and a four-bit command register (PDATA[3:0]). The internal pending flag (P) is automatically set when performing a write operation to the 4-bit command register, and is cleared when the Finished flag (F) is asserted. The host system 111 typically monitors the CMDACK pin to determine when the Finished flag (F) is asserted. On read cycles, PADR is set to 000 for one clock cycle before and after reading data to allow for bus turn-around. The soft-address register should be loaded with values using load soft address register command to point to the various internal registers in the DEBUG Registers 210. The 38-bit serial register is accessible only via the serial/parallel debug interface. Some of the commands use bits from the debug data field as a sub-field to extend the number of available commands. Table 3 is a map of available functions.
TABLE 3
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Serial/Parallel Debug Register Command Code Map
Command
Code Definition
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0000 Null (Not recognized by hardware, Finished flag not set)
0001 Load Soft Address register
0010 General register read
0011 General register write
0100 Serial/parallel Debug register read
0101 Serial/parallel Debug register write
0111 reserved
0111 Miscellaneous Serial/parallel Debug functions per debug.sub.--
data[3:0]
0 Exit via RESET (hard reset)
1 Exit via SRESET (soft reset)
2 Instructions step (may destroy soft address). Bit 7 of the Debug
Control/Status register
or the external STOPTX pin is monitored to determine when the
instruction step is
completed. Unlike TF bit, the command steps into interrupts.
3 Peripheral reset (CPU not reset)
4 Read trace buffer at displacement given in soft address
5 Exit to instruction at EIP
* Null
1000 8-bit memory write to [soft address]
1001 16-bit memory write to [soft address]
1010 32-bit memory write to [soft address]
1011 8-bit output to [soft address] (I/O cycle)
1100 16-bit output to [soft address] (I/O cycle)
1101 32-bit output to [soft address] (I/O cycle)
1110 Input or read per debug.sub.-- data[3:0]
0 8-bit read from [soft.sub.-- address]
1 16-bit read from [soft.sub.-- address]
2 32-bit read from [soft.sub.-- address]
3 8-bit input from [soft.sub.-- address] (I/O cycle)
4 16-bit input from [soft.sub.-- address] (I/O cycle)
5 32-bit input from [soft.sub.-- address] (I/O cycle)
* Null
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The Load Soft Address register command places a new 32-bit value for the soft address pointer in the debug data[31:0] field in combination with the command code and the pending bit (P). Debug logic transfers the data to the Soft Address register and asserts the Finished flag (F) and the CMDACK signal. The Memory or I/O read or write command is issued following a command that sets an address and port designation in the Soft Address register. For a read command, data is transferred directly to the debug data register when the Finished flag (F) and CMDACK pin is set. For a write command, data is supplied in the debug data register in combination with the command in the Debug Command register. The address is postincremented by the appropriate size for any read/write transfer to allow block transfers without continually setting up the Soft Address. On memory accesses of a microcontroller with multiple physical memory spaces, the appropriate chipset mapping registers are set prior to issue of the access command. Memory accesses occur as data accesses. A memory access is directed either to normal memory space or SMM space based on the setting of the SMMSP bit in the DCSR register. Issue of a General or Serial/parallel Debug Register Read command includes designation of a register address in the debug data register in combination with identification of the command in the Debug Command register. The address is transferred to the Soft Address register as a side effect to simplify read/modify/write setting of individual bits, and the register contents are transferred directly to the debug data register when the Finished flag/CMDACK pin is set. For a General or Serial/parallel Debug Register Write command, the Soft Address is used to hold the register address. The soft address is set up with a previous Read Register or Load Soft Address command. The data to be written is supplied in the debug data register in combination with the command in the Command register. The Read Trace Record command implements read access to the 256-record internal trace buffer 200 when the internal instruction trace configuration is selected. The read trace record command is not applicable to an external trace configuration since all trace record data is output to the bond-out DEBUG trace port upon generation. The read trace record command is invoked by setting bit 0 of the Instruction Trace Configuration Register (ITCR) to logic 1 to enable the instruction trace buffer 200, then the internal trace configuration is selected by setting bit 3 of the ITCR register to 0. The Read Trace Record command reads the 21-bit trace record at the displacement given in the soft address register, places the record in bits 20:0 of the debug data register and asserts the finished flag and CMDACK pin. The soft address register is post-incremented so that a subsequent read retrieves the next location in the buffer in reverse order of history. A read operation from displacement 0 retrieves the most recent trace record. A read operation from displacement 255 retrieves the oldest trace record in the buffer. When the instruction trace buffer 200 is read, the valid bit on each record is to be checked. If the valid bit of a record is zero, an event that occurs only when one or more of the 256 locations of the buffer is not loaded with trace record data since last initialized, the record should be discarded. The trace buffer 200 wraps around and continually overwrites the oldest data when full. Once the buffer has wrapped around, all valid bits are set, and are cleared only when the TINIT bit (bit 2) in the Instruction Trace Configuration Register is set. The Peripheral reset command sends a reset signal to all system logic except the processor core 104 to be pulsed active and released. The peripheral reset command allows peripheral logic to be reinitialized without resetting the processor core 104. A command to enter or exit Debug mode enables and disables debug functionality. Debug functions are enabled by writing the DEBUG instruction to the JTAG TAP controller. When a DEBUG instruction is received, the debug serial port register is enabled to receive commands. While the processor is executing instructions only the Debug Control/Status register, Instruction trace configuration register, SOFT.sub.-- ADDR register, RX.sub.-- DATA, and TX.sub.-- DATA registers are accessed through the serial interface. All serial debug registers become accessible when the processor has stopped. The processor may be stopped (forced into debug mode) by one of the following methods: Setting bit 1 of the Debug Control/Status register (DCSR) Pulsing the BRTC pin (low-to-high transition) Via legacy processor core 104 debug registers DRO-DR3 after setting bit 4 of the Debug Control/Status register (DCSR). Single stepping with the TF bit set causes entry to debug mode when DCSR bit 4 is set. Moving to and from debug registers with the bit 12 of DR7 set causes entry to debug mode when DCSR bit 4 is set. Executing a EDEBUG instruction. Inserting a EDEBUG instruction into the code stream enters debug mode at a specific, arbitrary point in source code. The processor core 104 is set in debug mode (DEBUG instruction is automatically written to the TAP controller). The EDEBUG instruction causes an invalid opcode execution if bit 12 of DR7 is not set. The external pin STOPTX or bit 7 of the Debug Control/Status register (DSCR) is optionally monitored to determine when the processor enters debug mode. The flushing of cache on entry to debug mode is controlled by the DISFLUSH bit of DCSR. If the bit is reset the cache is flushed (using the SLE486 FLUSH pin) upon entry to debug mode. If the bit is set the cache is not flushed on entry to debug mode. On receipt of the STOPTX signal, either by sampling debug of the STOPTX pin or by polling DCSR bit 7, the host system 111 starts writing commands. Debug mode is exited through command 0111. The exit options include: Exit and begin execution at current value of EIP. In one example, the processor jumps to a section of patch code. A breakpoint is set at the end of the patch code to enable reentry to debug mode. In another example, the processor state is restored to the original debug entry state, using the general register write commands, before exiting. Exit and perform a single instruction step. The processor executes a single instruction, takes a trap, and reenters debug mode. Exit via a hard reset. A hard CPU reset is asserted immediately. Exit via a soft reset. The X86 Enhanced Software debug mode supplies a trace and breakpoint interrupt debug functionality on the processor core 104 without inclusion of external debug hardware. The mode is enabled by setting DR7 bit 12. The serial interface does not need to be enabled. When the X86 Enhanced Software debug mode is enabled, access and control of the instruction trace buffer 200 and the ITCR (Instruction Trace Control Register) are supplied through a set of reserved instructions. The instructions cause an illegal opcode exception if executed when DR7 bit 12 is not set. Debug control and status is configured by setting the Debug Control/Status Register (DCSR) through the Serial/Parallel debug interface, using the serial/parallel debug registers read/write command, address 00. DCSR control and status bits are described, as follows: Bit 0 (FRESET) is a reset bit allowing the host system 111 to completely reset all devices on the target system 101 other than the Serial/Parallel controller. FRESET is useful in the event of a total target system crash. Bit 1 (FBRK) is a register version of the BRTC pin. The host system 111 writes a 1 followed by a 0 to FBRK to force a break into debug mode at the next instruction boundary following synchronization of the received command with the internal processor clock. Bit 2 (DSPC) is a processor clock disable bit for disabling the stopping of internal processor clocks that normally occurs when entering Halt and Stop Grant states. DSPC allows the processor to continue to respond to break requests while halted or in the Stop Grant state. Bit 3 (PARENB) is a parallel port enable bit that enables the auxiliary parallel data port. PARENB is not set on non bond-out versions of the target system 101. Bit 4 (DBTEN) is a debug trap enable bit that causes entry into a hardware debug mode for all debug traps/faults of the processor core 104 that otherwise cause a software INT 1. The trace mode on/off toggling control in the ITCR has priority over DBTEN in that breakpoints mapped for trace mode on/off toggling are not affected by setting of DBTEN. Bit 5 (BRKMODE) is a bit for controlling entry into debug mode. BRKMODE allows a developer to change the functionality of the BRTC pin to become an external control for enabling and disabling the trace capture operation. When the JTAG TAP controller 204 Instruction Register is programmed with a DEBUG instruction, the BRTC pin causes the processor core 104 to stop executing an instruction sequence and enter debug mode. Setting of the BRKMODE pin causes the BRTC pin to control activation of the trace capture operation. The trace capture status is designated by the TRON bit of the ITCR. Bit 6 (FRCRDY) is a bit that controls forcing the RDY signal to the processor that is active to enable the processor to move on to the next bus cycle in cases where a bus operation to an undefined memory or I/O space has occurred in the absence of a subtractive decode agent. Use of FRCRDY is to be coordinated with chipset logic. Bit 7 (STOP) is a stop bit that supports a software technique for checking the state of the STOPTX pin. When STOP reads back high, the processor is in debug mode and all debug commands are enabled. Bit 8 (SMMSP) is an SMM control bit that allows memory accesses initiated through the debug port 100 to take place in the SMM space. When SMMSP is reset, memory accesses initiated through the debug port 100 apply to the normal memory address space. Setting Of SMMSP causes memory accesses initiated through the debug port 100 to apply to the SMM address space. Bit 9 (DISFLUSH) is a control bit for controlling flushing of a cache on entry to debug mode. With DISFLUSH reset the cache is flushed on entry to debug mode. Setting DISFLUSH prevents the cache from flushing on entry to debug mode. Bit 10 (RX) is a data received bit that indicates whether data has been received from the host system 111 so that the processor core 104 can read the data from the RX.sub.-- DATA register. Bit 11 (TX) is a data transmit bit that indicates the processor core 104 is ready to transmit data so that the host system 111 can read the data from the TX.sub.-- DATA register. Communication between an operating system (OS) and Applications via the JTAG Debug port 100 is initiated by the host system 111 writing the DEBUG instruction to the JTAG instruction register in the JTAG TAP controller 204. Writing of the DEBUG instruction causes the Serial Debug Shifter 212 to connect to the JTAG TDI-TD0 serial interface of the JTAG TAP controller 204. The serial debug port 100, includes two debug registers for transmitting (TX.sub.-- DATA register) and receiving (RX.sub.-- DATA register) data. TX.sub.-- DATA and RX.sub.-- DATA are accessed using the soft address and serial/parallel debug register commands. The processor core 104 initiates a data transmission by first testing the read-only TX bit in the ITCR register. If the TX bit is set to 0 then the processor core 104 executes an X86 instruction to transfer the data to the TX.sub.-- DATA register. The serial port 100 sets the TX bit in the DCSR and ITCR registers indicating to the host system 111 data is ready for transmission. The serial port 100 also sets the STOPTX pin to high. After the host system 111 completes reading the transmit data from the TX.sub.-- DATA register, the TX bit is set to 0. A TXINTEN bit in the ITCR register, when set, generates a signal to interrupt the processor core 104. The interrupt is generated only when TX bit in the ITCR register makes a transition to 0. The communication is accomplished by the host system 111 writing the DEBUG instruction to the JTAG instruction register in the JTAG TAP controller 204, causing the Serial Debug Shifter 212 to connect to the JTAG TDI-TDO serial interface. Two of the debug registers 210 are available in the serial debug port 100 for the processor core 104 to transmit (TX.sub.-- DATA register) data and receive (RX.sub.-- DATA register) data from the host system 111. The receive and transmit data registers are accessed using the soft address and serial/parallel debug register commands. When the processor core 104 attempts to transmit the data, the processor core 104 first tests the TX bit in the ITCR register. If the TX bit is set to 0, the processor core 104 executes an X86 instruction to transfer the data to the TX.sub.-- DATA register. The serial port 100 sets the TX bit in the DCSR and ITCR registers indicating to the host system 111 a readiness to transmit data, and asserts the STOPTX pin active high. After the host system 111 completes reading the transmit data from the TX.sub.-- DATA register the TX bit is set to 0. A TXINTEN bit in the ITCR register, when set, generates a signal to interrupt the processor core 104. An output pin RXTX.sub.-- INTR is used to assert the interrupt. The interrupt is generated only when TX bit in ITCR makes a transition to 0. The TXINTRSTATUS bit in the ITCR register is set to 1. The interrupt output pin RXTX.sub.-- INTR is active high and remains active until the processor core 104 services the interrupt by reading the ITCR register. The processor core 104 detects that the TXINTRSTATUS bit set to 1 in the ITCR register and services the TX interrupt. At the end of the TX interrupt service the processor core 104 sets the TXINTRSTATUS bit to 0, acknowledging completion of service of the TX interrupt. When the processor core 104 writes a 0 to the TXINTRSTATUS bit, logic of the serial port 100 updates the bit in the ITCR only if the processor core 104 has previously read a 1 value at the beginning of the service routine. The interrupt pin RXTX.sub.-- INTR is deasserted after the processor core 104 sets the TXINTRSTATUS bit set to 0 in the ITCR register. When the TXINTEN bit is not set, the processor core 104 polls the ITCR register and monitors the TX bit to further transmit the data. When the host system 111 attempts to send data, the host system 111 first tests the RX bit in the DCSR register. If RX bit is set to 0, then the host system 111 writes the data to the receive data (RX.sub.-- DATA) register and the serial port 100 sets the RX bit to 1 in the DCSR and ITCR registers. A RXINTEN bit in the ITCR register, when set, generates a signal to interrupt the processor core 104. An output pin RXTX.sub.-- INTM is used to assert the interrupt. The interrupt is only generated when RX bit in the DCSR makes a transition to 1. The RXINTRSTATUS bit in the ITCR register is set to 1. The interrupt output pin RXTX.sub.-- INTR is active high and remains active until the processor core 104 services the interrupt by reading the ITCR register. The processor core 104 detects that the RXINTRSTATUS bit set to 1 in the ITCR register and services the RX interrupt. At the end of the RX interrupt service, the processor core 104 sets the RXINTRSTATUS bit to 0, acknowledging completion of service for the RX interrupt. When the processor core 104 writes a 0 to the RXINTRSTATUS bit, logic in the serial port 100 updates the bit in the ITCR only if the processor core 104 has previously read a 1 at the beginning of the service routine. The interrupt pin RXTX.sub.-- INTR is deasserted only after the processor core 104 sets the RXINTRSTATUS bit set to 0 in the ITCR register. When RXINTEN bit is not set, the processor core 104 polls the ITCR register, monitors the RX bit, and if the RX bit is set to 1 the processor core 104 executes an X86 instruction to read the data from the receive data (RX.sub.-- DATA) register. After the data is read by the processor core 104 from the RX.sub.-- DATA register, the RX bit is set to 0 by the serial port 100. The host system 111 continuously reads the DCSR register and monitors the RX bit to further send the data. Both the RX and TX bits can be set concurrently. If so, the RXTX.sub.-- INTR interrupt output is asserted. The host system 111 might complete reading the TX.sub.-- DATA register when the processor core 104 is servicing the RX interrupt. For interrupt controllers that are edge sensitive, a problem occurs because the RXTX.sub.-- INTR output signal is not asserted for the pending TX interrupt after the RX interrupt is serviced. To overcome the problem, a FRCDISINTR bit is defined in the ITCR register. If the interrupt controller logic is level sensitive, the FRCDISINTR bit need not be used. The FRCDISINTR bit is utilized because of the sharing of the RX and TX interrupts on one output RXTX.sub.-- INTR pin. When the processor core 104 begins servicing of the interrupt because of the RXTX.sub.-- INTR pin going active, the processor core 104 sets FRCDISINTR bit to 1 at the beginning of the service routine. At the end of the service routine, the processor core 104 sets the FRCDISINTR bit to 0. If an interrupt is pending during the service routine, the interrupt is disabled and then immediately activated when the FRCDISINTR bit is set 0, in turn causing the RXTX.sub.-- INTR output signal to go active. The processor core 104 then services the pending interrupt. The RXTX.sub.-- INTR output signal is asynchronous and remains active until the processor core 104 services the interrupt and sets the TXINTRSTATUS or RXINTRSTATUS bit to 0. The RX and TX bits in the DCSR and ITCR are read-only bits. The serial port 100 sets and resets the bits. The STATUS, TXP=RSTATUS, and FRCDISINTR bits in the ITCR are read-only bits for the host system 111. The processor core 104 and serial port 100 write the RXINTRSTATUS, TXINTRSTATUS, and FRCDISINTR bits. SERIAL/PARALLEL DEBUG REGISTER DESCRIPTIONS The Instruction Trace Configuration Register (ITCR) The ITCR register controls enabling/disabling and configuration of Instruction Trace debug functions. The ITCR register is accessed through the serial/parallel debug register write/read commands, at location 01, or via the reserved instruction MOV ITCR.
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Initial
BIT
Symbol
State
Description
Function
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31 RXINTR
0 RX Interrupt status
RX Interrupt status when RX interrupt is enabled.
STATUS when RX interrupt is
1 = RX Interrupt is active when RXINTEN is set to
1.
enabled. 0 = RX Interrupt is inactive when RXINTEN set to
1.
30 TXINTR
0 TX Interrupt Status
TX Interrupt status when TX interrupt is enabled.
STATUS when TX Interrupt is
1 = TX Interrupt is active when TXINTEN is set to
1.
enabled. 0 = TX Interrupt is inactive when TXINTEN set to
1.
29 RXINTEN
0 Enable Interrupt when
Enables Interrupt when RX bit is set.
RX bit is set
1 = Enable Interrupt when RX bit is set to 1.
0 = Disable Interrupt when RX bit is set to 1.
28 TXINTEN
0 Enable Interrupt when
Enables Interrupt when TX bit is set.
TX bit is set
1 = Enable Interrupt when TX bit is set to 0.
0 = Disable Interrupt when TX bit is set to 0.
27 TX 0 Trasmitting Data
Indicates that the target is ready to transmit data
to the
host and the data is available in the transmit
data
register:
1 = Ready to transmit data.
0 = No data is available for transmission.
26 RX 0 Received Data
Indicates that the data has been received from the
host
and is placed in the receive data register.
1 = Received Data from host.
0 = No data has been received from host.
25 DISL1TR
0 Disable level 1 tracing
0 = Trace record generation not disabled on
transitioning to level 1
1 = Trace record generation disabled when in level
1
24 DISL0TR
0 Disable level 0 tracing
0 = Trace record generation not disabled on
transitioning to level 0
1 = Trace record generation disabled when in level
0
23 FRCDIS-
0 Deactivate the pending
1 = Deactivates the pending interrupt when
servicing
INTR interrupt when servicing
the interrupt.
the interrupt. This bit is
0 = pending interrupt is not disabled when
servicing
to support edge-sensitive
the interrupt.
interrupt controller
logic.
22:
TSYNC
08h
Trace synchronization
The value programmed in this register sets the
16 [6:0] force count
maximum number of Branch Sequence trace records
(TCODE = 1) that may be output by the trace record
generator before a synch address record is forced.
15:
Reserved
0 Reserved Reserved
14
14 TRACE/
0 TRACE ON/OFF
When this bit is set the TRIG pin is used to
indicate
ON-OFF STATUS TRACE-ON/OFF STATUS
__________________________________________________________________________
The host system 111 sends data to the processor core 104 by first testing the read-only RX bit in the DCSR register. If the RX bit is set to 0, then the host system 111 writes the data to the receive data (RX.sub.-- DATA) register and the serial port 100 sets the RX bit to 1 in the DCSR and ITCR registers. The RXINTEN bit in the ITCR register, when set, generates a signal to interrupt the processor core 104. The interrupt is only generated when RX bit in the DCSR makes a transition to 1. When the RXINTEN bit is not set, the processor core 104 polls the RX bit of the ITCR register. If the RX bit is set to 1, the processor core 104 executes an X86 instruction to read the data from the receive data (RX.sub.-- DATA) register. After data is read by the processor core 104 from the RX.sub.-- DATA register, the RX bit is set to 0 by the serial port 100. The host system 111 continuously reads the DCSR register and monitors the RX bit to continue sending data. Referring to FIG. 8, a schematic state diagram illustrates operating states of the pending/finished state machine 224. The 38-bit serial register in the serial debug port shifter 227 operates as a serial command interface including the 32-bit data field, the 4-bit command, the command pending flag (P), and the command finished flag (F). The 32-bit data, 4-bit command, and the pending flag are shifted serially into the 38-bit serial shift register using the shift-DR state in the JTAG TAP controller. When the TAP controller enters the Update-DR state the 38-bit data is loaded into the internal data and command registers. The command pending flag is set. For commands that do not include a data transfer, bits in the data field are set to 0. The pending/finished state machine 224 enters and Idle state (state=0) 800 immediately after the TRST.sub.-- L JTAG input signal is asserted (See the JTAG standard signals designated in TABLE I). After shifting the 38-bit data, when the JTAG TAP controller 204 is in the Update-DR state and the pending flag is set (P=1), the state machine enters Cycle Pending state (state=1) 801. The pending/finished state machine 224 transitions to a Cycle Finished state (state=2) 802 when the JTAG TAP controller 204 is in the Capture-DR state and an indication occurs that the previous command is completed. The 38-bit serial debug shifter 227 is loaded with the 32-bit output data, the finished flag is set to 1 (F=1), and the command field cmd[3:0] (4'b0000) and the pending flag are set to 0. When the pending/finished state machine 224 is in the Cycle Finished state 802, the JTAG TAP controller 204 is in the Update-DR state, and the Pending Flag is set to 1 (P=1), then the pending/finished state machine 224 transitions to the Cycle Pending State(state=1) 801. Signals that set the finished flag (F) and pending flag (P) in the 38-bit shifter are set to 0 and 1, respectively. If the JTAG TAP controller 204 is in the Update-DR state and the Pending Flag is set to 0 (P=0), then the pending/finished state machine 224 transitions to the Idle State (state=0) 800. Signals that set the finished flag (F) and pending flag (P) are set to 0. Otherwise, the pending/finished state machine 224 in the Cycle Finished state 802. Signals that set the finished flag (F) and pending flag A) are set to 1 and 0, respectively. Referring to FIG. 9, a schematic state diagram depicts operating states of the debug port state machine 206. The debug port state machine 206 interfaces with the pending/finished state machine 224, the parallel port state machine 226, the processor interface state machine 202, and the command decode and processing block 208. The debug port state machine 206 generates output signals for command decoding and generates debug register clock signals for register write operations. The debug port state machine 206 issues a signal to the parallel port state machine 226 and the pending/finished state machine 224 when the command is completed. A JTAG reset, a reset of the JTAG TAP controller 204, is generated by a TRST.sub.-- L signal of the standard JTAG signals. Upon a JTAG reset, the debug port state machine 206 enters a Not JTAG Debug State (state=0) 900. When the host system 111 writes a DEBUG private instruction to the JTAG instruction register using the Capture-IR-Update IR sequence shown in the JTAG TAP controller state machine shown in FIG. 3, a JTAG debug instruction state variable is set to 1 and the debug port state machine 206 transitions to a JTAG Debug Mode state (state=1) 901. In the JTAG Debug Mode state 901, if the Pending flag is set (P=1), the TAP controller state in the previous cycle was Update-DR, and the JTAG debug instruction state variable is equal to 1, then the debug port state machine 206 transitions to a Decode 1 state (state=3) 903 and sets a JTAG decode output signal to 1. If the processor core 104 is in a debug mode so that a Debug Mode TCK signal is asserted and the JTAG debug instruction state variable is asserted, then the debug port state machine 206 transitions to a Debug Active state (state=2) 902 and sets a debug acknowledge TCK output signal to 1 with the finished flag (F) holding to the same value as in the previous state. If the JTAG debug instruction state variable is equal to 0, then the debug port state machine 206 transitions back to the Not JTAG Debug State (state=0) 900. When the debug port state machine 206 is in the Debug Active state 902, several state transitions are possible. If a command is written either through the JTAG TAP controller 204 or the parallel port 214, and the processor core 104 is in the debug mode so that the Debug Mode TCK signal is asserted, the debug port state machine 206 transitions to a Decode 2 state (state=4) 904. Upon entering the Decode 2 state 904, the JTAG decode output signal is set to 1 and the debug acknowledge TCK signal is set to 1, acknowledging entry to the debug mode to the parallel port state machine 226. If the processor core 104 leaves the debug mode which is indicated by the Debug Mode TCK signal being deasserted to 0, then the debug port state machine 206 transitions back to the JTAG Debug Mode state 901 and the output Finished flag (F) is set to the previous value. If the debug port state machine 206 transitions to the Debug Active state 902 from a CPU Trace Command Wait state (state=5) 905, then a parallel port acknowledge signal is asserted to 1 and the finished flag is asserted (F=1). The parallel port acknowledge signal is an acknowledgment to the parallel port state machine 226 indicating that the previous CPU/TRACE command has completed execution. In the Decode1 state 903, the debug port state machine 206 transitions to a Register Write state (state=6) 906 in the next clock cycle and sets a JTAG decode output signal to 1 indicating for the command decode and processing block 208 to decode the received command. Also in the transition to the Register Write state 906, the parallel port acknowledge signal is asserted to 1, the debug acknowledgment TCK signal retains the value of the previous cycle, a serial debug port (SDP) register write TCK clock signal is asserted to 1, and the finished flag is asserted (F=1). In the Decode2 state (state=4) 904, if the command decoded by the command decode and processing block 208 is a CPU command or a serial trace read command, the debug port state machine 206 transitions to the CPU Trace Command Wait state (state=5) 905, the JTAP decode output signal is asserted to 1, and the debug acknowledgment TCK signal retains the value of the previous cycle. If the decoded command is not a CPU command or a serial trace read command, the debug port state machine 206 transitions to the Register Write state 906 and the JTAG decode output signal is asserted to 1, the parallel port acknowledge signal is asserted to 1, the debug acknowledgment TCK signal retains the value of the previous cycle, the serial debug port (SDP) register write TCK clock signal is asserted to 1, and the finished flag is asserted (F=1). When the debug port state machine 206 is in the CPU Trace Command Wait state (state=5 ) 905 waiting for the CPU command or the serial trace command to complete and if a CPU command done TCK signal is asserted to 1, then the debug port state machine 206 transitions to the Debug Active state 902. In the transition to the Debug Active state 902, the debug acknowledgment TCK signal is asserted to 1, the finished flag is asserted (F=1), and the parallel port acknowledge signal is asserted to 1. In the Register Write state 906, if the serial debug port register write feedback signal is asserted to 1 and the processor core 104 is in the debug mode so that the Debug Mode TCK signal is asserted, then the debug port state machine 206 transitions to the Debug Active state 902. The asserted serial debug port register write feedback signal indicates that the clock signal for the register writes was generated. If the serial debug port register write feedback signal is asserted to 1 and the processor core 104 is not in the debug mode (the Debug Mode TCK signal is deasserted to 0), then the debug port state machine 206 transitions to the JTAG Debug mode state 901 and the finished flag (F) retains the previous value. Referring to FIG. 10, a schematic state diagram depicts operating states of the parallel port state machine 226. The parallel port state machine 226 reads data and commands from the parallel port 214 and establishes a request-grant handshake between the host system 111 and the target system 101. The parallel port state machine 226 communicates with the debug port state machine 206 when the command is read from the parallel port 214, as is indicated by a Parallel update signal that is asserted to 1. The debug port state machine 206 asserts the parallel port acknowledge signal to 1 when the CPU command or serial trace read command is completed. The parallel port state machine 226 also generates pad control signals from the parallel port lines CI.sub.-- PDATA[15:0] and CI.sub.-- PADR[2:0]. The parallel port state machine 226 generates a command acknowledge CO.sub.-- CMDACK signal. The parallel port state machine 226 enables pads CI.sub.-- PDATA[15:0], CI.sub.-- PADR[2:0], and CI.sub.-- PRW for generating output signals when a breakpoint request CO.sub.-- PBREQ signal is deasserted to 0 and the command acknowledge CO.sub.-- CMDACK signal is asserted to 1. Trace data[19:0] is transmitted on the 20-bit bus formed by the CI.sub.-- PDATA[15:0] and CI.sub.-- PADR[2:0], and CI.sub.-- PRW signals. When the parallel port 214 is enabled the CI.sub.-- PDATA[15:0] is used for sending output signals when CI.sub.-- PRW=1. When CI.sub.-- PRW=0, the 20-bit bus it is used as an input bus. The parallel port state machine 226 transitions to an Idle state (state=0) 1000 under several conditions. The parallel port state machine 226 enters the Idle state 1000 when a JTAG Test Reset signal is asserted to 1, when the parallel port enable (PARENB) signal is 0 in the Debug Registers 210, or when the JTAG debug instruction state variable is 0. In the Idle state 1000, an output signal tri.sub.-- pdata that is used for pad control of the parallel lines CI.sub.-- PDATA[15:0] is deasserted to 0 so that the port CI.sub.-- PDATA[15:0] is enabled as input to the parallel port 214. The parallel port state machine 226 operates using several state variables. For example, an output signal sel.sub.-- dt.sub.-- leo is used as a multiplexer select between usage of the parallel port 214 as the data bus and as the trace bus. A command acknowledge signal cmdack.sub.-- out indicates that a parallel port command is complete. A CO.sub.-- CMDACK signal designates a logical-OR condition of the command acknowledge output signal cmdack.sub.-- out and the finished flag (F). A signal low.sub.-- data.sub.-- up is used for latching the lower sixteen bits of data on the parallel port 214. A signal up.sub.-- data.sub.-- up is used for latching the upper sixteen bits of data on the parallel port 214. A parallel port read select signal par.sub.-- read.sub.-- sel is used to select an upper or lower word when the processorcore 104 reads data using the parallel port 214. In the Idle state 1000, the output signal sel.sub.-- d.sub.-- t.sub.-- leo is deasserted to 0, the CO.sub.-- PBREQ is deasserted to 0, the low.sub.-- data.sub.-- up signal and the up.sub.-- data.sub.-- up signal are deasserted to 0, and the par.sub.-- read.sub.-- sel signal is deasserted to 0. In the Idle state 1000, if the parallel port enable (PARENB) signal is asserted to 1and the debug acknowledgment TCK signal is asserted to 1, then the parallel port state machine 226 transitions to a parallel port mode state (state=1) 1001. Command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ are asserted to 1. Parallel bus read select, upper order data select, and lower order data select output signals, respectively, par.sub.-- read.sub.-- sel, up.sub.-- data.sub.-- up, and low.sub.-- data.sub.-- up are deasserted to 0. Up.sub.-- data.sub.-- up and low.sub.-- data.sub.-- up signals from the previous cycle are latched and used to generate a pulse that is used to latch the upper or lower 16-bits of parallel port data into ldata.sub.-- in[15:0] and 1 data.sub.-- in[15:0] registers. In the parallel port mode state 1001, the parallel port state machine 226 waits for the host system 111 to write data and commands, or read data from the target system 101. If the host system 111 asserts a parallel bus grant signal (CI.sub.-- PBGNT=1) and the parallel address bits are deasserted (CI.sub.-- PADR=2'b00), the parallel port state machine 226 transitions to a Grant Mode state (state=2) 1002 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Also in the parallel port mode state 1001, if the host system 111 asserts the parallel bus grant signal (CI.sub.-- PBGNT=1) but deasserts the parallel read/write signal (CI.sub.-- PRW=0 ), and the parallel address bits are set to CI.sub.-- PADR=2'b01, then the parallel port state machine 226 transitions to a Wait State (state=5) 1005 and asserts the parallel bus request (CO.sub.-- PBREQ =1) indicating that the host system 111 has completed writing the command. Also in the parallel port mode state 1001, if the host system 111 asserts the parallel bus grant signal (CI.sub.-- PBGNT=1) but deasserts the parallel read/write signal (CI.sub.-- PRW=0), and the parallel address bits CI.sub.-- PADR are set to either 2'b10 or 2'b11, then the parallel port state machine 226 transitions to a parallel read mode state (state=3) 1003 and asserts the command acknowledge and the parallel bus request (CO.sub.-- CMDACK=1 and CO.sub.-- PBREQ =1). In the transition to the parallel read mode state 1003, if the parallel address bits CI.sub.-- PADR are 2'b10, the parallel port state machine 226 asserts the upper order 16-bit data transfer signal (up.sub.-- data.sub.-- up=1). If the parallel address bits CI.sub.-- PADR are 2'b11, the parallel port state machine 226 asserts the lower order 16-bit data transfer signal (low.sub.-- data.sub.-- up=1). Also in the parallel port mode state 1001, if the host system 111 asserts the parallel bus grant signal and the parallel read/write signal (CI.sub.-- PBGNT=1 and CI.sub.-- PRW=1), and the parallel address bits CI.sub.-- PADR are set to either 2'b10 or 2'b11, then the parallel port state machine 226 transitions to a parallel write mode state (state=4) 1004 and asserts the command acknowledge and the parallel bus request (CO.sub.-- CMDACK=1 and CO.sub.-- PBREQ=1). In the transition to the parallel write mode state 1004, if the parallel address bits CI.sub.-- PADR are 2'b10, the parallel port state machine 226 asserts the parallel read select par.sub.-- read.sub.-- sel=1) indicating to multiplex the high-order 16-bits of data to the host system 111 on PDATA[15:0] bus. If the parallel address bits CI.sub.-- PADR are 2'b11, the parallel port state machine 226 deasserts the parallel read select (par.sub.-- read.sub.-- sel=0) indicating to multiplex the low-order 16-bits of data to the host system 111 on PDATA[15:0] bus. Also in the parallel port mode state 1001, if the debug acknowledgment TCK signal is deasserted to 0 indicating that the CPU is not in the debug mode, the parallel port state machine 226 transitions to the Idle state 1000, deasserting the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 0, and deasserting the parallel read select, upper order data, and lower order data signals par.sub.-- read.sub.-- sel=0, up.sub.-- data.sub.-- up=0, and low.sub.-- data.sub.-- up=0, respectively. In the Grant Mode state 1002, if the host system 111 deasserts the parallel bus grant signal CI.sub.-- PBGNT=0, then the parallel port state machine 226 transitions to the parallel port mode state 1001 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Also in the Grant Mode state 1002, if the debug acknowledgment TCK signal is deasserted to 0, the parallel port state machine 226 transitions to a DONE state (state=7) 1007 and deasserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 0, as well as deasserting the parallel read select, upper order data, and lower order data signals, respectively, par.sub.-- read.sub.-- sel, up.sub.-- data.sub.-- up, low.sub.-- data.sub.-- up, to 0. Also in Grant.sub.-- mode state 1002, if the parallel port read/write select signal CI.sub.-- PRW is deasserted to 0 and the parallel port address CI.sub.-- PADR selects 2'b01, then the parallel port state machine 226 transitions to a Wait state (state=5) 1005 and the parallel bus request CO.sub.-- PBREQ is asserted to 1 and CO.sub.-- CMDACK is set to 0. Otherwise in the Grant Mode state 1002, if the parallel port read/write select signal CI.sub.-- PRW is deasserted to 0 and the parallel port address CI.sub.-- PADR selects either 2'b10 or 2'b11, then the parallel port state machine 226 transitions to the parallel read mode state (state=3) 1003. In the transition to the parallel read mode state (state=3) 1003, the parallel port state machine 226 asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. If the parallel address bits CI.sub.-- PADR are 2'b10 , the parallel port state machine 226 asserts the upper order 16-bit data transfer signal (up.sub.-- data.sub.-- up=1). If the parallel address bits CI.sub.-- PADR are 2'b11, the parallel port state machine 226 asserts the lower order 16-bit data transfer signal (low.sub.-- data.sub.-- up=1). Also in Grant Mode state 1002, if the parallel read write select CI.sub.-- PRW is asserted to 1 and the parallel port address CI.sub.-- PADR is not equal to 2'b00, then the parallel port state machine 226 transitions to the parallel write mode state 1004 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. In the transition to the parallel write mode state 1004, if the parallel address bits CI.sub.-- PADR are 2'b10, the parallel port state machine 226 asserts the parallel read select (par.sub.--read.sub.-- sel=1) indicating to multiplex the high-order 16-bits of data to the host system 111 on PDATA[15:0] bus. If the parallel address bits CI.sub.-- PADR are 2'b11, the parallel port state machine 226 deasserts the parallel read select (par.sub.-- read.sub.-- sel=0) indicating to multiplex the low-order 16-bits of data to the host system 111 on PDATA[15:0] bus. In the parallel read mode state 1003, if the host system 111 deasserts the parallel bus grant signal CI.sub.-- PBGNT to 0, then the parallel port state machine 226 transitions to the parallel port mode state 1001 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Otherwise in the parallel read mode state 1003, if the host system 111 sets the parallel port address to 2'b00, then the parallel port state machine 226 transitions to the Grant Mode state 1002 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Otherwise in the parallel read mode state 1003, if the host system 111 sets the parallel port address to 2'b01, then the parallel port state machine 226 transitions to the Wait state 1005 and asserts the parallel bus request output signal CO.sub.-- PBREQ to 1. In the parallel write mode state 1004, if the host system 111 deasserts the parallel bus grant signal CI.sub.-- PBGNT to 0, then the parallel port state machine 226 transitions to the parallel port mode state 1001 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Otherwise in the parallel write mode state 1004, if the host system 111 sets the parallel port address to 2'b00, then the parallel port state machine 226 transitions to the Grant Mode state 1002 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Otherwise in the parallel write mode state 1004, if the host system 111 deasserts the parallel read write select CI.sub.-- PRW to 0 and sets the parallel port address to either 2'b10 or 2'b11, then the parallel port state machine 226 transitions to the parallel read mode state 1003 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. If the parallel address bits CI.sub.-- PADR are 2'b10, the parallel port state machine 226 asserts the upper order 16-bit data transfer signal (up.sub.-- data.sub.-- up=1). If the parallel address bits CI.sub.-- PADR are 2'b11, the parallel port state machine 226 asserts the lower order 16-bit data transfer signal (low.sub.-- data.sub.-- up=1). In the Wait state 1005, if the host system 111 deasserts the parallel bus grant signal CI.sub.-- PBGNT to 0, then the parallel port state machine 226 transitions to the parallel port mode state 1001 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Otherwise in the Wait state 1005, if the host system 111 sets the parallel port address CI.sub.-- PADR to 2'b00, then the parallel port state machine 226 transitions to the Grant Mode state 1002 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Otherwise in the Wait state 1005, if the parallel port acknowledge signal is 1, then the parallel port state machine 226 transitions to an Exit state (state=6) 1006 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. In the Exit state 1006, if the debug acknowledgment TCK signal is equal to 0, then the parallel port state machine 226 transitions to the Idle state 1000 and deasserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 0. Also in the transition to the Idle state 1000, the parallel port state machine 226 deasserts the parallel read select, upper order data, and lower order data signals, respectively par.sub.-- read.sub.-- sel, up.sub.-- data.sub.-- up, and low.sub.-- data.sub.-- up, to 0. Also in the Exit state 1006, if the host system 111 deasserts the parallel bus grant signal CI.sub.-- PBGNT to 0, then the parallel port state machine 226 transitions to the parallel port mode state 1001 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. Otherwise in the Exit state 1006, if the host system 111 asserts the parallel bus grant signal CI.sub.-- PBGNT to 1 and if debug acknowledgment TCK signal is asserted to 1, the parallel port state machine 226 transitions to the Grant Mode state 1002 and asserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 1. In the Done state 1007, the parallel port state machine 226 waits for a deasserted parallel bus grant signal CI.sub.-- PBGNT from the host system 111. When the host system 111 deasserts the parallel bus grant signal CI.sub.-- PBGNT to 0, the parallel port state machine 226 transitions to the Idle state 1000 and deasserts the command acknowledge and parallel bus request output signals CO.sub.-- CMDACK and CO.sub.-- PBREQ to 0, as well as deasserting the parallel read select, upper order data, and lower order data signals, respectively par.sub.-- read.sub.-- sel, up.sub.-- data.sub.-- up, and low.sub.-- data.sub.-- up, to 0. Referring to FIG. 11, a schematic state diagram depicts operating states of the processor interface state machine 202. The processor interface state machine 202 interfaces to the processor core 104 and operates at the same frequency as the processor core 104. The processor interface state machine 202 also interfaces to the trace control circuit 218 and performs several functions. For example, the processor interface state machine 202 take appropriate actions for commands that are decoded by the command decode and processing block 208. The processor interface state machine 202 generates multiplexer control signals for multiplexing data for read operations of the processor core 104 including selection of read operations directed to the RX.sub.-- DATA[31:0] register, the trace.sub.-- record[20:0], the ITCR[31:0] register, the soft.sub.-- address[31:0] register, the command[3:0] including upper-order data udata.sub.-- in[15:0] and lower-order data 1data.sub.-- in[15:0]. The processor interface state machine 202 generates write strobe signals for writing the data from the processor core 104 to the ITCR[31:0] register, the TX.sub.-- DATA[31:0] register, and the read.sub.-- data[31:0] register. Data from the read.sub.-- data register is read by the host system 111. For example, if the host system 111 requests a read operation from an EAX register in the processor core 104, data from the processor core 104 is placed in the read.sub.-- data register that is eventually read by the host system 111. If the host system 111 reads the data using the JTAG TAP controller 204 and the JTAG TAP controller state machine is in capture-DR state (see FIG. 3), data from the read.sub.-- data register is transferred to a shifter[37:6] register in the serial debug shifter 227. If the host system 111 uses the parallel port 214, data from the read.sub.-- data register is placed onto the PDATA[15:0] bus. The processor interface state machine 202 indicates to the trace control circuit 218 information regarding a serial trace read from a designated address in the soft address register. When the trace control circuit 218 completes reading of the trace data, the processor interface state machine 202 generates a command finished signal (cmd.sub.-- done) to the debug port state machine 206 and generates a write strobe signal for read.sub.-- data register. The processor interface state machine 202 enters an Idle State (state=0) 1100 following a CPU.sub.-- reset signal from the processor core 104. The command decode and processing block 208 decodes CPU commands and sends appropriate signals to the processor interface state machine 202. In the Idle State 1100, if the processor core 104 writes a DEBUG ACTIVATE command the processor interface state machine 202 remains in the Idle State 1100 and asserts the Debug Mode TCK output signal to 1, indicating that the processor core 104 is in debug mode. The Debug Mode TCK signal is used by the debug port state machine 206 to generate an acknowledgment signal. In the Idle State 1100, if the processor core 104 writes a DEBUG INACTIVATE command the processor interface state machine 202 remains in the Idle State 1100 and deasserts the Debug Mode TCK output signal to 0, indicating that the processor core 104 has exited debug mode. In the Idle State 1100, if the processor core 104 writes the READ ITCR REGISTER command the processor interface state machine 202 transitions to a Data Read Processor State (state=1) 1101 and sets a processor output select cpu.sub.-- out.sub.-- sel[2:0] output signal to 3'b010. The processor output select control the multiplexer for sending data to the processor core 104. In the Idle State 1100, if the processor core 104 sends the WRITE ITCR REGISTER command the processor interface state machine 202 transitions to a Write Processor TX ITCR Register state (state=5) 1105 and asserts an ICTR register write signal itcr.sub.-- wr.sub.-- str to 1 and asserts a multiplexer control signal data.sub.-- in.sub.-- mux.sub.-- cntl to 1. The ITCR register write signal itcr.sub.-- wr.sub.-- str is used to write the CPU data to the ITCR register. The multiplexer control signal data.sub.-- in.sub.-- mux.sub.-- cntl is used to control a 2:1 multiplexer 1534 which is used for multiplexing processor data and serial port data. In the Idle State 1100, if the processor core 104 writes a READ DEBUG DATA command the processor interface state machine 202 transitions to the Data Read Processor State 1101 and sets the processor output select cpu.sub.-- out.sub.-- sel[2:0] signal to 3'b011. The processor output select cpu.sub.-- out.sub.-- sel value of 3'b011 multiplexes upper order and low order data, respectively udata.sub.-- in[15:0] and ldata.sub.-- in[15:0], to the processor core 104. In the Idle State 1100, if the processor core 104 writes the READ DEBUG COMMAND the processor interface state machine 202 transitions to the Data Read Processor State 1101 and sets the processor output select cpu.sub.-- out.sub.-- sel[2:0] signal to 3'b100. The processor output select cpu.sub.-- out.sub.-- sel value of 3'b100 multiplexes command cmd[3:0] register data to the processor core 104. In the Idle State 1100, if the processor core 104 writes a WRITE DEBUG DATA command the processor interface state machine 202 transitions to the Data Write Processor State (state=3) 1103 and asserts a multiplexer select udb.sub.-- data.sub.-- reg.sub.-- wr.sub.-- enb signal to 1, controlling a multiplexer 1530 to select the processor data for writing to the read.sub.-- reg[31:0] register. When the processor interface state machine 202 is in the Idle State 1100 and the processor core 104 writes a READ SOFT ADDRESS REGISTER command, the processor interface state machine 202 transitions to the Data Read Processor State 1101 and sets the processor output select cpu.sub.-- out.sub.-- sel[2:0] signal to 3'b101, multiplexing the soft.sub.-- addr[31:0] register data to the processor core 104. When the processor interface state machine 202 is in the Idle State 1100 and the processor core 104 writes a WRITE IRBUF N command or a POST ITBUF N command, the processor interface state machine 202 remains in the Idle State 1100. The trace control circuit 218 logic also reads the commands from the processor core 104 and appropriately decodes the commands and performs the requested operations. In the Idle State 1100, if the processor core 104 writes a READ ITBUF N command the processor interface state machine 202 transitions to a the Read Processor Trace State (state=4) 1104. The processor output select signal cpu.sub.-- out.sub.-- sel signal is set to 3'b001 to select trace record data. When the processor interface state machine 202 is in the Idle State 1100 and the processor core 104 writes a command to read the receive data, the processor interface state machine 202 transitions to the Data Read Processor State 1101 and sets the processor output select cpu.sub.-- out.sub.-- sel[2:0] to 3'b000, thereby selecting the receive data register data. When the processor interface state machine 202 is in the Idle State 1100 and the processor core 104 writes a command to write data to the transmit data register, the processor interface state machine 202 transitions to the Write Processor TX ITCR Register state 1105 and asserts a write transmit register transmit.sub.-- reg.sub.-- wr.sub.-- str signal and a multiplex data data.sub.-- in.sub.-- mux.sub.-- cntl signal to 1. The write transmit register signal transmit.sub.-- reg.sub.-- wr.sub.-- str is used to write to the transmit register and also to set the TX bit in the ITCR register. The multiplex data signal data.sub.-- in.sub.-- mux.sub.-- cntl is used to multiplex 1534 the data from the processor core 104. When the processor interface state machine 202 is in the Idle State 1100 and the processor core 104 writes a command indicating that the serial/parallel port command is completed, the processor interface state machine 202 transitions to a Command Complete State 1106 and asserting the JTAG command done signal jtag.sub.-- cmd.sub.-- done to 1. The JTAG command done signal is used by the debug port state machine 206 to acknowledge command completion to the Host and accept new commands. When the processor interface state machine 202 is in the Idle State 1100 and if a processor reset signal cpu.sub.-- reset or a processor soft reset signal cpu.sub.-- sreset occur, or the freset bit in the DCSR register is asserted, then the processor interface state machine 202 remains in the Idle State 1100, retaining the Debug Mode TCK output signal at a value of 0 to indicate that the processor core 104 is not in the debug mode. When the processor interface state machine 202 is in the Idle State 1100 and the host system 111 writes a SERIAL TRACE READ command, the processor interface state machine 202 transitions to a Read Trace State 1102 and asserts a serial trace write enable serial.sub.-- trace.sub.-- wr.sub.-- enb signal and a serial trace read serial.sub.-- trace.sub.-- read signal to 1. The serial trace write enable signal serial.sub.-- trace.sub.--wr.sub.-- enb is used to select, using multiplexer control, 1530 the trace record for writing to the read.sub.-- data register. The host system 111 reads the trace data from the read.sub.-- data register. The serial trace read signal serial.sub.-- trace.sub.-- read is sent to the trace control circuit 218 logic indicating for the trace control circuit 218 to read the trace data from the address in the soft.sub.-- address register. In the Data Write Processor State 1103, the processor interface state machine 202 is waits for a write debug wr.sub.-- udb.sub.-- data signal from the processor core 104 which indicates that the processor core 104 writes the data. When the processor core 104 asserts the write debug wr.sub.-- udb.sub.-- data signal to 1, the processor interface state machine 202 transitions to the Idle State 1100. A write data signal udb.sub.-- data.sub.-- reg.sub.-- wr.sub.-- str is asserted to 1 and a multiplexer 1530 select signal udb.sub.-- data.sub.-- reg.sub.-- wr.sub.-- enb is set remain at the previous latched value. The write data signal udb.sub.-- data.sub.-- reg.sub.-- wr.sub.-- str is used to write data to the read.sub.-- data register. The multiplexer select signal udb.sub.-- data.sub.-- reg.sub.-- wr.sub.-- enb is used to multiplex 1530 select data from the processor core 104. In the Data Read Processor State 1101, the processor interface state machine 202 waits for a read data signal rd.sub.-- udb.sub.-- data from the processor core 104. The read data signal rd.sub.-- udb.sub.-- data indicates that the processor core 104 is reading the data. When the processor core 104 asserts the read data signal rd.sub.-- udb.sub.-- data to 1, the processor interface state machine 202 transitions to the Idle State 1100, setting the processor output select signal cpu.sub.-- out.sub.-- sel to 3'b011. If the previous latched value of the processor output select signal cpu.sub.-- out.sub.-- sel is equal to 3'b000, indicating that the processor core 104 requests a data read from the receive data register, then an RX bit clear output signal rx.sub.-- bit.sub.-- wr is asserted to 1, clearing the RX bit in the ITCR/DCSR registers. In Read Trace State 1102, the processor interface state machine 202 waits for a trace.sub.-- data.sub.-- done indication from the trace control circuit 218. When trace control circuit 218 asserts trace.sub.-- data.sub.-- done indication to 1, the processor interface state machine 202 transitions to the Command Complete State 1106. In the transition to the Command Complete State 1106 asserts serial trace write and enable read signals, respectively serial.sub.-- trace.sub.-- wr.sub.-- str and serial.sub.-- trace.sub.-- wr.sub.-- enb to 1, deasserts a serial trace read signal serial.sub.-- trace.sub.-- read to 0, and asserts the JTAG command complete jtag.sub.-- cmd.sub.-- done signal to 1. The serial trace write signal serial.sub.-- trace.sub.-- wr.sub.-- str is used to write the trace data to the read.sub.-- data register. The serial trace enable signal serial.sub.-- trace.sub.-- wr.sub.-- enb is used to multiplex 1530 select the trace data. The serial trace read signal serial.sub.-- trace.sub.-- read deasserted to 0 is used to indicate to the trace control circuit 218 that the serial trace is complete. The JTAG command complete signal jtag.sub.-- cmd.sub.-- done indicates to the debug port state machine 206 that the command is complete. In the Read Processor Trace State 1104, the processor interface state machine 202 waits for the trace.sub.-- data.sub.-- done indication from the trace control circuit 218, indicating that the data requested by the processor core 104 has been read from the trace buffer 200. When trace.sub.-- data.sub.-- done is set, the processor interface state machine 202 transitions to the Data Read Processor State 1101 and the processor output select signal cpu.sub.-- out.sub.-- sel[2:0] is set to 3'b001, multiplex selecting the trace data for processor core data read. In the Write Processor TX ITCR Register state 1105, the processor interface state machine 202 transitions to the Idle State 1100 in the next clock cycle with a data multiplex select output signal data.sub.-- in.sub.-- mux.sub.-- cntl asserted to 1, indicating for a multiplexer 1534 to select the processor core data for debug register write operations. In the Command Complete State 1106, the processor interface state machine 202 waits for a JTAG decode signal jtag.sub.-- decode.sub.-- ph2 to be asserted to 0, an indication from the debug port state machine 206 that the CPU command has been completed and the processor core 104 is ready to accept new commands from the host system 111. When the JTAG decode signal jtag.sub.-- decode.sub.-- ph2 is equal to 0, the processor interface state machine 202 transitions to the Idle State 1100 and deasserts the JTAG command output signal jtag.sub.-- cmd.sub.-- done to 0. Synchronization between Multiple Different Frequencies Referring again to FIG. 2, the host system 111 writes data to the Debug Registers 210, including ITCR, DCSR, RX.sub.-- DATA, TX.sub.-- DATA, and soft.sub.-- address registers, through the serial/parallel port 214. After the target system 101 reads the data and command for a write operation of a Debug Register 210, the debug port state machine 206 generates a serial debug port write TCK output signal (sdp.sub.-- reg.sub.-- write.sub.-- tck). The debug port state machine 206 operates at a frequency of 25 MHz. Referring to FIG. 12, a schematic circuit diagram illustrates an embodiment of a synchronization circuit 1200 for communicating commands and data between a communication port 214 which is operating at a specified lower frequency and a processor core 104 and trace control circuit 218 that are operating at multiple various frequencies that are higher than the specified lower frequency. The serial debug port register write TCK signal (sdp.sub.-- reg.sub.-- write.sub.-- tck) is synchronized through the usage of one or more flip-flops which are clocked by the processor clock operating at frequencies such as 33 Mhz, 66 Mhz, 99 Mhz, or 133 Mhz. In the illustrative embodiment, three flip-flops 1210, 1212, and 1214 are included in the synchronization circuit 1200. The rising edge of the serial debug port register write TCK signal (sdp.sub.-- reg.sub.-- write.sub.-- tck) is detected by a first flip-flop 1210 and is synchronized through a second flip-flop 1212 and a third flip-flop 1214 that are clocked by the processor clock (clk.sub.-- ph2). The output of the third flip-flop 1214 is qualified with a register enable signal generated by the command decode and processing block 208. The register enable signal is gated signal is used to clock the data to the registers of the Debug Registers 210. A reg.sub.-- write.sub.-- sync2 generated by the flip-flop 1216 is synchronized using a flip-flop 1218 clocked by a clock jtag signal (clk.sub.-- jtag) and the output clocked signal is sent to the debug port state machine 206. The serial debug port feedback signal (sdp.sub.-- reg.sub.-- write.sub.-- fbak) indicates to the debug port state machine 206 that the data has been written to the Debug Registers 210. The debug port state machine 206 in response indicates to the host system 111 the debug register write command completion status. Referring to FIG. 13 in combination with FIG. 12, a schematic block diagram illustrates synchronization elements of the embedded processor device 102 shown in FIGS. 1 and 2. Commands from the serial/parallel port 214 are decoded by the command decode and processing block 208. After the command is read from the host system 111, the debug port state machine 206 generates the JTAG decode (jtag.sub.-- decode) output signal that is used by the command decode and processing block 208 to decode the command in the command register. If the decoded command from the host system 111 employs intervention of the processor core 104, the command decode and processing block 208 generates a processor command TCK clock signal (sle486.sub.-- cpu.sub.-- cmd.sub.-- tck.sub.-- signal). The processor command TCK clock signal (sle486.sub.-- cpu.sub.-- cmd.sub.-- tck.sub.-- signal) is synchronized through multiple back to back flip-flops 1210, 1212, and 1214, clocked by the processor clock, and the output processor command phase signal (sle486.sub.-- cpu.sub.-- cmd.sub.-- ph2) is sent to the processor interface state machine 202. The processor interface state machine 202 responds by sending notification of the command to the processor core 104. The processor core 104 reads the command and responds with suitable and appropriate actions. After recognizing the CPU command, the debug port state machine 206 enters a wait state and waits for the processor core 104 to complete execution of the command. After the processor core 104 completes command execution, the processor core 104 writes a command indicating that the CPU command is completed. The command indicating completion is decoded by the command decode and processing block 208, which issues a processor command done (cpu.sub.-- cmd.sub.-- done) signal to the processor interface state machine 202 and to the debug port state machine 206. The processor command complete signal (cpu.sub.-- cmd.sub.-- done) is synchronized by multiple back-to-back flip-flops, for example flip-flops 1210, 1212, and 1214, clocked by the clock tag (clk.sub.-- tag) and sent to the debug port state machine 206. The debug port state machine 206 indicates to the host system 111 that the command is completed and deasserts the JTAG decode signal (jtag.sub.-- decode) to 0. The JTAG decode (jtag.sub.-- decode) signal is synchronized by the multiple back-to-back flip-flops clocked by the processor clock. The processor interface state machine 202 waits for the JTAG DECODE (jtag.sub.-- decode) signal from the debug port state machine 206 to go low (0) and transitions to an Idle state (the Not JTAG Debug State (state=0) 900 shown in FIG. 9). A similar synchronization technique and apparatus is used to communicate with the trace control circuit 218. Handshaking between Serial-Trace-Processor When the host system 111 completes writing a command, the debug port state machine 206 generates a JTAG DECODE (jtag.sub.-- decode) signal output to the command decode and processing block 208. If the command is a CPU command the command decode and processing block 208 logic generates the processor command TCK clock signal (sle486 .sub.-- cpu.sub.-- cmd.sub.-- tck signal) which is synchronized in a synchronization logic block 232. The synchronized output processor command phase signal (sle486.sub.-- cpu.sub.-- cmd.sub.-- ph2) is sent to the processor interface state machine 202 state machine. The debug port state machine 206 is in the wait state till the processor core 104 completes the execution of the command. A jump command pending (jmp.sub.-- cmd.sub.-- pending) signal and a jump command done (jmp.sub.-- cmd.sub.-- done) signal are generated by the processor core 104. An asserted jump command pending (jmp.sub.-- cmd.sub.-- pending) signal indicates that the processor core 104 is ready to accept new serial port/parallel port commands. An asserted jump command done (jmp.sub.-- cmd.sub.-- done) signal indicates that the processor core 104 has written a command to the serial port/parallel port 214 and is waiting for command completion. The processor interface state machine 202 generates and sends an output signal processor debug jump (sle486.sub.-- debug.sub.-- jmps) to the processor core 104. Processor debug jump (sle486.sub.13 debug.sub.-- jmps) indicates either that the command sent by the processor core 104 is complete or a new serial port command is available for the processor core 104. The processor core 104 interprets the signal based on the jump command done (jmp.sub.-- cmd.sub.-- done) or jump command pending (jmp.sub.-- cmd.sub.-- pending) signals. When the synchronization logic block 232 generates the processor command phase signal (sle486.sub.-- cpu.sub.-- cmd.sub.-- ph2), and when the CPU asserts the jmp.sub.-- cmd.sub.-- pending signal the processor interface state machine 202 asserts sle486.sub.-- debug.sub.-- jmps. The processor core 104 reads the command and completes execution of an appropriate task in one or a plurality of processor core 104 commands. When the command is completed, the processor core 104 writes a CMD.sub.-- DONE command on a debug data bus (udb.sub.-- data) and asserts a write command (wr.sub.-- udb.sub.-- cmd) signal. The processor core 104 also periodically asserts the jump command done (jmp.sub.-- cmd.sub.-- done) signal and samples sle486.sub.-- debug.sub.-- jmps until the processor debug jump (sle486.sub.-- debug.sub.-- jmps) signal is asserted. The command decode and processing block 208 logic decodes the command and generates a processor command finished (cpu.sub.-- cmd.sub.-- finished) output signal to the processor interface state machine 202. The processor interface state machine 202 transitions to a wait state and asserts the processor command finished (cpu.sub.-- cmd.sub.-- done) signal which is synchronized to a clock jtag (clk.sub.-- tag) signal in the synchronization logic block 232 and sent to the debug port state machine 206. The processor interface state machine 202 also asserts the processor debug jump (sle486.sub.-- debug.sub.-- jmps) signal. When CPU asserts the jmp.sub.-- cmd.sub.-- done indicating to the processor core 104 that the CMD.sub.-- DONE command is completed. The debug port state machine 206 transitions to a state that accepts further commands from the host system 111 and generates a command completion status flag to the host system 111. The debug port state machine 206 deasserts the JTAG DECODE jtag.sub.-- decode) signal output. When the JTAG DECODE (jtag.sub.-- decode) signal is equal to zero, the processor interface state machine 202 transitions to the Idle State 1100. To read data from the serial port/parallel port 214, the processor core 104 asserts read data (rd.sub.-- udb.sub.-- data) signals and reads data from the processor data output (cpu.sub.-- data.sub.-- out) bus. The processor interface state machine 202 multiplexes the data requested by the processor core 104 by generating processor output select (cpu.sub.-- out.sub.-- sel[3:0]) multiplex controls. To read trace data from the trace control circuit 218, the host system 111 writes a command through serial port/parallel port 214. The debug port state machine 206 asserts the JTAG DECODE (jtag.sub.-- decode) signal and the command decode and processing block 208 logic decodes the command and generates a serial trace read (serial.sub.-- trace.sub.-- read) signal. The debug port state machine 206 waits until the trace control circuit 218 completes reading the trace data. The serial trace read (serial.sub.-- trace.sub.-- read) signal is synchronized to the processor core 104 clock in the synchronization logic block 232 and a serial trace read phase two (ser.sub.-- trace.sub.-- read.sub.-- ph2) signal is sent to the processor interface state machine 202. The processor interface state machine 202 generates the serial trace read (serial.sub.-- trace.sub.-- read) signal to the trace control circuit 218 and transitions to a wait state for the trace control circuit 218 to complete reading the data. When the serial trace read (serial.sub.-- trace.sub.-- read) signal is asserted the trace control circuit 218 reads the data from the trace buffer 200 from an address designated by an instruction buffer address (ITBUF.sub.-- ADDR) bus. The trace control circuit 218 completes reading the data, asserts a trace data finished (trace.sub.-- data.sub.-- done) output signal, and sends the trace information via a trace record (trace.sub.-- record) bus. The processor interface state machine 202 transitions to another state and asserts the processor command finished (cpu.sub.-- cmd.sub.-- done) signal for the debug port state machine 206. The processor command finished (cpu.sub.-- cmd.sub.-- done) signal is synchronized to the clock jtag (clk.sub.-- tag) signal in the synchronization logic block 232 and the debug port state machine 206 deasserts JTAG DECODE (jtag.sub.-- decode) signal and transitions to a state that accepts new commands from the host system 111. The debug port state machine 206 also sets command completion status flag for the host system 111. Data Steering When the parallel port 214 is enabled, PDATA[15:0], PADR[2:0], and PRW are used as bidirectional pins. Controls for the pins are generated in the parallel port state machine 226 based on the PARENB bit in the DCSR register and the CO.sub.-- PBREQ output signal. When external tracing is enabled the bidirectional pins are used to generate output trace record signals. The data and commands from the JTAG TAP controller 204 port, and the parallel port 214 are latched into the 1data.sub.-- in[15:0], udata.sub.-- in[15:0], and cmd.sub.-- in[3:0] registers in the Debug Registers 210 block, shown in FIG. 2. The data and commands are multiplexed from the serial/parallel port 214 to the registers by a 2:1 multiplexer. Data and commands that originate from the JTAG TAP controller 204 port are written to the Debug Registers 210 when the JTAG TAP controller 204 is in the update-DR state. When the data originates from the parallel port 214, the parallel port state machine 226 generates write strobe signals to the registers. After the command is written to a command input (cmd.sub.-- in[3:0]) register the debug port state machine 206 transitions to the DECODE1 or DECODE2 state and generates the JTAG DECODE (jtag.sub.-- decode) output signal. The command decode and processing block 208 uses the JTAG DECODE (jtag.sub.-- decode) signal to decode the command in the command input (cmd.sub.-- in) register. The command decode and processing block 208 also decodes processor commands and the processor interface state machine 202 generates a multiplex control signal (data.sub.-- in.sub.-- mux.sub.-- cntl) to select data from either the serial/parallel port 214 or from the processor core 104. The multiplexed output data.sub.-- in[31:0] is used to write to the debug registers (ITCR, DCSR, RX.sub.-- DATA, TX.sub.-- DATA, SOFT.sub.-- ADDR) 210. The debug port state machine 206 generates a serial debug port write (sdp.sub.-- reg.sub.-- write) strobe for serial/parallel port data that is synchronized with the processor clock and qualified with the decoded signal to write to the registers. The processor interface state machine 202 generates the write strobe signals for writing the processor data to the Debug Registers 210 block. The processor interface state machine 202 generates the multiplex select signals when the processor core 104 attempts to read the data from the serial port of the JTAG TAP controller 204. While the invention has been described with reference to various embodiments, it will be understood that these embodiments are illustrative and that the scope of the invention is not limited to them. Many variations, modifications, additions and improvements of the embodiments described are possible. For example, those skilled in the art will readily implement the steps necessary to provide the structures and methods disclosed herein, and will understand that the process parameters, materials, and dimensions are given by way of example only and can be varied to achieve the desired structure as well as modifications which are within the scope of the invention. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope and spirit of the invention as set forth in the following claims.
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