Trace synchronization in a processor6009270Abstract A processor provides trace synchronization information to ensure that address information for reconstructing instruction execution flow is provided in trace records with sufficient frequency. A trace record is provided for instructions that change the program flow such as conditional branches. However, target address information is not provided in the trace record for such instructions as conditional branches, only an indication of whether the branch was taken. Target address information is provided, however, for those instructions in which the target address is in some way data dependent. The processor determines whether each trace record includes address information. Each trace entry providing address information causes a counter to be reloaded to a predetermined value which is the desired maximum number of trace records generated before current program address information is provided. The counter counts each trace record produced which does not include address information. When the count of such trace records reaches the predetermined number, trace logic provides the current program address as a trace entry, thereby providing trace synchronization information. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
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##STR1##
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This JTAG instruction register is selected by toggling the test mode select signal TMS. The test mode select signal TMS allows the JTAG path of clocking to be changed in the scan path, enabling multiple paths of varying lengths to be used. Preferably, the JTAG instruction register is accessible via a short path. This register is configured to include a soft register for holding values to be loaded into or received from specified system registers. Referring now to FIG. 3, a simplified block diagram depicting the relationship between an exemplary instruction trace memory 200 and other components of an embedded processor device 102 according to the present invention is shown. In one contemplated embodiment of the invention, the trace memory 200 is a 128 entry first-in, first-out (FIFO) circular memory that records the most recent trace entries. Increasing the size of the trace memory 200 increases the amount of instruction trace information that can be captured, although the amount of required silicon area may increase. As described in more detail below, the trace memory 200 of the disclosed embodiment of the invention stores a plurality of 20-bit (or more) trace entries indicative of the order in which instructions are executed by the processor core 104. Other information, such as task identifiers and trace capture stop/start information, can also be placed in the trace memory 200. The contents of the trace memory 200 are provided to external hardware, such as the host system H, via either serial or parallel trace pins 230. Alternatively, the target system T can be configured to examine the contents of the trace cache 200 internally. FIG. 4 provides a high-level flow chart of command passing when using a standard JTAG interface. Upon entering debug mode in step 400 the DEBUG instruction is written to the TAP controller 204 in step 402. Next, step 404, the 38-bit serial value is shifted in as a whole, with the command pending flag set and desired data (if applicable, otherwise zero) in the data field. Control proceeds to step 406 where the pending command is loaded/unloaded and the command finished flag checked. Completion of a command typically involves transferring a value between a data register and a processor register or memory/IO location. After the command has been completed, the processor 104 clears the command pending flag and sets the command finished flag, at the same time storing a value in the data field if applicable. The entire 38-bit register is shifted out to the host to monitor the command finished and command pending flags. If the pending flag is reset to zero and the finished flag is set to one, the previous command has finished. The status of the flags is captured by the control interface state machine 206. A slave copy of the flags' status is saved internally to determine if the next instruction should be loaded. The slave copy is maintained due to the possibility of a change in flag status between TAP controller 204 states. This allows the processor 104 to determine if the previous instruction has finished before loading the next instruction. If the finished flag is not set as determined in step 408, control proceeds to step 410 and the loading/unloading of the 38-bit command is repeated. The command finished flag is also checked. Control then returns to step 408. If the finished flag is set as determined in step 408, control returns to step 406 for processing of the next command. DEBUG mode is exited via a typical JTAG process. Returning to FIG. 2, the aforementioned optional sideband signals are utilized in the enhanced debug port 100 to provide extra functionality. The optional sideband signals include a break request/trace capture signal BRTC that can function as a break request signal or a trace capture enable signal depending on the status of bit set in the debug control/status register. If the break request/trace capture signal BRTC is set to function as a break request signal, it is asserted to cause the processor 104 to enter debug mode (the processor 104 can also be stopped by scanning in a halt command via the convention JTAG signals). If set to function as a trace capture enable signal, asserting the break request/trace capture signal BRTC enables trace capture. Deasserting the signal turns trace capture off. The signal takes effect on the next instruction boundary after it is detected and is synchronized with the internal processor clock. The break request/trace capture signal BRTC may be asserted at any time. The trigger signal TRIG is configured to pulse whenever an internal processor breakpoint has been asserted. The trigger signal TRIG may be used to trigger an external capturing device such as a logic analyzer, and is synchronized with the trace record capture clock signal TRACECLK. When a breakpoint is generated, the event is synchronized with the trace capture clock signal TRACECLK, after which the trigger signal TRIG is held active for the duration of trace capture. The stop transmit signal STOPTX is asserted when the processor 104 has entered DEBUG mode and is ready for register interrogation/modification, memory or I/O reads and writes through the debug port 100. In the disclosed embodiment of the invention, the stop transmit signal STOPTX reflects the state of a bit in the debug control status register (DCSR). The stop transmit signal STOPTX is synchronous with the trace capture clock signal TRACECLK. The command acknowledge signal CMDACK is described in conjunction with FIG. 5, which shows simplified command passing in the enhanced debug port 100 of FIG. 2. Again, to place the target system T into DEBUG mode, a DEBUG instruction is written to the TAP controller 204 in step 502. Control proceeds to step 504 and the command acknowledge signal CMDACK is monitored by the host system H to determine command completion status. This signal is asserted high by the target system T simultaneously with the command finished flag and remains high until the next shift cycle begins. When using the command acknowledge signal CMDACK, it is not necessary to shift out the JTAG instruction register to capture the command finished flag status. The command acknowledge signal CMDACK transitions high on the next rising edge of the test clock signal TCK after the command finished flag has changed from zero to one. When using the enhanced JTAG signals, a new shift sequence (step 506) is not started by the host system H until the command acknowledge signal CMDACK pin ha s been asserted high. The command acknowledge signal CMDACK is synchronous with the test clock signal TCK. The test clock signal TCK need not be clocked at all times, but is ideally clocked continuously when waiting for a command acknowledge signal CMDACK response. Also included in debug register block 210 is an instruction trace configuration register (ITCR) shown in Table 2. This 32-bit register provides for the enabling/disabling and configuration of instruction trace debug functions. Numerous such functions are contemplated, including various levels of tracing, trace synchronization force counts, trace initialization, instruction tracing modes, clock divider ratio information, as well as additional functions shown in the following table. The ITCR is accessed through a JTAG instruction register write/read command as is the case with the other registers of the debug register block 210, or via a reserved instruction.
TABLE 2
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BIT SYMBOL DESCRIPTION/FUNCTION
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31:30
Reserved Reserved
29 RXINTEN Enables interrupt when RX bit is set
28 TXINTEN Enables interrupt when TX bit is set
27 TX Indicates that the target system T is ready
to transmit data to the host system H and
the data is available in the TX.sub.-- DATA register
26 RX Indicates that data has been received from
the host and placed in the RX.sub.-- DATA register
25 DISL1TR Disables level 1 tracing
24 DISL0TR Disables level 0 tracing
23 DISCSB Disables current segment base trace record
22:16
TSYNC{6:0} Sets the maximum number of Branch
Sequence trace records that may be output
by the trace control block 218 before a
synchronizing address record is forced
15 TSR3 Sets or clears trace mode on DR3 trap
14 TSR2 Sets or clears trace mode on DR2 trap
13 TSR1 Sets or clears trace mode on DR1 trap
12 TSR0 Sets or clears trace mode on DR0 trap
11 TRACE3 Enables Trace mode toggling using DR3
10 TRACE2 Enables Trace mode toggling using DR2
9 TRACE1 Enables Trace mode toggling using DR1
8 TRACE0 Enables Trace mode toggling using DR0
7 TRON Trace on/off
6:4 TCLK{2:0} Encoded divider ratio between internal
processor clock and TRACECLK
3 ITM Sets internal or external (bond-out)
instruction tracing mode
2 TINIT Trace initialization
1 TRIGEN Enables pulsing of external trigger
signal TRIG following receipt of any
legacy debug breakpoint; independent of the
Debug Trap Enable function in the DCSR
0 GTEN Global enable for instruction tracing
through the internal trace buffer or via
the external (bond-out) interface
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Another debug register, the debug control/status register (DCSR) shown in Table 3, provides an indication of when the processor 104 has entered debug mode and allows the processor 104 to be forced into DEBUG mode through the enhanced JTAG interface. As shown in the following table, the DCSR also enables miscellaneous control features, such as: forcing a ready signal to the processor 104, controlling memory access space for accesses initiated through the debug port, disabling cache flush on entry to the DEBUG mode, the TX and RX bits, the parallel port 214 enable, forced breaks, forced global reset, and other functions. The ordering or presence of the various bits in either the ITCR or DCSR is not considered critical to the operation of the invention.
TABLE 3
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BIT SYMBOL DESCRIPTION/FUNCTION
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31:12 Reserved Reserved
11 TX Indicates that the target system T is
ready to transmit data to the host system
H and the data is available in the
TX.sub.-- DATA register
10 RX Indicates that data has been received from
the host and placed in the
RX.sub.-- DATA register
9 DISFLUSH Disables cache flush on entry to DEBUG mode
8 SMMSP Controls memory access space
(normal memory space/system
management mode memory) for
accesses initiated through the Debug Port 100
7 STOP Indicates whether the processor 104 is in
DEBUG mode (equivalent to stop transmit
signal STOPTX
6 FRCRDY Forces the ready signal RDY to the processor
104 to be pulsed for one processor clock;
useful when it is apparent that the processor
104 is stalled waiting for a ready signal
from a non-responding device
5 BRKMODE Selects the function of the break
request/trace capture signal BRTC (break
request or trace capture on/off)
4 DBTEN Enables entry to debug mode or toggle
trace mode enable on a trap/fault via
processor 104 registers DR0-DR7 or
other legacy debug trap/fault mechanisms
3 PARENB Enables parallel port 214
2 DSPC Disables stopping of internal processor
clocks in the Halt and Stop Grant states
1 FBRK Forces processor 104 into DEBUG mode at
the next instruction boundary (equivalent
to pulsing the external BRTC pin)
0 FRESET Forces global reset
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When in cross debug environment such as that of FIG. 1, it is necessary for the parent task running on the target system T to send information to the host platform H controlling it. This data may consist, for example, of a character stream from a printf() call or register information from a Task's Control Block (TCB). One contemplated method for transferring the data is for the operating system to place the data in a known region, then via a trap instruction, cause DEBUG mode to be entered. Via debug port 100 commands, the host system H can then determine the reason that DEBUG mode was entered, and respond by retrieving the data from the reserved region. However, while the processor 104 is in DEBUG mode, normal processor execution is stopped. As noted above, this is undesirable for many real-time systems. This situation is addressed according to the present invention by providing two debug registers in the debug port 100 for transmitting (TX.sub.-- DATA register) and receiving (RX.sub.-- DATA register) data. These registers can be accessed using the soft address and JTAG instruction register commands. As noted, after the host system H has written a debug instruction to the JTAG instruction register, the serial debug shifter 212 is coupled to the test data input signal TDI line and test data output signal TDO line. When the processor 104 executes code causing it to transmit data, it first tests a TX bit in the ITCR. If the TX bit is set to zero then the processor 104 executes a processor instruction (either a memory or I/O write) to transfer the data to the TX.sub.-- DATA register. The debug port 100 sets the TX bit in the DCSR and ITCR, indicating to the host system H that it is ready to transmit data. Also, the STOPTX pin is set high. After the host system H completes reading the transmit data from the TX.sub.-- DATA register, the TX bit is set to zero. A TXINTEN bit in the ITCR is then set to generate a signal to interrupt the processor 104. The interrupt is generated only when the TX bit in the ITCR transitions to zero. When the TXINTEN bit is not set, the processor 104 polls the ITCR to determine the status of the TX bit to further transmit data. When the host system H desires to send data, it first tests a RX bit in the ITCR. If the RX bit is set to zero, the host system H writes the data to the RX.sub.-- DATA register and the RX bit is set to one in both the DCSR and ITCR. A RXINT bit is then set in the ITCR to generate a signal to interrupt the processor 104. This interrupt is only generated when the RX in the ITCR transitions to one. When the RXINTEN bit is not set, the processor 104 polls the ITCR to verify the status of the RX bit. If the RX bit is set to one, the processor instruction is executed to read data from the RX.sub.-- DATA register. After the data is read by the processor 104 from the RX.sub.-- DATA register the RX bit is set to zero. The host system H continuously reads the ITCR to determine the status of the RX bit to further send data. This technique enables an operating system or application to communicate with the host system H without stopping processor 104 execution. Communication is conveniently achieved via the debug port 100 with minimal impact to on-chip application resources. In some cases it is necessary to disable system interrupts. This requires that the RX and TX bits be examined by the processor 100. In this situation, the communication link is driven in a polled mode. Some embedded systems require instruction trace to be examined while maintaining I/O and data processing operations. Without the use of a multi-tasking operating system, a bond-out version of the embedded processor device 102 may be preferable to provide the trace data, as examining the trace cache 200 via the debug port 100 requires the processor 104 to be stopped. In the disclosed embodiment of the invention, a parallel port 214 is also provided in an optional bond-out version of the embedded processor device 102 to provide parallel command and data access to the debug port 100. This interface provides a 16-bit data path that is multiplexed with the trace pad interface port 220. More specifically, the parallel port 214 provides a 16-bit wide bi-directional data bus (PDATA{15:0}), a 3-bit address bus (PADR{2:0}), a parallel debug port read/write select signal (PRW), a trace valid signal TV and an instruction trace record output clock TRACECLK (TC). Although not shared with the trace pad interface port 220, a parallel bus request/grant signal pair PBREQ/PBGNT (not shown) are also provided. The parallel port 214 is enabled by setting a bit in the DCSR. Serial communications via the debug port 100 are not disabled when the parallel port 214 is enabled. The bond out port is shown in Table 4. Some of the pins are exclusive to the parallel port, some are exclusive to the trace port and the remainder shared. When the port is selected as a debug port, the TCK is used to synchronize all data transactions. When the port is selected as a trace port, the TRACECLK is provided to synchronize the output data.
TABLE 4
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Resis- Sync
Name I/O tor Clock Description
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TRACECLK
Out- -- -- Instruction Trace record
put output clock
TV Out- PD TRACECLK
0 = Valid trace record,
put 1 = no trace record
This pin not shared with
parallel bus interface
PDATA Bidi PD TCK/ Parallel debug port data
[15:0] TRACECLK
path. Shared with pins
TBUS[15:0]
PADR Bidi PD TCK/ Parallel debug port address.
[2:0] TRACECLK
Shared with pins
TBUS[18:16]
PRW Bidi PD TCK/ Parallel debug port read/
TRACECLK
write select. Shared with
pin TBUS[19]
1 = Perform a parallel
read from the serial
debig register
0 = Perform a parallel
write to the serial
debug register
PBREQ Out- TCK 1 = Request Host to
put enable parallel bus
interface
0 = Request Host to
disable parallel bus
interface
This pin not shared
with trace bus interface
PBGNT Input PD TCK 1 = Host has enabled
parallel bus interface
0 = Host has disabled
parallel bus interface
This pin not shared
with trace bus interface
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The parallel port 214 provides for fast downloads/uploads to and from target system T memory. The parallel port 214 may be used for all debug communications with the target system T whenever the processor 104 is stopped. The serial debug signals (standard or enhanced) are used for debug access to the target system T when the processor 104 is executing instructions. In a similar manner to the JTAG standard, all inputs to the parallel port 214 are sampled on the rising edge of the test clock signal TCK, and all outputs are changed on the falling edge of the test clock signal TCK. In the disclosed embodiment, the parallel port 214 shares pins with the trace pad interface 220, requiring parallel commands to be initiated only while the processor 104 is stopped and the trace pad interface 220 is disconnected from the shared bus. The parallel bus request signal PBREQ and parallel bus grant signal PBGNT are provided to expedite multiplexing of the shared bus signals between the trace cache 200 and the parallel port 214. When the host interface to the parallel port 214 determines that the parallel bus request signal PBREQ is asserted, it begins driving the parallel port 214 signals and asserts the parallel bus grant signal PBGNT. When entering or leaving DEBUG mode with the parallel port 214 enabled, the parallel port 214 is used for the processor state save and restore cycles. The parallel bus request signal PBREQ is asserted immediately before the beginning of a save state sequence penultimate to entry of DEBUG mode. On the last restore state cycle, the parallel bus request signal PBREQ is deasserted after latching the write data. The parallel port 214 host interface responds to parallel bus request signal PBREQ deassertion by tri-stating its parallel port drivers and deasserting the parallel bus grant signal PBGNT. The parallel port 214 the n enables the debug trace port pin drivers, completes the last restore state cycle, asserts the command acknowledge signal CMDACK, and returns control of the interface to trace control logic 218. When communicating via the parallel port 214, the address pins PADR{2:0} are used for selection of the field of the JTAG instruction register, which is mapped to the 16-bit data bus PDATA{15:0} as shown in table 5:
TABLE 5
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PADR{2:0} Data Selection
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0 0 0 No selection (null operation)
0 0 1 4-bit command register; command driven on
PDATA{3:0}
0 1 0 High 16-bits of debug.sub.-- data
0 1 1 Low 16-bits of debug.sub.-- data
1 0 0-1 1 1 Reserved
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It is not necessary to update both halves of the debug.sub.-- data {31:0} register if only one of the halves is being used (e.g., on 8-bit I/O cycle data writes). The command pending flag is automatically set when performing a write operation to the four-bit command register, and is cleared when the command finished flag is asserted. The host system H can monitor the command acknowledge signal CMDACK to determine when the finished flag has been asserted. Use of the parallel port 214 provides full visibility of execution history, without requiring throttling of the processor core 104. The trace cache 200, if needed, can be configured for use as a buffer to the parallel port 214 to alleviate any bandwidth matching issues. OPERATING SYSTEM AND DEBUGGER INTEGRATION In the disclosed embodiment of the invention, the operation of all debug supporting features, including the trace cache 200, can be controlled through the debug port 100 or via processor instructions. These processor instructions may be from a monitor program, target hosted debugger, or conventional pod-wear. The debug port 100 performs data moves which are initiated by serial data port commands rather than processor instructions. Operation of the processor from conventional pod-space is very similar to operating in DEBUG mode from a monitor program. All debug operations can be controlled via processor instructions. It makes no difference whether these instructions come from pod-space or regular memory. This enables an operating system to be extended to include additional debug capabilities. Of course, via privileged system calls such a ptrace(), operating systems have long supported debuggers. However, the incorporation of an on-chip trace cache 200 now enables an operating system to offer instruction trace capability. The ability to trace is often considered essential in real-time applications. In a debug environment according to the present invention, it is possible to enhance an operating system to support limited trace without the incorporation of an "external" logic analyzer or in-circuit emulator. Examples of instructions used to support internal loading and retrieving of trace cache 200 contents include a load instruction trace cache record command LITCR and a store instruction trace cache record command SITCR. The command LITCR loads an indexed record in the trace cache 200, as specified by a trace cache pointer ITREC.PTR, with the contents of the EAX register of the processor core 104. The trace cache pointer ITREC.PTR is pre-incremented, such that the general operation of the command LITCR is as follows: ITREC.PTR<-ITREC.PTR+1; ITREC{ITREC.PTR}<-EAX. In the event that the instruction trace record (see description of trace record format below) is smaller that the EAX record, only a portion of the EAX register is utilized. Similarly, the store instruction trace cache record command SITCR is used to retrieve and store (in the EAX register) an indexed record from the trace cache 200. The contents of the ECX register of the processor core 104 are used as an offset that is added to the trace cache pointer ITREC.PTR to create an index into the trace cache 200. The ECX register is post-incremented while the trace cache pointer ITREC.PTR is unaffected, such that: EAX<-ITREC{ECX+ITREC.PTR}; ECX<-ECX+1. Numerous variations to the format of the LITCR and SITCR commands will be evident to those skilled art. Extending an operating system to support on-chip trace has certain advantages within the communications industry. It enables the system I/O and communication activity to be maintained while a task is being traced. Traditionally, the use of an in-circuit emulator has necessitated that the processor be stopped before the processor's state and trace can be examined , unlike ptrace(). This disrupts continuous support of I/O data processing. Additionally, the trace cache 200 is very useful when used with equipment in the field. If an unexpected system crash occurs, the trace cache 200 can be examined to observe the execution history leading up to the crash event. When used in portable systems or other environments in which power consumption is a concern, the trace cache 200 can be disabled as necessary via power management circuitry. In the disclosed embodiment of the invention, an instruction trace record is 20 bits wide and consists of two fields, TCODE (Trace Code) and TDATA (Trace Data). A valid bit V may also be included. The TCODE field is a code that identifies the type of data in the TDATA field. The TDATA field contains software trace information used for debug purposes. ##STR2## In one contemplated embodiment of the invention, the embedded processor device 102 reports eleven different trace codes as set forth in table 6:
TABLE 6
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TCODE #
TCODE Type TDATA
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0000 Missed Trace Not Valid
0001 Conditional Branch
Contains Branch Sequence
0010 Branch Target Contains Branch Target Address
0011 Previous Segment
Contains Previous Segment Base
Base Address and Attributes
0100 Current Segment Base
Contains Current Segment Base
Address and Attributes
0101 Interrupt Contains Vector Number of
Exception or Interrupt
0110 Trace Synchronization
Contains Address of Most
Recently Executed Instruction
0111 Multiple Trace
Contains 2nd or 3rd Record of Entry
With Multiple Records
1000 Trace Stop Contains Instruction Address Where
Trace Capture Was Stopped
1001 User Trace Contains User Specified Trace Data
1010 Performance Profile
Contains Performance Profiling Data
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The trace cache 200 is of limited storage capacity; thus a certain amount of "compression" in captured trace data is desirable. In capturing trace data, the following discussion assumes that an image of the program being traced is available to the host system H. If an address can be obtained from a program image (Object Module), then it is not provided in the trace data. Preferably, only instructions which disrupt the instruction flow are reported; and further, only those where the target address is in some way data dependent. For example, such "disrupting" events include call instructions or unconditional branch instructions in which the target address is provided from a data register or other memory location such as a stack. As indicated in the preceding table, other desired trace information includes: the target address of a trap or interrupt handler; the target address of a return instruction; a conditional branch instruction having a target address which is data register dependent (otherwise, all that is needed is a 1-bit trace indicating if the branch was taken or not); and, most frequently, addresses from procedure returns. Other information, such as task identifiers and trace capture stop/start information, can also be placed in the trace cache 200. The precise contents and nature of the trace records are not considered critical to the invention. FIG. 6A illustrates an exemplary format for reporting conditional branch events. In the disclosed embodiment of the invention, the outcome of up to 15 branch events can be grouped into a single trace entry. The 16-bit TDATA field (or "BFIELD") contains 1-bit branch outcome trace entries, and is labeled as a TCODE=0001 entry. The TDATA field is initially cleared except for the left most bit, which is set to 1. As each new conditional branch is encountered, a new one bit entry is added on the left and any other entries are shifted to the right by one bit. Using a 128 entry trace cache 200 allows 320 bytes of information to be stored. Assuming a branch frequency of one branch every six instructions, the disclosed trace cache 200 therefore provides an effective trace record of 1,536 instructions. This estimate does not take into account the occurrence of call, jump and return instructions. In the disclosed embodiment of the invention, the trace control logic 218 monitors instruction execution via processor interface logic 202. When a branch target address must be reported, information contained within a current conditional branch TDATA field is marked as complete by the trace control logic 218, even if 15 entries have not accumulated. As shown in FIG. 6B, the target address (in a processor-based device 102 using 32-bit addressing) is then recorded in a trace entry pair, with the first entry (TCODE=0010) providing the high 16-bits of the target address and the second entry (TCODE=0111) providing the low 16-bits of the target address. When a branch target address is provided for a conditional jump instruction, no 1-bit branch outcome trace entry appears for the reported branch. Referring now to FIG. 6C, it may be desirable to start and stop trace gathering during certain sections of program execution; for example, when a task context switch occurs. When trace capture is stopped, no trace entries are entered into the trace cache 200, nor do any appear on the bond-out pins of trace port 214. Different methods are contemplated for enabling and disabling trace capture. For example, an x86 command can be provided, or an existing x86 command can be utilized to toggle a bit in an I/O port location. Alternatively, on-chip breakpoint control registers (not shown) can be configured to indicate the addresses where trace capture should start/stop. When tracing is halted, a trace entry (TCODE=1000, TCODE=0111) recording the last trace address is placed in the trace stream. When tracing is resumed, a trace synchronization entry (TCODE=0110, TCODE=0111) containing the address of the currently executing instruction is generated. It may be important to account for segment changes that occur while tracing is stopped. This situation can be partially resolved by selecting an option to immediately follow a TCODE=1000 entry with a current segment base address entry (TCODE=0100, TCODE=0111), as shown in FIG. 6C. A configuration option is also desirable to enable a current segment base address entry at the end of a trace prior to entering Debug mode. By contrast, it may not be desirable to provide segment base information when the base has not changed, such as when an interrupt has occurred. Referring to FIG. 6D, following the occurrence of an asynchronous or synchronous event such as an interrupt or trap, a TCODE=0101 trace entry is generated to provide the address of the target interrupt handler. However, it is also desirable to record the address of the instruction which was interrupted by generating a trace synchronization (TCODE=0110) entry immediately prior to the interrupt entry, as well as the previous segment base address (TCODE=0011). The trace synchronization entry contains the address of the last instruction retired before the interrupt handler commences. FIG. 6E illustrates a trace entry used to report a change in segment parameters. When processing a trace stream in accordance with the invention, trace address values are combined with a segment base address to determine an instruction's linear address. The base address, as well as the default data operand size (32 or 16-bit mode), are subject to change. As a result, the TCODE=0011 and 0111 entries are configured to provide the information necessary to accurately reconstruct instruction flow. The TDATA field corresponding to a TCODE=0011 entry contains the high 16-bits of the previous segment base address, while the associated TCODE=0111 entry contains the low 15 or 4 bits (depending on whether the instruction is executed in real or protected mode). The TCODE=0111 entry also preferably includes bits indicating the current segment size (32-bit or 16-bit), the operating mode (real or protected), and a bit indicating whether paging is being utilized. Segment information generally relates to the previous segment, not a current (target) segment. Current segment information is obtained by stopping and examining the state of the processor core 104. There are circumstance when an application program or operating system may wish to add additional information into a trace stream. For this to occur, an x86 instruction is preferably provided which enables a 16-bit data value to be placed in the trace stream at a desired execution position. The instruction can be implemented as a move to I/O space, with the operand being provided by memory or a register. When the processor core 104 executes this instruction, the user specified trace entry is captured by the trace control logic 218 and placed in the trace cache 200. As shown in FIG. 6F, a TCODE=1001 entry is used for this purpose in the disclosed embodiment of the invention. This entry might provide, for example, a previous or current task identifier when a task switch occurs in a multi-tasking operating system. When executing typical software on a processor-based device 102 according to the disclosed embodiment of the invention, few trace entries contain address values. Most entries are of the TCODE=0001 format, in which a single bit indicates the result of a conditional operation. When examining a trace stream, however, data can only be studied in relation to a known program address. For example, starting with the oldest entry in the trace cache 200, all entries until an address entry are of little use. Algorithm synchronization typically begins from a trace entry providing a target address. The processor can provide trace synchronization information to ensure that address information for reconstructing instruction execution flow is provided in trace records with sufficient frequency. If the trace cache 200 contains no entries providing an address, then trace analysis cannot occur. This situation is rare, but possible. A trace record (or an indication in a trace record), is provided for instructions that change the program flow such as conditional branches. However, as previously discussed, target address information is not provided in the trace record for instructions such as conditional branches where the branch target address can be determined according to whether the branch was taken or not taken. In such cases, the trace record provides only an indication of whether the branch was taken. Address information is provided, however, for those instructions in which the target address is in some way data dependent and for other synchronizing events shown in Table 6. For this reason, a synchronization register TSYNC is provided to allow injection of synchronizing address information. In the disclosed embodiment, TSYNC contains 7 bits. If the synchronization register TSYNC is set to zero, then trace synchronization entries are not generated. ##STR3## The processor determines whether each trace record includes address information by, e.g., assuming all TCODES except for TCODE=1 are synchronizing events providing address information. Thus, in the described embodiment, each trace entry having a TCODE not equal to "1" causes a counter to be loaded to the value in the TSYNC register which allows the counter to count the desired maximum number of trace records generated before current program address information is provided. Thus, depending on if the counter is configured as an up counter or down counter, the counter is either loaded with zero or the maximum count, respectively. The counter counts each trace record produced which does not include address information. When the count of such trace records reaches the predetermined number; trace logic provides the current program address as a trace entry, thereby providing said trace synchronization information. FIG. 6G depicts an exemplary trace synchronization record. The first entry, with a TCODE=6, provides the most significant 16 bits of the extended instruction pointer (EIP) for the current instruction logical address. The next entry, TCODE=7, provides the least significant 16 bits. Referring to FIG. 7, in operation, a counter 701 is set to the value contained in the synchronization register TSYNC 703 whenever a synchronizing trace entry (e.g., containing a branch target address) is generated. Trace control logic 218 determines when a synchronizing trace entry is generated and provides load signal 705 whenever such addresses are generated. This can be summarized as follows. The counter is decremented by one for each TCODE=1, thus providing for a maximum number of consecutive conditional branch instructions. Thus, counter 701 is reloaded each time a target address is generated or other appropriate TCODE is generated indicating a synchronizing record has been provided. Counter 701 is decremented by one for trace entries not having an address. If the counter reaches zero, an indication 707 is asserted by counter 701 and provided to trace control 218. In response, trace control 218 causes a trace entry to be inserted with a code indicating that it is a synchronization entry (TCODE=0110) and a current program address. The current program address can be, e.g., the most recently retired instruction. In addition, when a synchronizing entry is recorded in the trace cache 200, it can also be provided to trace pins 220 to ensure sufficient availability of synchronizing trace data for full-function ICE equipment. Note that counter circuit 701 may be included in trace control logic 218. Trace entry information can also be expanded to include data relating to code coverage or execution performance. This information is useful, for example, for code testing and performance tuning. Even without these enhancements, it is desirable to enable the processor core 104 to access the trace cache 200. In the case of a microcontroller device, this feature can be accomplished by mapping the trace cache 200 within a portion of I/O or memory space. A more general approach involves including an instruction which supports moving trace cache 200 data into system memory. Thus, a processor-based device providing a flexible, high-performance solution for furnishing instruction trace information has been described. The processor-based device incorporates an instruction trace cache capable of providing trace information for reconstructing instruction execution flow on the processor without halting processor operation. Both serial and parallel communication channels are provided for communicating trace data to external devices. The disclosed on-chip instruction trace cache alleviates various of the bandwidth and clock synchronization problems that arise in many existing solutions, and also allows less expensive external capture hardware to be utilized. The foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details of the illustrated circuitry and construction and method of operation may be made without departing from the spirit of the invention.
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