Mini-programmable controller4282584Abstract A small, low-cost programmable controller is programmed with both bit-oriented and word oriented program instructions that are stored in a main memory. A microprocessor couples each program instruction to a respective interpreter routine of machine instructions stored in an interpreter memory. Bit-oriented program instructions with a common operation code but different bit-pointer codes are coupled to their own respective interpreter routines. The program instructions have operation codes and bit pointer codes that are assigned by a program panel, and are then translated by a translator PROM as they are coupled to an interpreter routine. Operand addresses are read through the translator PROM unchanged. Error-locating circuitry assists in detecting faulty chips in the main memory as the control program is executed. The hardware required to execute the control program is minimized, while the translator PROM allows the processor unit to be used with prior program panels. Claims We claim: Description BACKGROUND OF THE INVENTION
TABLE 1
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Bit-Oriented Instructions
MNEMONIC
OPERATION CODE BIT POINTER CODE
OPERAND ADDRESS
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XIC 1 1 0 1 0 b b b r r r s s s I/O
L/H
XIO 1 1 0 1 1 b b b r r r s s s I/O
L/H
OTU 1 1 1 0 0 b b b r r r s s s I/O
L/H
OTL 1 1 1 0 1 b b b r r r s s s I/O
L/H
OTE 1 1 1 1 0 b b b r r r s s s I/O
L/H
Instruction
Bit (Octal)
17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0
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As seen in Table 1, three bits associated with each operation code form a bit pointer code. Three bits in the operand address specify a rack number and three other bits in the operand address specify a slot number. One bit in the operand address identifies whether the slot address contains an input module or an output module and the last bit specifies whether the I/O address is the low byte or the high byte of a sixteen-bit slot. The operations performed by the bit-oriented instructions are briefly defined as follows: XIC Examine status bit closed or is the status bit in a logic high state? XIO Examine status bit open or is the status bit in a logic low state? OTU If condition is true, turn status bit off (low), and if condition is false do nothing. OTL If condition is true turn status bit on (high), and if false do nothing. If condition is true turn status bit on (high), and if conditions are false turn status bit off (low). The control macro-instructions include those summarized in Table 2 which follows.
TABLE 2
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Control Instructions
MNEMONIC
OPERATION CODE
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NOP 0 0 0 0 0 0 0 X X X X X X X X X
BND 1 1 0 0 0 0 0 0 X X X X X X X X
BST 1 1 0 0 1 0 0 0 X X X X X X X X
MCR 1 0 1 1 1 0 0 0 X X X X X X X X
ZCL 0 0 1 1 0 1 0 0 X X X X X X X X
END 0 0 1 0 0 1 0 0 X X X X X X X X
Instruction
Bit (Octal)
17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0
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Note:
X means "don't care.
It should be noticed that although these control instructions have a sixteen-bit operation code, only bits in the second or high byte determine the control operation. The operations performed by these control instructions are briefly defined as follows: NOP No operation. BND Branch end: terminates a Boolean subbranch. BST Branch start: opens a Boolean subbranch. MCR Master control relay: if decision is false, it forces all following rungs to be false until another MCR instruction produces a true decision. ZCL Zone control: if decision is false execution is turned off unitl another ZCL instruction is executed. END Signals end of control program and beginning of I/O scan routine. The word-oriented macro-instructions include those summarized in Table 3.
TABLE 3
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Word-Oriented Instructions
MNEMONIC
OPERATION CODE OPERAND ADDRESS
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TOF 0.1 0 0 0 0 1 0 0 0 c c c s s s*
P/A
L/H
TON 0.1 0 0 0 0 1 1 0 0 c c c s s s*
P/A
L/H
RTO 0.1 0 0 0 1 0 0 0 0 c c c s s s*
P/A
L/H
TOF 1.0 0 0 0 0 1 0 1 0 c c c s s s*
P/A
L/H
TON 1.0 0 0 0 0 1 1 1 0 c c c s s s*
P/A
L/H
RTO 1.0 0 0 0 1 0 0 1 0 c c c s s s*
P/A
L/H
CTD 0 0 0 1 0 1 1 0 c c c s s s*
P/A
L/H
CTU 0 0 0 1 0 1 0 0 c c c s s s*
P/A
L/H
RTR 0 0 1 0 0 0 1 0 c c c s s s*
P/A
L/H
CTR 0 0 1 0 0 0 0 0 c c c s s s*
P/A
L/H
LES 0 0 0 1 1 1 1 0 r r r s s s*
X L/H
EQU 0 0 0 1 1 1 0 0 r r r s s s*
X L/H
PUT 0 0 0 1 1 0 1 0 r r r s s s*
X L/H
GET 0 0 0 1 1 0 0 0 r r r s s s*
X L/H
IIN 0 0 1 1 0 1 1 0 r r r s s s*
X L/H
IOT 0 0 1 1 1 0 0 0 r r r s s s*
X L/H
ADD 0 0 1 0 0 1 1 0 r r r s s s*
X L/H
SUB 0 0 1 0 1 0 0 0 r r r s s s*
X L/H
MPY 0 0 1 0 1 0 1 0 r r r s s s*
X L/H
DIV 0 0 1 0 1 1 0 0 r r r s s s*
X L/H
Instruction
Bit (Octal)
17 16 15 14 13 12 11 10 7 6 5 4 3 2 1 0
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Note:
c c c timer or counter group,
s s s slot location,
P/A preset or accumulator value,
r r r rack group,
s s s* slot location in memory outside of physical rack range, and
L/H low byte or high byte,
X don't care.
The first group of word-oriented instructions in Table 3 are timer instructions, the second group are counter instructions, the third group are miscellaneous instructions, and the fourth group are arithmetic instructions. The operations performed by these word-oriented instructions are briefly defined as follows: TOF If conditions are true turn output on, otherwise, wait until time is out then turn output off. TON If conditions are true wait until time is out, then turn output on, otherwise, turn output off. RTO If conditions are true wait until time is out, then turn output on, otherwise, stop timer. CTD If the conditions are true reduce the count by one. CTU If the conditions are true increase the count by one. RTR If the conditions are true reset the timer. CTR If the conditions are true reset the counter. EQU Is the value stored in the microprocessor accumulator equal to the value stored on the selected memory line? LES Is the value stored in the microprocessor accumulator less than the value stored on the selected memory line? PUT If conditions are true write the number in the microprocessor accumulator in the selected memory line, otherwise, do nothing. GET Fetch the word on the selected memory line and store in the microprocessor accumulator. IIN If decision is true, input immediately. IOT If decision is true, output immediately. ADD If decision is true, add operands of two previous GET instructions and store result in memory. SUB If decision is true, subtract operands of two previous GET instructions, and store result in memory. MPY If decision is true, multiply operands of two previous GET instructions and store in two memory locations (two instructions). DIV If decision is true, divide operands of two previous GET instructions and store in two memory locations (two instructions). The microprocessor 36 must first fetch each macroinstruction before it can be executed. A FETCH routine, given in Table 4 below, is executed as a final portion of an interpreter routine for a current macro-instruction to obtain the next macro-instruction in the control program 44. During this routine the operation code and the operand address, if any, are loaded into certain internal registers in the microprocessor 36.
TABLE 4
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FETCH Routine
Instruction
Mnemonic Comment
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POP HL Get next instruction; store the operand
address in the L register; and store the
operation code in the H register.
LD E,L Load operand address (the low byte of the
control program instruction) into the E
register.
LD L,H Form the address in HL which specifies a
LD H,C location in the jump table 47 in the ROM 23.
JP (HL) Jump indirect via the jump table 47 in the
ROM 23 to a selected interpreter routine.
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The microprocessor 36 utilizes several internal registers in executing the fetch routine, these registers including: PC--a 16-bit program counter SP--a 16-bit stack pointer B&C--eight bit registers arranged as a pair D&E--eight bit registers arranged as a pair H&L--eight bit registers arranged as a pair The program counter PC stores the memory address of the current microprocessor instruction to be read from the interpreter PROM 45. While this instruction is being read from the interpreter PROM 45, the program counter PC is incremented to address the next line in the interpreter PROM 45. The stack pointer SP stores the memory address of the macro-instruction to be read from the RAM 40. It is initialized to point at the first instruction in the control program 44, and, as each sixteen-bit instruction is fetched, the stack pointer SP is incremented two counts to address the next control program instruction. The operation code that is fetched by the microprocessor 36 is, in fact, an address in the jump table 46 in the interpreter PROM 45. The jump table 46 given in Appendix A contains statements for jumping to an address of a first instruction in one of the interpreter routines 48 also given in Appendix A. The last portion of each interpreter routine includes the fetch routine as explained above. Where control program instructions are used to manipulate single bits of data, five bits of the operation code specify the operation such as XIC or XIO, and the other three bits form a bit pointer code. Thus, eight different interpreter routines are required for the XIC group of macro-instructions, i.e., XIC 0, XIC 1, XIC 2, XIC 3, XIC 4, XIC 5, XIC 6 and XIC 7. The interpreter routines match up with the bit selected by the bit pointer code. The interpreter routine for XIC 2 from Appendix A is reproduced in Table 5 below. This interpreter routine examines bit 2 of an input status byte in the I/O image table 42. Bit 2 in this instance represents the status of some relay contacts (not shown).
TABLE 5
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XIC 2 Interpreter Routine
Instruction Mnemonic
Comment
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LD A,(DE) Load operand in the A register.
BIT 2,A Test the specified bit.
JR NZ,FETCH Jump to fetch next macro-instruction
if bit 2 equals 1 (which represents
closed contacts).
RES O,B Reset rung status if bit 2 equals 0
(which represents open contacts).
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FETCH: (see Table 4 above.)
Still referring to FIG. 2, the control instructions in the RAM 40 have operation codes (and bit pointer codes) that cannot be mapped directly to the interpreter routines 48 in the interpreter PROM 45. Instead, the control program instructions 44 in the RAM 40 have operation codes and bit pointer codes that are assigned by the program panel 17, and which shall be referred to as untranslated (UNTRANS.) codes. This allows the program panel 17 to be used with other programmable controllers that recognize the untranslated codes. To relate the untranslated codes to operation codes and bit pointer codes recognized by the microprocessor 36, a translator PROM 56 is connected in the data bus 31. Besides the bypass branch 31a, the main data bus 31 is divided into a main branch 31b, an input branch 31c, and an output branch 31d, both of which stem from the main branch 31b, and both of which are connected by a two-way branch 31e to the RAM 40. A set of input buffers 47 are connected in the input branch 31c, and the translator PROM 56 is connected in the output branch 31d. The translator PROM 56 is a 512-line-by-8-bit mask-programmable read-only memory with nine address inputs, A.sub.8 -A.sub.0, and eight data outputs 58. Address lines All and A0 in the PI address bus 30 are connected through a NAND gate 59 to the most significant address input A.sub.8 on the translator PROM 56. The lower eight address inputs A.sub.7 -A.sub.0 of the PROM 56 are coupled to the RAM 40 through branch 31e of the data bus 31, while the eight data outputs 58 are coupled to the main branch 31b of the data bus 31. The translator PROM 56 is enabled through a translator enable line 60 coming from a RAM enable and parity checking circuit 61, so that data can be read from its outputs 58. Another enable line 62 connects this circuit 61 to an enable input on the input buffers 57. The input buffers 57 are enabled through this line 62, so that data can be written into the RAM 40. In the RAM 40 bit-oriented instructions and word-oriented instructions are each stored on two lines in memory, one line containing an operand address and a succeeding line containing an untranslated operation code, and an untranslated bit pointer code, if applicable. Control instructions have only an untranslated operation code. Where control program instructions have both an operand address and an operation code, the operand address is stored on an even-numbered line while the operation code is stored on an odd-numbered line in the RAM 40. In the translator PROM 56 the upper 256 lines contain all possible eight-bit operand addresses arranged is sequence so that a one-to-one mapping of data occurs when the upper half of the PROM 56 is addressed. The translated operation codes, which are recognized by this controller, are stored in the lower 256 lines. In the following Table 6 the untranslated codes for macro-instructions in Tables 1-3 are shown in hexadecimal notation with their translated equivalents, also in hexadecimal notation. Each untranslated code corresponds to the portion of a translator PROM address received at terminals A.sub.7 -A.sub.0, while each translated code is the data stored at that address in the lower half of the translator PROM 56. For bit-oriented instructions the bit pointer code and the operation code are translated together.
TABLE 6
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PROGRAM PROGRAM
PANEL PROCESSOR PANEL PROCESSOR
CODE CODE CODE CODE
MNEMONIC
(UNTRANS.)
(TRANS.)
MNEMONIC
(UNTRANS.)
(TRANS.)
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NOP 00-07 03 XIO 0 D8 69
TOF 0.1 08 06 1 D9 6C
TOF 1.0 0A 09 2 DA 6F
TON 0.1 0C 0C 3 DB 72
TON 1.0 0E 0F 4 DC 75
RTO 0.1 10 12 5 DD 78
RTO 1.0 12 15 6 DE 7B
CTU 14 18 7 DF 7E
CTD 16 1B OTL 0 E0 81
GET 18 1E 1 E1 84
PUT 1A 21 2 E2 87
EQU 1C 24 3 E3 8A
LES 1E 27 4 E4 8D
CTR 20 2A 5 E5 90
RTR 22 2D 6 E6 93
END 24 34 7 E7 96
ADD 26 C9 OTU 0 E8 99
SUB 28 CC 1 E9 9C
MPY 2A CF 2 EA 9F
DIV 2C D2 3 EB A2
MCR 42 4 EC A5
ZCL B8-BF 33 5 ED A8
BND C0-C7 45 6 EE AB
BST C8-CF 48 7 EF AE
XIC 0 D0 4B OTE 0 F0 B1
1 D1 4E 1 F1 B4
2 D2 51 2 F2 B7
3 D3 54 3 F3 BA
4 D4 57 4 F4 BD
5 D5 5A 5 F5 C0
6 D6 5D 6 F6 C3
7 D7 60 7 F7 C6
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When a logic low signal is transmitted on the All address line, a logic high signal is input to the address terminal A.sub.8 on the translator PROM, the upper 256 lines are addressed and a one-to-one mapping of data occurs. This allows untranslated program instructions and other data to be read during the panel interrupt service routine. When the All address line carries a logic high signal, the translator PROM 56 is switched to its translating mode of operation in which both translated and untranslated data are read as control program instructions are fetched. During the FETCH routine an operand address on an even-numbered line of the RAM 40 is loaded first. A logic low signal is generated on the A0 address line to apply a logic high at the A.sub.8 address terminal and to provide the one-to-one mapping of data for operand addresses. The address on the PI address bus 30 is then incremented to address an odd-numbered line of the RAM 40 to obtain an operation code. A logic low signal is applied to the A.sub.8 address terminal on the translator PROM 56 and a translated operation code is read from one of the lower 256 lines of the PROM 56 onto the PI data bus 31. The translated operation code is then used to couple the microprocessor 36 to one of the interpreter routines 48 as explained above. The microprocessor 36 is connected to the decoding circuit 53 to address locations in memory and to address other circuitry on the PI module 10. The PI microprocessor is connected to the decoding circuit 53 through the read and write control lines 51 and 52, a memory request (MREQ) line 65 and a refresh (RFSH) line 66. The microprocessor 36 is also connected to the decoding circuit 53 through lines A10-A15 of the address bus 30. Through these lines the microprocessor 36 generates the address signals to be decoded. For example, the interpreter PROM 45 is connected to the decoding circuit 53 through a four-line PROM enable bus 67. Data is read from the interpreter PROM 45 by generating an address in the PROM 45 on lines A0-A11 of the address bus 30. Lines A0-A9 actually specify the address, while lines A11 and A10 are decoded by the decoding circuit 53 to enable one of four 1 k byte memory chips (not shown) in the POM 45 through a line in the PROM enable bus 67. Similarly, the RAM 40 is addressed and enabled when signals on lines A10-A15 of the address bus 30 are decoded by the decoding circuit 53, and are coupled to the RAM 40 through the RAM enable and parity checking circuit 61. The A10 address line and a RAM enable line 68 coming from the decoding circuit 53 are connected to the RAM enable and parity checking circuit 61. Signals on these lines are further decoded and coupled through two chip select (CS1 and CS2 lines) 69 and 70 to the RAM 40. Through each chip select line 69 and 70, a 1K-by-9-bit block of the RAM is enabled for read and write operations. The RAM 40 is a 2K-by-9-bit memory that stores data in eight bits of each line and a parity bit in the ninth bit in each line. The stored parity is read out on a parity output line 71 connecting the RAM 40 and the parity checking circuit 61. The RAM enable and parity checking circuit 61 is connected to the data bus 31 to receive data read from the RAM 40, and it calculates the parity of this data and compares it to the stored parity received on the parity output line 71. When data is read into the RAM through the input buffers 57, the parity of the data is calculated, and then transmitted through a parity input line 72 to the proper location in the RAM 40. The RAM enable and parity checking circuit 61 is connected through a parity error (PE) line 73 and a parity error complement (PE) line 74 to a watchdog circuit 75 to signal a parity error. The watchdog circuit 75 responds to malfunctions in the operation of the PI module 10 by "timing out" and generating a nonmaskable interrupt (NMI) signal on an NMI line 76 connected to an input on the microprocessor 36. Either the timing out of the watchdog timer circuit 75 or a parity error will generate a nonmaskable interrupt. When the interrupt is generated, the microprocessor 36 executes an error routine. At the end of this routine, the watchdog circuit 75 is reset through a dog reset line 77 and a kickdog line 78 connecting the decoding circuit 53 to the watchdog circuit 75. During the execution of the error routine the microprocessor 36 reads the status of any errors through a watchdog status line 79 and an error status line 80. These lines connect the watchdog circuit 75 to inputs on the decoding circuit 53. The decoding circuit 53 includes a status port that can be addressed through lines A10-A15 of the PI address bus 30 to read the status of various circuits through lines D0-D7 of the PI data bus 31. Error signals are coupled through the PE line 73, the watchdog status line 78 and the error status line 80 to lines D5-D7, respectively, of the PI data bus 31. A single-pole, three-position mode switch 81 is also connected to the decoding circuit 57 through three inputs 82, so that its status can be read on lines D2-D4 of the PI data bus 31. The PI module 10 also includes four-bit and eight-bit parity error address latches 83 and 84 and an eight-bit parity error data latch 85. The four-bit address latch 83 has inputs connected to the lines A8-A10 of the PI address bus 30 and the eight-bit address latch 84 has inputs connected to lines A0-A7 of the PI data bus 31. Each of these latches 83-85 has a clock input connected to the PE line 73 coming from the RAM enable and parity checking circuit 61. When a parity error is signalled on the PE line 73, the address on the PI address bus 30 is clocked into the address latches 83 and 84. At the same time the data on the PI data bus 31 is clocked into the data latch 85. The outputs of the latches 83-85 are left unconnected, so that they can be read with test equipment by a maintenance person. The data in the latches 83-85 will provide the exact location in memory where the parity error originated. The RAM 40 is comprised of four 1,024.times.4-bit memory chips (not shown) and two 1,024.times.1-bit memory chips (not shown). Each pair of 4-bit wide chips stores 1 K bytes of data, and is associated with a 1-bit wide chip that stores the parity of the data. By knowning what signal was last present on the A10 address line, it can be determined which of the chip enable lines 69 and 70 was enabled when the parity error occurred. This will isolate a pair of the 1,024.times.4-bit memory chips as the source of the error. By reading the other ten address bits A0-A9, the line of the RAM in which the parity error occurred can be determined. Because each line in the RAM 40 has four bits stored on one chip, and four other bits stored on another chip, it is necessary to know the precise bit in which the parity error occurred. This is accomplished by reading the data in the data latch 85. The userthen has the option to reprogram and test the RAM chip involved, or replace it. The latches 83-85 are cleared when the watchdog circuit 75 and the RAM enable and parity checking circuits 61 are reset through the dog reset line 78. The reset signal is generated by the microprocessor 36 through the decoding circuit 53 and the dog reset line 78, which connects to R (reset) inputs on each of the latches 83-85. In place of the latches 83-85 described herein, the microprocessor 36 could also be programmed to save the address and data on the buses 30 and 31 in specified internal working registers. The location of the error could then be communicated to peripheral devices, such as the program panel 17. The decoding circuit 53, the RAM enable and parity checking 61, and the watchdog circuit 75, which have been generally described thus far, are shown in more detail in FIGS. 3-5. The components for these circuits are listed with the other components of FIG. 2 in Appendix B. As seen in FIG. 3, the decoding circuit 53 has a 2-line-to-4-line decoder 86 and a 3-line-to-8-line decoder 87 for decoding signals on lines A10-A15 of the PI address bus 30. Lines A10 and A11 connect to a "1" input and a "2" input on the 2-line-to-4-line decoder 86. This decoder 86 has outputs "0-3" that connect to four lines in the ROM enable bus 67. Lines A12-A14 connect to the "1," "2" and "4" inputs on the second decoder 87. The A15 address line, the MREQ line 65, and the RFSH line 66, connect to three enable inputs 88 on the decoder 87. Outputs "0-7" on the decoder 87 are connected to various enable lines, to enable various hardware circuits on the PI module 10 in response to signals on lines A10-A15. The "0" output is coupled with the read line 51 through an OR gate 89 to an enable input 90 on the 2-line-to-4-line decoder 86. The "2" output is connected to the RAM enable line 68. The "5" output is coupled with the write line through another OR gate 90 to the kickdog line 77, and the "5" output is also coupled with the read line 51 through another OR gate 91 to an enable input 92 on a set of buffers 93. The buffers 93 form a status port where data is coupled from the buffer inputs to lines D0-D7 of the PI data bus 31. The "6" output on the decoder 87 is connected to the USART enable line 54, and the "7" output on the decoder 87 is coupled with the write line 52 through another OR gate 94 to the dog reset line 78. It will be apparent to those skilled in the art that the various circuits on the PI module 10 reside at the following hexadecimal addresses: ROM 45-up to 1,000; RAM 40 (untranslated)-2,000 to 227FF; RAM 40 (translated)-2,800 to 2FFF; status port-5,000 (when read line 51 is active); kickdog line 77-5,000 (when write line 52 is active); program panel interface 50-6,000; and dog reset line 78-7,000. FIG. 3 also shows more particularly how the mode switch 81 and the error status lines 73, 79 and 80 are coupled through the buffers 93 to lines D2-D7 of the data bus 31. The mode switch 81 has a movable, grounded contact 95 that can be positioned to pull one of three lines, labeled LOAD, TEST and RUN, respectively, to a logic low level. When not pulled low by the grounded contact 95, the lines are pulled high through pull-up resistors 96-98 connecting the lines by a positive d-c voltage source 99. The LOAD, TEST and RUN lines are coupled through S-R type flip-flops 100-102, respectively, to buffer inputs 103-105, respectively. The Q outputs of the flip-flops 100-102 are coupled back through NOR gates 106-108 to an R (reset) input on each other pair of flip-flops 100-102 to assure that only one of the flip-flops 100-102 will be set at a given time. Thus, as seen in FIG. 3, the mode switch is in the TEST mode position to set flip-flop 102 and reset flip-flops 100 and 102. Referring to FIG. 4, the RAM enable and parity checking circuit 61 more particularly includes a 2-line-to-4-line decoder 109 having a "1" input connected to receive signals on the A10 address line, and having a "2" input that is grounded. The decoder 109 has its "0" and "1" outputs connected to the chip select line 69 and 70. The decoder 109 also has an enable input 110 connected to the RAM enable line 68. When the decoder 109 is enabled through the RAM enable line 68, signals on the A10 address line control the enabling of alternate 1K sections of the RAM 40. The RAM enable line 68 also connects to an enable input 111 on another 2-line-to-4-line decoder 112. The read line 51 is connected to a "1" input on this decoder 112, and the "2" input is grounded. A logic low signal on the read line 51 enables the translator PROM 56 (seen in FIG. 2) through the translator PROM enable line 60 connected to the "0" output of the decoder 112. A logic high signal on the read line 51 enables the input buffers 57 (also seen in FIG. 2) through the buffer enable line 62 connected to the "1" output of the decoder 111. The parity checking portion of the circuit 61 includes a parity generator 113 connected to branch 31e of the PI data bus 31. The parity output line 71 and the read line 51 are coupled to an input on the parity generator 113 through a NAND gate 114. When data is read from the RAM 40, a stored parity bit is received by the parity generator 113 and compared with the data received through branch 31e of the PI data bus 31. When data is written into the RAM 40, the parity generator 113 calculates the parity of the data and the calculated parity is written into the RAM 40 through the parity input line 72. When parity is compared by the parity generator 113, a logic signal is generated on a line connecting the parity generator 113 to a D input on a parity error flip-flop 115. When data read from the RAM 40 has faulty parity, a logic low signal is received at the D input of the flip-flop 115. If a positive-going clock pulse is then received at a clock input on the flip-flop 115 through the translator PROM enable line 60, the flip-flop 115 is reset and a parity error is signaled on the PE line 73 and the PE line 74. The dog reset line 78 connects to an S (set) input on this flip-flop 115, so that parity errors can be cleared. It can now be more fully appreciated how an address and data are clocked into the parity error latches 83-85 in FIG. 2 by a signal on the PE line 73. It can also be seen how those latches 83-85 are reset together with the parity error flip-flop 115 through the dog reset line 78. As seen in FIG. 5, the PE line 73 and the PE line 74 are also connected to the watchdog circuit 75. The main component of the watchdog circuit 75 is a multivibrator which is connected to an RC coupling circuit to form a monostable multivibrator 116. The monostable multivibrator 116 remains in an unstable state for a time period of approximately 70 milliseconds before returning to its stable state. The kickdog line 77 is connected to a dual input clock terminal on the multivibrator 116 and the dog reset line 78 is connected to an R (reset) input. The other clock input is pulled high through a resistor 117 by a positive d-c voltage source 118. A Q output on the multivibrator 116 is connected to the watchdog status line 79 and a Q output is connected through two inverters 119 and 120 to the ERR status line 80, and through yet an additional inverter 121 to the NMI line 76. In the watchdog circuit 75, one LED (light emitting diode) 122 is provided to indicate satisfactory operation of the PI module 10 while another LED 123 is provided as a fault indicator. The Q output is connected with the PE line 73 to a NAND gate 124 that has its output connected through the LED 122 and a pull-up resistor 125 to a positive d-c voltage source 126. When logic high signals are present on both the PE line 73 and the watch-dog status line 79, the LED 122 will be illuminated. The Q output is connected through an inverter 127, the other LED 123, and a pull-up resistor 128 to a positive d-c voltage source 129, to provide a visible signal when the watchdog timer 116 has "timed out." This occurs when the multivibrator 116 is reset, or when a parity error is indicated on the PE line 74. The PE line 74 is connected through an inverter 130 to perform a "wired OR" function with the line coming from the Q output through the inverter 119. When a logic high voltage signal is present at the Q output or on the PE line 74, a non-maskable interrupt signal will be generated. The second LED 123 will be illuminated and the error can be sensed on the ERR statusline 80. The watchdog timer 116 is reset through the dog reset line 78, but is not started until a signal is received through the kickdog line 77. If the timer 116 is reset, but not started through the kickdog line 77, and the PE line 81 is held low, an interrupt signal cannot be generated on the NMI line 76. Thus, the watchdog circuit 74 can be disabled. What has been disclosed is a mini-programmable controller that efficiently divides tasks between programmed and unprogrammed circuits to provide greater economy in the manufacture of such controllers. The translator PROM provides a means for converting untranslated codes used in a prior programmable controller to translated codes that are recognized by this controller. A Boolean processor is eliminated by assigning the functions of the Boolean processor to a microprocessor. The architecture of the PI module is such that these additional functions, including the interpretation of bit-oriented macro-instructions, do not cause an undue increase in the average processing time for the control program. Fault detection apparatus is included in the PI module to locate the exact source of parity errors which occur when data is coupled to and from the memory that stores the control program macro-instructions.
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Appendix A
INTERPRETER JUMP TABLE AND
BIT-ORIENTED MACRO-INSTRUCTIONS
Location Contents Instruction
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0000 C30001 JP PTO
0003 C31309 JP NOPY
0006 C3FB09 JP TOF01
0009 C3F609 JP TOF10
000C C39B09 JP TON01
000F C39609 JP TON10
0012 C3790A JP RTO01
0015 C3740A JP RTO10
0018 C3C50A JP CTU
001B C32B0B JP CTD
001E C32208 JP GET
0021 C33608 JP PUT
0024 C35408 JP EQL
0027 C37308 JP LES
002A C3A10A JP CTR
002D C3A10A JP CTR
0030 C30303 JP FLGOUT
0033 C3E408 JP ZCL
0036 00 NOP
0037 00 NOP
0038 FDCB00FE SET 7,(IY + 0)
003C C37A03 JP INTR
003F C35009 JP IDT
0042 C3CA08 JP MCR
0045 C3B408 JP BND
0048 C39708 JP BST
004B C39204 JP XIC0
004E C39E04 JP XIC1
0051 C3AA04 JP XIC2
0054 C3B604 JP XIC3
0057 C3C204 JP XIC4
005A C3CE04 JP XIC5
005D C3DA04 JP XIC6
0060 C3E604 JP XIC7
0063 C31809 JP I
0066 C36701 JP NMIR
0069 C3F204 JP XI00
006C C3FE04 JP XI01
006F C30A05 JP XI02
0072 C31605 JP XI03
0075 C32205 JP XI04
0078 C32E05 JP XI05
007B C33A05 JP XI06
007E C34605 JP XI07
0081 C35205 JP OTL0
0084 C36B05 JP OTL1
0087 C38405 JP OTL2
008A C39D05 JP OTL3
008D C3B605 JP OTL4
0090 C3CF05 JP OTL5
0093 C3E805 JP OTL6
0096 C30106 JP OTL7
0099 C31A06 JP OTU0
009C C33306 JP OTU1
009F C34C06 JP OTU2
00A2 C36506 JP OTU3
00A5 C37E06 JP OTU4
00A8 C39706 JP OTU5
00AB C3B006 JP OTU6
00AE C3C906 JP OTU7
00B1 C3E206 JP OTE0
00B4 C30A07 JP OTE1
00B7 C33207 JP OTE2
00BA C35A07 JP OTE3
00BD C38207 JP OTE4
00C0 C3AA07 JP OTE5
00C3 C3D207 JP OTE6
00C6 C3FA07 JP OTE7
00C9 C35E0B JP ADDD
00CC C38B0B JP SUBT
00CF C3CF0B JP MTY
00D2 C3DC0B JP DIV
00D5 C3E90B JP JUMP
00D8 C3F60B JP BYTE
00DB C3FB0B JP LIMIT
00DE C31309 JP NOPY
00E1 C31309 JP NOPY
00E4 C31309 JP NOPY
00E7 C31309 JP NOPY
00EA C31309 JP NOPY
00ED C31309 JP NOPY
00F0 C31309 JP NOPY
00F3 C31309 JP NOPY
00F6 C31309 JP NOPY
00F9 C31309 JP NOPY
00FC C31309 JP NOPY
00FF 76 HALT
______________________________________
Generalized XIC Macro-Instruction
For Bit N
Instruction Comment
______________________________________
XIC N :
LD A,(DE) Load operand in A.
BIT N,A Test the specified bit.
JR NZ,FETCH Do nothing if closed.
RES O,B Reset rung status if open.
FETCH :
POP HL L = operand address; H = op code.
LD E,L Low byte of operand address in E.
LD L,H Form address of
LD H,C jump statement in HL.
JP (HL) Jump via jump table.
______________________________________
Location Instruction Comment
______________________________________
0492 XIC 0 : LD A,(DE)
Location of first machine
: : instruction in XIC 0
: : macro-instruction.
049E XIC 1 : LD A,(DE)
: :
04AA XIC 2 : LD A,(DE)
: :
04B6 XIC 3 : LD A,(DE)
: :
04C2 XIC 4 : LD A,(DE)
: :
04CE XIC 5 : LD A,(DE)
: :
04DA XIC 6 : LD A,(DE)
: :
04E6 XIC 7 : LD A,(DE)
______________________________________
Generalized XIO Macro-Instruction
For Bit N
Instruction Comment
______________________________________
XIO N : LD A,(DE)
BIT N,A
JR Z,FETCH Do nothing if open.
RES O,B
FETCH : POP HL
LD E,L
LD L,H
LD H,C
JP (HL)
______________________________________
Location
Instruction Comment
______________________________________
04F2 XIO 0 : LD A,(DE)
First machine instruction
: : in XIO 0 macro-instruction.
04FE XIO 1 : LD A,(DE)
: :
050A XIO 2 : LD A,(DE)
: :
0516 XIO 3 : LD A,(DE)
: :
0522 XIO 4 : LD A,(DE)
: :
052E XIO 5 : LD A,(DE)
: :
053A XIO 6 : LD A,(DE)
: :
0546 XIO 7 : LD A,(DE)
______________________________________
Generalized OTL Macro-Instruction
For Bit N
Instruction Comment
______________________________________
OTL N : BIT 4,B Test master control relay.
JR Z:NEWFE If relay off, start new rung.
BIT O,B Test rung status.
JR Z:NEWFE If rung status is zero,
start new rung.
LD L,E Form operand address
LD H,D in HL.
SET N,(HL) Set bit N in HL.
NEWFE : DI Disable interrupts.
LD A,FO(H) Mask off rung status.
AND B Clear rung status.
LD B,A
SET O,B
EI Enable interrupt.
FETCH : POP HL L = operand address; H = op
code.
LD E,L Low byte of operand in E.
LD L,H Form address of
LD H,C jump statement in HL.
JP (HL) Jump via jump table.
______________________________________
Location Instruction Comment
______________________________________
0552 OTL 0 : BIT 4,B
Location of first machine
: : instruction in OTL 0
: : macro-instruction.
056B OTL 1 : BIT 4,B
: :
0584 OTL 2 : BIT 4,B
: :
059D OTL 3 : BIT 4,B
: :
05B6 OTL 4 : BIT 4,B
: :
05CF OTL 5 : BIT 4,B
: :
05E8 OTL 6 : BIT 4,B
: :
0601 OTL 7 : BIT 4,B
______________________________________
Generalized OTU Macro-Instruction
For Bit N
Instruction Comment
______________________________________
OTU N : BIT 4,B
JR Z,NEWFE
BIT O,B
JR Z,NEWFE
LD L,E
LD H,D
RES N,(HL) Reset bit N in HL.
NEWFE : DI
LD A,FO(H)
AND B
LD B,A
SET O,B
EI
FETCH : POP HL
LD E,L
LD L,H
LD H,C
JP (HL)
______________________________________
Location Instruction Comment
______________________________________
061A OTU 0 : BIT 4,B
Location of first
: : machine instruction in
: : OTU 0 macro-instruction.
0633 OTU 1 : BIT 4,B
: :
064C OTU 2 : BIT 4,B
: :
066F OTU 3 : BIT 4,B
: :
067E OTU 4 : BIT 4,B
: :
0697 OTU 5 : BIT 4,B
: :
06B0 OTU 6 : BIT 4,B
: :
06C9 OTU 7 : BIT 4,B
______________________________________
Generalized OTE Macro-Instruction
For Bit N
Instruction Comment
______________________________________
OTE N : LD L,E Form operand address
LD H,D in HL.
BIT 4,B
JR Z,RES
BIT O,B
JR Z,RES
SET N,(HL) Set bit N in HL.
NEWFE : DI
LD A,FO(H)
AND B
LD B,A
SET O,B
EI
FETCH : POP HL
LD E,L
LD L,H
LD H,C
JP (HL)
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