| 6260190 |
Unified compiler framework for control and data speculation with recovery code |
| Jul-10-2001 |
A method and system for scheduling computer instructions for execution as part of a compilation process in which an original computer program that defines a set of operations is compiled to produce an... |
| 6230317 |
Method and apparatus for software pipelining of nested loops |
| May-8-2001 |
A method for executing software pipelined executable code generated by compiling a set of unexecutable instructions having an inner loop and an outer loop is disclosed. Instructions are executed that perform... |
| 6192515 |
Method for software pipelining nested loops |
| Feb-20-2001 |
A method for software pipelining nested loops combines the inner and outer loops of the nested loop to form a merged loop. One or more operations from the outer loop are activated on selected passes through... |
| 6044222 |
System, method, and program product for loop instruction scheduling hardware lookahead |
| Mar-28-2000 |
Improved scheduling of instructions within a loop for execution by a computer system having hardware lookahead is provided. A dependence graph is constructed which contains all the nodes of a dependence... |
| 6038396 |
Compiling apparatus and method for a VLIW system computer and a recording medium for storing compile execution programs |
| Mar-14-2000 |
A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each... |
| 6026240 |
Method and apparatus for optimizing program loops containing omega-invariant statements |
| Feb-15-2000 |
Apparatus, methods, and computer program products are disclosed for optimizing programs containing single basic block natural loops with a determinable number of iterations. The invention optimizes, for... |
| 5950007 |
Method for compiling loops containing prefetch instructions that replaces one or more actual prefetches with one virtual prefetch prior to loop scheduling and unrolling |
| Sep-7-1999 |
Prefetch instructions having a function to move data to a cache memory from main memory are scheduled simultaneously with execution of other instructions. The prefetch instructions are scheduled by replacing,... |
| 5930510 |
Method and apparatus for an improved code optimizer for pipelined computers |
| Jul-27-1999 |
Apparatus, methods, systems and computer program products are disclosed to provide improved optimizations of single-basic-block-loops. These optimizations include improved scheduling of blocking instructions... |
| 5920724 |
Software pipelining a hyperblock loop |
| Jul-6-1999 |
An iterative software pipelining method promotes instructions of a program loop to previous loop iterations and then reschedules the instructions until either 1) the resultant schedule is optimal (i.e.,... |
| 5901318 |
Method and system for optimizing code |
| May-4-1999 |
An optimizing compiler for optimizing code in a computer system having a CPU and a memory. The code has a loop wherein the loop includes statements conditionally executed depending on the evaluation of... |
| 5894576 |
Method and apparatus for instruction scheduling to reduce negative effects of compensation code |
| Apr-13-1999 |
A method is described for scheduling an instruction of a computer program. The instruction is scheduled into an active block of the computer program if no compensation copy is necessary, or if any necessary... |
| 5887174 |
System, method, and program product for instruction scheduling in the presence of hardware lookahead accomplished by the rescheduling of idle slots |
| Mar-23-1999 |
Instructions are scheduled for execution by a processor having a lookahead buffer by identifying an idle slot in a first instruction schedule of a first basic block of instructions, and by rescheduling... |
| 5867711 |
Method and apparatus for time-reversed instruction scheduling with modulo constraints in an optimizing compiler |
| Feb-2-1999 |
Apparatus and methods are disclosed for performing time-reversed scheduling of a data dependency graph representing a target program instruction loop in an optimizing compiler. The instruction scheduling... |
| 5854934 |
Optimizing compiler having data cache prefetch spreading |
| Dec-29-1998 |
A method of scheduling prefetch instructions in a compiler is described that improves performance by minimizing the performance degradation due to dirty cache misses. The method determines the length N... |
| 5850551 |
Compiler and processor for processing loops at high speed |
| Dec-15-1998 |
A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before... |
| 5835776 |
Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions |
| Nov-10-1998 |
Apparatus and methods are disclosed for scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modern microprocessors have the ability to issue multiple... |
| 5822593 |
High-level loop fusion |
| Oct-13-1998 |
A processor is provided with a software program specifying an overall computation that includes operations. Each operation implies a set of subcomputations, without explicitly specifying a control structure... |
| 5819088 |
Method and apparatus for scheduling instructions for execution on a multi-issue architecture computer |
| Oct-6-1998 |
Improved parallelism in the generated schedules of basic blocks of a program being compiled is advantageously achieved by providing an improved scheduler to the code generator of a compiler targeting a... |
| 5809308 |
Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler |
| Sep-15-1998 |
Apparatus and methods are disclosed for determining a recurrence minimum iteration interval (rmii) vector for use in modulo scheduling target program instructions during the code optimization pass of an... |
| 5794029 |
Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor |
| Aug-11-1998 |
For certain classes of software pipelined loops, prologue and epilogue control is provided by loop control structures, rather than by predicated execution features of a VLIW architecture. For loops compatible... |
| 5704053 |
Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications |
| Dec-30-1997 |
A compiler that facilitates efficient insertion of explicit data prefetch instructions into loop structures within applications uses simple address expression analysis to determine data prefetching requirements.... |
| 5606698 |
Method for deriving optimal code schedule sequences from synchronous dataflow graphs |
| Feb-25-1997 |
A method is disclosed for deriving code schedule sequences for a target code generator from an input ordering of nodes and prime factors of their respective ordered invocation rates from an SDF graph representative... |
| 5522074 |
Vectorization system for vectorizing loop containing condition induction variables |
| May-28-1996 |
A vectorization system is constituted with a conditional induction variable detector portion, a conditional induction variable reference state analyzing portion and a conditional induction variable iteration... |
| 5491823 |
Loop scheduler |
| Feb-13-1996 |
A loop scheduler in a software compiler system for generating a schedule for executing in a target computer loops of instructions contained in a computer program is described. The loop scheduler operates... |
| 5317734 |
Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies |
| May-31-1994 |
A method of synchronizing the parallel processors of a multiple instruction stream multiprocessor employs a limited number of register channels, which may be re-used, for enforcing cross-stream data or... |
| 5230053 |
Processor scheduling method for iterative loops |
| Jul-20-1993 |
A compiling method is described whereby a source program written in a conventional high-language for execution by a serial architecture computer can be automatically converted to an object program for... |
