| 7028290 |
Method and apparatus for prioritizing software tests |
| Apr-11-2006 |
A computer system and method is provided for prioritizing software tests. Software tests are prioritized based on coverage indicators for the software tests and an indication of impacted areas of the software.... |
| 7013460 |
Specifying an invariant property (range of addresses) in the annotation in source code of the computer program |
| Mar-14-2006 |
Method and apparatus for verifying at runtime an invariant property of a data structure. In various example embodiments, code that verifies whether a runtime value of the data structure is consistent with... |
| 6993757 |
Method and apparatus for multi-versioning loops to facilitate modulo scheduling |
| Jan-31-2006 |
One embodiment of the present invention provides a system that facilitates multi-versioning loops to facilitate modulo scheduling. Upon receiving a computer program, the system analyzes the code to locate... |
| 6988266 |
Method of transforming variable loops into constant loops |
| Jan-17-2006 |
A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping... |
| 6976157 |
Circuits, systems and methods for performing branch predictions by selectively accessing bimodal and fetch-based history tables |
| Dec-13-2005 |
Branch prediction circuitry including a bimodal branch history table, a fetch-based branch history table and a selector table is provided. The local branch history table includes a plurality of entries... |
| 6952817 |
Generating hardware interfaces for designs specified in a high level language |
| Oct-4-2005 |
A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate... |
| 6938247 |
Small memory footprint system and method for separating applications within a single virtual machine |
| Aug-30-2005 |
A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more "original" classes. Only one copy of each original class is maintained,... |
| 6922826 |
Debugger impact reduction through breakpoint motion |
| Jul-26-2005 |
A first type of debugger impact reduction includes removing, from within a loop, an initial conditional breakpoint ("ICB"); extracting a first Boolean expression ("BE_1") therefrom; setting a special conditional... |
| 6922824 |
System and method for transforming object code |
| Jul-26-2005 |
A method comprising: converting bytecodes into a graph of jop objects to track where jump operations pointed before modification of the bytecodes; adjusting constant pool references from local to global... |
| 6912709 |
Mechanism to avoid explicit prologs in software pipelined do-while loops |
| Jun-28-2005 |
The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined... |
| 6901586 |
Safe language static variables initialization in a multitasking system |
| May-31-2005 |
A system and method are provided for thread-safe initialization of static variables in a multitasking system. In one embodiment, the static fields of a class may be "virtualized" such that each application... |
| 6895580 |
Expression reduction during compilation through routine cloning |
| May-17-2005 |
An apparatus, program product, and method utilize routine cloning to optimize the performance of a compiled computer program. Within a compiled representation of a computer program, an implementation of... |
| 6883166 |
Method and apparatus for performing correctness checks opportunistically |
| Apr-19-2005 |
A method and an apparatus that enable spare instruction slots within a code module to be utilized opportunistically for insertion of instructions associated with correctness check functions. The apparatus... |
| 6880074 |
In-line code suppression |
| Apr-12-2005 |
Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly... |
| 6871343 |
Central processing apparatus and a compile method |
| Mar-22-2005 |
Systems and methods are disclosed for generating a program executed by a central processing apparatus for assigning instructions of the program. The systems and methods may include dividing the program... |
| 6836882 |
Pipeline flattener for simplifying event detection during data processor debug operations |
| Dec-28-2004 |
Pipeline activity information associated with all stages of execution of an instruction in an instruction pipeline of a data processor is presented to an event detector in timewise aligned format. This... |
| 6832370 |
Data speculation within modulo scheduled loops |
| Dec-14-2004 |
Optimizing compiler performance by applying data speculation within modulo scheduled loops to achieve a higher degree of instruction-level parallelism. The compiler locates a schedule for specifying an... |
| 6772415 |
Loop optimization with mapping code on an architecture |
| Aug-3-2004 |
A loop transformation step, to be performed on code and improving data transfer and storage, while executing said transformed code on a parallel processor, is disclosed. Improval of the data locality and... |
| 6757892 |
Method for determining an optimal partitioning of data among several memories |
| Jun-29-2004 |
A method and system for optimizing variable locations within disparate storage elements in a target processing environment according to a least cost analysis based upon the number of times a variable is... |
| 6754893 |
Method for collapsing the prolog and epilog of software pipelined loops |
| Jun-22-2004 |
A method for reducing a code size of a software pipelined loop, the software pipelined loop having a kernel and an epilog. The method includes first evaluating a stage of the epilog. This includes selecting... |
| 6751792 |
Using value-expression graphs for data-flow optimizations |
| Jun-15-2004 |
A new method and apparatus for use in post compilation optimizers is presented. The present invention is based on the use of a new graphical representation of code in a linked program called an operands... |
| 6748590 |
Method for generating instruction sequences for integer multiplication |
| Jun-8-2004 |
The invention pertains to an improved method for generating ALU instruction sequences for performing integer multiplication. The invention analytically helps to find an optimal sequence of shift, add and... |
| 6738893 |
Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations |
| May-18-2004 |
A process for scheduling computer processor execution of operations in a plurality of instruction word formats including the steps of arranging commands into properly formatted instruction words beginning... |
| 6718541 |
Register economy heuristic for a cycle driven multiple issue instruction scheduler |
| Apr-6-2004 |
A method for scheduling operations utilized by an optimizing compiler to reduce register pressure on a target hardware platform assigns register economy priority (REP) values to each operation in a basic... |
| 6675380 |
Path speculating instruction scheduler |
| Jan-6-2004 |
Path speculating instruction scheduler. According to one embodiment of the present invention instructions are placed into a control flow graph having blocks of the instructions, the control flow graph... |
| 6671878 |
Modulo scheduling via binary search for minimum acceptable initiation interval method and apparatus |
| Dec-30-2003 |
Disclosed herein is an instruction set scheduling system for scheduling instruction sets in a pipelined processing system. In particular, the scheduling system includes a binary search technique for ascertaining... |
| 6658551 |
Method and apparatus for identifying splittable packets in a multithreaded VLIW processor |
| Dec-2-2003 |
A method and apparatus are disclosed for allocating functional units in a multithreaded very large instruction word (VLIW) processor. The present invention combines the techniques of conventional very... |
| 6654952 |
Region based optimizations using data dependence graphs |
| Nov-25-2003 |
Region based optimization may be accomplished by creating dependence graphs for each block and then incrementally computing a single dependence graph for the region. First dependence DAGs are created for... |
| 6651247 |
Method, apparatus, and product for optimizing compiler with rotating register assignment to modulo scheduled code in SSA form |
| Nov-18-2003 |
In a computer having rotating registers, a schedule-assigner for allocating the rotating registers. The scheduler-assigner includes a software-pipelined instruction scheduler that generates a first software-pipelined... |
| 6637026 |
Instruction reducing predicate copy |
| Oct-21-2003 |
When compiling software for a processor that supports predication, an alerting instruction can be inserted to alert a global register allocator to map particular virtual predicates into the same physical... |
| 6634024 |
Integration of data prefetching and modulo scheduling using postpass prefetch insertion |
| Oct-14-2003 |
The present invention integrates data prefetching into a modulo scheduling technique to provide for the generation of assembly code having improved performance. Modulo scheduling can produce optimal steady... |
| 6634023 |
Compile method, exception handling method and computer |
| Oct-14-2003 |
The present invention enables re-ordering of instructions to be executed while assuring a precise exception. In Java language, an optimization process of re-ordering instructions to be executed is performed... |
| 6615403 |
Compare speculation in software-pipelined loops |
| Sep-2-2003 |
The present invention provides a mechanism for implementing compare speculation in software pipelined loops. A data dependency graph (DDG) is generated for a loop that includes a control compare instruction,... |
| 6609249 |
Determining maximum number of live registers by recording relevant events of the execution of a computer program |
| Aug-19-2003 |
The present invention is a method and apparatus for compiler optimization that determines the maximum number of live computer registers, or pressure point. The present invention improves the productivity... |
| 6609248 |
Cross module representation of heterogeneous programs |
| Aug-19-2003 |
An output translator provides for cross module representations of components within a heterogeneous program by translating modifying a platform-neutral intermediate representation (IR) of the program into... |
| 6588009 |
Method and apparatus for compiling source code using symbolic execution |
| Jul-1-2003 |
A method and apparatus for optimizing the compilation of a computer program by exposing parallelism are disclosed. Information describing the operations in the program and their sequence is extracted and... |
| 6567976 |
Method for unrolling two-deep loops with convex bounds and imperfectly nested code, and for unrolling arbitrarily deep nests with constant bounds and imperfectly nested code |
| May-20-2003 |
A compiler for compiling source code whereby the compiled source code is optimized by performing outer loop unrolling (a generalization of "unroll and jam" on selected loop nests. The present invention... |
| 6567974 |
Small memory footprint system and method for separating applications within a single virtual machine |
| May-20-2003 |
A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more "original" classes. Only one copy of each original class is maintained,... |
| 6539543 |
Method and apparatus for compiling source code by flattening hierarchies |
| Mar-25-2003 |
A method and apparatus for optimizing the compilation of computer program by exposing parallelism are disclosed. The computer program contains steps which involve index expressions. The program also involves... |
| 6526573 |
Critical path optimization-optimizing branch operation insertion |
| Feb-25-2003 |
A compiler optimization method for optimizing a scheduled block of instructions inserts a conditional branch instruction in place of a merge instruction to select between alternative paths when a condition... |
| 6516462 |
Cache miss saving for speculation load operation |
| Feb-4-2003 |
Compiler optimization methods and systems for preventing delays associated with a speculative load operation on a data when the data is not in the data cache of a processor. A compiler optimizer analyzes... |
| 6507947 |
Programmatic synthesis of processor element arrays |
| Jan-14-2003 |
A programmatic method transforms a nested loop in a high level programming language into a set of parallel processes, each a single time loop, such that the parallel processes satisfy a specified design... |
| 6487715 |
Dynamic code motion optimization and path tracing |
| Nov-26-2002 |
A method of reordering instructions. Barrier instructions are determined. The method determines when a processor stall may occur, and hoists subsequent instructions to fill in the stall time. However,... |
| 6463580 |
Parallel processing utilizing highly correlated data values |
| Oct-8-2002 |
A speculative execution method decreases execution time. A key value and a correlated value are stored as a correlated data values pair. Upon matching a current value to the key value, the correlated value... |
| 6446258 |
Interactive instruction scheduling and block ordering |
| Sep-3-2002 |
In some embodiments, the invention includes a method of compiling instructions of a program. The method includes receiving instructions for code motion and controlling the code motion while interacting... |
| 6421826 |
Method and apparatus for performing prefetching at the function level |
| Jul-16-2002 |
One embodiment of the present invention provides a system for compiling source code into executable code that performs prefetching for memory operations within regions of code that tend to generate cache... |
| 6374403 |
Programmatic method for reducing cost of control in parallel processes |
| Apr-16-2002 |
A parallel compiler exploits temporal recursion to reduce the cost of control code generated in transforming a sequential nested loop program into a set of parallel processes mapped to an array of processors.... |
| 6341370 |
Integration of data prefetching and modulo scheduling using postpass prefetch insertion |
| Jan-22-2002 |
The present invention integrates data prefetching into a modulo scheduling technique to provide for the generation of assembly code having improved performance. Modulo scheduling can produce optimal steady... |
| 6301705 |
System and method for deferring exceptions generated during speculative execution |
| Oct-9-2001 |
The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative... |
| 6289443 |
Self-priming loop execution for loop prolog instruction |
| Sep-11-2001 |
A method of operating a multiple execution unit microprocessor in a software pipelined loop is disclosed. This method executes the loop body before the pipeline is fully initialized, thus replacing prolog... |
