| 7039905 |
Compiler device and computer-readable recording medium recorded with compiler program |
| May-2-2006 |
A compiler device and a computer-readable recording medium recorded with a compiler program, adapted to generate a code for performing a procedure call in a program, making use of a dynamically and thread-piece-wise... |
| 7000213 |
Method and apparatus for automatically generating hardware from algorithms described in MATLAB |
| Feb-14-2006 |
Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC... |
| 6993756 |
Optimization apparatus that decreases delays in pipeline processing of loop and computer-readable storage medium storing optimization program |
| Jan-31-2006 |
An optimization apparatus is capable of improving the execution efficiency of a loop that includes a loop carry dependency between consecutive iterations of the loop. For example, a value resulting from... |
| 6988266 |
Method of transforming variable loops into constant loops |
| Jan-17-2006 |
A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping... |
| 6986131 |
Method and apparatus for efficient code generation for modulo scheduled uncounted loops |
| Jan-10-2006 |
A method of efficient code generation for modulo scheduled uncounted loops includes: assigning a given stage predicate to each instruction in each stage, including assigning a given stage predicate to... |
| 6986130 |
Methods and apparatus for compiling computer programs using partial function inlining |
| Jan-10-2006 |
A method and system makes inlining decisions that are efficient for subprograms that have significantly varying execution times over a range of variables or execution paths. A subprogram of a computer... |
| 6968547 |
Dynamic trap table interposition for efficient collection of trap statistics |
| Nov-22-2005 |
A system and method for monitoring the performance of a computer system by dynamically interposing an instrumented trap table. A base address of a trap table, which may be contained in a trap base address... |
| 6964043 |
Method, apparatus, and system to optimize frequently executed code and to use compiler transformation and hardware support to handle infrequently executed code |
| Nov-8-2005 |
The present invention relates to a method, apparatus, and system to optimize frequently executed code and to use compiler transformation and hardware support to handle infrequently executed code. The method... |
| 6954927 |
Hardware supported software pipelined loop prologue optimization |
| Oct-11-2005 |
A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating an... |
| 6948160 |
System and method for loop unrolling in a dynamic compiler |
| Sep-20-2005 |
Provided is a method for performing loop-unrolling optimization during program execution. In one example, a method for loop optimization within a dynamic compiler system is disclosed. A computer program... |
| 6934935 |
Method and apparatus for accurate profiling of computer programs |
| Aug-23-2005 |
An object code expansion profiler equips a program for execution profiling by preprocessing the object code files of the program so as to add profiling monitoring code to the beginning of all or substantially... |
| 6928642 |
Code generation for mapping object fields within nested arrays |
| Aug-9-2005 |
A method and device for generating mapping source code to establish mapping connections between enterprise system nested array object fields and legacy system nested array object fields is disclosed. For... |
| 6912709 |
Mechanism to avoid explicit prologs in software pipelined do-while loops |
| Jun-28-2005 |
The present invention provides a mechanism that facilitates speculative execution of instructions within software-pipelined loops. In accordance with one embodiment of the invention, a software-pipelined... |
| 6842895 |
Single instruction for multiple loops |
| Jan-11-2005 |
Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple... |
| 6820250 |
Mechanism for software pipelining loop nests |
| Nov-16-2004 |
A method is provided for processing nested loops that include a modulo-scheduled inner loop within an outer loop. The nested loop is scheduled to execute the epilog stage of the inner loop for a given... |
| 6772414 |
Lifetime-sensitive mechanism and method for hoisting invariant computations out of loops in a computer program |
| Aug-3-2004 |
A mechanism and method for hoisting invariant computations from loops analyzes the lifetimes of fixed processor resources defined by an instruction, and determines whether a group of computations present... |
| 6757892 |
Method for determining an optimal partitioning of data among several memories |
| Jun-29-2004 |
A method and system for optimizing variable locations within disparate storage elements in a target processing environment according to a least cost analysis based upon the number of times a variable is... |
| 6748589 |
Method for increasing the speed of speculative execution |
| Jun-8-2004 |
A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions... |
| 6732354 |
Method, system and software for programming reconfigurable hardware |
| May-4-2004 |
The method, system and tangible medium storing computer readable software of the present invention, provide for program constructs, such as commands, declarations, variables, and statements, which have... |
| 6721943 |
Compile-time memory coalescing for dynamic arrays |
| Apr-13-2004 |
In general, the malloc-combining transformation optimization during compile-time of a source program engaged in dynamically constructing multi-dimensional arrays provides an effective method of improving... |
| 6683624 |
System and method for managing programming object visual representations participating in alternative execution paths |
| Jan-27-2004 |
A method and apparatus for depicting programming state of programming objects through a combination of associating semantic stat space with programming objects, updating semantic state through affiliated... |
| 6671878 |
Modulo scheduling via binary search for minimum acceptable initiation interval method and apparatus |
| Dec-30-2003 |
Disclosed herein is an instruction set scheduling system for scheduling instruction sets in a pipelined processing system. In particular, the scheduling system includes a binary search technique for ascertaining... |
| 6658471 |
Method and system for zero overhead software performance measurement instrumentation |
| Dec-2-2003 |
A method, system, and computer program product is presented for minimizing overhead that may be incurred by executing specialized code, such as debug code or instrumentation code for monitoring the performance... |
| 6651246 |
Loop allocation for optimizing compilers |
| Nov-18-2003 |
Loop allocation for optimizing compilers includes the generation of a program dependence graph for a source code segment. Control dependence graph representations of the nested loops, from innermost to... |
| 6637026 |
Instruction reducing predicate copy |
| Oct-21-2003 |
When compiling software for a processor that supports predication, an alerting instruction can be inserted to alert a global register allocator to map particular virtual predicates into the same physical... |
| 6634024 |
Integration of data prefetching and modulo scheduling using postpass prefetch insertion |
| Oct-14-2003 |
The present invention integrates data prefetching into a modulo scheduling technique to provide for the generation of assembly code having improved performance. Modulo scheduling can produce optimal steady... |
| 6571385 |
Early exit transformations for software pipelining |
| May-27-2003 |
The invention is directed to the transformation of software loops having early exit conditions, thereby allowing the loops to be more effectively converted to a single basic block for software pipelining.... |
| 6564372 |
Critical path optimization-unzipping |
| May-13-2003 |
A method and apparatus for optimizing scheduling of a block of program instructions to remove a condition resolving instruction from the critical path where the resolution of a condition controls the selection... |
| 6546550 |
Method to determine dynamic compilation time and to select bytecode execution mode |
| Apr-8-2003 |
To perform efficient execution of a bytecode by combining an interpreter and a compiler. At a time of a bytecode execution by an interpreter, if an instruction to be executed is a backward conditional... |
| 6539541 |
Method of constructing and unrolling speculatively counted loops |
| Mar-25-2003 |
A method of constructing and unrolling speculatively counted loops. The method of the present invention first locates a memory load instruction within the loop body of a loop. An advance load instruction... |
| 6484314 |
Exception handling method and system |
| Nov-19-2002 |
The present invention provides a method and a system for generating an exception handling instruction and for avoiding the execution of unnecessary instructions. More particularly, an internal opcode in... |
| 6477641 |
Method for translating between source and target code with heterogenous register sets |
| Nov-5-2002 |
An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The... |
| 6374403 |
Programmatic method for reducing cost of control in parallel processes |
| Apr-16-2002 |
A parallel compiler exploits temporal recursion to reduce the cost of control code generated in transforming a sequential nested loop program into a set of parallel processes mapped to an array of processors.... |
| 6292939 |
Method of reducing unnecessary barrier instructions |
| Sep-18-2001 |
Unnecessary barrier instructions are dynamically reduced in a parallel processing object program, program module or object code section to be parallel processed in a multiprocessor system by a compiler... |
| 6286135 |
Cost-sensitive SSA-based strength reduction algorithm for a machine with predication support and segmented addresses |
| Sep-4-2001 |
A compiler optimization algorithm that deals with aggressive strength reduction of integer machine instructions found in loops. The algorithm permits the strength reduction of such machine instructions... |
| 6282706 |
Cache optimization for programming loops |
| Aug-28-2001 |
A cache memory architecture 50, which may be, for example, a set associative cache memory, has a cache controller (52) with an internal register for storing the address of the active line currently latched... |
| 6282704 |
Method for analyzing array summary for loop including loop exit statement |
| Aug-28-2001 |
A method for analyzing an array summary to improve the accuracy of an array summary analysis of a loop containing a loop exit statement, thereby to improve applicability of array privatization. If a loop... |
| 6282702 |
Method and apparatus of translating and executing native code in a virtual machine environment |
| Aug-28-2001 |
A method and apparatus of translating and executing native code in a virtual machine environment. Debugging of a virtual machine implementation is made easier through binary translation of native code,... |
| 6279152 |
Apparatus and method for high-speed memory access |
| Aug-21-2001 |
When a processing unit of a vector computer detects an optimization directive line for optimizing a list accessing method during the compilation, an access method is automatically changed according to... |
| 6272676 |
Method and apparatus for finding loop-- lever parallelism in a pointer based application |
| Aug-7-2001 |
A method and apparatus for finding loop_level parallelism in a sequence of instructions. In one embodiment, the method includes the steps of determining if a variable which identifies a memory address... |
| 6269440 |
Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously |
| Jul-31-2001 |
An apparatus and method that speeds the processing of data vectors in a digital processor is disclosed. In accordance with the present invention, a vector zero overhead loop with parallel issue processes... |
| 6253373 |
Tracking loop entry and exit points in a compiler |
| Jun-26-2001 |
The inventive system and method separates the tracking of the loop entry and exit points and loop optimization information, from the generation of the instrumentation code at the loop entry and exit points.... |
| 6253371 |
Method for supporting parallelization of source program |
| Jun-26-2001 |
In order to generate a source program or an object code which can be executed in parallel efficiency by detecting an independent operation of a large grain size from a program which can not be analyzed... |
| 6088525 |
Loop profiling by instrumentation |
| Jul-11-2000 |
The inventive system and method prepares a loop within a section of program code for profiling by placing instrumentation slots into the section at particular points. Entry slots are inserted just prior... |
| 6074433 |
Optimization control apparatus and optimization control method for array descriptions |
| Jun-13-2000 |
In order to generate optimum codes for array descriptions having a new language specification, an optimization control apparatus or method for array description executes a function of determining a scope... |
| 6038396 |
Compiling apparatus and method for a VLIW system computer and a recording medium for storing compile execution programs |
| Mar-14-2000 |
A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each... |
| 6016399 |
Software pipelining a hyperblock loop |
| Jan-18-2000 |
An iterative software pipelining method promotes instructions of a program loop to previous loop iterations and then reschedules the instructions until either 1) the resultant schedule is optimal (i.e.,... |
| 5850551 |
Compiler and processor for processing loops at high speed |
| Dec-15-1998 |
A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before... |
| 5835776 |
Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions |
| Nov-10-1998 |
Apparatus and methods are disclosed for scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modern microprocessors have the ability to issue multiple... |
| 5809308 |
Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler |
| Sep-15-1998 |
Apparatus and methods are disclosed for determining a recurrence minimum iteration interval (rmii) vector for use in modulo scheduling target program instructions during the code optimization pass of an... |
