Method and apparatus for providing autoprobe features in a graphical data flow diagram

Abstract

An autoprobe feature which illustrates the data output of each node as data propagates through a data flow program. As each node in the diagram executes or fires, a routine is invoked which displays the resultant data on the block diagram. Thus, a user can select the autoprobe feature and visually see the data flow out each node as the block diagram executes. Thus, the user can immediately determine if one node is providing incorrect output.

Claims

I claim:

1. A computer-implemented method for improved debugging of a data flow diagram in a computer system including a video screen and means for creating a graphical data flow diagram, wherein the data flow diagram comprises a plurality of interconnected function icon, wherein the function icons perform operations in the graphical data flow diagram, the method comprising:

receiving a request to enable an autoprobe feature to display data associated with or produced by said icons in said data flow diagram;

beginning execution of said data flow diagram after said receiving said request to enable said autoprobe feature, wherein said request is a request to display data associated with all of said plurality of interconnected function icons;

executing said plurality of function icons after beginning execution, wherein each of said plurality of function icons generate data as said function icons are executed; and

automatically displaying on the screen data output from each of said plurality of function icons proximate to each of said plurality of function icons during said executing said plurality of function icons, wherein said displaying on the screen said data output from each of said plurality of function icons is performed in response to said autoprobe feature being enabled;

wherein said displaying on the screen said data output from each of said plurality of function icons proximate to said function icons is automatically performed for each of said plurality of function icons as said function icons are executed.

2. A computer-implemented method for improved debugging of a data flow diagram in a computer system including a video screen and means for creating a graphical data flow diagram, wherein the data flow diagram comprises a plurality of interconnected function icons and a first input terminal icon coupled to one or more of the plurality of interconnected function icons, wherein the function icons perform operations in the graphical data flow diagram, the method comprising:

receiving a request Go enable an autoprobe feature to display data associated with or produced by said icons in said data flow diagram;

beginning execution of said data flow diagram after said receiving said request to enable said autoprobe feature, wherein said request is a request to display data associated with all of said plurality of interconnected function icons;

automatically displaying on the screen input data to the first input terminal icon proximate to the first input terminal icon, wherein said displaying on the screen said input data to the first input terminal icon is automatically performed in response to said autoprobe feature being enabled;

executing said plurality of function icons after beginning execution, wherein each of said plurality of function icons generate data as said function icons are executed; and

automatically displaying on the screen data output from each of said plurality of function icons proximate to each of said plurality of function icons during said executing said plurality of function icons, wherein said displaying on the screen said data output from each of said plurality of function icons is performed in response to said autoprobe feature being enabled.

3. A computer-implemented method for improved debugging of a data flow diagram in a computer system including a video screen and means for creating a graphical data flow diagram, wherein the data flow diagram comprises a plurality of function icons and a plurality of wires connecting said plurality of function icons, wherein each of said plurality of wires is connected to an output of one of said plurality of interconnected function icons or is connected to an input of one of said plurality of interconnected function icons, and wherein the function icons perform operations in the graphical data flow diagram, the method comprising:

receiving a request to enable an autoprobe feature to display data associated with or produced by said icons in said data flow diagram;

beginning execution of said data flow diagram after said receiving said request to enable said autoprobe feature, wherein said request is a request to display data associated with all of said plurality of interconnected function icon;

executing said plurality of function icons are beginning execution, wherein each of said plurality of function icons generate data as said function icons are executed;

automatically displaying on the screen data output from each of said plurality of function icons proximate to each of said plurality of function icons during said executing said plurality of function icons, wherein said displaying on the screen said data output from each of said plurality of function icons is performed in response to said autoprobe feature being enabled; and

automatically displaying on the screen one or more objects propagating along said plurality of wires during said displaying on the screen data output from each of said plurality of function icons;

wherein said displaying on the screen said one or more objects propagating along said plurality of wires is performed for a respective wire as data is provided to one or more of said plurality of function icons connected by said respective wire.

4. The method of claim 3, wherein said displaying on the screen said one or more objects propagating along said plurality of wires comprises displaying on the screen one or more bubbles propagating along said plurality of wires.

5. A compute-implemented method for improved debugging of a data flow diagram in a computer system including a video screen and means for creating a graphical data flow diagram, wherein the data flow diagram comprises a first input terminal icon and a plurality of interconnected function icons, wherein the plurality of interconnected function icons include a first function icon including at least one input and at least one ouput, a first wire connected to the at least one input of the first function icon to provide data to the first function icon, a second function icon including at least one input and a least one output, a second wire connected to the at least one output of the first function icon and also connected to the at least one input of the second function icon to provide data from the first function icon to the second function icon, and a first input terminal icon connected to the first wire to provide data to the first function icon, the method comprising:

receiving a request to enable an autoprobe feature to display data associated with or produced by icons in said data flow diagram;

beginning execution of said data flow diagram after said receiving said request to enable said autoprobe feature;

automatically displaying on the screen input data to the first input terminal icon proximate to the first input terminal icon, wherein said displaying on the screen said input data to the first input terminal icon is automatically performed in response to said autoprobe feature being enabled;

the first function icon executing after said beginning execution, wherein the first function icon generates first data;

automatically displaying on the screen the first data output from the first function icon proximate to the first function icon after the first function icon executes, wherein said displaying on the screen said first data output from the first function icon is automatically performed in response to said autoprobe feature being enabled;

the second function icon executing after the first function icon executes, wherein the second function icon generates second data; and

automatically displaying on the screen the second data output from the second function icon proximate to the second function icon after the second function icon executes, wherein said displaying on the screen the second data output from the second function icon is automatically performed in response to said autoprobe feature being enabled.

6. A computer-implemented method for improved debugging of a data flow diagram in a computer system including a video screen and means for creating a graphical data flow diagram, wherein the data flow diagram comprises a plurality of interconnected function icons, wherein the plurality of interconnected function icons include a first function icon including a least one input and at least one output, a first wire connected to the at least one input of the first function icon to provide data to the first function icon, a second function icon including at least one input and at least one output, and a second wire connected to the at least one output of the first function icon and also connected to the at least one input of the second function icon to provide data from the first function icon to the second function icon, the method comprising:

receiving a request to enable an autoprobe feature to display data associated with or produced by icons in said data flow diagram;

beginning execution of said data flow diagram after said receiving said request to enable said autoprobe feature;

automatically displaying on the screen one or more objects propagating on said first wire;

the first function icon executing after said beginning execution, wherein the first function icon generates first data;

automatically displaying on the screen the first data output from the first function icon proximate to the first function icon after the first function icon executes, wherein said displaying on the screen said first data output from the first function icon is automatically performed in response to said autoprobe feature being enabled;

automatically displaying on the screen one or more objects propagating on said second wire;

the second function icon executing after the first function icon executes, wherein the second function icon generates second data; and

automatically displaying on the screen the second data output from the second function icon proximate to the second function icon after the second function icon executes, wherein said displaying on the screen the second data output from the second function icon is automatically performed in response to said autoprobe feature being enabled.

7. The method of claim 6, wherein said displaying on the screen one or more objects propagating on said first and second wires comprises displaying on the screen one or more bubbles propagating on said first and second wires.

8. A computer-implemented method for improved debugging of a data flow program in a computer system including a video screen and means for displaying images to control data flow operations, the method comprising:

displaying on the screen a first input terminal icon that references a first input variable;

displaying on the screen a first output terminal icon that references a first output variable;

displaying on the screen a plurality of function icons that each perform respective functions;

assembling on the screen a data flow diagram including said first input terminal icon coupled to one or more of said plurality of function icons, wherein said plurality of function icons are interconnected, and wherein one or more of said plurality of function icons are connected to said first output terminal icon, wherein the data flow diagram displays a first procedure for producing at least on value for the at least one first output terminal icon from at least one value for the at least one first input terminal icon,

receiving a request to enable an autoprobe function to display data associated with or produced by said icons in said data flow diagram;

beginning execution of said data flow diagram after said receiving said request to enable said autoprobe feature;

executing said plurality of function icons after beginning execution, wherein each of said plurality of function icons generates data as said function icons are executed; and

automatically displaying on the screen data output from each of said plurality of function icons proximate to each of said plurality of function icons during said executing said plurality of function icons, wherein said displaying on the screen said data output from each of said plurality of said function icons is automatically performed in response to said autoprobe feature being enabled;

wherein said displaying on the screen said data output from each of said plurality of function icons is automatically performed for each of said plurality of function icons as said function icons are executed.

9. The method of claim 8, further comprising:

automatically displaying on the screen input data to the first input terminal icon proximate to the first input terminal icon after beginning execution and prior to said displaying on the screen data output from each of said plurality of function icons, wherein said displaying on the screen said input data to the first input terminal icon is automatically performed in response to said autoprobe feature being enabled.

10. The method of claim 8, wherein said data flow diagram includes a plurality of wires connecting said plurality of function icons, wherein each of said plurality of wires is connected to an output of one of said plurality of function icons or is connected to an input to one of said plurality of function icons, the method further comprising:

automatically displaying on the screen one or more objects propagating along said plurality of wires during said displaying on the screen the data output from each of said plurality of function icons;

wherein said displaying on the screen said one or more objects propagating along said plurality of wires is performed for a respective wire as data is provided between two or more of said plurality of function icons connected by said respective wire.

11. The method of claim 10, wherein said displaying on the screen said one or more objects propagating along said plurality of wires comprises displaying on the screen one or more bubbles propagating along said plurality of wires.

Description

RESERVATION OF COPYRIGHT

A portion of the disclosure of this patent document contains material to which a claim of copyright protection is made. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but reserves all other rights whatsoever.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to graphical systems for creating and executing data flow programs, and more specifically to a method and apparatus for providing autoprobe features in a graphical data flow diagram.

2. Description of the Related Art

A computer system can be envisioned as having a number of levels of complexity. Referring now to FIG. 1, the lowest level of a computer system may be referred to as the digital logic level. The digital logic level comprises the computer's true hardware, primarily consisting of gates which are integrated together to form various integrated circuits. Other hardware devices include printed circuit boards, the power supply, memory, and the various input/output devices, among others. Gates are digital elements having one or more digital inputs, signals representing 0 or 1 states, and which compute an output based on these inputs according to a simple function. Common examples of gates are AND gates, OR gates, etc. It is also noted that there is yet another level below level 0 which can be referred to as the device level. This level deals with the individual transistors and semiconductor physics necessary to construct the gates comprising the digital logic level.

The next level, referred to as level 1, is referred to as the microprogramming level. The microprogramming level is essentially a hybrid between computer hardware and software. The microprogramming level is typically implemented by software instructions stored in ROM (read only memory), these instructions being referred to as microcode. The microprogramming level can be thought of as including various interpreters comprised of sequences of microcode which carry out instructions available at the machine language level, which is at level 2. For example, when an instruction such as an arithmetic or shift function appears at the machine language level, this instruction is carried out one step at a time by an interpreter at the microprogramming level. Because the architecture of the microprogramming level is defined by hardware, it is a very difficult level in which to program. Timing considerations are frequently very important in programming at this level and thus usually only very skilled, experienced microprogrammers operate at this level.

As mentioned above, the level above the microprogramming level is referred to as the machine language level. The machine language level comprises the l's and 0's that a program uses to execute instructions and manipulate data. The next level above the machine language level is referred to as the assembly language level. This level includes the instruction set of the computer system, i.e. the various op codes, instruction formats, etc. that cause the computer to execute instructions. In assembly language each instruction produces exactly one machine language instruction. Thus, there is a one to one correspondence between assembly language instructions and machine language instructions. The primary difference is that assembly language uses very symbolic human-readable names and addresses instead of binary ones to allow easier programming. for example, where a machine language instruction might include the sequence "1001101," the assembly language equivalent might be "ADD." Therefore, assembly language is typically the lowest level language used by programmers, and assembly language programming requires a skilled and experienced programmer.

The next level includes high level text-based programming languages which are typically used by programmers in writing applications programs. Many different high level programming languages exist, including BASIC, C, FORTRAN, Pascal, COBOL, ADA, APL, etc. Programs written in these high level languages are translated to the machine language level by translators known as compilers. The high level programming languages in this level, as well as the assembly language level, are referred to in this disclosure as text-based programming environments.

Increasingly computers are required to be used and programmed by those who are not highly trained in computer programming techniques. When traditional text-based programming environments are used, the user's programming skills and ability to interact with the computer system often become a limiting factor in the achievement of optimal utilization of the computer system.

There are numerous subtle complexities which a user must master before he can efficiently program a computer system in a text-based environment. For example, text-based programming environments have traditionally used a number of programs to accomplish a given task. Each program in turn often comprises one or more subroutines. Software systems typically coordinate activity between multiple programs, and each program typically coordinates activity between multiple subroutines. However, in a text-based environment, techniques for coordinating multiple programs generally differ from techniques for coordinating multiple subroutines. Furthermore, since programs ordinarily can stand alone while subroutines usually cannot in a text-based environment, techniques for linking programs to a software system generally differ from techniques for linking subroutines to a program. Complexities such as these often make it difficult for a user who is not a specialist in computer programming to efficiently program a computer system in a text-based environment.

The task of programming a computer system to model a process often is further complicated by the fact that a sequence of mathematical formulas, mathematical steps or other procedures customarily used to conceptually model a process often does not closely correspond to the traditional text-based programming techniques used to program a computer system to model such a process. For example, a computer programmer typically develops a conceptual model for a physical system which can be partitioned into functional blocks, each of which corresponds to actual systems or subsystems. Computer systems, however, ordinarily do not actually compute in accordance with such conceptualized functional blocks. Instead, they often utilize calls to various subroutines and the retrieval of data from different memory storage locations to implement a procedure which could be conceptualized by a user in terms of a functional block. In other words, the requirement that a user program in a text-based programming environment places a level of abstraction between the user's conceptualization of the solution and the implementation of a method that accomplishes this solution in a computer program. Thus, a user often must substantially master different skills in order to both conceptually model a system and then to program a computer to model that system. Since a user often is not fully proficient in techniques for programming a computer system in a text-based environment to implement his model, the efficiency with which the computer system can be utilized to perform such modeling often is reduced.

One particular field in which computer systems are employed to model physical systems is the field of instrumentation. An instrument is a device which collects information from an environment and displays this information to a user. Examples of various types of instruments include oscilloscopes, digital multimeters, pressure sensors, etc. Types of information which might be collected by respective instruments include: voltage, resistance, distance, velocity, pressure, frequency of oscillation, humidity or temperature, among others. An instrumentation system ordinarily controls its constituent instruments from which it acquires data which it analyzes, stores and presents to a user of the system. Computer control of instrumentation has become increasingly desirable in view of the increasing complexity and variety of instruments available for use.

In the past, many instrumentation systems comprised individual instruments physically interconnected. Each instrument typically included a physical front panel with its own peculiar combination of indicators, knobs, or switches. A user generally had to understand and manipulate individual controls for each instrument and record readings from an array of indicators. Acquisition and analysis of data in such instrumentation systems was tedious and error prone. An incremental improvement in the manner in which a user interfaced with various instruments was made with the introduction of centralized control panels. In these improved systems, individual instruments were wired to a control panel, and the individual knobs, indicators or switches of each front panel were either preset or were selected to be presented on a common front panel.

A significant advance occurred with the introduction of computers to provide more flexible means for interfacing instruments with a user. In such computerized instrumentation systems the user interacted with a software program executing on the computer system through the video monitor rather than through a manually operated front panel. These earlier improved instrumentation systems provided significant performance efficiencies over earlier systems for linking and controlling test instruments.

However, these improved instrumentation systems had significant drawbacks. For example, due to the wide variety of possible testing situations and environments, and also the wide array of instruments available, it was often necessary for a user to develop a program to control the new instrumentation system desired. As discussed above, computer programs used to control such improved instrumentation systems had to be written in conventional text-based programming languages such as, for example, assembly language, C, FORTRAN, BASIC, or Pascal. Traditional users of instrumentation systems, however, often were not highly trained in programming techniques and, in addition, traditional text-based programming languages were not sufficiently intuitive to allow users to use these languages without training. Therefore, implementation of such systems frequently required the involvement of a programmer to write software for control and analysis of instrumentation data. Thus, development and maintenance of the software elements in these instrumentation systems often proved to be difficult.

U.S. Pat. No. 4,901,221 to Kodosky et al discloses a graphical system and method for modeling a process, i.e. a graphical programming environment which enables a user to easily and intuitively model a process. The graphical programming environment disclosed in Kodosky et al can be considered the highest and most intuitive way in which to interact with a computer. Referring now to FIG. 1A, a graphically based programming environment can be represented at level 5 above text-based high level programing languages such as C, Pascal, etc. The method disclosed in Kodosky et al allows a user to construct a diagram using a block diagram editor such that the diagram created graphically displays a procedure or method for accomplishing a certain result, such as manipulating one or more input variables to produce one or more output variables. As the user constructs the data flow diagram using the block diagram editor, machine language instructions are automatically constructed which characterize an execution procedure which corresponds to the displayed procedure. Therefore, a user can create a text-based computer program solely by using a graphically based programming environment. This graphically based programming environment may be used for creating virtual instrumentation systems and modeling processes as well as for any type of general programming.

In debugging a block diagram or graphical program, it is desirable to be able to view the block diagram in operation during the debugging process. It is well known in the art to provide a feature in a graphical data flow diagram wherein a bubble appears and propagates down the wires to mark the movement of data as the block diagram executes. This provides the user with an indication of where in the block diagram action is occurring at a particular moment. However, it would be highly desirable to have a more intuitive debugging feature provided for graphical data flow programs.

SUMMARY OF THE INVENTION

The present invention comprises an autoprobe feature which illustrates the data output of each node as data propagates through the data flow program. As each node in the diagram executes or fires, a routine is invoked which displays the resultant data on the block diagram. Thus, a user can select the autoprobe feature and visually see the data flow out each node as the block diagram executes. Thus, the user can immediately determine if one node is providing incorrect output. This provides a more useful debugging tool than that previously known in the art.

BRIEF DESCRIPTION OF THE DRAWINGS

The purpose and advantages of the present invention will be apparent to those skilled in the art from the following detailed description in conjunction with the appended drawings in which:

FIG. 1 illustrates various levels of complexity in a computer system according to the prior art;

FIG. 1A illustrates the various levels of complexity of a computer system including a graphical programming environment as the highest level;

FIG. 2 is a block diagram illustrating a system for modeling a process according to the present invention;

FIG. 3 is an illustrative drawing of a representation of a virtual instrument produced using the system of FIG. 2;

FIG. 4 shows a block diagram of an instrumentation system including the system of FIG. 2;

FIG. 5 is a representative drawing of various choices for an illustrative hardware instrumentation system of the preferred embodiment; embodiment;

FIG. 5A is an illustrative hardware instrumentation system of the preferred

FIG. 6 block diagram of the computer system of FIGS. 5 and 5A;

FIG. 7 shows a block diagram representing an exemplary data flow system;

FIG. 8A illustrates a virtual instrument data structure diagram used by the system of FIG. 2 and the instrumentation system of FIG. 4;

FIG. 8B shows a legend applicable to the illustration of FIG. 8A;

FIGS. 9A-L are flowchart diagrams illustrating operation of the execution subsystem of FIGS. 2 and 4;

FIG. 10 shows an illustrative front panel produced using the front panel editor of the instrumentation system of FIG. 4;

FIG. 11 shows an illustrative icon produced using the icon editor of the instrumentation system of FIG. 4;

FIG. 12A shows a graphical representation of a sequence structure;

FIG. 12B shows a graphical representation of an iterative loop structure;

FIG. 12C shows a graphical representation of a conditional structure;

FIG. 12D shows a graphical representation of an indefinite loop structure;

FIG. 12E shows a graphical representation of shift registers on the indefinite loop structure of FIG. 12D;

FIG. 13 shows an illustrative block diagram generally corresponding to the graphical representation of a sequence structure shown in FIG. 12A;

FIG. 14 shows an illustrative block diagram generally corresponding to the graphical representation of an iterative loop structure shown in FIG. 12B;

FIG. 15 shows an illustrative block diagram generally corresponding to the graphical representation of a conditional structure shown in FIG. 12C;

FIG. 16 shows an illustrative block diagram generally corresponding to the graphical representation of an indefinite loop structure shown in FIG. 12D;

FIG. 17 shows an illustrative block diagram generally corresponding to the graphical representation of an iterative loop structure including a shift register shown on the left in FIG. 12E;

FIG. 18 illustrates a type descriptor used to describe data structures;

FIGS. 19A-C illustrate computer video displays during each successive step in a construction of an exemplary block diagram using the block diagram editor of FIGS. 2 or 4;

FIGS. 20A-K illustrate a system representation corresponding to FIGS. 19A-D;

FIGS. 21A-B illustrate a system representation corresponding to FIGS. 19E and 19H;

FIG. 22 is a drawing representing a block diagram according to the present invention as displayed on a computer video monitor to model the illustrative hardware system of FIG. 5A;

FIG. 23 illustrates serial execution mode of a VI;

FIG. 24 illustrates "wait" icon execution:

FIG. 25 illustrates parallel execution mode for a VI;

FIG. 26 illustrates a ready node list, also referred to as the run queue;

FIG. 27 illustrates how nodes are placed on the run queue as they become ready and are interleaved with other nodes;

FIG. 28 illustrates parallel execution of nodes in a block diagram virtual instrument;

FIGS. 29-37 illustrate various virtual instrument execution states;

FIG. 38 illustrates an execution road map;

FIG. 39 illustrates execution state symbols;

FIGS. 40-41 illustrates virtual instruments in various execution states;

FIG. 42 illustrates an example of the front panel for a temperature VI;

FIG. 43 illustrates the block diagram for the temperature VI in FIG. 42;

FIG. 44 illustrates the icon and connector for the temperature VI in FIGS. 42 and 43;

FIGS. 45 and 46 illustrate the front panel and block diagram of a VI that uses the temperature VI,in FIGS. 42-44 as a subVI in its block diagram;

FIG. 47 illustrates a front panel and its associated block diagram;

FIG. 48 illustrates the run mode palette that appears at the top of the window when a VI is in run mode;

FIGS. 49A-D illustrate the run button and its associated icons;

FIGS. 50A-B illustrate the mode button in run mode and edit mode;

FIGS. 51A-B illustrate the icons associated with the continuous run button;

FIGS. 52A-B illustrate breakpoint button icons;

FIGS. 53A-C illustrate icons associated with the step mode button;

FIGS. 54A-B illustrate executing highlighting button icons;

FIGS. 55A-B illustrate print mode button icons;

FIGS. 56A-C illustrate data logging button icons;

FIGS. 57 illustrates the edit mode palette;

FIGS. 58A-B illustrate operating tool icons;

FIGS. 59A-C illustrate positioning tool icons;

FIGS. 60A-C illustrate labeling tool icons;

FIG. 61 illustrates the wiring tool;

FIGS. 62A-B illustrate the coloring tool;

FIG. 63 illustrates the menu bar in its active state;

FIG. 64 illustrates the file menu;

FIG. 65 illustrates the edit menu;

FIG. 66 illustrates the operate menu;

FIG. 67 illustrates the controls menu;

FIG. 68 illustrates the windows menu;

FIG. 69 illustrates the text menu;

FIG. 70 illustrates the menu bar when the diagram window is active;

FIG. 71 illustrates the functions menu;

FIG. 72 illustrates examples of numeric controls and indicators;

FIG. 73 illustrates examples of Boolean controls and indicators;

FIG. 74 illustrates how controls and indicators are configured;

FIG. 75 illustrates the panel window and diagram window of a VI illustrating nodes, terminals, and wires;

FIG. 76 illustrates icons grouped together into a lower level VI;

FIG. 77 and 78 illustrates a VI that adds three numbers together and returns their result;

FIG. 79 illustrates icons grouped together into a lower level VI;

FIG. 80 illustrates a VI that adds three numbers together and returns their results;

FIG. 81 illustrates activating the icon editor;

FIG. 82 illustrates the tools that may be used to create an icon design;

FIG. 83 illustrates the show connector function in the icon pane pop-up menu which may be used to define a connector;

FIG. 84 illustrates a front panel with the connector replacing the icon pane in the upper right corner of the panel window;

FIG. 85 illustrates the various choices for terminal patterns selected using the patterns option from the pop-up menu;

FIG. 86-88 illustrates how a user assigns front panel controls and indicators to the terminals using the wiring tool;

FIG. 89 illustrates the VI option which is used to place a VI as a subVI in the block diagram of another VI;

FIG. 90 illustrates the help window for a subVI icon;

FIG. 91 illustrates a While Loop selected from the Structs and Constants palette of the Functions menu;

FIG. 92 illustrates a while loop;

FIG. 93 illustrates an example of a while loop;

FIG. 94 illustrates a for loop;

FIG. 95 illustrates an example of a for loop;

FIG. 96 illustrates the grey dot created during numeric conversions;

FIG. 97 illustrates a shift register;

FIG. 98 illustrates the operation of a shift register;

FIG. 99 illustrates a shift register with additional terminals to access values from previous iterations;

FIG. 100 illustrates operation of initialized and uninitialized shift registers;

FIG. 101 illustrates selection of a case structure from the Structs and Constants palette of the Function Menu.

FIG. 102 illustrates a numerical case structure;

FIG. 103 illustrates a Boolean case structure;

FIG. 104 is an example of a Boolean case structure;

FIG. 105 illustrates a sequence structure selected from the Structs and Constants menu palette of the functions Menu;

FIG. 106 illustrates a sequence structure;

FIG. 107 illustrates an example of a three framed sequence structure using sequence locals;

FIG. 108 illustrates a formula node selected from the structs and constants palette of the functions menu;

FIG. 109 illustrates an equation implemented using arithmetic functions;

FIG. 110 illustrates the same equation implemented using a formula node;

FIG. 111 illustrates a waveform chart;

FIG. 112 illustrates the three update modes of a waveform chart, referred to as strip chart, scope chart, and sweep chart;

FIG. 113 illustrates how a scalar output is directly wired to a waveform chart;

FIG. 114 illustrates how a waveform chart accommodates more than one plot using the bundle function;

FIG. 115 illustrates an execution highlighting feature wherein movement of data is marked by bubbles moving along wires in a data flow diagram;

FIG. 116 illustrates use of the probe feature;

FIG. 117 illustrates a menu for selecting the autoprobe feature of the present invention; and

FIGS. 118-121 illustrate one example of the autoprobe feature according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following U.S. Patents are hereby incorporated by reference.

U.S. Pat. No. 4,901,221 titled "Graphical System for Modeling a Process and Associated Method," issued on Feb. 13, 1990.

U.S. Pat. No. 4,914,568 titled "Graphical System for Modeling a Process and Associated Method," issued on Apr. 3, 1990.

The following U.S. patent applications are hereby incorporated by reference.

U.S. patent application Ser. No. 07/380,329 filed Jul. 12, 1989 titled "Graphical Method for Programming a Virtual Instrument," now U.S. Pat. No. 5,301,336."

U.S. patent application Ser. No. 07/979,416 filed Nov. 19, 1992 titled "Graphical System for Executing a Process and for Programming a Computer to Execute a Process Including Graphical Variable Inputs And Variable Outputs", which is now U.S. Pat. No. 5,291,587.

U.S. patent application Ser. No. 07/647,785 titled "Polymorphic Data Flow Block Diagram System and Method for Programming a Computer" and filed Jan. 30, 1991which is now U.S. Pat. No. 5,301,301.

Referring now to FIG. 2, a system 28 for modeling a process or creating a data flow program is shown. The system 28 includes a respective block diagram editor 30, an execution subsystem 32, an icon editor 34, and a front panel editor 36 all interconnected. The system 28 also includes a control processor 38 which connects to each of the front panel editor 36, icon editor 34, block diagram editor 30 and execution subsystem 32. The system 28 can be used for a number of purposes. In the preferred embodiment, the system 28 is shown primarily in creating "virtual instruments" (VIs), which are instruments created in software. However, the system 28 of the present invention has many other applications, including modeling a process or any other type of general programming.

As will be explained more fully below, the block diagram editor 30 is used to construct and display a graphical diagram, referred to as a block diagram, which visually displays a procedure by which a value for a input variable produces a value for one or more output variables. This procedure, together with the input and output variables, comprises a process model. Furthermore, as the user constructs the graphical diagram, the block diagram editor 30 constructs execution instructions which characterize an execution procedure which corresponds to the displayed procedure. In the preferred embodiment, the block diagram editor 30 constructs instructions in the machine language which execute the block diagram created by the user. The execution subsystem 32 assigns at least one value to the input variable and executes the execution instructions to produce a value for the output variable. In the preferred embodiment, the block diagram editor 30 and the execution subsystem 32 are constructed in software. The control processor 38 implements the block diagram editor 30 and the execution subsystem 32 of the preferred embodiment.

The system 28 permits a user to construct a virtual instrument (also referred to as a VI) 40 such as that represented in generalized form in the illustrative drawings of FIG. 3. The virtual instrument 40 includes a front panel 42 which permits interactive use of the virtual instrument 40 by a user. As will be explained more fully below, the front panel 42 permits graphical representation of input and output variables provided to the virtual instrument 40. The respective graphical representations on the front panel 42 for input and output variables are referred to as controls and indicators, respectively; although in some instances controls and indicators are referred to collectively as controls. The virtual instrument 40 also includes an icon 44 which permits use of the virtual instrument 40 as a subunit in other virtual instruments (not shown). The virtual instrument 40 also includes a block diagram 46 which graphically provides a visual representation of a procedure or method by which a specified value for an input variable displayed in the front panel 42 can produce a corresponding value for an output variable in the front panel 42. In other words, the user uses the block diagram editor 30 to create a graphical program, and the resultant graphical icons appear in the block diagram 46. The virtual instrument 40 itself is a hierarchical construction which may comprise within its block diagram 46 respective icons 48 and 50 referencing other virtual instruments (sub-VIs) indicated generally by respective blocks 52 and 54. The block diagram 46 may also include one or more "primitives" corresponding to simple functions that may be performed. Together sub-VIs, primitives and other types of data processing elements comprised within the block diagram 46 are referred to as function icons. Function icons in the block diagram 46 have associated control means or software which implement the desired functions.

The generalized block diagram of FIG. 4 shows an instrumentation system 56 incorporating the system 28 shown in FIG. 2. Elements of the instrumentation system 56 which are substantially identical to those of second system 28 are designated with the same reference numerals as those of the system 28 for convenience. The instrumentation system 56 includes a keyboard and display 58 and an instrument 60. In a presently preferred embodiment, the control processor 38 and the keyboard and display 58 may be implemented using any type of general purpose computer.

The instrumentation system 56 is preferably used to control the instrument 60, i.e., acquire data from the instrument 60, analyze that data, store that data, and present that data to the user in a meaningful way. The block diagram editor 30 can also be used to create virtual instruments as desired.

FIG. 5 illustrates various design choices available in an instrumentation system 204 in the preferred embodiment. As shown, a computer system 206 programmed according to the present invention can interface with a unit under test 212, i.e., can perform data acquisition and control of the unit under test 212, using a number of methods. These methods include using GPIB instruments 12, plug-in data acquisition boards 19 with associated signal conditioning logic 11, or VXI instruments 14. In addition a serial RS-232 method (not shown) can be used, as desired. It is noted that the computer 206 may be any type of computer including any type of Apple computer, IBM PC-compatible computer, PS/2, Sun workstation, etc.

FIG. 5A shows an illustrative hardware configuration of an instrumentation system 204 according to the present invention. The system 204 includes a computer 206 which includes the control processor 38 as well as the front panel editor 36, icon editor 34, block diagram editor 30, and execution subsystem 32. As previously mentioned the elements 30-36 are preferably implemented in software. The computer 206 illustrated in FIG. 5 includes an interface to a GPIB (general purpose instrument bus) 207 which in turn is connected to a Tektronix 5010 Function generator 208 and a Fluke 8840A digital multimeter 210. A unit under test 212 is coupled between the function generator 208 and multimeter 210 as shown.

Referring ahead briefly to FIG. 22, a computer generated display of a completed block diagram for the instrumentation system 204 in FIG. 5A is shown. The block diagram in FIG. 22 is created by a user using the block diagram editor 30 of FIG. 2. As previously mentioned, the block diagram is essentially the graphical program representing the instrumentation system's operation and shows the interconnections between the elements of the instrument, the signal paths, and the relationship to other virtual instruments. Referring again to FIG. 5, a user uses the block diagram editor 30 to create the block diagram 46 in FIG. 22 to control the operation of the instrumentation system 204. Also, as discussed further below, the user uses the front panel editor 36 to create a front panel 42 to control the function or waveform generator 208 and multimeter 210. Once the block diagram 46 and front panel 42 have been created using the block diagram editor 30 and front panel editor 36, the user can then execute the block diagram (FIG. 22) using the execution subsystem 32. As discussed further below, the block diagram 46 can, for example, control the output of the waveform generator 208 to the unit under test 212 and can also be used to receive, analyze and present the output from the unit under test 212 which is provided from the multimeter 210.

It is also noted that other types of configurations for an instrumentation system 204 may be used. As discussed with regard to FIG. 5, instead of using actual instruments 208 and 210, the instrumentation system 204 may include one or more modular instruments on plug-in boards in conjunction with plug-i bus specification. The plug-in board instruments would then assume the function of the function generator 208 and multimeter 210. In addition, instead of requiring instruments 208 and 210 or plug-in modular instruments, the computer 206 can include a data acquisition card including A-D (analog to digital) and D-A (digital to analog) convertors, wherein the D-A convertor generates waveform signals to the unit under test 212 and the output from the unit under test 212 is then provided through an A-D convertor to the computer system 206.

Referring now to FIG. 6, a block diagram of the computer system 206 is shown. The elements of a computer system not necessary to understand the operation of the present invention have been omitted for simplicity. The computer system 206 includes a central processing unit or CPU 21 which is coupled to a processor or host bus 24. The CPU 21 acts as the control processor 38. The CPU may be any of various types, including an Intel x86 processor such as the i486, a CPU from the Motorola family of processors, as well as others. Main memory 22 is coupled to the host bus 24 by means of memory controller 23. The main memory 22 stores the front panel editor 36, icon editor :34, block diagram editor 30 and execution subsystem 32. Host bus 24 is coupled to an expansion or input/output bus 26 by means of a bus controller 25. The expansion bus 26 includes slots for various devices, including video 16 and hard drive 17. In one embodiment where the system and method of the present invention are used in an instrumentation application, a data acquisition card 19 is connected to the expansion bus 26. The data acquisition card 19 receives analog signals from an external sensor or instrument and in turn produces digital data that is provided to the CPU 21 and used by the system and method of the present invention. The computer system 206 also includes a GPIB (General Purpose Interface Bus) card 18 that interfaces to one or more instruments via the GPIB bus 15. The computer system 206 also includes an MXI card 10 that connects to VXI chassis 14.

The following discussion regarding data flow principles and a virtual instrument data structure diagram will assist in understanding the operation of the block diagram editor 30 and the execution subsystem 32 of the system 28 and the instrumentation system 56.

Referring now to FIG. 7, a block diagram 186 of an exemplary data flow system is shown. The block diagram 186 includes three respective input registers 188, 190 and 192 which provide an accumulation of input data. As soon as all input data are present, output of AND gate 194 becomes TRUE, and computation and/or control element 196 will begin computation. The computation element 196 begins generating output data which are stored in respective output registers 198, 200 and 202. When all output data are available, an output token is generated by the computation element 196 indicating that output data are available for transmission to a next system (not shown). It will be appreciated that the computation element 196 can be a combination of more than one subsystem (not shown).

FIG. 8A illustrates a virtual instrument data structure diagram. The system 2g of FIG. 2 and the instrumentation system 56 of FIG. 4 each utilize the principles set forth in the data structure diagram of FIG. 8A. It will be appreciated that implementation of a system utilizing a data structure such as that diagrammed in the diagram of FIG. 8A advantageously permits the implementation of an extended data flow system like that illustrated in FIG. 7.

Furthermore, it will be appreciated that implementation of the data structure like that of the diagram of FIG. 8A advantageously permits the implementation of a system in which execution instructions are constructed in a graphical fashion. More particularly, execution instructions are constructed by constructing a visual display or block diagram in which at least one input variable produces at least output variable according to a displayed procedure. Furthermore, the execution instructions are constructed such that, when a value is assigned to a particular input variable, a value for a corresponding output variable is produced according to the procedure illustrated in the visual display. Additionally, the execution instructions are constructed in response to the construction of a block diagram comprising the graphical display. Thus, a user need only construct an appropriate visual display or block diagram in order to construct the execution instructions.

Moreover, implementation of data flow principles by using a data structure such as that shown in the diagram of FIG. 8A advantageously permits the use of parallel processing which increases the speed with which the execution of execution instructions can be accomplished.

More particularly, FIG. 8A shows a system representation of a virtual instrument. Boxes 8a-8k, indicate conceptual objects in the system that have well-defined properties. Objects 8i, 8j, and 8k are grouped into shaded box 8s and share some properties and form a class of objects.

As indicated in FIG. 8B which represents a legend applicable to the illustration of FIG. 8A, a solid line with an arrow is used to indicate a potential one-to-many relationship, i.e., the source object contains zero or more destination objects (e.g., a vehicle containing zero or more wheels). A dashed line with an arrow is used to indicate a potential one-to-one relationship, i.e., the source object may reference zero or one destination object (e.g., a library book may or may not have a borrower).

Line 8n indicates that a virtual instrument 8b contains a front panel with a multiplicity of controls 8c. A control may be of clustered type in which case it contains a multiplicity of subcontrols as indicated by line 8p. Line 8q indicates that a virtual instrument contains an icon with a multiplicity of terminals 8d. Line 8l indicates that virtual instruments also contains a multiplicity of block diagrams Be.

In the system of the present invention, a virtual instrument either contains one diagram or none. Built in virtual instruments representing primitive computations (primitives) have no diagrams. Line 8r indicates that a block diagram contains a multiplicity of objects of the node class. A block diagram contains exactly one self reference node 8i, and an arbitrary number of structure nodes 8j or instrument use nodes 8k. Line 8t indicates that a structure node contains a multiplicity of subdiagrams.

As discussed below with regard to FIGS. 12A-D, a sequence structure or a conditional structure contains one or more subdiagrams, and an iterative loop structure or indefinite loop structure contains exactly one subdiagram. Line 8m indicates that an instrument use node (I-use node) is used to reference another virtual instrument. The instrument use node may reference a virtual instrument in real-time; or it may reference previous data acquired by the virtual instrument. Line 8u indicates that each object of the node class contains a multiplicity of terminals 8g. Line 8v indicates that a block diagram also contains a multiplicity of signal paths 8f. Each signal path contains a multiplicity of terminals as indicated by line 8w. There is at most one terminal per signal path that is designated as the source of the signal. Each terminal contained in a signal path also is contained in a node. However, there may be terminals in nodes which are not in signal paths. The terminals in a signal path are typically in different nodes. Lines 8y and 8z indicate that each terminal may reference a front panel control or a block diagram control (e.g., a constant). A terminal references exactly one control, and it is either on the front panel or on the block diagram.

Execution Subsystem Referring now to FIGS. 9A-L, a flowchart diagram illustrating the operation of the execution subsystem is shown. In FIG. 9A, the main execution loop of the block diagram execution subsystem is shown. At power on, in step 302 the execution subsystem 32 initializes the run queue. The run queue is the main queue in which all nodes are scheduled to be operated on by the execution subsystem 32. As discussed further below, the initial node is scheduled on the run queue by the execution subsystem 32, with all subsequent nodes in the block diagram being scheduled by preceding nodes in the data flow diagram. In step 304 the execution subsystem 32 relinquishes control to allow other graphical environment functions to be performed. For example, other functions include the front panel editor 36 which allows a user to create a front panel, the icon editor 34 which allows a user to create and edit icons, the block diagram editor 30 which allows a user to use the graphical programming environment to create programs, etc. These other functions at some point will invoke the execution subsystem 32. For example, when the user builds a block diagram and then clicks on the run arrow to execute the diagram, the execution subsystem 32 is invoked. When the execution subsystem 32 is invoked, the subsystem 32 checks the run queue to determine if anything has been placed on the queue. If nothing is placed on the run queue in step 306, then the execution subsystem 32 returns to step 304 and allows other systems to perform their functions until something is placed on the queue.

If a node is placed on the run queue in step 306, then the execution subsystem 32 advances to step 308 and de-queues the node having the highest priority. In step 310 the execution subsystem 32 executes the node. The node execution step includes executing all or a portion of a node and is discussed in much greater detail below. Upon completion of step 310, the execution subsystem 32 then advances to step 312 and determines whether the node has indicated a desire to be re-queued on the run queue. In general, if only a portion of the node was executed in step 310, the node will indicate in its return that it wishes to be replaced on the run queue to have its remaining portion executed. If the node has expressed a desire to be re-queued on the run queue in step 312, i.e. if the node has not been fully completed in step 310, then the execution subsystem 32 advances to step 314, re-enqueues the node on the run queue, and then returns back to step 304. If the node has completed in step 310 and thus the node has not indicated a desire to be re-placed on the run queue, the execution subsystem 32 returns from step 312 directly to step 304. In step 304 other parts of the graphical programming environment execute. When control returns to the execution subsystem 32, the execution subsystem 32 performs steps 306-314 as previously described.

Referring now to FIG. 9B, a flowchart diagram illustrating operation of step 310, the execute node step, in FIG. 9A is shown. In step 320, the execution subsystem performs node specific functions, i.e., specific functions for the particular type or node being executed. As discussed further below, a plurality of different types of nodes can be placed on the run queue, including a self reference node, an instrument use node, a simple node such as a primitive node or code interface node, a loop structure node, a case structure node, a sequence structure node, an asynchronous node, and a long computational node. The specific functions performed by the execution subsystem for respective nodes are discussed further below with regard to FIGS. 9C-9K. When the node-specific functions have been executed in step 320, the execution subsystem 32 determines in step 322 if execution of the node has completed. If not, the subsystem 32 returns to step 312 and determines if the node should be re-queued on the run queue. If the node has completed in step 322, the subsystem 32 advances to step 324. In step 324 the execution subsystem 32 determines if the node being executed has any outputs that need to be propagated. If the node has any outputs then a certain number of those output signals will need to be propagated to subsequent nodes in the data flow diagram. If no more output signals need to be propagated, the execution subsystem 32 sets the desire to be requeued for that respective node to false in step 325 and returns to step 312. Since the node was determined to have completed step 322 and has propagated all of its signals in step 324, the node has completed all operations, and thus its desire to be requeued is set to false.

If the node does include more output signals which need to be propagated, the execution subsystem 32 advances to step 326 and copies the data that was computed in step 320 to destination nodes, i.e., nodes which receive the outputs of the respective node being executed as inputs. The destination nodes are the respective nodes which the outputs of the node being executed are connected to. In step 328 the execution subsystem 32 decrements the destination node's short count, which is described below.

Each node includes two count numbers referred to as a fire count and a short count. Each node's fire count refers to the number of inputs received by that node. Prior to execution of the block diagram, the node's short count is set to the respective node's fire count. For example, if a node has three inputs, the node's fire count would be three, and prior to execution the node's short count would also be set to three. As various output signals are produced which are received as inputs to that respective node, the short count is decremented until all inputs to that node have been received. When the node's short count has reached zero, then all inputs to that node have been received. When this occurs the node is ready for execution and thus can be placed on the run queue. In other words, a node can only be placed on the run queue for execution when all of its inputs have been received, i.e. all nodes having outputs connected to the inputs of the respective node have executed and have propagated their signals to the respective node. Thus, in step 326 when data is copied to a destination node, one of the inputs to that destination node has received its required data and thus the destination node's short count is decremented.

In step 330 the execution subsystem 32 determines if the destination node's short count has reached zero. If that node's destination short count has reached zero, then that destination node is enqueued on the run queue in step 332. The execution subsystem 32 then returns to step 324 to determine if any more output signals need to be propagated. If the respective destination node's short count has not reached zero in step 330, then that destination node is not enqueued on the run queue, but rather the execution subsystem 32 returns to step 324. The subsystem 32 continues to execute steps 324-332 as long as any output signals need to be propagated from the respective node.

Node Specific Function Execution

Referring now to FIGS. 9C-K, the node-specific function executed in step 320 of FIG. 9B depend on the type of node being executed. As previously discussed, there are a plurality of different nodes that can be executed, including a self-reference node, loop structure node, case structure node, etc. Each type of node includes a plurality of different starting points where execution can begin in step 320, these starting points being referred to as 0 for the initial starting point or initial execution of the node and 1 for a later starting point of execution in the node. The exception to this is the long computational node which includes three starting points referred to as 0, 1, and 2.

Self Reference Node Execution

FIGS. 9C and 9D illustrate the steps performed if the node executed in step 320 is a self-reference node. In step 342, the execution subsystem 32 determines if this is the initial call to the 0 starting point of the self-reference node at the beginning of the respective diagram, or a call to the self-reference node at starting point 1 signifying the end of a diagram. Each VI, sub-VI, and loop diagram includes a self-reference node that is referenced when the diagram is entered to initialize the node and propagate signals to the node and also when the diagram is exited to place the node that called the self-reference node back on the run queue. In step 344 the execution subsystem 32 determines if the self-reference node being executed is a top level self-reference node, i.e., a self-reference node corresponding to a main block diagram. If not, the subsystem 32 advances to step 350. If so, the execution subsystem 32 advances to step 346 and determines if the self-reference node being executed was called as a sub-VI. If the self-reference node was determined to have been called as a sub-VI in step 346, then the execution subsystem 32 advances to step 348 and copies in the parameters from the instrument (I-use) node that called the self-reference node, referred to as the caller I-use node, which is at the head of the wait queue. The wait queue is described further below. The execution subsystem 32 then advances to step 350. If the self-reference node was not called as a sub-VI, the subsystem 32 advances directly to step 350.

In step 350 for each node comprised within the self-reference node's diagram, the execution subsystem 32 sets each node's short count to its fire count. In step 351 the execution subsystem 32 sets each node's starting point to its initial starting point, i.e. starting point 0. The subsystem 32 also sets the starting point of itself to its second starting point, starting point 1, in step 352. In step 353 the execution subsystem 32 sets node complete to true and returns to step 322. It is noted here that setting node complete to true where the node was entered at starting point 0 is different from all other nodes. With regard to all other nodes, node complete is set to true only at the last entry into the node. For a self-reference node, node complete is set to true in step 353 at starting point 0 of the node because it is necessary to propagate all signals to the nodes in the diagram associated with the self-reference node at the initial call to the self-reference node. With all other nodes, node complete is set to true after execution of the node, i.e., only after the last starting point of the node has been entered and the node has completed.

If the node-specific function is not an initial call to starting point 0 of the self-reference node in step 342, but rather enters at starting point 1, meaning the self-reference node is at the end of its respective diagram, then in step 354 the execution subsystem 32 again determines if the self-reference node corresponds to the diagram of a top level block diagram. If not, then the self-reference node corresponds to the diagram of a structure node such as a loop structure node, a case structure node, or a sequence structure node. The execution subsystem 32 advances to step 356 and enqueues the owning structure node of the self-reference node diagram on the run queue. The execution subsystem 32 then advances to step 364 and resets the self-reference node starting point to 0.

If the self-reference node does correspond to a top level diagram in step 354, then in step 358, the execution subsystem 32 determines if the caller I-use node is at the self-reference node wait queue head. Each self-reference node includes a wait queue where the I-use node corresponding to a call to the subVI is enqueued. This is for the situation where the self-reference node being executed corresponds to that of a sub-VI when it is called from an I-use node.

The wait queue is for the situation where a higher level VI (also referred to as a caller VI) includes one or more usages of a sub-VI, i.e. one or more instrument usage nodes (referred to as caller I-use nodes) for the same sub-VI. Where two or more usages of a sub-VI are comprised within a caller VI, it is imperative that only one usage of that sub-VI be executing at any one time (parallel or reentrant mode is discussed later). This is because each sub-VI includes its own block diagram having a corresponding self-reference node. Since there is only one self-reference node for the sub-VI (in serial node), only one version of that sub-VI can be running at any one time. Therefore, the execution subsystem must ensure that only one usage of a sub-VI executes from start to finish before another usage of the same sub-VI is initiated. In summary, since each sub-VI includes only one self-reference node in serial mode, only one usage of that sub-VI can execute at any one time, and thus the sub-VI includes a wait queue where calls to that sub-VI are placed to ensure that only one usage of the sub-VI is executing at any one

If the caller I-use node is not at the wait queue head in step 358, the execution subsystem 32 advances to step 364. If the caller I-use node is at the wait queue head, then the execution subsystem 32 advances to step 360 and copies out the parameters to the caller I-use node. The execution subsystem 32 then dequeues the caller I-use node from the self-reference node wait queue in step 361 and enqueues the caller I-use on the run queue in step 362. This completes a single usage of this VI as a subVI.

In step 364, the execution subsystem 32 resets the self-reference node starting point to starting point 0, i.e., the initial staring point. Thus, when the self-reference node is again called, it will be as if it were an initial self-reference node call in step 342. Upon completion of step 364, node complete is set to false in step 366, and the execution subsystem 32 determines if another instrument usage node is at the wait queue head in step 368. If not, then in step 370 the execution subsystem 32 sets the node wish to be requeued to false and returns to step 312. If another instrument usage node is determined to be at the wait queue head in step 368, then in step 372 the execution subsystem 32 sets the desire to be requeued to a true value and returns to step 312. In this instance, the diagram corresponding to the self-reference node has again been invoked, and thus the self-reference node needs to be requeued.

Instrument Use Node

An instrument use or usage node (I-use node) is used to call a sub-VI diagram, or more correctly is used to call the self-reference node of a sub-VI diagram. Referring now to FIG. 9E, a flowchart diagram illustrating operation of the instrument use node is shown. In step 382 the execution subsystem 32 determines if the I-use node is at starting point 0, i.e. this is the initial entry into the I-use node. If not, then in step 396 the execution subsystem 32 sets node complete to true. In this instance, this is the second call to the respective I-use node, i.e. the I-use node starting point is at 1. Thus node complete is set equal to true and the node completes. This will happen when the subVI has finished executing on behalf of this Instrument usage node.

If the I-use node is at its 0 starting point in step 382, then in step 384 the execution subsystem 32 sets the I-use node starting point to 1. This is done so that the next entry to this I-use node causes the decision in step 382 to be false. In step 386 the execution subsystem 32 queues the I-use node on the sub-VI diagram's self-reference node wait queue. This is a queue where the calling nodes wait their turn to run a respective sub-VI's top level diagram, i.e. a respective sub-VI. As previously noted, if multiple usages of the respective sub-VI or diagram appear in a caller top level block diagram, only one usage of the sub-VI or diagram can execute at any one time because each contains only self-reference node. Therefore, calling I-use nodes must wait their turn in the wait queue to be able to run a respective sub-VI.

In step 388, the execution subsystem 32 determines if the I-use node is at the head of the sub-VI self-reference node wait queue. If the I-use node is at the head of the self-reference node wait queue in step 388, then in step 390 it enqueues the sub-VI self-reference node on the node on the run queue. The execution subsystem then advances to step 392. If the I-use node is not at the head of the wait queue in step 388, then the execution subsystem 32 advances directly to step 392. (in this situation the subVI is already executing on behalf of another caller I-use node.)

In step 392, the execution subsystem sets node complete to false. Since this was the 0 starting point of the I-use node and the self-reference node was just placed on the run queue in step 390, node complete is set to false to enable the I-use node to be called again to complete operations at a later time when the subVI finishes executing on it's behalf. In step 394 the execution subsystem sets the desire to be requeued to false. In this situation, the sub-VI self-reference node has been placed on the run queue and is required to run before the instrument use node is again called at the end of the sub-VI self-reference node execution. Therefore, instead of setting the desire to requeue the I-use node to true, the sub-VI self-reference has the task of placing the I-use node on the run queue, which occurs in step 362 at FIG. 9D. The I-use node execution then completes.

Simple Node

Referring now to FIG. 9F, a flowchart diagram illustrating the execution of a simple node is shown. A simple node includes primitive nodes and code interface nodes. In step 398, the execution subsystem 32 performs the function indicated by the node. For example, if the node is a simple add or subtract node or an attribute node, bundle node, etc., the execution subsystem 32 performs the indicated operation. If the node being executed is a code interface node, then in step 398 the execution subsystem 32 invokes a text-based language routine previously credited by the user which performs a desired function. In step 399 the execution subsystem 32 sets node complete to true. Thus, when the execution subsystem 32 returns to step 322 in FIG. 9B, the node's output signals will be propagated in steps 324-332.

Loop Structure Node

A loop structure node corresponds to an iterative loop structure node or an indefinite loop structure node, which are discussed with reference to FIGS. 12B and 12D. Referring now to FIG. 9G, if the node being executed in step 310 is a loop structure node, then the following node specific functions are executed in step 320. In step 402 the execution subsystem 32 determines if it has begun execution at the loop node's 0 starting point, i.e. the loop node's initial starting point. If so, then in step 404 the execution subsystem 32 sets the loop node starting point to 1. In step 406 the subsystem 32 prepares a loop counter and in step 408 prepares auto-indexing for the loop. Auto-indexing is a feature of loop structure nodes wherein arrays are indexed or accumulated at the loop boundary automatically. In step 410 the execution subsystem 32 enqueues the self-reference node (SRN) of the subdiagram on the run queue. In step 412 the subsystem sets node complete to false and in step 414 sets the node's desire to be requeued to false. The node's desire to be requeued is set to false because the node places itself back on the run queue in step 424, as discussed below.

If execution of the loop begins at starting point 1 and hence this is not the loop's initial starting point in step 402, then in step 416 the subsystem increments the loop counter to index into the loop. The execution subsystem 32 progresses auto-indexing in step 417 and evaluates the reiteration in step 418. In step 420 the subsystem 32 determines if the loop will reiterate. If not, then the loop is done, i.e., the loop has finished iterating, and the subsystem sets node complete to true in step 422 and returns to step 322 (FIG. 9B). It finishes the auto-indexing feature in step 421. Here it is noted that the node complete question in step 322 will be answered in the affirmative and thus the subsystem will advance to step 324 and propagate signals. If the loop has not completed and thus further iterations are determined to be required in step 420, then in step 424 the subsystem 32 enqueues the subdiagram self-reference node on the run queue in step 420 and advances to step 412. In steps 412 and 414, node complete is set to false and the desire to be requeued is also set to false. The execution subsystem then returns to step 322 (FIG. 9B). Here it is noted that the node complete question in step 322 will be answered in the negative, and thus the subsystem will return back to step 312 (FIG. 9A).

Case Structure Node

A case structure node corresponds to the conditional structure illustrated in FIG. 12C. Referring now to FIG. 9H, if the node being executed in step 310 is a case structure, then the node specific functions performed in step 320 are as follows. In step 430 the execution subsystem 32 determines if the case node has been entered at its 0 starting point, i.e. if this is the initial entry into execution of the case node. If so, then in step 432 the execution subsystem sets the starting point of the case node to 1. Thus, the next time the case node is entered, the question in step 430 will be answered in the negative. In step 434 the execution subsystem 32 checks the select input to determine which of the N diagrams will run. In other words, since a case statement includes a number of possible cases, one of which will be executed depending upon the select input, the input must be checked to determine which of the N diagrams in the case statement will be executed. In step 436 the subsystem enqueues the selected subdiagram self-reference node on the run queue. In step 438, the execution subsystem sets node complete to false and in step 440 sets the desire to be requeued to false. Execution then completes. If the case node starting point is determined to be 1 in step 430, then in step 441 the execution subsystem sets node complete to true and then completes.

Sequence Structure Node

A sequence structure node corresponds to the sequence structure illustrated in FIG. 12A. Referring now to FIG. 9I, if the node executed in step 310 is a sequence structure node, then the following node specific functions are executed in step 320. In step 442, the subsystem determines if this is the initial starting point (starting point 0) for the sequence structure node. If so, then in step 444 the subsystem 32 sets the sequence node starting point to 1. In step 446 the execution subsystem 32 sets a variable referred to as Diagram Number to zero. The variable Diagram Number refers to the particular diagram of the sequence structure, which includes a plurality of diagrams. In step 448 the subsystem 32 enqueues the Diagram Number's self-reference node on the run queue. In step 450 the subsystem 32 sets node complete to false and completes.

If the entry into the sequence structure node is determined not to be the initial entry in step 442, but rather is determined to be entry at stalling point 1, then in step 452 the subsystem 32 increments the variable Diagram Number by one. In step 454 the subsystem 32 then determines if Diagram Number is equal to N, i.e. if all the diagrams in the sequence structure node have been executed. If not, the execution subsystem returns to step 448 and enqueues the self-reference node of the next Diagram Number on the run queue and sets node complete to false in step 450. If all the diagrams have been executed in step 454, then the subsystem 32 sets node complete to true and completes. It is noted that the node will be determined to have completed in step 322 (FIG. 9B), and thus the subsystem 32 will then proceed to step 324 to propagate its signals.

Asynchronous Node

An asynchronous node is a node which is required to wait on external events before executing. Referring now to FIG. 93, if the node executed in step 310 is an asynchronous node then the following node specific functions are executed in step 320. In step 460 the execution subsystem 32 determines if the asynchronous node has entered execution 32 at starting point 0. If so, then in the node the execution subsystem 32 sets the node starting point to 1 so that a subsequent entry into this node will affect a negative choice in step 460. In step 464 the execution subsystem 32 provides the respective external device with information needed to asynchronously enqueue this node after external functions have completed. For example, this external device may be a timer or a device driver or it may be another node if an occurrence has been set. For more information on occurrences, please see related co-pending application Ser. No. 08/125,642, entitled "Method and Apparatus for More Efficient Function Synchronization in a Data Flow Program," and filed Sep. 22, 1993 which is hereby incorporated by reference. In step 466 the execution subsystem sets node complete to false and then in step 468 sets the desire to be requeued to false. The node specific function for the asynchronous node then completes. At some later time after the respective external device has completed operations and has enqueued the asynchronous node, the asynchronous node will again be entered in step 460. If an occurrence has been set, the node will be re-entered in step 460 when the occurrence is triggered. For more information on this, please see the above-referenced application. When the node is reentered, the asynchronous node starting point will be determined to be 1. When this occurs, node complete is set equal to true in step 470 and the node specific operation for the asynchronous node completes.

Long Computational Node

A long computational node can be described as a node which requires a large amount of computation and thus is required to share execution time with other nodes. Unlike other nodes, the long computational node includes any number of different starting points. In the example illustrated in FIG. 9K, the long computational node includes three different starting points referred to as 0, 1, and 2. Referring now to FIG. 9K, when the long computational node is first called, it enters at starting point 0, its initial starting point. In step 482 the execution subsystem 32 sets its starting point to a later point referred to as point 1. In step 484 the execution subsystem 32 begins computation on the long computational node, performing a portion of the computation required. In step 486 the subsystem sets node complete to false and in step 488 sets the desire to be requeued to true. The desire to be requeued is set to true because further computations are required to complete the node.

When the long computational node is again entered, it enters at point 1. As shown in step 492, the execution subsystem 32 sets the starting point to 2. In step 492 the execution subsystem 32 performs further computations on the node. In steps 494 and 496 the subsystem 32 sets node complete to false and sets the desire to be requeued to true, respectively.

When the long computational node is entered for a third time, it enters at starting point 2. In step 497, the subsystem 32 finishes computation on the node and in step 498 sets node complete to true. It is again noted that additional similar stages may be present and a long computational node with 3 stages is shown only as an example.

Starting a Top Level VI

Referring now to FIG. 9L, a flowchart diagram illustrating operation of the routine which kicks off the first self-reference node of a large block diagram is shown. In step 499 the execution subsystem 32 enqueues the top level diagram's self-reference node on the run queue. This flowchart is necessary to place the first self-reference node on the run queue. Subsequent to this, the self-reference node places other nodes within respective self-reference node on the run queue. As data output signals are propagated, other nodes in turn are placed on the run queue and so forth. The operation in FIG. 9L is necessary merely to place the initial self-reference node in the run queue to "kick things off."

Execution Subsystem Operation Overview

The following description summarizes and further describes the operation of the execution subsystem 32 of the system 28 and the instrumentation system 56.

The first step in the execution of a virtual instrument is accomplished by executing its block diagram. The first step in the execution of a block diagram is accomplished by scanning the terminals contained in the diagram's self-reference node. For each terminal which is the source of a signal, the data token is moved from the control reference by the terminal to the terminal itself. The second step in the execution of a diagram is to initialize the token short-count of each node in the diagram to the number of input signals to that node, i.e. its fire count. The third step in the execution of a diagram is to propagate signals from the self-reference node. Propagation of signals from a node is accomplished by scanning all of the node's terminals. For each terminal that is source of a signal the data token on the terminal is copied to each destination terminal of the signal path. Each token placed on a destination terminal causes the short count of the node containing the terminal to be decremented. If it becomes zero in the process, then that node is scheduled to execute.

The first step in the execution of a node is accomplished by copying the tokens from the node's terminals to the reference controls. The second step depends upon the type of node. For an instrument use node that references a real-time virtual instrument, the next execution step is to copy the tokens from the node's controls to the virtual instrument's controls and to execute the virtual instrument. For an instrument use node that references previously stored data of a virtual instrument, the tokens from the appropriate data record are read in and placed on the node's terminals. For a sequence structure node, the next step is to execute the first subdiagram. For a conditional structure node, the next step is to execute the subdiagram indicated by the value of the token on the selected control. For an iterative or indefinite loop structure node, the next step is to set the value of the token on the iteration number control to zero and to execute the subdiagram. For a self-reference node, the next step is to perform the next step in the execution of the node or the virtual instrument which contains the diagram that contains the self-reference node.

The third step in the execution of a node also depends upon the type of node. For an instrument use node or a conditional structure node the output data tokens are propagated along the signal paths. For a sequence structure node, the next subdiagram is executed, if one exists, and if not, the output tokens are propagated. For a loop structure node, the shift registers are clocked (the data is shifted), the iteration number incremented, and the subdiagram is reexecuted, if appropriate; otherwise the output tokens are propagated.

The second step in the execution of the virtual instrument is to log the tokens on the front panel controls if data logging is enabled. The third step in the execution of the virtual instrument is to copy the tokens from the virtual instrument's indicators to the instrument use node's output terminals and to schedule the instrument use node to execute its next step. The third step of virtual instrument execution is performed only if the virtual instrument was executed in response to an instrument use node request. If the virtual instrument was executed interactively, there is no third step.

Front Panel Generation

FIG. 10 shows details of an illustrative front panel 62 which is produced using the front panel editor 36 and which is displayed using the keyboard and display 58. It will be appreciated that the illustration of FIG. 10 represents an actual graphical computer-generated display of an exemplary front panel for the instrument 60. The graphical representation of FIG. 10 illustrates physical control dials and switches for providing variable input information and illustrates a coordinate plane type indicator for displaying variable output information. More particularly, FIG. 10 shows a circular turn-dial and a slide switch for setting input variable data. The turn-dial and slide switch each correspond to respective rectangular boxes for digitally illustrating variable input data in digital form. The illustrative front panel also includes a display for illustrating variable output data. The graphical representations of input controls and output indicators are stored in a memory library, and a user may select from among a variety of different graphical representations of input controls and output indicators in order to construct a panel display which conforms to a user's intuitive understanding of how the instrument 60 is controlled and how it provides data.

FIG. 11 illustrates an icon 64 which can be used to reference a front panel (not shown). A visual representation of the icon 64 can be produced using the icon editor 34. The icon 64 corresponds to a particular front panel (not shown). As will be explained more fully below, the icon 64 can be used as a building-block in a hierarchical system constructed using the block diagram editor 30. The dashed lines of FIG. 11 indicate the one-to-one correspondence between the icon 64 and the respective two-dimensional regions (or hot spots) 66 and 68 which correspond to respective variable input data and variable output data illustrated by controls and displays of the corresponding front panel (not shown). For example, the front panel might include input data in the form a sequence of samples and might provide output data in the form of an indicator showing voltage reading per sample. The icon 64 then might be divided into two two-dimensional regions 68 and 66 which respectively correspond to the input sample count and the voltage reading for that sample count.

Structure Nodes

The drawings of FIGS. 12A-E show the graphical representations of structures utilized in constructing a block diagram as described below using the block diagram editor 30. The structures represented in FIGS. 12A-E substantially facilitate the application of data flow programming techniques which are used in the preferred embodiments of the present invention. FIG. 12A illustrates a sequence structure. FIG. 12B illustrates an iterative loop structure. FIG. 12C illustrates a conditional structure. FIG. 12D illustrates an indefinite loop structure. FIG. 12E illustrates a shift register on an indefinite loop structure.

It will be appreciated that the graphical representations of the structures illustrated in FIGS. 12A-E can be stored in a memory library as can execution instructions corresponding to the respective structures. Thus, a user can call upon a graphical structure library in order to display any one or more of the structures using the display facilities of the control processor 38 and keyboard and display 58 of the instrumentation system of FIG. 4.

Sequence Structure

The sequence structure, which has its graphical representation illustrated in FIG. 12A, serves to divide a data-flow diagram into two subdiagrams, one representing an inside and another representing an outside of the sequence Structure borders. The outside diagram behaves exactly as if the sequence structure and its contents were replaced by an icon with a terminal (or hot spot) for each line crossing the sequence structure border. The drawing of FIG. 12A shows a three-diagram sequence. In order to minimize space used on a computer console screen, only one diagram of the sequence structure is visible at a time. Inside the structure border, multiple diagrams (not shown) can be constructed which execute in sequence. The sequence of diagrams are indicated by the respective numbers in the respective sequence diagrams. When the first diagram (indicated by the number 0) in this sequence completes its execution, the next one begins. The process is repeated until all diagrams in the sequence have been executed.

Each diagram in the sequence uses a subset of incoming signal paths and produces a subset of outgoing signal paths (the outgoing subsets must be mutually exclusive, but the incoming subsets are arbitrary). Constants may be used with any of the diagrams without any constraints. Sequence variables indicated by rectangular boxes attached to the inside edge of the sequence structure (not shown in FIG. 12A) can be used multiple times in the diagrams following the diagram where the variable was assigned.

In accordance with data-flow principles used in the preferred embodiments of the present invention, the sequence structure does not begin execution until all incoming signal paths have data available, and none of the outgoing signal paths produce data until all diagrams have completed execution.

FIG. 13 shows an illustrative block diagram 70 of a sequence structure. The sequence structure is coupled to receive input signals on respective lines 72 and 74 and to provide respective output signals on respective lines 76, 78, and 80. Input registers 82 and 84 are provided to collect input data. A decoder 86 is provided to determine which computation and/or control element 88, 90, or 92 to select, and a sequence counter 94 is included to undertake a count for sequencing between respective elements 88, 90, and 92. When all data inputs are present, an output of AND gate 96 becomes TRUE. This starts computation in computation and/or control element 88 (assuming that it is the first element selected). When the control element 88 has completed computation, its output is stored in register 98. When the first element 88 has completed computation, the sequence counter 94 is free to advance by one. The decoder 86 will select the second computation element 90. The output of AND gate 96 will become TRUE again and, computation will begin in the second element 90. The output of the second element 90. The output of the second element 90 will be stored in output register 100. The sequence repeats for the third element 92, and its output is stored in output register 102. After the completion of the computation by the third element 92, the output data from all computations will be available for further computation by other instruments (not shown) of a block diagram system as will be explained more fully below.

Iterative (For) Loop Structure

The iterative loop structure, a graphical representation of which is shown in FIG. 12B is similar to the sequence structure in that the iterative loop structure partitions the data-flow graph into two parts. The interior diagram contains the body of the loop. Signal paths crossing the border of an iteration loop structure typically have a transformation applied. Incoming data are indexed in the most significant dimension so that the data inside the structure have dimensionality one less than outside. Outgoing data has the inverse transformation performed. The iterative loop structure is similar in operation to a for-next loop in a text-based program.

It is possible to disable the indexing on a signal path, in which case, the data behaves as if it were a constant available to each iteration. If indexing is disabled on an outgoing signal path, the data value is repeatedly overwritten and only the last value propagates out from the iteration structure.

There are two special variables which behave as constants within the body of the iterative loop structure: the number of iterations, N, and the iteration number or index, i. Usually, the number of iterations to be executed is automatically set by the size of the dimension being indexed for an incoming signal path (or the minimum of the indexed dimension sizes of all the incoming signal paths if there are more than one). In the event that there are no incoming signal paths, a scalar value must be specifically connected to the variable to specify the number of iterations. The iteration number, i, is similar to a constant within the diagram except that its value is 0 for the first iteration and increments by 1 at the end of each iteration.

Iteration Structures that have no data dependencies can, in principle, be executed in any order or completely in parallel except in the case where a non-reentrant virtual instrument is used by more than one structure. An example of a non-reentrant virtual instrument is a VI which controls an instrument or data acquisition card. In that case, the iteration structures would be executed strictly sequentially, in accordance with data flow principles. All inputs must be available to start execution of an iteration loop. Furthermore, all outputs are generated after execution completes.

Referring to the illustrative drawings of FIG. 14, there is shown a block diagram 104 for an iterative loop. An iterative loop structure operates on data in an array one element at a time. The data for each element are sequentially stored in respective input buffers 106 and 108. A counter 110 begins its count at 0. When the first data elements are available for both inputs of both respective input buffers 106 and 108, computation and/or control element 112 will generate outputs to be stored in respective output buffers 114 and 116. At that time, the counter 110 will advance to 1, and the process will repeat for the second data element in the array. This process will repeat until the counter 110 reaches N-1 making a total of N computations. At that time a complete cycle signal will be generated by the comparator 118. The output signals stored in the respective output buffers 114 and 116 then will be available for use by other computation instruments (not shown).

Conditional Structure

The conditional structure, a graphical representation of which is shown in FIG. 12C, is similar in appearance to the sequence structure in its use of screen space, but it differs in its handling of signal paths crossing its border in that in each case a diagram may use any subset of incoming signal paths, but must produce all outgoing signal paths. In accordance with data-flow principles, all inputs must be available in order to start execution. Furthermore, all outputs are generated after execution is completed. The conditional structure is similar in operation to a case or switch statement used in certain text-based programming environments.

There must be a signal path that terminates at the case-selection terminal on the structure border. In the simplest case, a Boolean-valued scalar is connected to the selector to select between case FALSE and case TRUE. In the general case, a scalar number is connected to the selector to select among diagram case 0, case 1, etc.

The drawings of FIG. 15 illustrate a block diagram 120 corresponding to a conditional structure. The block diagram 120 for the conditional structure is substantially similar to that of the block diagram 70 for the sequence structure. The block diagram 120 for the conditional structure includes respective input registers 122 and 124, a decoder 126, an AND gate 128, three respective computation and/or control elements 120, 132, and 134 and three respective output registers 136, 138, and 140 all coupled as shown in the drawings of FIG. 15. In operation, the conditional structure block diagram 120 operates in a manner substantially similar to that of the sequence structure block diagram 70, except that the decoder 126 of block diagram 120 is directly controlled by the case selection input provided on line 142 to select only one diagram.

Indefinite (While) Loop Structure

The indefinite loop structure, a graphical representation of which is shown in FIG. 12D, is similar in concept to the iterative loop structure in that the interior of the structure diagram represents the body of the loop, but it differs in that signal paths crossing the border of the indefinite loop structure do not usually have an indexing transformation applied. The indefinite loop structure is similar to a do-while loop in text-based programming languages.

There are two special variables applied within the body of the indefinite loop structure: iteration number or index, i, and continuation flag. The iteration number starts at zero and increments by one at the end of each iteration. A boolean value or expression is connected to the continuation flag. A value of TRUE means that another iteration will be performed. If the continuation flag is left unconnected, it is equivalent to connecting a FALSE constant. In accordance with data-flow principles applied in the preferred embodiments, all inputs must be available in order to start execution. Furthermore, outputs are generated after execution is complete.

The illustrative drawing of FIG. 16 shows a block diagram 144 which corresponds to the graphical representation of an indefinite loop structure shown in FIG. 11. In operation, when data inputs are available on both respective input registers 145 and 148, an output of AND gate 150 will become TRUE to enable computation and/or control element 152. After computation is complete, output data are stored in respective output registers 154 and 156. After completion of the first loop, counter 158 increments, and the cycle begins again. This process continues until a continuation flag provided on line 160 goes FALSE. The output data are present after each cycle.

Shift Register

A special construction available for use only within the respective loop structures is the shift register. A graphical representation of each respective loop structure type incorporating a shift register is shown in FIG. 12E. The shift register eliminates the need for cycles in a data-flow graph, making the result easier to comprehend and to prove correct. The shift register behaves as if it were an ordered set of two or more variables, all of the same type and dimensionality.

The first variable in a set is an output of the loop-body diagram and is located on the right border of the loop structure. The other variables of the set are inputs to the loop-body diagram and are located on the left border of the structure at the same elevation.

At the conclusion of each loop iteration, the data from the shift register output variable are shifted into the first input variable, and the previous value of the first input variable is shifted into the second input variable.

The drawing of FIG. 17 shows an illustrative block diagram 162 illustrating operation of an iterative loop structure including a shift register. Respective latches 164 and 166 are provided to implement the shift register. In operation, the block diagram 162 of FIG. 17 (which represents an iterative loop structure with a shift register) operates similarly to the block diagram 104 of FIG. 14 (which represents an iterative loop structure minus a shift register) except that computation inputs are provided which give the system feedback from a previous cycle.

An output provided by loop counter 168 is sensed by the comparator 170. For the first loop, the multiplexor control 172 selects preselect inputs from respective preset gates 174 and 176. For all other cycles, respective latches 164 and 166 are selected. The selected input is fed into the computation and/or control element 178. data from input buffer 180 also is fed into the computation element 178. After each cycle, the computed output data are fed into respective output buffers 182 and 184. When the comparator 170 reaches N-1, the process is completed, and the output data can be passed to a next instrument (not shown).

Type Descriptors

The system and method according to the preferred embodiment uses type descriptors to describe the contents of clusters and arrays. A type descriptor is essentially a language or grammar for describing data types used in the preferred embodiment. Referring now to FIG. 18, a diagram illustrating a type descriptor for a cluster containing an integer, a string, a character, and a float is shown. The block diagram editor encodes this cluster in the following manner. The first three elements in the type descriptor are a size word representing the size of the cluster, 22 bytes in this example a word containing the number 50 representing a cluster code; and a word containing 4 for the number of elements within the cluster. The next word contains the number 4 representing the size of the first element of the cluster in bytes followed by the code of the first element of the cluster, an integer, which is encoded as a 3. The next element in the cluster also has a size of 4 bytes and it is a type string, which is encoded as a 30. Thus the next element is encoded as 4, 30. The third element has a size of 4 and is a character, so it is encoded as a 4,1. The last element has a size of 4 and is encoded as a 10. Therefore, in summary, the type descriptor includes elements for size, data type code, and number of elements, as well as a size and code for each of the elements in the data structure.

Construction of an Exemplary Block Diagram

FIGS. 19A-K illustrate computer screen displays during each successive step in a construction of an exemplary block diagram using the block diagram editor 30 such as that of FIGS. 2 or 4. In FIGS. 19A-D, the front panel window appears on the left and the block diagram window appears on the right.

More particularly, in FIG. 19A, a control knob is placed in the front panel, and its associated terminal automatically appears in the block diagram. Referring to FIG. 20A, the system representation shows the virtual instrument with a diagram containing a self reference node, and a terminal in the self reference node which references the front panel control.

In FIG. 19B, a control graph indicator type is placed in the front panel, and its associated terminal automatically appears in the block diagram in the same position relative to the other terminal as the graph is to the knob. This makes it possible to distinguish the terminal even without supplementing the graphics with text labels.

In FIG. 19C, a constant with value 20 is placed in the block diagram. As shown in FIG. 20B, this is reflected in the system representation by another terminal and control attached to the self reference node.

In FIG. 19D, an icon referring to a built-in virtual instrument is placed in the block diagram. (An alternative view of the block diagram could show the icon terminals instead of the icon itself). As shown in FIG. 20C the system representation shows another node of instrument use type in the virtual instrument diagram and three terminals and controls corresponding to the terminals and controls in the referenced virtual instrument.

In FIG. 19E, an iterative loop structure is placed in the block diagram. As shown in FIG. 21A, the system representation shows the structure node in the diagram along with terminals and controls for the loop variables. Note that the iteration number is accessible only from within the loop; while the iteration limit is available inside and outside the loop as evidenced by the two terminals which reference it, one in the structure node and the other in the self-reference node of the diagram within the structure node.

In FIG. 19F, an icon referencing another built-in virtual instrument is placed inside the iterative loop structure.

In FIG. 19G, a wire is connected from the terminal associated with the front panel knob to the loop limit terminal of the loop structure. The front panel knob terminal is determined to be the signal source.

In FIG. 19H, a wire is connected from the iteration number terminal to a terminal on the virtual instrument inside the loop. This signal path lies completely within the loop structure subdiagram. As shown in FIG. 21B, the system representation shows the signal path with the iteration number terminal and the terminal on the instrument use node. The iteration number terminal is determined to be the signal source.

In FIG. 19I, the constant is wired to a terminal of the virtual instrument within the loop. In this case, the wire crosses the structure border so that a pair of terminals and a control are created, and the wire is split into two signal paths, one outside the loop structure and one inside. The constant is determined to be the source terminal of the outside signal, and the inside terminal at the border is determined to be the source of the inside signal.

In FIG. 19J, a wire is drawn from the virtual instrument inside the loop to the virtual instrument outside the loop. This wire crosses the border so it is split into two signal paths. The wire on the outside is thicker because it represents an array signal path (as will be explained more fully below).

In FIG. 19K, the output of the virtual instrument outside the loop is connected to the terminal associated with the front panel graph. The wire pattern indicates that it represents a cluster signal path (as will be explained more fully below).

Block Diagram of FIG. 5A

FIG. 22 shows a drawing of a computer-generated display of a completed block diagram for the design example of FIG. 5A. This block diagram is the graphical program representing the instrument's operation, showing the interconnections between the elements of the instrument, the signal paths, and the relationship to other virtual instruments. The large rectangular region in the center of the diagram is an iteration loop structure. The diagram placed inside this region is executed multiple times: for i=0 to N-1. At the upper left of the diagram, four front panel inputs from controls are shown connected to the iteration loop. The inputs to the iteration loop are the Number of Steps, High and Low Frequencies, and Amplitude.

The Number of Steps and High and Low Frequency inputs are connected to a Formula Node icon called "Calculate Frequency," which is comprised within the iteration loop. This icon is a built-in function which in this example includes a formula that calculates a frequency.

The Number of Steps input is connected to the loop-count (the N at the upper left corner) of the iteration loop, which in turn, is connected to the variable N in the Formula Node. The index i of the iteration loop is connected to the variable i of the Formula Node. The High and Low Frequency inputs are connected to the Fh and Fl inputs of the Formula Node.

Two virtual instrument icons referred to as Tek and Fluke are also inside the iteration loop. The Tek VI takes as input Amplitude and the frequency Fi output from the Formula Node and performs the appropriate IEEE-488 operations to set the function generator 208 of FIG. 5A. The Fluke VI performs the appropriate IEEE-488 operations to obtain a voltage measurement from the multimeter 210 of FIG. 5A. These two icons represent simple virtual instruments that are easily designed using built-in high level IEEE-488 functions to communicate with the multimeter 210. The output from the multimeter (Fluke) icon is provided to logic nodes which convert from the RMS (root-mean square) value. This signal is output from the iteration loop and provided to nodes which convert the data to dB (decibel) form. This output is then provided to a bundle node which also receives the output from the Formula Node. The bundle node is a bundle by position node and acts to bundle the two arrays of data it receives, i.e., frequency and response for plotting purposes. This bundled data in then provided to an indicator on the front panel.

Each iteration of the iteration loop produces as output the input frequency and the corresponding voltage measurement. This results in two arrays of values which exit the loop at the right. The bundle function converts these two arrays into X, Y plots which are then provided to the front panel graph indicator. Note the self-documenting effect of the graphical language, with the iteration loop structure contributing to the readability of the program.

With the front panel and block diagram complete, the instrument is ready to be used. The instrument is operated from the front panel. To execute the instrument, the user simply configures the input controls and "clicks" the Run Arrow button on the top of the screen (as will be appreciated from the description below).

VI Execution Overview

The graphical system and method described above permits the computer-aided modeling of a process using graphical techniques which generally are more easily comprehended, especially by persons who do not possess specialized skills in computer programming techniques. The use of a computer-generated image of a front panel display permits a user to easily understand how data is provided to a system being modeled and how data is provided by the system. The block diagram editor permits a user to construct a graphical representation of a procedure for producing output data from input data using icons which reference modularized procedural units. A user may use the icon editor to construct his own icons; or he may call upon a ready-made library of icons. The execution subunit executes execution instructions which are constructed in response to the graphical images produced by a user to model a process. Thus, a user can program a computer substantially by constructing a hierarchy of icons connected to one another so as to model a process. A user, therefore, can use the system and method of the present invention to program a computer to model a process using graphical techniques which generally are easier to comprehend.

Furthermore, the system and method of the present invention advantageously can use data flow techniques. The use of the structures illustrated in FIGS. 12A-E facilitates the use of such data flow techniques. By using such techniques, a system modelled in block diagram form can operate in a parallel fashion, since each individual icon in a hierarchy comprising such a block diagram operates as soon as all input data provided to it are available. In addition, such structures render graphical representations of block diagrams using such data flow techniques more comprehensible to a user, and, therefore, simplify the task of using such techniques.

Parallel and Serial VI Execution

Having described how a VI is constructed and used, additional explanation regarding the execution description is provided. In the preferred embodiment, all VIs are referred to as diagram VIs. Diagram VIs in turn are comprised of nodes, which are discussed with regard to FIGS. 9C-9K. Referring once again to FIG. 8B, a node (icon or structure) begins execution when all its inputs are available. If a diagram has two or more icons referring to the same VI and a second one has all its inputs available before the first finishes execution, it is not always clear how to handle this second node. In fact, it depends on the "execution mode" of the VI. Absent some way to execute VIs in parallel, VIs would be executed in serial. In a serial mode of execution, the second node is placed on a FIFO wait queue of the self-reference node associated with the VI, and execution of the VI in the context of the second node is delayed until the execution in the context of the first node is completed.

Parallel or reentrant execution dynamically creates multiple instances of the VI at execution time in order to allow multiple nodes to execute in parallel. In the preferred embodiment, parallel execution is implemented for VIs designated as reentrant by the user.

FIGS. 23 and 25 illustrate serial and parallel execution modes. In FIG. 23, one "thermometer" icon must wait until the other finishes execution before it can start, even though it has all its inputs at the same time as the other. This is because the "thermometer" VI is a serial VI.

In FIG. 24, the asynchronous behavior of the wait VI (the watch icon)is shown. It is a code type VI that does not execute atomically. During the time that it is executing (waiting) other components of the diagram may execute.

In FIG. 25, both "wait" icons execute at the same time showing the parallel execution mode of the wait VI. If execution were not parallel either the "thermometer" VI or the "IMD/THD" VI would effectively wait for the sum of the time delay intervals caused by the two "wait" VIs together.

The preferred embodiment can be embodied in software, hardware, or a combination of both. One way to implement a parallel VI in hardware is to have enough instances of the hardware to account for the maximum number of VI instances that must run in parallel.

The present invention provides the ability of a virtual instrument (with icon, front panel, and diagram or code) to be a template and effectively automatically replicate itself as necessary in order to allow multiple instances to run in parallel.

A node is executed when all its inputs have data ready. When this happens the node is put on a list of ready nodes, i.e., is placed on the run queue. This is illustrated in FIG. 26. One by one the ready nodes are taken off the list and executed. When more than one of the ready nodes are I-use nodes which refer to the same virtual instrument the scheduling of the execution depends on the mode of the virtual instrument. The possible modes are serial and parallel.

Serial Mode (Block Diagram Virtual Instruments)

Serial mode instruments place contending nodes on a list of nodes which execute the block diagram of the virtual instrument in turn. This list of nodes is the self-reference node wait queue. Because the block diagram of an instrument consists of more nodes which will become ready, the execution of the block diagram instrument is not atomic. The nodes of the diagram are put onto the ready node list or run queue as they become ready and are "interleaved" with ready nodes from other diagrams. This is illustrated in FIG. 27. The dashed box 318 once again contains the node on whose behalf the block diagram 322 of the virtual instrument is executing. The node 324 outside the dashed box must wait for the diagram to complete before it gets its turn. The arrow from the block diagram to the Ready Nodes list 326 shows that the block diagram 322 will produce more ready nodes which will be added to this list.

Parallel Mode (Block Diagram Virtual Instruments)

Block diagram instruments can be built to execute in parallel or reentrant mode. The means of making parallel execution possible for block diagram instruments is by using the instrument as a template to make identical copies of the instrument automatically as needed for contending nodes. Each block diagram then executes, producing ready nodes for the Ready Nodes list or run queue in such a way that the nodes can be "interleaved" and the execution of the identical diagrams takes place "at the same time." This is illustrated in FIG. 28. Inside the dashed box 338 the replicated virtual instrument 340, 342 is shown and each I-use node has "its own copy" of the instrument. Both diagrams are shown putting ready nodes onto the Ready Nodes 334 list.

Execution States

The fundamental capability which execution states permit is the interactive operation of more than one virtual instrument at a time, as well as the construction or editing of some virtual instruments while others are executing.

When a VI is interactively started (i.e., run from its front panel) it enters its active state. It remains active until it completes, at which time it returns to its idle state. At the point it becomes active all lower level VIs are "reserved." This prevents them from being changed (a change could result in an execution error). A reserved VI executes in the context of one or more icon nodes within the diagrams of one or more higher level VIs. It is unreserved when all those higher level VIs become idle.

Reserved VIs can have their front panel and block diagram windows open while they execute. This ability to observe VIs at any and all levels of the hierarchy while they execute is a powerful troubleshooting aid. While a VI is reserved it may not be edited; however the values assigned to its front panel controls may be changed. Depending on the design of the VI and the point in time when the control value is changed such a change may produce unexpected results.

A "breakpoint" may be set so that a reserved VI enters its "suspended" state when it is about to execute. "Suspended" is similar to idle in that the VI can be run interactively one or more times. However, a suspended VI can be resumed (passing its outputs back to the icon node) and reenter its reserved state. It can actually be resumed without running it at all. While it is suspended its indicators (outputs) can be modified as well as its controls (inputs). This capability enables top-down implementation and testing. "Stub" VIs can be built (icons and front panels but no diagram or code), and their execution simulated by setting the breakpoint, supplying relevant outputs when the VI becomes suspended, and then resuming.

Breakpoints have been used in conventional programming languages, but there is no analogy in instrumentation systems. A related but different analogy in instrumentation is remote/local loosely related to reserved/idle (no analogy to suspended). Stubs are known in programming but not in hardware or instrumentation development.

The present invention provides the ability of VIs to exist in different states in order to protect execution from editing changes. Furthermore, it provides the ability to change the value of a VI indicator (output) while it is in its suspended state.

Controls

As illustrated in FIG. 29, whenever a token is propagated to a control the control is set to its normal or error state depending on whether the value of the token is in or out of range for the control.

Signals

In FIG. 30, after a wiring change or a control type, dimension, direction, or unit change the type propagation code will set each signal to bad or normal. The VI is not executable unless all its signals are normal. When a diagram is about to be executed, all its signals are set to their armed state. When a signal is propagated from its source node it is set to its normal state. When the owning VI becomes idle all remaining armed signals are set to their normal states.

Diagrams

In FIG. 31, when a diagram begins execution it is set to its active state. When it finishes it is set to its normal state. When the owning VI becomes idle all active diagrams are set to their normal states. The diagram state is needed only for reset to be able to identify the active diagram of a select or sequence structure.

Self Reference Nodes

In FIG. 32, when a diagram is about to be executed the self reference node as well as all the other nodes in the diagram are set to their armed states. When all the other nodes have finished executing the self reference node is scheduled to run by being placed on the run queue. At that point it is set to its fired state. When it is removed frame the run queue and executed, signalling the completion of the diagram, it is set to its normal state. When the owning VI becomes idle all remaining armed self reference nodes are set to their normal states.

Structure Nodes

In FIG. 33, When a diagram is about to be executed all the nodes in the diagram are set to their armed states. When a node's short count is decremented to zero, it is scheduled to run by being placed on the run queue. At that point the node is set to its fired state. When it is removed from the run queue and begins execution it is set to its active state. When the subdiagrams finish (the required number of iterations) the structure node is set to its normal state and its outputs are propagated. When the owning VI becomes idle all remaining armed structure nodes are set to their normal states.

Instrument Usage Nodes

In FIG. 34, after a load operation or a change to the front panel of the sub VI the linking code will set the node to bad or normal (a node is bad also if the link is good but the sub VI is not executable). The owning VI is not executable unless all its nodes are normal. When a diagram is about to be executed all nodes are set to their armed states. When a node's short count is decremented to zero it is scheduled to run by being placed on the run queue. At that point the node is set to its fired state. When an instrument usage node is removed from the run queue and enqueued on the sub VI's self-reference node wait queue it is set to its pending state. When the sub VI actually begins execution in the context of the calling node the calling node is set to its active state. When the sub VI completes normally and the calling node is dequeued from the VI's ready queue the calling node is set to this normal state. If the referenced VI is stopped in its suspended state or executing in its retrying state the calling node is set to its suspended state. When the owning VI becomes idle all remaining armed nodes within it are set to their normal states.

Serial virtual instruments

In FIG. 35, after a block diagram edit operation the type propagation code sets the VI to its bad or normal state depending on the presence of bad signals or nodes (a serial VI is bad also if any sub VI is not executable, or if it or any sub VI contains a recursive reference to it). When the go button is hit the VI in the front window (panel or diagram) is set to its active state. At this point all of its subVIs and all of theirs, etc., are set to their reserved states. When the VI completes normally or with an error it is placed in its idle state. If the reset button is hit while the VI is in its active state it is placed in its idle state, and all nodes in their pending, active, or error states are reset (which may involve resetting their subVIs). When a VI enters its idle state from its active or reserved state each of its subVIs still in its reserved state checks all its callers to see if it too can return to its idle state.

When a reserved VI actually begins execution in the context of a calling node it is placed in its running state. Whenever a VI has to abort execution because its calling node is being reset it is placed in its reserved state (it may subsequently have the opportunity to discover whether it should return to its idle state).

If the VI has a breakpoint set or if it detects an error on a control then instead of being placed in its running state at the start of execution it is placed in its suspended state.

When a VI completes normally it is placed back in its reserved state. If a VI detects an error on an indicator the VI is placed in its suspended state. When the retry button is hit the VI is placed in the retrying state. If the VI then completes normally or with an error or if the reset button is hit it is placed in the suspended state. A suspended VI is placed in the reserved state when the resume button is hit.

Front panel controls can be adjusted in any VI state but the effects are nondeterministic except for the idle and suspended states. Edit changes to the front panel or block diagram are not allowed in any state except idle and bad. The go button is inoperative except in the idle state. The reset button is inoperative except in the active and retrying states. The resume and retry buttons are inoperative except in the suspended state.

While the VI is in its running, suspended, or retrying state, additional pending I-Use nodes may be enqueued on its wait queue. When the current node is completed it is dequeued from the wait queue, the next one is set active, and the VI begins execution in its context.

Parallel Block Diagram virtual instruments

In FIG. 37, a parallel block diagram VI is similar to a serial VI except it has no suspended or retrying states. When a parallel VI actually begins execution in the context of a calling node a clone is created and placed in its running state. FIG. 36 illustrates a clone. When the clone completes normally it is discarded. The clone is discarded also whenever it has to abort execution because its calling node is