Method and apparatus for restoring a target MCU debug session to a prior state5701488Abstract A Target MCU is restored to a Target State. A Host Trace of Debug Commands is preserved as the Target MCU is driven from a known first state to the Target State by executing a series of Debug Commands. The Target MCU is then reinitialized to the known first state. The Debug Commands are read from the Host Trace and sent to a Modular Development System (MDS) for execution by the Target MCU until the Target MCU is again is driven to the Target State. Claims We claim: Description CROSS REFERENCE TO RELATED APPLICATION
TABLE T-1
__________________________________________________________________________
Bus State Analyzer
Fr# Adr.
Data Label Code Bus Cycle
__________________________________________________________________________
4181
0123
0F 0F 01 MAIN: BRCLR
7,$0F,127
›00FF=23!
4191
0156
03 C0 OCFCNT:
DEC OCFS ›00C0=02!
4196
0158
26 06 BNE ENDRTI
4199
0160
B6 13 ENDRTI:
LDA TSR ›0013=60!
4202
0162
B6 17 LDA OCRL ›0017=A2!
4205
0164
80 UNUSED
RTI
4214
0123
0F C1 FD MAIN: BRCLR
7,TIC,MAIN
›00C1=00!
4219
0123
0F C1 FD MAIN: BRCLR
7,TIC,MAIN
›00C1=00!
4224
0123
0F C1 FD MAIN: BRCLR
7,TIC,MAIN
›00C1=00!
__________________________________________________________________________
As discussed in the previous sections, there are features that an embedded application development environment should provide. MCUdebug has been designed with backward compatibility in mind, while providing an extension to previously available tools. Backward compatibility has been maintained in object file format support, command language (currently supports the full Motorola MMDS05/MMDS08 command set), and in some cases even the screens. The following section describes some of the features of the MCUdebug application development environment. As described previously, the task of maintaining an project in an application is very beneficial. MCUdebug provides a user the capability to define a project, add/delete source files, customize their generation toolset, and build his applications from within the same interface. If desired using the MCUdebug script file generation capabilities, the user can define his project using the graphical interface, save his entire project configuration to an ASCII file, and then later retrieve it if his wish to re-use their settings for another project. This allows reuse of previous work and eliminates the hassle of regenerating "makefiles" for each development project. It also provides a user with a more user friendly environment for project management. On a MDS development systems that support Bus State Analysis capabilities, MCUdebug provides a rich set of functions which can allow a user to view analyzer data in variety of ways. The Bus State Analyzer window displayed in Table 1 is an example of the "Instructions Only" view mode of the bus state analyzer data. In the right section of the window (under the label "Bus Cycle") the data displayed shows the actual bus cycle that occurred on the execution of that particular instruction. MCUdebug currently supports the Avocet SYM, IEEE 695 (as defined by HP/MRI), COFF (as generated by the Motorola MCUasm.TM. assembler), and the P&E Microsystems MAP File Format. Support for all these object file formats is important since it allows the user a great diversity in the range of toolsets that can be supported under the MCUdebug development environment. MCUdebug supports both toolsets for the Motorola MC68HC05.TM. and MC68HC08.TM. microcontroller families, so if a user decides to migrate between these microcontrollers, he will still be able to develop applications using the MCUdebug environment. If applications are being developed using two or more different toolsets, then sometimes the toolsets will generate different object file formats for each application. Keeping track of which application was generated using which application can be a cumbersome task, especially if applications are being development for the same microcontroller family. MCUdebug allows the user to load an object file for debugging without the user having to specify what the "type" of the object file format that they are loading. The object code format is identified and loaded by the "Autoloader" function. If the user tries to load an object file format that MCUdebug does not support, then an appropriate error message is provided. That provides the user with the relief of not keeping track of which object file format each of their applications is generated with. Options are important for controlling the specific toolset used for application generation. MCUdebug allows the user to specify the toolset options which they wish to generate their application with. For example, a user might want the compiler to generate code using the -O2 option. MCUdebug provides features so a user can setup their Compiler, Assembler, Linker and if available, a locator. While adding source files to the project MCUdebug automatically determines the type of the source file being added. Therefore, adding a "C" source file requires the user to define a "C compiler" and if assembly language source files are used then an assembler must be defined. MCUdebug features extensive support for user customization of the graphical user interface. Features such as window layout, colors and toolbar buttons. This section describes some of the customization facilities available to the user through MCUdebug. The MCUdebug toolbar provides a user a quick way to execute "most frequently used commands." As defined by the MCUdebug command language, any command which can be entered on the command line can also be executed through a menubar option. If a command has a dialog associated with it, then typing that command on the command line without any arguments will cause MCUdebug to bring up the associated dialog. MCUdebug allows a user to "program" toolbar buttons i.e., program the available buttons to execute user defined commands. User defined aliases are also allowed as toolbar buttons command. FIG. 1 shows the hardware components of the host portion of the MCUdebug system. The Host Computer 20 has a Computer Processor 22 connected through a bus 26 to RAM and ROM Memory 24. Also connected to the bus 26 are a disk drive 30, auxiliary storage 32, monitor 34, keyboard 36, and printer 38. The current implementation of the MCUdebug system uses either an x86 based Host Computer 20 running the Windows.TM. operating system or a SUN Microsystems SPARC.TM. workstation running the UNIX.TM. operating system. However, any computer with preferably a graphical user interface may be used. The auxiliary storage 32 may be tape, diskette, CD-Roms, or even storage belonging to another computer located across a network. Originally loaded from the auxiliary storage 32 into Memory 24 and disk 30 are the various portions of the MCUdebug system. Executing on the Computer Processor 22 in the Memory 24 are the host portions of the MCUdebug program 70. Finally, connected via a communications link 28 to the host computer 20 is the Modular Development System (MDS) 40. A nine (9) pin serial RS232 interface is used. FIG. 2 shows the hardware components of the Modular Development System (MDS) 40. The Modular Development System (MDS) 40 is connected via a communications link 28 to the Host Computer 20. The MDS 40 has two microcontrollers: a Station Controller 42, and a Target MCU 58. The Station Controller 42 operates as a debug monitor for the target MCU 58. In the MDS commercially available from assignee, a Motorola 68HC11.TM. processor is used for the Station Controller 42. The Motorola MDS is primarily used to test and debug Motorola 68HC05.TM. and 68HC08.TM. target MCUs. However, this invention will work with other Station Controllers 42 and Target MCUs 58. Testing the execution of the target MCU 58 in turn is the primary purpose of the invention. It can be connected via another cable 66 to a Target MCU User 68. The cable 66 will usually connect to an IC carrier that replaces the actual Integrated Circuit (IC). For example, if the purpose of the Target MCU 58 is to time an automobile engine, then the cable 66 can be used to connect the Target MCU 58 to an actual engine. This provides the engineers optimizing engine performance the full debug capabilities available until now only for computer applications. The Station Controller 42 MCU is connected to a station bus 46. Also connected to the station bus 46 are station controller RAM 44, Dual Ported Memory 48, a trace buffer 50, and a hardware breakpoint detect 54. The Dual Ported Memory 48 is shared with the Target MCU 58, providing a Shared Memory to the two microprocessors. This allows the Station Controller 42 to monitor a portion of the Target MCU's 58 memory activities and to change Target MCU 58 memory "on-the-fly". The Station Controller's 42 memory map includes the Dual Ported Memory 44, and the controller RAM 44. The Trace Buffer 50 is used to trace the execution of the Target MCU 58. Finally, the Hardware Breakpoint Detect 54 can be used by the Station Controller 42 to interrupt the Target MCU 58. Note that though the Hardware Breakpoint Detect 54 is shown connected to the station bus 46, it can also be connected directly to the Station Controller 42, as well as the Memory Mapper 60, and Trace Buffer 56. These three modules primarily use the Hardware Breakpoint Detect 54 module to interrupt the Target MCU 58. The Target MCU 58 is connected to a target bus 52. Also connected to the target bus 52 are the Dual Ported Memory 48, Trace Buffer 50, Hardware Breakpoint Detect 54, foreground/background switch 56, memory map 60, pseudo-ROM 62, and a target interface 64. The target interface is connected by cable 66 to the target MCU user 68 such as the automobile engine described above. The Target MCU 58 can operate in one of two modes controlled by the foreground/background switch 56. These two modes are similar to problem (or user) mode and supervisor mode on many computer processors. While in foreground mode, the Target MCU 58 executes the code being debugged. For example, the Target MCU 58 may be providing timing signals to an automobile engine. Switching to background operation gives control to a monitor program. One of the primary methods of switching to background mode is through activation by the Hardware Breakpoint Detect 54 module. This module can be programmed, either by the Station Controller 42, or by the Target MCU 58 in background mode, to interrupt the Target MCU 58, causing it to enter a background mode interrupt routine. The Hardware Breakpoint Detect 54 module can be programmed to interrupt on certain memory accesses or execution of certain program instructions. Finally, it provides a convenient way for the Station Controller 42, Memory Map module 60, and Trace Buffer 50 to interrupt a Target MCU 58 operating in foreground mode. The memory map for the Target MCU 58 is controlled by the Memory Map module 60. This module allows the Target MCU 58 in background mode to map the Dual Port Memory 48 and the pseudo-ROM 62 into the Target MCU's 58 memory space. Different executions of the target program may be mapped differently. For example, different portions of the Target MCU 58 memory space may be mapped into the Dual Port Memory 48 allowing monitoring and modification of these portions by the Station Controller 42, and thus by the MCUdebug program 70 running in the Host Computer 20. The Memory Map module 60 can be programmed to treat certain portions of the address map as readonly (ROM), other portions as read/write (RAM), and still other portions as non-existent. The Memory Map module 60 may be programmed to interrupt or ignore readonly writes and/or non-existent memory reads and/or writes. As noted above, interruption of the Target MCU 58 can be initiated with a signal to the Hardware Breakpoint Detect 54 module. The Trace Buffer 50 or Bus State Analyzer traces or records everything on the Target Bus 52. Currently, the trace buffer 50 has 128 kb of RAM memory configured as 8192.times.16 byte frames. With current technology, for timing reasons, SRAM is preferable to using DRAM for the trace buffer 50. Each frame contains all of the relevant signals, including all bus and tag lines, for one bus cycle. Each frame uses 32 bits or 4 bytes for a time stamp and another 16 bits or two bytes can be used to record data from logic clips. When 8192 entries or flames have been inserted in the Trace Buffer 50, the tracing can either stop, or wrap. If the tracing is to stop, an interrupt may be raised to force the Target MCU 58 into background mode. The time stamp intervals may correspond to either asynchronous events, or to bus cycles. The MCUdebug program 70 has a number of constituent parts. First, there is the generic debug program executing on the Host Computer 20. When a Station Controller 42 is initialized, it notifies the Host Computer 20. The Host Computer queries the Station Controller 42 for the type of the Station Controller 42 and type of Target MCU 58. After determining the type of Station Controller 42, the appropriate MCUdebug Station Controller routines are downloaded into the controller RAM 44. Then when the host portion of the MCUdebug program 70 determines the type of Target MCU 60 installed in the MDS 40, the appropriate monitor and user program are read from disk 30, sent across communications line 28, and loaded into the Pseudo-ROM 62 and Dual Ported Memory 48. A corresponding memory map is loaded into the Memory Map module 60. The monitor is a set of Target MCU specific routines that are executed when the Target MCU 58 is in background mode. Meanwhile, the host portion of the MCUdebug program 70 loads into host Memory 24 copies of the code and data downloaded to the Target MCU 58. The MCUdebug program 70 is dynamically reconfigured to correspond to the software and hardware loaded in the Target MCU memory 48, 62. This reconfiguration includes loading appropriate symbol tables and assembler mnemonic tables into Host Memory 24. Dynamically loading and reconfiguring assembler mnemonic tables can be done utilizing the invention in our copending patent application entitled METHOD AND APPARATUS FOR DYNAMICALLY RECONFIGURING A PARSER, filed of even date herewith, assigned to the assignee hereof, and incorporated herein by reference. Selection of which configuration and programs to download can be done either by creating a set of filenames based on the "Id" of the Target MCU 58, or by using the "Id" to index into a configuration file stored on disk 30. A similar mechanism can be used to select the portion of the MCUdebug program 70 to download into the station controller memory 44. However, this selection can be hard-coded if the number of selections is small and not expected to change quickly. The interaction between the Host Computer 20 and the Station Controller 42 over interface 28 is via an internal protocol. This protocol allows the Host Computer 20 to send commands to the Station Controller 42 and receive back status responses. Many of the commands are directly equivalent to the line mode commands described hereinabove. The Station Controller 42 then either executes the commands directly, or interrupts the Target MCU 58 to execute the commands. Normal operation of the Target MCU 58 after being loaded and initialized to a known state is to receive debug commands from the Host Computer 20 via the Station Controller 42. These commands are processed in background mode, and may set breakpoints, read and/or write memory, and registers, and the bus state analyzer or Trace Buffer 50. Ultimately a command to "run" is received. The Target MCU 58 then switches into foreground mode and executes the designated Target MCU code. At some point the Target MCU will "halt" and switch into background mode. This can be triggered by the Hardware Breakpoint Detect 54 encountering a breakpoint, an illegal memory access, or upon command of the Station Controller 42. The registers, including the program counter ("pc"), are sent to the Host Computer 20. These values are displayed on the screen 34 attached to the Host Computer 20. Uploading the program counter (pc) allows the MCUdebug program to highlight the pc location in the source code, and to display the surrounding code. The contents of the Trace Buffer 50 may also be uploaded in order to display the Bus State Analyzer contents. FIG. 3 is a flowchart showing how the host MCUdebug program 70 determines the identity of the Target MCU 58. The program enters, step 100, and sends a break or flush port, step 102, across the communications line 28. Next, a zero character `0` is sent, step 104. The host program then waits for input, step 106. When the input arrives, it is validated as a boot command, step 108. If other than a boot command is detected, step 108, the program exits, indicating that no hardware is connected, step 110. Otherwise, if a boot command was found, the single character one ("1") is sent, step 112, across the communications line 28. The host program then waits until the MDS 40 indicates that the "boot" command, step 114, has been accepted. At that point, an S-Record containing an Ident program is sent, step 116, to be run in the MDS 40. The Host program then waits for a response to the Ident program, step 118. Upon receipt of a Target MCU Id from the Ident program, step 118, the program exits, step 120, with the identity of the Target MCU 58. FIG. 4 is a flow chart showing the Autoloader function of the MCUdebug program 70. This function is used once the identity of the Target MCU 58 has been determined (see FIG. 3) to select the proper routines to use to load the object code into host memory 24, and to download into the MDS 40. The Autoloader function selects the appropriate routines based on the object code format of the selected object code files. The Autoloader function starts with an object file name, step 200. This can be the result of either manufacturing a filename based on Target MCU 58 Id (see FIG. 3 step 120), and/or from an entry in a configuration file. The object file is first read as if it were in P&E Microsystem format, step 202. If successful, the Autoloader returns indicating P&E format, step 204. Otherwise, an attempt is made to read the file as COFF format, step 206. If successful, the Autoloader returns indicating COFF format, step 208. Otherwise, an attempt is made to read the file as Avocet `.sym` format, step 210. If successful, the Autoloader returns indicating Avocet format, step 212. Otherwise, an attempt is made to read the file as IEEE695 formatted, step 214. If successful, the Autoloader returns indicating IEEE formatted object file, step 216. Otherwise, the Autoloader returns a status indicating an Invalid Type, step 218. Note that only one of the possible orderings of the above tests has been shown as an example. FIG. 5 is a flow chart showing the operation of the test for P&E format module 202. The module enters, step 220, and checks whether it is the same object file type, step 222. If not, the module error returns, step 223. Otherwise, a check is made for an S-Record, step 224. If an S-Record is not found, step 224, the module error returns, step 225, indicating that no S-Record could be found. Otherwise, the executable code is downloaded to the emulator, step 226. Pointers to symbolic debugging information are setup, step 228. This is followed by reading the symbolic debugging information into memory, step 230. The user's source file is opened, step 232, the source code around the entry point is displayed in a window, the entry point is highlighted in that window, step, 234, and the module exits, step 236. FIG. 6 is a flow chart showing the COFF Format Read procedure, step 206. The module is entered, step 240, and a check is made that the same object file type is being used, step 242. If not, the procedure error returns, step 244. Otherwise, the symbol tables are initialized, step 246, and the Object File is read, step 248. A check is made whether there is more to read, step 250, and if there is more to read, the procedure loops, reading the next object file, step 248. When there is no more to read, step 250, the executable code is downloaded to the emulator, step 252, the user's source file is opened, step 254, the source code around the entry point is displayed in a window, the entry point is highlighted in that window, step 256, and the module returns normally, step 258. The modules to read Avocet ".sym" formatted files, step 210, and IEEE 695 formatted files, step 214, as well as routines for reading other object file formats, are similar to the procedures shown in FIG. 5 and FIG. 6. However, the states required by each different object file format differ. Note that most object code formats can be distinguished from each other by the format of the corresponding object file headers. For example, different "Magic Numbers" are found in the first bytes of many different types of object file formats. FIG. 7 is a program structure chart showing the relationship among the high level modules in the monitor program executed by the Station Controller 42. The President module 302 includes the declarations and defines used throughout the lower level modules. If C++ is used as the programming language, the President module 302 would include all data structures and attributes inherited by the lower level routines. The Executive module 304 controls the lower level modules. One implementation utilizes a single repeating loop that can check for things to do, execute appropriate lower level routines, and then wait until an external event (including possible expiration of a timer) triggers it awake. The Executive 304 invokes the Host.sub.-- IO module 306 to perform all host communications 314. The asynchronous analyzer module 308 controls the Bus State Analyzer or Trace Buffer 50 (see FIG. 2). The asynchronous HC05 module 310 controls and communicates with the Target MCU 58. Finally, the Exec.sub.-- CMD routine 312 executes all host commands 316. FIG. 8 is a state chart showing the state transitions encountered by the Station Controller 42 when executing commands. The normal status is IDLE 322. When a command is received, the monitor program enters CMDBEGIN state 324. After the command is initiated, the monitor enters CMDPENDING state 326. It stays in this state until the command is complete, at which time it enters CMDFINISH state 328 to cleanup prior to reentering IDLE state 322. Note that regardless of state, a CANCEL 320 will force the monitor back to IDLE state 322. FIG. 9 is a procedure call diagram showing the operation of the Station Controller 42 Executive module 304. As noted above, the Executive module 34 loops looking for things to do. When the Executive module 34 receives a message from the host, the Host.sub.-- IO module 306 is called. The Host.sub.-- IO module calls GET.sub.-- PACKET 342 to get the packets necessary to interpret a command received from the host. Then the Parse routine 344 is entered to parse the command. If the parse command was successful, a response, if necessary, is sent back to the host 346. After a command has been parsed 344, it is executed when the Executive module 304 invokes the EXEC.sub.-- CMD module 312. If the host command is to update Shared Memory, the MEMSET routine 336 is invoked. If the host command is to read Shared Memory, the MEMGET routine 338 is invoked, and the Shared Memory read is returned as a response 346. Otherwise, the NOIMPLEMENT module 340 is invoked to recover from unimplemented host commands. FIG. 10 shows a typical memory map 400 of a Target MCU 58. The Memory Map module 60 (see FIG. 2) maps the Pseudo-ROM/RAM 62 and Dual Port Memory 48 into the Target MCU's 58 memory space. The memory map usually has I/O low memory 404 at the bottom of the memory map 400. This is followed by a statck in RAM 406, user ROM 408 containing the user program, an empty hole 410, self check ROM 412, possibly another hole 414, and interrupt vectors 416 in ROM. It should be noted there that the memory map shown is for illustrative purposes only. MCUdebug is not limited to this exact, or even similar memory mapings, but rather supports an unlimited number of different memory mapings. Note that the Memory Map module 60 allows the Target MCU's 58 address space to be mapped to exactly correspond to the actual embedded memory of the Target MCU when fully implemented in silicon. The Pseudo ROM/RAM 62 and the Dual Port Memory 48 are implemented in the MDS as RAM. ROM and hole functionality are simulated by specifying in the memory map downloaded from the Host Computer 20 the actions taken by the Memory Map module 60 when reads and/or writes of readonly memory and holes are encountered. These illegal accesses can either be ignored, or the Target MCU 58 interrupted and placed in background mode by a signal from the Memory Map module 60 to the Breakpoint Detection module 54. The Memory Map module 60 also is used to specify which memory addresses in the Target MCU 58 address space are visible to the Station Controller 42. This feature is used to allow the Station Controller 42 to monitor the shared portion of the Target MCU's 58 memory for changes and to make changes in the Target MCU's 58 memory in real-time. Different portions of the Target MCU address space may be monitored and modified on different executions of the Target MCU program by simply loading different memory maps into the Memory Map module 60. FIG. 11 is a block diagram showing the interaction between the Target MCU 58 memory and a real time display of the memory on the Host Computer 20. The address space 426 of the Target MCU 58 includes shared 422, 424, and nonshared areas 420. Typically, the shared portions of memory ("Shared Memory"), 422, 424, are mapped by the Memory Map module 60 into the Dual Ported Memory 48, while the "Nonshared Memory" areas 420, are mapped into the Pseudo-ROM 62 memory. The reason for sharing the memory is two-fold: it allows the Station Controller 42 to monitor Shared Memory for changes made by the Target MCU 58, and it allows the Station Controller 42 to update or modify the Shared Memory in real-time. As noted above, different portions of the Target MCU 58 address space can be mapped into the shared Dual Port Memory 48 at different times by loading different memory maps into the Memory Map module 60. At a minimum, the Shared Memory is shadowed in the Host memory 24. This allows the MCUdebug program 70 executing on the Host Computer 20 to display the current status of the Target MCU 58 memory at all times. It can also be shadowed in the Controller RAM 44 in order for the Station Controller 42 to detect changes in the Shared Memory. A portion of the Target MCU 58 memory is displayed by the MCUdebug program 70 in a window 432 on the display 34 attached to the Host Computer 20. The window 432 display includes a number of Lines of Text 430 and a scroll bar 434. The scroll bar 434 has a standard scroll button 436 used to scroll up and down. The number of Lines of Text 430 displayed at any time can be dynamically modified by resizing the window 432. The Lines of Text can be displayed in the window 432 in Hex, Octal, ASCII, and/or instruction format. The Lines of Text displayed 430 correspond to the visible portion ("Visible Memory") 424 of the Shared Memory. The remainder of the Shared Memory is temporary invisible ("Invisible Memory") 422. There is an array of Dirty Flags 428 in the Station Controller RAM 44, and another similar array of Dirty Flags located in the Host Computer memory 24. There is one Dirty Flag 228 in each computer for each Line of Text in the Shared Memory. The Lines of Text are each an arbitrary fixed length. In one implementation, each Line of Text is 8 bytes long. The MCUdebug program 70 allows an engineer to view the contents of the Target MCU 58 memory in real-time. This means that any changes that the Target MCU 58 makes to the Shared Memory are immediately reflected in the window 432 if the memory changed is in the Visible Memory 424. The display of the Invisible Memory 422 is postponed until the Window 432 is scrolled 436, causing the Invisible Memory 422 to become visible. The MCUdebug program 70 also allows an engineer to modify the display of Target MCU 58 memory displayed in a window 432 on his monitor 34. He just has to "point and click". Changes to the memory are performed by the Station Controller 42 in real-time, without requiring a Target MCU 58 to stop and interrupt what it is doing. Thus, automotive engineers can tweak timing parameters without having to start and stop an engine being timed by the Target MCU 58. This real-time display and modification of the Target MCU 58 memory provides substantial improvements in MCU testing for users of the MCUdebug system. FIG. 12 through FIG. 18 are flow charts showing the interaction between the Host Computer 20 and the Station Controller 42 in the MDS in maintaining the consistency of the two versions of the Shared Memory. FIG. 12 is a flow chart showing part of the monitor activity of the Station Controller 42. One of the jobs of the Station Controller 42 is to detect changes in the memory shared via the Dual Ported Memory 48 with the Target MCU 58. One method of detecting changes is by keeping a copy of the Shared Memory in the station controller RAM 44. The Station Controller 42 would then periodically compare this copy with the actual Shared Memory. An alternative to this is to checksum each of the lines of Shared Memory, and then to compare the checksums to stored checksums. In either case, the comparisons should be done on a reasonably periodic basis. Since the primary purpose of the comparisons is to make sure the Lines of Text displayed in the window 430 are consistent with the corresponding contents of the Visible Memory 424 portion of the Shared Memory, criteria in determining the frequency of comparisons include the limits of human perceptions. A frequency of 3-5 times a second yields acceptable results. In the flow chart in FIG. 12, the change routine is entered, step 500, and a check is made whether a given Line of Text in the Shared Memory has been changed, step 502. If the line has been changed, a check is made whether the line dirty flag 428 is set, step 504. If the Line Dirty Flag 428 for the changed line not set, it is set, step 506, and a message is sent to the Host Computer 20 that the given Line of Text is now dirty, step 508. Setting the Line Dirty Flag 428 for the Line of Text indicates that the Host Computer 20 has been notified of the change, but that it has not requested that its copy of the line be updated. In any case, the change routine will either return, check the next Line of Text, or restart the change routine with the first Line of Text, step 510, as appropriate. FIG. 13 is a flow chart that shows the actions taken by the Host Computer 20 when a Line Dirty message is received from the MDS 40. As noted in FIG. 12, a Line Dirty message is sent by the Station Controller 42 when it first detects a change in the Shared Memory. The Received Line Dirty Message routine enters, step 516, and checks the corresponding Line Dirty Flag, step 518, in the Host Memory 24. If the Line Dirty Flag is not set, it is set, step 520. Next a check is made whether the corresponding Line of Text is within the displayed window, step 522. If the Line of Text is currently in the displayed window, a message is sent to the Station Controller 42 requesting that the Line of Text be read from the Shared Memory and sent, step 524, to the Host Computer 20. In any case, the routine then exits, step 526. FIG. 14 is a flow chart that shows the actions taken by the Station Controller 42 when it receives a request that a specified Line of Text be read from Shared Memory and sent to the Host Computer 20 (see FIG. 13 flowchart). After a read request is received from the Host Computer 20, the routine is entered, step 590. The corresponding line is read from the Dual Ported Memory 48, step 592, and is sent to the Host Computer 20, step 594. The corresponding Line Dirty flag is cleared, step 596, by the Station Controller 42, and the routine returns, step 598. FIG. 15 is a flow chart that shows the actions taken by the Host Computer 20 when it receives a Line of Text from the MDS 40. This is usually in response to a request by the Host Computer 20 as was shown in FIG. 14. When the updated Line of Text is received, the Line of Text Received routine in the Host is entered, step 530. The corresponding Line Dirty Flag in the Host Memory 24 is cleared, step 532. The shadow copy of the Line of Text in the Host Memory 24 is updated to correspond to the newly received Line of Text, step 534. A check is then made whether the newly updated Line of Text is in the current window, step 536. This is a check whether the Line of Text just received is in the visible portion 422 (see FIG. 11), or Invisible Memory portion 424 of the Shared Memory. If the Line of Text is in the currently displayed window, the corresponding line on the monitor 34 is updated, step 538. In any case, the routine then exits, step 540. FIG. 16 is a flow chart that shows the actions taken by the Host Computer 20 when the MCUdebug operator scrolls the Window 432 (see FIG. 11) by moving the scroll button 436 in the scroll bar 434. The Move Window routine is entered, step 544, and a check is made whether more new Lines of Text are currently in the Window 432, step 546 (i.e. the Lines of Text are in Visible Memory 424). When no more new Lines of Text are in the window 430, the routine exits, step 554, until the screen is again scrolled. Otherwise, the appropriate Line of Text 430 in the Window 432 is updated to display, step 548, the corresponding shadow copy of the Shared Memory stored in the Host Memory 24. Next, the Line Dirty flag is checked for the Line of Text, step 550. If the Line Dirty flag is set, a request is sent to the Station Controller 42 to read the Line of Text from the Shared Memory, step 552. In any case, this is repeated until there are no more new lines in the Window 432. Note here that the shadow copy of Shared Memory is only updated in the Host Memory 24 when scrolling the Window 432 makes the Shared Memory visible 424. FIG. 17 is a flow chart showing the actions of the Host Computer 20 taken to synchronize versions when updating the Shared Memory. This can be triggered by the MCUdebug operator pointing at a location in the memory window 430 and typing in new values, or through batch commands. In either case, the Host Update Line routine is entered, step 560. An Write or Update Request is sent to the Station Controller 42 with the new values for the Line of Text to be modified, step 562. A check is then made whether the Line of Text is currently visible 424 in the Window 430, step 564. If visible, the Line of Text in the Window 430 is updated from the shadow version stored in the Host Memory 24. By restoring the Line of Text in the Window 430 to its pre-modified state, MCUdebug guarantees that the display is consistent with the actual contents of the Shared Memory. In any case, the routine then exits, step 568. FIG. 18 is a flow chart showing the actions taken by the Station Controller 42 when receiving a Write or Update command from the Host Computer 20. This command is usually generated as in FIG. 17 through commands by the MCUdebug operator to Write or Update Shared Memory. The routine is entered, step 570, and the Dual Ported Memory 48 is written to correspond to the Write command, step 572. The corresponding Line Dirty flag 428 is then checked, step 574. If the Line Dirty flag 428 is not set, it is set, step 576, and a Line Dirty message is then sent to the Host Computer 20, step 578. Note that upon receipt of this message, the Host Computer would then request that the line be Read from Shared Memory and returned, if the Line of Text is currently in the visible portion of Shared Memory 424 (see FIG. 13 flowchart). Finally, the routine returns, step 580. FIG. 19 is a flow chart showing the operation of the MCUdebug restart facility. It will be remembered that the MCUdebug user has the capability of recording all debug commands issued in a script or log file. Screen commands, such as inline modification of memory, are translated into and recorded as command line type debug commands. The restart facility starts, step 600, and initializes, step 602. The initialization, step 602, includes loading the Target MCU program into the Target MCU memory 48, 62, setting the Target MCU 58 program counter ("pc") to the appropriate start location, initializing variables, clearing the remainder of the Target MCU memory 48, 62, loading symbol tables into the Host Memory 24, opening source code files, displaying the text around the start location in the symbolic listing of the Target MCU program, and highlighting the start location in the symbolic listing window. This results in the application initialized to begin at a known initial state. After initialization, step 602, the restart facility checks the script or log file for more log entries, step 604. If no more log entries are found, step 604, the restart facility exits, step 606, leaving the Target MCU in the state it was in at the time the log was closed or restart entry was inserted in the script or log file. Otherwise, a check is made for commands in the script or log file, step 608. If there are commands to issue in the script or log file, they are sent by the Host computer 20 to the MDS 40 for execution, step 610. In any case, a Start command for the Target MCU 58 is then sent by the Host computer 20 to the MDS 40, step 612. The restart facility in the Host computer 20 then waits until the Target MCU 58 again stops, step 614. Steps 604-614 are repeated until no more script or log entries are found, step 604. One of the primary purposes for the MCUdebug system is to facilitate testing and debugging MCU configurations and programs before being embedded in Integrated Circuits (IC). The MCUdebug system significantly reduces circuit design turnaround. The manufacture of Integrated Circuits is extensively disclosed in the two volumes of "Silicon Processing for the VLSI Era" by Stanley Wolf, published by Lattice Press of Sunset Beach, Calif. Volume I subtitled "Process Technology" was copyrighted in 1986 by Lattice Press and has an ISBM of 0-961672-3-7. Volume II subtitled "Process Integration" was copyrighted in 1990 by Lattice Press and has an ISBM of 0-961672-4-5. Both volumes are incorporated herein by reference for the purpose of teaching the manufacture of Integrated Circuits. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.
APPENDIX
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Equates for MC68HC05P9 MCU Paced Loop Example Program
Bit names are labled with <port name><bit number> (ex.
PA7 equates to the seventh bit of port A. Bit names
are used in the commands that operate on individual
bits, such as BSET and BCLR.
A bit name followed by a dot indicates a label that
will be used to form a bit mask.
This equates file contains only a subset of the HC05P9
memory map--primarily those used by this paced loop
example program. To include the other ports and
registers of the P9, please consult the MC68HC05P9
Technical Data reference manual.
$BASE 10T
PORTA EQU $00 ;I/O PORT A
PA7 EQU 7 ;BIT#7 OF PORT A
PA6 EQU 6
PA5 EQU 5
PA4 EQU 4
PA3 EQU 3
PA2 EQU 2
PA1 EQU 1
PA0 EQU 0
PA7. EQU $80 ;BIT POSITION PA7
PA6. EQU $40
PA5. EQU $20
PA4. EQU $10
PA3. EQU $08
PA2. EQU $04
PA1. EQU $02
PA0. EQU $01
DDRA EQU $04 ;PORT A DATA DIRECTION REGISTER
DDRA7 EQU 7 ;BIT #7 OF PORT A DDR
DDRA6 EQU 6
DDRA5 EQU 5
DDRA4 EQU 4
DDRA3 EQU 3
DDRA2 EQU 2
DDRA1 EQU 1
DDRA0 EQU 0
DDRA7. EQU $80 ;BIT POSITION OF DDRA7
DDRA6 EQU $40
DDRA5. EQU $20
DDRA4. EQU $10
DDRA3. EQU $08
DDRA2. EQU $04
DDRA1. EQU $02
DDRA0. EQU $01
TCR EQU $12 ;TIMER CONTROL REGISTER
ICIE EQU 7 ;INPUT CAPTURE INTERRUPT ENABLE BIT
OCIE EQU 6 ;OUTPUT COMPARE INTERRUPT ENABLE BIT
TOIE ;TIMER OVERFLOW INTERRUPT ENABLE BIT
ICIE. EQU $80 ;INPUT CAPTURE INTERRUPT BIT POSITION
OCIE. EQU $40 ;OUTPUT COMPARE INTERRUPT BIT POSITION
TOIE. EQU $20 ;TIMER OVERFLOW INTERRUPT BIT POSITION
TSR EQU $13 ;TIMER STATUS REGISTER
ICF EQU 7 ;INPUT CAPTURE FLAG BIT
OCF EQU 6 ;OUTPUT COMPARE FLAG BIT
TOF EQU 5 ;TIMER OVERFLOW FLAG BIT
ICF. EQU $80 ;INPUT CAPTURE FLAG BIT POSITION
OCF. EQU $40 ;OUTPUT COMPARE BIT POSITION
TOF. EQU $20 ;TIMER BIT POSITION
OCRH EQU $16 ;OUTPUT COMPARE REGISTER (HIGH BYTE)
OCRL EQU $17 ;OUTPUT COMPARE REG (LOW BYTE)
TCRH EQU $18 ;TIMER COUNTER REGISTER (HIGH BYTE)
TCRL EQU $19 ;TIMER COUNTER REG (LOW BYTE)
ACRH EQU $1A ;ALTERNATE COUNTER REG (HIGH BYTE)
ACRL EQU $1B ;ALTERNATE COUNTER REG (LOW BYTE)
RAMStart
EQU $00C0 ;START OF ON-CHIP RAM
ROMStart
EQU $0100 ;START OF ON-CHIP ROM
ROMEnd EQU $08FF ;END OF ON-CHIP ROM
Vectors
EQU $1FF8 ;RESET/INTERRUPT VECTOR AREA
Application specific equates
LED EQU PA7 ;LED ON WHEN PA7 IS LOW
LED. EQU PA7. ,LED BIT POSITION
Put program variables here (Use RMBs)
ORG $00C0 ;START OF 705P9 RAM
OCFs RMB 1 ;3 OUTPUT COMPARE INTERRUPTS/TIC (3-0)
TIC RMB 1 ;10 TICS = 1 TOC (10-0) (MSB=1 INDICATES
;OCFs ROLLOVER)
TOC RMB 1 ;1 TOC=10 TICS (1 TIC = 3 OUTPUT COMPARE
;INTERRUPTS = 3 * 131.072ms OR 393.216ms)
;THUS 1 TOC = 10 * 393.216ms = 3.93216s)
Program area starts here
ORG $0100 ;START OF 705P9 ROM
START CLRA ;Clear the accumulator
STA PORTA ;TURN OFF LED
LDA #led. ;configure led
STA DDRA ;MAKE LED PIN AN OUTPUT
LDA #OCIE. ;ENABLE OUTPUT COMPARE INTERRUPTS
STA TCR
BRCLR OCF,TSR,NEXT ;IF OCF IS NOT SET, SKIP INTERRUPT FLAG
RESET
LDA TSR ;READ TIMER STATUS & OUTPUT COMPARE
REGISTER
LDA OCRL ;TO CLEAR THE INTERRUPT
NEXT LDA #3 ;OCFs COUNT 3.fwdarw.0
STA OCFs ;SET OUTPUT COMPARE INTERRUPT COUNT
TO 3
CLR TIC ;INITIALIZE VALUE FOR TIC
CLR TOC ;INITIALIZE VALUE FOR TOC
LDA TCRH ;READ HIGH BYTE OF TIMER COUNT
STA OCRH ;STORE COUNT INTO HIGH BYTE OF OCR
LDA TCRL ;READ LOW BYTE OF TCNT AND STORE TO OCR
STA OCRL ;SET OCR SO THAT INTERRUPT IS GENERATED
;ON THE NEXT OCCURENCE OF THE COUNT VALUE
;COPIED FROM THE TIMER COUNTER REGISTER.
;THIS COUNT WILL OCCUR AFTER ONE COMPLETE
;CYCLE OF THE COUNTER, THAT IS 262,144 CYCLES
;FOR A TOTAL OF 131.072ms OF TIME (2 MHz INT
;OPERATING FREQUENCY)
CLI ;CLEAR I BIT IN STATUS REG TO ENABLE INTERRUPT
MAIN -- Beginning of main program loop. Loop is
executed once every 400ms (393.216ms). A pass through
all major task routinestakes less than 400mS and then
time is wasted until MSB of TIC is set (every 3 OCFs
interrupts=393.216ms). At each OCF interrupt, the
interrupt is serviced (OCFs gets decremented (3.fwdarw.0)
and then cleared by reading the TSR and low byte of
the Output Compare Register (OCRL). When OCFs=0, MSB
of TIC gets set and OCFs is set back to 3.
(3*131.072ms/OCF = 393.216ms)
The variable TIC keeps track of 400ms periods. When
TIC increments from 9 to 10 it is cleared to 0 and TOC
is incremented (i.e. at 4 second intervals).
MAIN BRCLR
7,TIC,MAIN
;LOOP HERE UNTIL TIC FLAG IS SET
LDA TIC ;GET CURRENT TIC VALUE
AND #$0F ;CLEARS MSB
INCA ;TIC=TIC+1
STA TIC ;UPDATE TIC
CMP #10 ;10TH TIC?
BNE ARNC1 ;IF NOT, SKIP NEXT CLEAR
CLR TIC ;CLEAR TIC ON 10TH
ARNC1 EQU *
End of synchronization to 400ms TIC; Run main tasks &
branch back to main within 400ms.
JSR TIME ;UPDATE TOCS
JSR BLINK ;BLINK LED
Other main tasks may be inserted here.
BRA MAIN ;BACK TO MAIN LOOP FOR NEXT TIC
END of Main Loop
TIME -- Update TOCs (Update occurs following TIC roll-
over from 10 to 0)
If TIC=0, increment 0.fwdarw.59
Else, just skip the whole routine
TIME EQU *
TST TIC ;UPDATE TOCS
BNE XTIME ;IF TIC<>0, JUST EXIT
INC TOC ;TOC=TOC+1
LDA #60
CMP TOC ;TOC=60?
BNE XTIME ;IF NOT, JUST EXIT
CLR TOC ;TOCs ROLLOVER
XTIME RTS ;RETURN FROM TIME
BLINK -- Update LED
If TOC is even, light LED
Else turn LED off
BLINK EQU *
LDA TOC ;IF EVEN, LSB WILL BE ZERO
LSRA ;SHIFT LSB TO CARRY
BCS LEDOFF ;IF NOT, TURN LED OFF
BSET LED,PORTA
;TURN ON LED
BRA XBLINK ;THEN EXIT
LEDOFF BCLR LED,PORTA
;TURN OFF LED
XBLINK RTS
OCF Interrupt Service Routine
OCFCNT DEC OCFs ;ON EACH OCF, DECREMENT OCFs
BNE ENDRTI ;DONE IF OCFs NOT ZERO
LDA #3 ;OCFs COUNTS 3.fwdarw.0
STA OCFs ;RESET OCFs COUNT
BSET 7,TIC ;SET MSB AS A FLAG TO MAIN
ENDRTI LDA TSR ;CLEAR OCF INTERRUPT
LDA OCRL
AnRTI RTI ;RETURN FROM OCF INTERRUPT
UNUSED EQU AnRTI ;USE RTI AT AnRTI FOR UNUSED
;INTERRUPTS TO JUST RETURN
Interrupt & reset vectors
ORG $1FF8 ;START OF VECTOR AREA
TIMEVEC
FDB OCFCNT ;COUNT OCFs 3/TIC
IRQVEC FDB ;CHANGE IF VECTOR USED
SWIVEC FDB UNUSED ;CHANGE IF VECTOR USED
RESETV FDB START ;BEGINNING OF PROGRAM ON RESET
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