Modem with firmware upgrade feature

Abstract

Updated operating code and parameters can be reprogrammed into a modem system with no disassembly of the modem hardware. The modem system includes a memory chip in which operating code and parameters are stored. Two control programs control the reprogramming of updated operating code. One of the control programs is designed for manufacturing and testing purposes. The other control program allows remote reprogramming of updated operating code or parameters from a remote location such as a customer site. A user can thus remotely upgrade system firmware with updates, bug fixes, enhancements or other new releases of system operating code by downloading the update over a phone line to a host PC and reprogramming the memory chip of the modem over the serial port from the host PC. The user can also remotely upgrade the modem system firmware by directly programming the memory chip of the modem without the assistance of the host PC. The modem system is portable, obtaining power from a standard 9 volt battery. Therefore, various power saving features are also incorporated into the modem system.

Claims

1. An apparatus comprising:

an interface adapted to couple with a communication network;

a controller coupled to the interface;

a boot program executable by the controller;

a first operating code to control the apparatus;

a first memory coupled to the controller and adapted to store the boot program and the first operating code; and

a second memory coupled to the controller, the controller operable for executing the boot program to receive a plurality of packets from a remote computer coupled to the communication network and to check the validity of each packet of the plurality of packets and to store a portion of each packet in a second memory coupled to the controller, and after receiving an upgrade command from the remote computer and after checking the validity, to replace the first operating code with a second operating code based on the portion of each packet stored in the second memory.

2. The apparatus of claim 1 further comprising a serial line interface coupled to the controller and adapted to couple with a local computer.

3. The apparatus of claim 1 wherein the interface includes a telephone line coupler.

4. The apparatus of claim 1 further comprising a data pump coupled to the controller.

5. The apparatus of claim 1 wherein the second memory includes random access memory (RAM).

6. The apparatus of claim 1 wherein the first memory includes programmable read only memory (PROM).

7. The apparatus of claim 1 further comprising a modem adapted for communicating with the remote computer.

8. A method comprising:

coupling a modem to a communication network;

executing a boot program of the modem;

executing a first operating code for the modem stored in a first memory of the modem based on an instruction executed by the boot program;

receiving a plurality of packets via the communication network;

checking validity of each packet of the plurality of packets;

storing a portion of each packet of the plurality of packets in a second memory of the modem; and

after receiving an upgrade command via the communication network replacing the first operating code in the first memory with a second operating code based on the portion of each packet of the plurality of packets stored in the second memory.

9. The method of claim 8 further comprising executing the boot program after replacing the first operating code in the first memory with the second operating code.

10. The method of claim 8 wherein storing the portion of each packet of the plurality of packets in the second memory includes storing the portion in a location of the second memory based on an address of each packet.

11. The method of claim 8 further comprising copying the boot program to a random access memory.

12. The method of claim 8 wherein checking validity includes checking for errors.

13. The method of claim 8 further comprising generating a local checksum data byte at the modem.

14. The method of claim 13 further comprising receiving a remote checksum via the communication network and comparing the local checksum and the remote checksum.

15. The method of claim 8 further comprising executing a hard boot of the modem.

16. The method of claim 15 wherein executing the hard boot of the modem includes executing the second operating code.

17. The method of claim 8 wherein receiving the plurality of packets includes receiving a plurality of packets each packet having a field containing a packet length and a checksum.

18. A method comprising:

executing a first operating code stored in a first memory;

receiving a plurality of packets via a communication network, each packet having an address field having an address and an operating code field having a portion of program data;

checking each packet of the plurality of packets for validity;

for each packet, storing the portion of program data of the packet at an address of a second memory based on the address of the packet; and

after receiving an upgrade command via the communication network, replacing the first operating code in the first memory with a second operating code based on the program data stored in the second memory.

19. The method of claim 18 wherein checking each packet of the plurality of packets for validity includes comparing a checksum.

20. The method of claim 18 further comprising executing the first operating code if a packet of the plurality of packets includes an error.

21. The method of claim 18 wherein replacing the first operating code in the first memory with the second operating code includes reprogramming a flash programmable read only memory (PROM).

Description

FIELD OF THE INVENTION

The present invention relates to communications systems and in particular to a modem in which the firmware which controls the operation of the modem can be changed or upgraded remotely.

BACKGROUND

Presently, there are several mechanisms through which software upgrades, bug fixes and the like are distributed to users. In systems employing firmware storage of operating programs, such as Electrically Programmable Read Only Memory (EPROM) and the like, bug fixes or enhancements to system firmware require programming a new EPROM with the updated code and shipping the new EPROM to the customer. A technician then travels to the site, disassembles the hardware, and replaces the old EPROM with the new one.

Unfortunately, these methods are very inconvenient. First, a considerable time delay is encountered while waiting for the manufacturer to program and ship the replacement parts. Second, the hardware may not be operable if the user is waiting for a bug fix. Especially true in cases of bug fixes where the hardware might not be operable without the updated operating code. Also, the replacement of the old with the new EPROM requires a technician to travel to the site and use special tools to disassemble the hardware and replace the outdated on faulty part or parts. This results in an increased expense for repairs or upgrades because technician time and special tools are required. Current update methods are thus time consuming, expensive and inefficient.

There is a need in the art, therefore, for a modem which allows remote changes and/or upgrades to be made to the firmware stored operating code, without requiring disassembly and replacement of parts, technician time, or special tools, thus resulting in the more efficient and cost effective means of updating firmware.

SUMMARY

To overcome the shortcomings in the art described above, and to provide other advantages which will become apparent upon reading and understanding the present specification, the present system is a modem system which includes hardware and software components. The system allows the user to connect to remote locations equipped with a similar system or with modems or facsimile machines over a single analog telephone line. The incorporation of various power saving features allow practical implementation of a small, lightweight and easily transportable modem system powered from a standard 9 volt battery. The present modem system also incorporates storage of operating code and parameters in an in-circuit reprogrammable memory chip. Multiple embodiments of the present invention are discussed which allow for remote programming of the modem system. In one embodiment, a user can thus remotely upgrade system firmware with updates, bug fixes, enhancements or other new releases of system operating code by downloading the update over a phone line to a host PC and reprogramming the memory chip of the modem over the serial port from the host PC. In another embodiment, the user can remotely upgrade the modem system firmware by directly programming the memory chip of the modem without the assistance of the host PC.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings, where like numerals refer to like components throughout the several views:

FIG. 1 shows the telecommunications environment within which the present system may operate;

FIG. 2 is a block diagram of the hardware components of the present system;

FIG. 3 is a key for viewing the detailed electrical schematic diagrams of FIGS. 4A-6C to facilitate understanding of the interconnections between the drawings;

FIGS. 4A-4E, 5A-5C and 6A-6C are detailed electrical schematic diagrams of the circuitry of the hardware components of the present system;

FIG. 7 shows a flow diagram of the process for downloading the HEX files containing the updated operating code from a bulletin board to the host PC in a first embodiment of the present invention;

FIGS. 8A-8C show a flow diagram of the upgrade control program from the perspective of the host PC in a first embodiment of the present invention;

FIGS. 9A-9D show a flow diagram of the upgrade control program from the perspective of the modem in a first embodiment of the present invention;

FIG. 10 shows a flow diagram of the process for directly downloading files containing updated operating code from a remote PC to the modem in a second embodiment of the present invention;

FIGS. 11A-11C show a flow diagram of the upgrade control program from the perspective of the remote PC in a second embodiment of the present invention; and

FIGS. 12A-12D show a flow diagram of the upgrade control program from the perspective of the modem in a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present inventions is defined by the appended claims.

FIG. 1 shows a typical arrangement for the use of the present modem system. Hardware components 20 contain the present modem system and are connected to laptop computer 10. Hardware components 20 communicate over a standard telephone line 30 to one of a variety of remote sites. For example, one of the remote sites may be equipped with the present modem system including hardware components 20a and laptop computer 10a. The present modem system can also connect over phone lines 30 to fax machine 60, to a personal computer and associated modem 40, or to a network of personal computers 90. Those skilled in the art will readily recognize the wide variety of communication interconnections possible with the present system by reading and understanding the following detailed description.

Hardware Components

FIG. 2 is a block diagram of the hardware components of the present system corresponding to reference number 20 of FIG. 1. These components form the link between the user, the laptop or personal computer (PC) and the telephone line interface.

The preferred embodiment of the present system preferably includes a data pump circuit 211, which includes a digital telephone coder-decoder (CODEC) and a digital signal processor (DSP) for communicating over the telephone line interface 209. The data pump DSP of circuit 211 performs functions such as modulation, demodulation and echo cancellation to communicate over the telephone line interface 209 using a plurality of telecommunications standards including FAX and modem protocols. The main controller circuit 213 directly controls the DSP data pump circuit 211.

As described more fully below, the main controller circuit 213 includes, in the preferred embodiment, a microprocessor which controls the functions and operation of all of the hardware components shown in FIG. 2. The main controller is connected to RAM circuit 216 and a programmable and electrically erasable read only memory or Flash PROM circuit 217. The Flash PROM circuit 217 includes non-volatile memory in which the executable control programs for the main controller circuits 213 are stored.

The RS232 serial interface 215 communicates to the serial port of the personal computer which is running the software components in the first embodiment of the present system. The RS232 serial interface circuit 215 is connected to a serial input/output circuit 214 with main controller circuit 213.

In one embodiment of the present invention, data is received from the telephone line over telephone line interface circuit 209 and forwarded by the data pump circuit 211 and the main controller circuit 213 over the serial line interface circuit 215 to the personal computer. If the data is upgrade program data, then it is processed and transmitted back to serial line interface circuit 215 to be loaded into RAM circuit 216, and ultimately, into Flash PROM circuit 217.

In a second embodiment of the present invention, upgrade program data is received from the telephone line over telephone line interface circuit 209 and stored in RAM 216 via data pump circuit 211 and main controller circuit 213. The upgrade program data stored in RAM circuit 216 is later programmed into Flash PROM circuit 217.

Detailed Electrical Schematic Diagrams

The detailed electrical schematic diagrams comprise FIGS. 4A-E, 5A-C, 6A-C and 7A-C. FIG. 3 shows a key for how the schematic diagrams may be conveniently arranged to view the passing of signals on the electrical lines between the diagrams. The electrical connections between the electrical schematic diagrams are through the designators listed next to each wire. For example, on the right side of FIG. 4A, address lines A0-A19 are attached to an address bus for which the individual electrical lines may appear on other pages as A0-A19 or may collectively be connected to other schematic diagrams through the designator "A" in the circle connected to the collective bus. In a like fashion, other electrical lines designated with symbols such as RNGL on the lower left-hand side of FIG. 4A may connect to other schematic diagrams using the same signal designator RNGL.

Beginning with the electrical schematic diagram of FIGS. 4D and 4E, the DAA circuitry (telephone line interface) is shown. The telephone line connection in the preferred embodiment is through connector J201 which is a standard six-pin modular RJ-11 jack. In the schematic diagram of FIG. 4E, only the tip and ring connections of the first telephone circuit of the RJ-11 modular connector are used. Ferrite beads FB201 and FB202 are placed on the tip and ring wires of the telephone line connections to reduce high frequency or RF noise that may radiate from telephone line. The incoming telephone line is also overvoltage protected through SIDACTOR R205. The incoming telephone line is full wave rectified by the full wave bridge comprised of diodes CR230, CR226, CR227 and CR228 of FIG. 4D.

Also connected across the incoming telephone line is a ring detect circuit. Optical isolator U220 (part model number CNY17) senses the ring voltage threshold when it exceeds the breakdown voltages on zener diodes CR201 and CR202.

The DAA circuitry is physically isolated from the rest of the system by transformer T1, optocoupler U220 and two solid state relays X215 and X202 which are optically coupled. Connector J203 is a four pin header used for automatic testing during manufacturing and for diagnostics.

Relay X215 shown in FIG. 4D is used to accomplish pulse dialing by opening and shorting the tip and ring wires. Transistor Q203 along with the associated discrete resistors comprise a holding circuit to provide a current path or current loop on the telephone line to grab the line. The DAA circuitry shown in FIGS. 4D and 4E can be customized to interface to the varying telephone standards used in the United States and in many different European countries.

Connector J202 shown in FIG. 4D connects the telephone line interface circuitry described above to connector J102 shown in FIG. 6A and thusly to the rest of the circuit. Incoming RXA signals are buffered by the two operational amplifiers U104 as shown in FIG. 6B. The first stage of buffering is used to drive the transmit carrier signal to the telephone line. The second stage of the input buffering is configured for a moderate amount of gain before driving the signal into CODEC U101. This stage is also used to reduce the amount of transmit signal that is fed back into the receiver. The signal from amplifiers U104 is also fed to speaker driver U105, which drives speaker X101.

Data and address buses A and B shown in FIGS. 4A and 4B connect the Z80180 microprocessor in microcontroller U5 with the Z80 KIO circuit U4 and a gate array circuit U3, and to other portions of the electrical schematic diagrams. Gate array U3, also shown in FIGS. 4A and 4B, includes the "glue logic" used to support various functions in the hardware components of the present invention. Gate array U3 includes miscellaneous latch and buffer circuits for the present system which normally would be found in discrete SSI or MSI integrated circuits. By combining a wide variety of miscellaneous support circuits into a single gate array, a much reduced design complexity and manufacturing cost is achieved.

CODEC chip U101 shown in FIG. 6B, interface chip U1 shown in FIG. 5A and digital signal processor (DSP) chip U2 shown in FIG. 5A comprise a data pump chip set manufactured and sold by AT&T Microelectronics. A detailed description of the operation of these three chips in direct connection and cooperation with one another is described in the publication entitled "AT&T V.32bis/V.32/FAX High-Speed Data Pump Chip Set Data Book" published by AT&T Microelectronics, December 1991, which is incorporated herein by reference. This AT&T data pump chip set comprises the core of an integrated, two-wire full duplex modem which is capable of operation over standard telephone lines or leased lines. The data pump chip set conforms to the telecommunications specifications in CCITT recommendations V.32bis, V.32, V.22bis, V.22, V.23, V.21 and is compatible with the Bell 212A and 103 modems. Speeds of 14,400, 9600, 4800, 2400, 1200, 12,000 and 300 bits per second are supported. This data pump chip set consists of a ROM-coded DSP16A digital signal processor U2, and interface chip U1 and an AT&T T7525 linear CODEC U101. The AT&T data pump chip set is available from AT&T Microelectronics.

The chip set U1, U101 and U2 on FIGS. 5A and 6B perform all A/D, D/A, modulation, demodulation and echo cancellation of all signals placed on or taken from the telephone line, and performs DTMF tone generation and detection, signal analysis of call progress tones, etc. The transmission of information on the telephone line from CODEC U101 is through buffers U104, and through line buffer U105 as described above.

The main controller of controller circuit 213 and the support circuits 212, 214, 215, 216 and 217 are shown in FIGS. 4A-4C and 5A. In the preferred embodiment of the present system, the main controller U5 shown in FIGS. 4A and 4B is a Z80180 eight-bit microcontroller chip. In the preferred implementation, microcontroller chip U5 is a Z80180 microprocessor, by Zilog, Inc. of Campbell, Calif. The Zilog Z80180 eight-bit microprocessor operates at a 12.288 MHz internal clock speed by means of an external crystal XTAL, which in the preferred embodiment, is a 24.576 MHz crystal. The crystal circuit includes capacitors C1 and C2 which are 20 pf capacitors and resistor R15 which is a 33 ohm resistor. The crystal and support circuitry is connected according to manufacturer's specifications found in the Zilog Intelligent Peripheral Controllers Data Book published by Zilog, Inc. The product description for the Z80180 Z180 MPU from the Z80 CPU Product Specification pages 351-392 of the Zilog 1991 Intelligent Peripheral Controllers databook is incorporated herein by reference.

The Z80180 microprocessor in microcontroller chip U5 is intimately connected to a serial/parallel I/O counter timer chip U4 which is, in the preferred embodiment, a Zilog 84C90 CMOS Z80 KIO serial/parallel/counter/timer integrated circuit available from Zilog, Inc. This multi-function I/O chip U4 combines the functions of a parallel input/output port, a serial input/output port, bus control circuitry, and a clock timer circuit in one chip. The Zilog Z84C90 product specification describes the detailed internal operations of this circuit in the Zilog Intelligent Peripheral Controllers 1991 Handbook available from Zilog, Inc. Z84C90 CMOS Z80KIO Product specification pgs. 205-224 of the Zilog 1991 Intelligent Peripheral Controllers databook is incorporated herein by reference.

The memory chips which operate in conjunction with the Z180 microprocessor in microcontroller chip U5 are shown in FIG. 4C. The connections A, B correspond to the connections to the address and data buses, respectively, found on FIG. 4A. Memory chip U7 is a read-only memory (ROM) chip which is electrically reprogrammable in circuit. This programmable ROM, typically referred to as a flash PROM, holds the operating code and operating parameters for the present system in a non-volatile memory. Upon power-up, microcontroller chip U5 executes the program code that is stored in the flash PROM U7. In the preferred embodiment, RAM chip U6 is a pseudostatic RAM which is a dynamic RAM with a built-in refresh. Those skilled in the art will readily recognize that a wide variety of memory chips may be used and substituted for pseudo-static RAM U6 and flash PROM U7 without departing from the scope of the present invention.

The interface between the main controller circuit 213 and the personal computer is through SIO circuit 214 and RS232 serial interface 215. RS232 connection J103 is shown on FIG. 6A with the associated RS232 driver circuit U102 and interface and ring detect circuitry used to generate and receive the appropriate RS232 standard signals for a serial communications interface with a personal computer.

FIG. 6C is a detailed electrical schematic diagram showing the generation of various voltages for powering the hardware components of the electrical schematic diagrams described herein. The power for the present hardware components described herein is received from either a standard 9 volt battery or through AC adaptor J104 which is a standard 3 Pin Power Jack. When the AC adaptor is plugged in, the battery is disconnected. Power is controlled by power switch S101. The preferred modem system is designed to run off of a standard 9 Volt battery, thus resulting in a small, lightweight and easily transportable package. However, it shall be understood that the modem could also be run from any other power source using standard interfaces and conversion circuitry known well in the art. 5 volt regulator U107 is a linear regulator with a low drop out voltage of about 5.3. Q102 is a MOSFET which controls on/off as directed by power switch S101. Power switch S101 turns on MOSFET Q102, and has three positions, on, off, or auto. In auto position, power switch S101 senses the Data Terminal Ready Signal from the computer, and if that is not present, then the power to the modem is turned off completely. Thus, if no communications software is loaded, the modem is automatically off such that no power is wasted. From the circuitry of FIG. 6C, the +9 volts DC is regulated down to 5 volts, and is also inverted via U106 to get a negative voltage. The negative voltage is used to drive the RS232 driver U102 shown in FIG. 6A. As a result, five volts are derived for operating the various memory, logic and controller chips and support circuitry of the present system.

FIG. 5B shows connector J1 which interfaces with connector J101 shown in FIG. 6A. FIG. 5C shows the interconnection of the status LED's found on the front display of the modem of the present invention.

Power Saving Features

Referring again to FIG. 5A, the interface chip U1, discussed in detail above is shown. Also shown in the upper left portion of FIG. 5A is power saving circuitry which is incorporated into the present modem system to enable the practical implementation of a small, lightweight and easily portable modem suitable for use with a laptop computer, for example. The power saving features of the present modem system allow the design to be powered from a standard 9 volt battery as discussed above with respect to FIG. 6C.

In order to conserve power, various power saving features are provided which allow the present modem system to be put in a low power, or "sleep" mode. In sleep mode the power to the modem is greatly reduced. There are three main power saving features in the sleep mode. First, additional circuitry has been added in the preferred embodiment to allow additional power savings to be realized. Second, the AT&T data pump chip set has a built in low power mode. Third, the Z180 MPU U5 also has a built in low power mode.

The AT&T data pump chip set U1, U2 and U101 described in detail above has the ability to be put into a low power mode. When in low power mode, the CODEC bit clock TCODEC generated by interface chip U1 shown on FIG. 5A is slowed to 115 kHz to provide a required clock signal to DSP chip U2 and CODEC U101. The data pump chip set enters sleep mode automatically after a reset, a disconnect or by user command. The chip set automatically wakes up when a ring signal or host command is received. The built-in sleep mode of the AT&T data pump chip set is described in more detail in the aforementioned publication entitled "AT&T V.32 bits/V.32/FAX High-Speed Data Pump Chip Set Data Book" published by AT&T Microelectronics, December 1991.

In addition to the power saving sleep mode provided by the AT&T data pump chip set U1, U2 and U101, the present invention provides additional power saving features. These features include providing an external clock oscillator XTL1. Circuitry is provided such that external clock oscillator XTL1 can also be put in sleep mode (disabled). This results in a significant power savings as the oscillator would consume power unnecessarily when the modem is not in use. When XTL1 is disabled, the clock to CODEC U101 is switched to a low frequency, approximately 100 KHz signal generated from K10 U4 of FIG. 4A via NAND gate U10 of FIG. 5B.

Crystal XTL2 is a 20.275 MHZ crystal which is used in conjunction with an internal oscillator provided on interface chip U1. The internal oscillator is described in the above listed documentation for interface chip U1.

The present modem system can be assembled with either the crystal XTL2/C17/C18 combination or the external clock oscillator XTL1/C19 combination. With either combination, the power saving feature built into the AT&T data pump chip set U1, U2 and U101 can be used. However, with the XTL1/C19 combination the AT&T data pump chip set power saving feature and also the additional feature of disabling external oscillator XTAL1 can be used for even greater power savings. External clock oscillator XTL1 is part number CO2810 available from Raltron Corporation of Miami, Fla. External clock oscillator XTL1 has a frequency of 40.5504 MHz and is described in more detail in the publication entitled "CLOCK OSC, Model CO2810 Series (SMD Type OSC)", published by Raltron Corporation, which is incorporated herein by reference. In the preferred embodiment, external clock oscillator XTL1 is used as the main clock for the AT&T data pump chip set U1, U2 and U101 and runs at 40.5504 MHZ to drive the interface chip U1.

When the present modem system is off-hook and the Z180 MPU U5 is not processing, the Z180 MPU U5 can be put into a low power or SLEEP mode. The Z180 MPU SLEEP mode places the CPU into a state in which the internal CPU clock stops, thereby consuming less current. The Z180 MPU U5 wakes up when one of the interrupts INT0, INT1 or INT2 shown in FIGS. 4A and 4B is asserted.

INT0 wakes up the Z180 MPU U5 in response to interrupts generated by K10 U4. INT1 wakes up the Z180 MPU U5 in response to a RNGL or watchdog timer (WDOUT-) signal. The watchdog is a slow timer (in the seconds) which allows the processor to keep track of time. For example, the processor must keep track of the time for which the modem cannot call a blacklist of forbidden phone numbers. INT2 wakes up the Z180 MPU U5 in response to a DTE data signal (TD shown in FIG. 5B).

The built in SLEEP mode of the Zilog Z180 MPU U5 is described in more detail in the aforementioned publication Zilog Intelligent Peripheral Controllers 1991 Handbook.

Functional Description of Upgrade Control Program For A First Embodiment of the Modem System

A first embodiment of the modem system includes two control programs which control the remote in-circuit reprogramming of system firmware, a flash control program and a boot control program. In this embodiment, the flash control program runs in the host PC and receives updated operating code downloaded from a bulletin board. The updated code is downloaded to the host PC in the form of Intel HEX files. The flash control program processes the HEX files and creates the packets containing the updated code which are actually sent to the modem. Each packet contains a field containing the packet length, the address at which to store the updated code, the actual program data and a checksum. The boot control program running in the modem checks that the packet was correctly transmitted and programs the updated operating code at the address specified in the address field of the packet.

In summary, the flash control programs control the host PC side of the process of in-circuit reprogramming of flash PROM U7. The boot control program controls the modem side. As described above, flash PROM U7 is an in-circuit programmable and electrically erasable read only memory. As is well known to those of skill in the art, these memory chips allow in-circuit reprogramming of the operating code and parameters which are stored in the flash PROM chip U7. Although the present modem system is described with respect to a particular flash PROM U7, it shall be understood that any in-circuit reprogrammable memory configuration could be used without departing from the scope of the present invention.

Before flash PROM U7 is assembled in the modem circuit, the boot control program is burned, or programmed into flash PROM U7 using conventional PROM programmers and programming techniques.

When a bug fix, enhancement or other new release of system operating code becomes available, the flash control program is used to control the remote loading and processing of operating code downloaded over telephone line from a central bulletin board. The boot control program receives the updated code from the host PC over the serial port and controls in-circuit reprogramming of the new operating code into flash PROM U7.

The field programmable feature of the modem system of the present invention has several advantages. Because a user can remotely load new operating code over a remote telephone connection, code updates can be obtained immediately as soon as they are available instead of waiting for new parts to be shipped. In addition, no physical removal or replacement of parts is required thus significantly reducing the chance of breakages. Further, no special tools are required to remove and replace parts, and no special PROM programming equipment is required to reprogram the memory chips. Finally, the need for a technician to travel to the remote site to perform the upgrade is avoided thus significantly reducing costs associated with the upgrade.

Detailed descriptions of the flash control program and boot control program will now be given. The illustrative embodiments of the flash control program and boot control program described and shown herein is with special reference to a PC-based DOS operating system. It shall be understood, however, that the present invention is in no way limited to a DOS operating system. The preferred modem system can also be used with a UNIX-based operating system, MacIntosh operating system, or any of a number of operating system platforms simply by customizing the user interface to run on the desired operating system.

Detailed Description of Flash Control Program for a First Embodiment of the Present Invention

The flash control program is used to control the reprogramming of updated operating code and parameters into the flash part of the modem.

The updated operating code is distributed to the user according to the procedure shown in FIG. 7. To get the update, HEX files containing the updated operating code are downloaded over a phone line from a computer bulletin board to the host PC. The HEX files are preferably in the Intel MCS-86 HEX format. This is an industry standard for HEX files.

The HEX files contain entirely ASCII characters and include three record types: Data Record, End Record and Extended Address Record. The formats of the three record types are described in detailed at page 27 of the User Manual for the Gtek EPROM programmer model 9000, dated Jan. 11, 1988, which is incorporated herein by reference, and are as follows (next page):

• Inventors
  Nelson, Craig A.; Arimilli, Harinarayana; Johnson, Richard David;
• Assignee
  Multi-Tech Systems, Inc. (Mounds View, MN)
• Published
  Aug-9-2005
• Current US Classes:
  375/222
  717/172
• Application #
  975529
• International Classes
  H04B 001/38; G06F 009/44
• Field of Search
  375/222 375/219 717/168 717/171 717/172 717/173 717/170
• Examiner
  Nguyen; Madeleine
• Agent
  Schwegman, Lundberg, Woessner & Kluth, P.A.
• US Patent References:
  4203006
  4592069
  4725977
  4782462
  4830757
  4893271
  4903263
  4982430
  5001729
  5132716
  5155847
  5175845
  5237610
  5239652
  5268928
  5293376
  5301122
  5305196
  5337044
  5367670
  5390350
  5408522
  5425051
  5428790
  5434849
  5450425