Method for checking the syntax of an instruction list program to determine if the program is expressible as a relay ladder diagram by a programmable logic controller5058052Abstract A method is provided by which a programmable logic controller checks each statement of an instruction list (IL) program to determine if any such statement or the order of statements violates one of a set of syntax rules which are stored in a memory in the controller. If a rule violation is found, an error indication is generated to signify that the particular IL program under test by the controller can not be accurately converted or translated into a relay ladder diagram. However, if no rule violation is found by the controller, then the controller accepts the IL program. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 2
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INSTRUCTION GROUPS
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fblk.sub.-- 0
:: [NOOP ENDSW CEND]
fblk.sub.-- 1x
:: [MCR JUMP]
fblk.sub.-- 1
:: [TMR ADD DPADD SUB
DBSUB MUL DIV MOD EQ NE GT GE
LT LE AND OR NOT MOVEI
MOVIN BMOVI MOVEW MOVWN
BMOVW BLKCL COMRQ INT BCD
DOI/O ROL ROR DPMUL DPDIV
DPMOD DPEQ DPNE DPGT DPGE
DPLT DPLE SYSRQ]
fblk.sub.-- 2
:: [ONDTR UPCTR DNCTR SHL SHR
SHFRI SHFRW]
fblk.sub.-- 3
:: [SEQB]
load :: [LD LD NOT]
and :: [AND AND NOT]
and.sub.-- or
:: [AND AND NOT OR OR NOT]
out :: [OUT OUTM OUT NOT OUTM
NOT SET SETM RST RSTM]
out.sub.-- tr
:: [OUT+ OUT-]
ld.sub.-- bl
:: [LD BLK]
out-bl :: [OUT BLK]
a.sub.-- o.sub.-- bl
:: [AND BLK OR BLK]
nop :: [NOP]
eop :: [<END OF PROGRAM>]
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The NEEDED VARIABLES used in the statement processor are presented below in Table 3.
TABLE 3
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NEEDED VARIABLES
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state :: [0..8] VALUE 0/*9; state validity
check*/
max.sub.-- dp
:: [7 /*30,35*/]; Maximum depth of
stack
stk.sub.-- dp
:: [1..max.sub.-- dp] /* Monitor depth of
stack*/; stack depth
par.sub.-- br
:: [FALSE TRUE] /*Multi-branch
sequence indicator*/
stk.sub.-- cn
:: ARRAY [stk.sub.-- dp] OF [TRUE FALSE]
/*Stack element from
LD BLK*/; stack
counter
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Although the complete statement processor code has been shown in Appendix 1, to further understanding of the invention, a state diagram flow chart of the statement processor program is shown in FIGS. 5A-5I which are now discussed in detail. It is assumed that the statement processor program in programmable logic controller 50 begins processing statements at the first statement of the particular IL program under test. Thus, this first statement of the IL program under test by controller 50 is initially considered to be the subject statement on which the statement processor operates according to the set of rules set forth in Table 1. It is also assumed that when processing the first statement of the IL program, the statement processor starts at State 0 which is seen at the center of the state diagram of FIG. 5A. The terms statement and instruction are used interchangeably herein. After testing of the first statement of the IL program is completed by the statement processor in controller 50, then the next statement in the IL program becomes the subject statement which is subjected to test by the statement processor. Starting in State 0 of FIG. 5A, it is seen that if the subject statement of the IL program is a member of the fblk.sub.-- 0 instruction group of Table 2 (that is, a NOOP, ENDSW or CEND statement as seen in the fblk.sub.-- 0 group of Table 2), then flow returns back to State 0. However, if the subject statement is a member of the load instruction group (LD, LD NOT), then flow continues to State 1. If the subject statement is a member of the eop instruction group (<END OF PROGRAM>), then flow goes to State 8 whereas if the subject statement is a member of the nop instruction group (NOP), then flow continues back to State 0. However, if the subject statement is determined to be a member of none of the above instruction groups of State 0 (that is, neither fblk.sub.-- 0, load, eop nor nop instruction groups), then as indicated by the ELSE flow line in FIG. 5A, a "sequence start error" is issued. This error signifies that the subject statement can not be accurately represented in a relay ladder diagram. Hence if this error or another error occurs during a particular IL program under test by the statement processor in controller 50, this indicates that this IL program is one which can not be converted to a relay ladder diagram. It is noted that each time flow proceeds to another state or loops back to the same state, the statement processor in programmable logic controller 50 proceeds to the next statement in the sequence of instructions in the IL program. This next statement in the IL program then becomes the subject statement. The statement processor in controller 50 then performs the prescribed tests on this subject statement or instruction according to the present state. FIG. 5B is a state diagram of State 1 of the statement processor. When State 1 is entered, flow proceeds to the center circle of the state diagram of FIG. 5B which is designated State 1. If the subject statement under test is a member of the out.sub.-- tr instruction group of Table 2 (namely, OUT+ or OUT-) or a member of the fblk.sub.-- 1x instruction group (namely, MCR or JUMP), then a test is conducted to see if par.sub.-- br (parallel branch) flag is not set. If par.sub.-- br is not set, then flow proceeds back to State 0 and the next statement in the IL program sequence is tested. Otherwise, an "illegal branch error" is issued as indicated in the state diagram of FIG. 5B. An illegal branch error indicates that the subject statement under test is not convertible to a relay ladder diagram. If, however, the subject statement is found to be a member of the and.sub.-- or instruction group (AND, AND NOT, OR, OR NOT) of Table 2, then flow proceeds back to State 1 at which the next statement in the IL program is processed. If the subject statement is determined to be a member of the out instruction group (OUT, OUTM, OUT NOT, OUTM NOT, SET, SETM, RST, RSTM) of Table 2, then flow continues to State 2 and the next IL program statement is processed by the statement processor. However, if the subject statement is found to be a member of the fblk.sub.-- 1 instruction group, then a test is performed to determine if par.sub.-- br is not set. If par.sub.-- br is found to be not set, then flow proceeds to State 3 and the next statement is processed. Otherwise, if par.sub.-- br is found to be set, then an "illegal branch error" is issued. If the subject statement is found to be a member of the load instruction group listed in Table 2, then the stack depth (stk.sub. -- dp) is set to 1, a stack counter stk.sub.-- cn[stk.sub.-- dp] is set to FALSE and flow then continues to State 4 at which the next IL statement is processed. If, however, the subject statement is determined to be a member of the ld.sub.-- bl (load block) instruction group of Table 2, then par.sub.-- br is set to TRUE, the stack depth (stk.sub.-- dp) is set to 1 and the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to TRUE and flow then continues to State 5 at which the next IL statement is processed. If the subject statement is found to be a member of the nop instruction group of Table 2, then process flow loops back to State 1 where the next statement in the IL program sequence is processed. However, if the subject statement is not found to be in any of the instruction groups in the State 2 state diagram above, then an "illegal transition error" is issued and the statement processor is terminated. The generation of the illegal transition error or other error indicates that the statement under test cannot be accurately represented as a relay ladder diagram. FIG. 5C is a state diagram of State 2 of the statement processor in controller 50. When State 2 is entered, flow proceeds to the center circle of the state diagram of FIG. 5C which is designated State 2 and at which par.sub.-- br is set to FALSE. If the subject statement under test is a member of the fblk.sub.-- 0 instruction group, then flow proceeds back to State 0. If the subject statement is found to be a member of the load instruction group, then flow proceeds to State 1. However, if the subject statement is determined to be a member of the out instruction group or the nop instruction group, then flow continues back to State 2. If the subject statement is found to be a member of the eop instruction group, then flow goes to State 8 which is discussed later. If the subject statement is not found to be a member of any of the fblk.sub.-- 0, load, out, eop or nop instruction groups of Table 2, then flow continues along the ELSE line and an "illegal transition error" is issued signifying that conversion is not possible. FIG. 5D is a state diagram of State 3 of the statement processor. The processing of the next statement in the IL program commences at the center of the state diagram of FIG. 5D which is designated State 3. If the subject statement is one of the instructions from instruction groups out.sub.-- tr or fblk.sub.-- 1x of Table 2, then flow proceeds to State 0 at which the next IL program statement is processed. Similarly, if the subject statement is one of the group of instructions from the fblk.sub.-- 0 instruction group, the flow continues to State 0. If the subject statement is from the load instruction group, however, then par.sub.-- br is set to FALSE and flow proceeds to State 1. If the subject statement or instruction is from the out instruction group, then flow continues to State 2. In contrast, if the subject statement is from the fblk.sub.-- 1 instruction group or the nop instruction group, then flow loops back to State 3. If the subject statement is determined to be a member of the eop instruction group then flow continues to State 8. However, if the subject statement is from none of the above instruction groups (out.sub.-- tr, fblk.sub.-- 1x, fblk.sub.-- 0, load, out, fblk.sub.-- 1, eop or nop) then an illegal transition error is issued as seen in FIG. 5D thus signifying that conversion to a relay ladder diagram is not possible. FIG. 5E is a state diagram of State 4 of the statement processor. The processing of the next statement in the IL program commences at the center of the state diagram of FIG. 5E which is designated State 4. If the next statement of the IL program (now the subject statement) is from the a.sub.-- o.sub.-- bl instruction group of Table 2, then a test is conducted to determine if stk.sub.-- cn[stk.sub.-- dp] is FALSE. If it is determined that stk.sub.-- cn[stk.sub.-- dp] is FALSE, then the stack depth stk.sub.-- dp is decremented by 1. A further test is then conducted to determine if the stack depth stk.sub.-- dp is now 0 after such decrementing. If it is determined that the stack depth stk.sub.-- dp is now 0, then flow proceeds to State 1 at which the next IL statement is processed. Otherwise, if the stack depth is not 0, then flow continues to State 4 at which the next IL statement is processed. If in the step of determining if the stack counter stk.sub.-- cn[stk.sub.-- dp] is FALSE, it is determined that the stack counter stk.sub.-- cn[stk.sub.-- dp] is in fact TRUE, then a "stack mismatch error" is issued. Since a stack mismatch error has occurred, this particular IL program is invalid. It will be appreciated that the statement processor checks for a mismatch between the number of PUSHES and the number of POPS, and if such a violation is found where the number of PUSHES and POPS is not equal, then an appropriate stack mismatch error is issued. In this manner a check is provided to determine if a particular IL program is valid in addition to the check to determine if the IL program can otherwise be translated to a relay ladder diagram. If in entering State 4 it is determined that the subject statement is within the fblk.sub.-- 2 instruction group, then a test is made to determine if par.sub.-- br is set to FALSE. If par.sub.-- br is set to FALSE then a further determination is made to find if the stack depth stk.sub.-- dp equals 1. If the stack depth does equal 1, then flow proceeds to State 3. Otherwise, a parameter mismatch error is issued as shown in the state diagram of FIG. 5E. If in the earlier determination of whether par.sub.-- br is set to FALSE, it is determined that par.sub.-- br is set to TRUE, then an illegal branch error is issued as seen in FIG. 5E. If, in entering State 4, it is determined that the subject statement is a member of the fblk.sub.-- 3 instruction group, then a test is made to determine if par.sub.-- br is set to FALSE. If par.sub.-- br is determined to be FALSE, then a further determination is made to find if the stack depth stk.sub.-- dp equals 2. If the stack depth is found to equal 2, then flow proceeds to State 3. Otherwise, a "parameter mismatch error" is issued as shown in the state diagram of FIG. 5E. If however it was determined earlier that par.sub.-- br is set to TRUE, then an "illegal branch error" is issued. If, upon entering State 4, it is determined that the subject statement is a member of the and.sub.-- or instruction group of Table 2, then loops back to State 4 as represented by the State 4 circle in the center of the state diagram of FIG. 5E. If it is determined that upon entering State 4 the subject statement is a member of the load instruction group of Table 2, then a test is made to determine if the stack depth stk.sub.-- dp is less than the maximum stack depth max.sub.-- dp. If it is found that the stack depth stk.sub.-- dp is indeed less than the maximum stack depth max.sub.-- dp, then the stack depth stk.sub.-- dp is incremented by 1, the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to FALSE and flow continues back to State 4. Otherwise, if the stack depth stk.sub.-- dp is not found to be less than the maximum stack depth max.sub.-- dp, then a "stack overflow error" is issued. A stack depth violation is indicated in this manner. If it is determined that upon entering State 4 the subject statement is a member of the ld.sub.-- bl instruction group of Table 2, then a test is made to determine if the stack depth stk.sub.-- dp is less than the maximum stack depth max.sub.-- dp. If it is determined that the stack depth stk.sub.-- dp is less than the maximum stack depth max.sub.-- dp, then par.sub.-- br is set to TRUE, the stack depth stk.sub.-- dp is incremented by 1, the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to TRUE and flow continues back to State 5. Otherwise, if the stack depth stk.sub.-- dp is not found to be less than the maximum stack depth max.sub.-- dp, then an "stack overflow error" is issued indicating that the particular IL program is invalid. If, when State 4 is entered, it is determined that the subject statement is a member of the out instruction group, then flow continues to State 6. However, if when entering State 4 it is determined that the subject statement is a member of the nop instruction group, then flow loops back to State 4 and the next statement in the IL program sequence is processed. If upon entering State 4 it is determined that the subject statement is from none of the above instruction groups (a.sub.-- or.sub.-- bl, fblk.sub.-- 2, fblk.sub.-- 3, and.sub.-- or, load, ld.sub.-- bl, out, nop), then an illegal transition error is issued as seen in FIG. 5E signifying that the IL program is not convertible. FIG. 5F is a state diagram of State 5 of the statement processor. Upon entering State 5, the entry point to which is signified by the circle designated State 5 at the center of the state diagram of FIG. 5, a test is made to determine if the subject statement is a member of the and instruction group. If the subject statement is found to be a member of the and instruction group, then flow loops back to State 5 and the next statement in the IL program is processed. If upon entering State 5, it is determined that the subject statement is a member of the load instruction group, then a further test is made to determine if the stack depth stk.sub.-- dp is less than the maximum stack depth max.sub.-- dp. If so, then the stack depth stk.sub.-- dp is incremented by 1, the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to FALSE and flow proceeds to State 4 at which the next statement in the IL program is processed. If, however, it is determined that the stack depth stk.sub.-- dp is not less than the maximum stack depth max.sub.-- dp, then a "stack overflow error" is issued indicating that the subject IL program is invalid. If upon entering State 5, it is determined that the subject statement is a member of the ld.sub.-- bl instruction group, then a further test is made to determine if the stack depth stk.sub.-- dp is less than the maximum stack depth max.sub.-- dp. If so, the stack depth stk.sub.-- dp is then incremented by 1, the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to TRUE and flow proceeds back to State 5 at which the next statement in the IL program is processed. However, if it is determined that the stack depth stk.sub.-- dp is not less than the maximum stack depth max.sub.-- dp, then a "stack overflow error" is issued. If it is found that upon entering State 5 that the subject statement is a member of the out instruction group, then flow proceeds to State 6 at which the next statement in the IL program is processed. If, however, it is found that when State 5 is entered that the subject statement is a member of the nop instruction group, then flow loops back to State 5 and the next statement or instruction in the IL program is processed. However, if upon entering State 5 it is determined that the subject statement is from none of the above instruction groups (and, load, ld.sub.-- bl, out, nop), then an illegal transition error is issued as seen in FIG. 5F. The illegal transition error signifies that the IL program is not convertible to a relay ladder diagram. FIG. 5G is a state diagram of State 6 of the statement processor. Upon entering State 6, the entry point to which is signified by the circle designated State 6 at the center of the state diagram of FIG. 5G, a test is made to determine if the subject statement is a member of the out instruction group. If the subject statement is found to be a member of the out instruction group, then flow loops back to State 6 and the next statement in the IL program is processed. However, if upon entering State 6, it is determined that the subject statement is a member of the out.sub.-- bl instruction group, then a further test is made to determine if the stack counter stk.sub.-- cn[stk.sub.-- dp] flag is set to true or false. A true flag indicates that the top item on the stack was put there by a Ld.sub.-- bl and not by a load instruction. Since out.sub.-- bl instructions are associated with Ld.sub.-- bl instructions, a true flag results in decrementing of stk.sub.-- dp by 1 and flow proceeds to State 7 at which the next statement in the IL program is processed. If, however, it is determined that the stack counter stk.sub.-- cn[stk.sub.-- dp] is false, then a stack mismatch error is generated. If, upon entering State 6, it is determined that the subject statement is a member of the nop instruction group, then flow loops back to State 6 and the next statement in the IL program is processed. However, if upon entering State 6 it is determined that the subject statement is from none of the instruction groups mentioned above in the discussion of State 6, then an illegal transition error is generated indicating that the subject statement is not accurately translatable to a relay ladder diagram. FIG. 5H is a state diagram of State 7 of the statement processor. If upon entry to State 7 it is found that the subject statement is a member of the and instruction group, then flow proceeds back to State 7. However, if it is found that the subject statement in the IL program is an out statement, then a further test is conducted to determine if the stack depth stk.sub.-- dp is 0. If the stack depth stk.sub.-- dp is found to be 0, then flow continues to State 2 and the next statement of the IL program is processed according to State 2. If the stack depth stk.sub.-- dp is not found to be 0 when the subject statement is from the out instruction group, then flow continues to State 6 where the next IL instruction is processed. If, upon entry to State 7, it is found that the subject statement is a member of the load instruction group, then stack depth stk.sub.-- dp is incremented by 1, the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to FALSE and flow proceeds to State 4 where the next IL program statement is processed. If however, upon entry to State 7 it is determined that the subject instruction is from the ld.sub.-- bl instruction group, then stack depth stk.sub.-- dp is incremented by 1, the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to TRUE and flow proceeds to State 5 where the next IL program statement is processed. Alternatively, if when State 7 is entered it is found that the subject instruction is from the nop instruction group, then flow loops back to State 7. However, if upon entering State 7 it is determined that the subject statement is from none of the instruction groups mentioned above in the discussion of State 7, then an illegal transition error is generated. FIG. 5I is a state diagram of State 8 of the statement processor. Upon entry of State 8, processing of the IL program ends normally. If the statement processor reaches this normal end, this indicates that the tests in the statement processor have found no violations of the set of rules of Table 1 by the IL program under test. Thus the IL program is convertible to a relay ladder diagram and the subject IL program is valid. If, however, the statement processor terminates abnormally (that is, with one of the above described error messages), then the IL program under test is one which is either not convertible to a relay ladder diagram or is otherwise invalid. To illustrate more fully the operation of the method of the present invention in programmable logic controller 50, a discussion is now undertaken of the action of the statement processor on an IL program which is capable of successfully being converted to a relay ladder diagram. For comparison purposes, the action of the statement processor on an IL program which is not convertible to a relay ladder diagram is also discussed later. The IL program of FIG. 3A is an example of one IL program which may be converted to a relay ladder diagram. For purposes of the subsequent discussion, it is assumed that this IL program is loaded into programmable logic controller 50 and that the statement processor stored in RAM 56 performs the above described tests on the IL program to determine if the IL program abides by the set of rules of Table 1. To aid in this discussion, reference is made to the state diagrams of FIGS. 5A-5I. While each statement is being sequentially processed by the statement processor, each statement is referred to as the subject statement for that period of time during which it is being tested by the statement processor program in controller 50. The first statement of the IL program of FIG. 3A is LD % I1 which is now considered to be the subject statement. The statement processor commences processing IL program statements in State 0 and thus reference is now made to the State 0 state diagram of FIG. 5A. At the entry point to State 0 (namely the central circle of the State 0 state diagram), a determination is made as to which instruction group the subject LD statement is a member. It is determined that the subject LD statement is from the load instruction group of Table 2 and thus flow continues to State 1 according to the state diagram of FIG. 5A. The next statement is the IL program, namely the AND % I2 statement, becomes the subject statement which is then tested in State 1 as shown in the State 1 state diagram of FIG. 5B. In State 1, it is determined that the subject AND statement is from the and.sub.-- or instruction group and thus flow loops back to State 1. The next statement in the IL program, namely the LD % I3 statement, becomes the subject statement which is still processed in State 1 of FIG. 5B. In State 1 it is determined that the subject LD % I3 statement is a member of the load instruction group and thus the stack depth stk.sub.-- dp is set to 1, the stack counter stk.sub.-- cn[stk.sub.-- dp] is set to FALSE and flow continues to State 4 at which the next statement in the IL program is processed. It is noted that setting the stack counter stk.sub.-- cn[stk.sub.-- dp] to FALSE indicates that we are dealing with a LOAD instruction (LD) whereas if the stack counter stk.sub.-- cn[stk.sub. -- dp] is set to TRUE indicates that we are dealing with a LOAD BLK (LOAD BLOCK instruction. As previously described, a block signifies an operation on a previous subexpression so that an AND instruction differs from an AND.sub.-- bl instruction. Flow now continues in State 4, shown in FIG. 5E, where the next statement in the IL program, namely OR BLK, becomes the subject statement which is processed. In State 4 it is determined that the subject OR.sub.-- BLK statement is a member of the a.sub.-- o.sub.-- bl (AND or OR block) instruction group and thus a further test is conducted to determine if stk.sub.-- cn[stk.sub.-- dp] is FALSE. From the discussion above, it is seen that in State 4 of FIG. 5E it will be determined that the stk.sub.-- cn[stk.sub.-- dp] stack counter was set to FALSE and thus the stack depth stk.sub.-- dp (which was 1) is decremented by 1. Thus the stack depth stk.sub.-- dp is now set to 0. Yet another test is then conducted to determine if the stack depth stk.sub.-- dp is set to 0. Since the stack depth stk.sub.-- dp is 0, flow continues back to State 1 according to the State 4 diagram of FIG. 5E. Now that flow has proceeded back to State 1 of FIG. 5B the next statement of the IL program, namely OUT % Q1, becomes the subject statement which is processed. In State 1 it is found that the subject OUT % Q1 statement is a member of the out instruction group and thus flow proceeds to State 2 of FIG. 5C. Once in State 2 the next statement in the IL program, <END OF PROGRAM>, is processed. In State 2 the <END OF PROGRAM> statement is found to be a member of the eop instruction group and therefore flow continues to State 8 of FIG. 5I at which the statement processor ends the processing of the IL program normally. Since processing has ended normally without an abnormal termination or error message, this signifies that this particular IL program is one which is convertible to the form of a relay ladder diagram and which is valid. The IL program of FIG. 4A is an example of one IL program which is not accurately convertible to a relay ladder diagram. Processing of this IL program begins with the first statement thereof, namely LD % I1, which is now considered to be the subject statement. As before, processing of the IL program begins in State 0 shown in FIG. 5A. A determination is made that the subject statement is a member of the load instruction group and thus flow continues to State 1 of FIG. 5B at which the next statement, AND % I2, is processed as the subject statement. At State 1, a determination is made that the subject statement is a member of the and.sub.-- or instruction group and thus flow continues back to State 1. The next statement OUT % Q1 is now the subject statement which is processed in State 1. A determination is then made in State 1 that the subject statement is a member of the out instruction group and process flow goes to State 2 of FIG. 5C. In State 2, the next statement of the IL program, namely OR % I3, becomes the subject statement which is processed. A determination is made in State 2 that the subject statement is not a member of any instruction group which State 2 recognizes (i.e., fblk.sub.-- 0, load, out, eop, nop) and thus an "illegal transition error" is generated. The issuance of this illegal transition error is an abnormal termination which signifies that this particular IL program is not accurately convertible to a relay ladder diagram or is otherwise not valid. If a particular IL program is found to exhibit no violations of the set of rules of Table 1 which are embodied in the statement processor program in memory 56 of controller 50, then controller 50 goes ahead and converts the subject IL program to a relay ladder diagram which is displayed on display 60 of FIG. 2. The technology by which controller performs this conversion of IL programs to relay ladder diagram is already known. For example, the GE Fanuc Autmation N.A., Inc. model PLC 90-30 controller is one such product which converts an IL program to a relay ladder diagram and displays the diagram to the user. However, the present invention exhibits the advantage that if an error is indicated by the controller as it tests the individual statement of the IL program sequence, then no such conversion of the IL program to a relay ladder diagram occurs. The generation of inaccurate converted relay ladder diagrams is thus avoided. The foregoing describes a method for checking the syntax of an IL program to assure that such program is convertible to a relay ladder diagram. The programmable logic controller checks each statement of the IL program against a set of rules which is stored in the controllers memory. If the controller finds any syntax violations which would cause inaccurate results upon conversion to a relay ladder diagram or conditions which would otherwise cause the IL program to be invalid, then an error is indicated to the user and the conversion from the IL program format to the relay ladder diagram does not occur. However, if no such errors are indicated by the controller as it test the statements of an IL program, then the controller proceeds to convert the IL program to a relay ladder diagram and to display that diagram. While only certain preferred features of the invention have been shown by way of illustration, many modifications and changes will occur to those skilled in the art. It is, therefore, to be understood that the present claims are intended to cover all such modifications and changes which fall within the true spirit of the invention. ##SPC1##
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