System for dividing processing tasks into signal processor and decision-making microprocessor interfacing therewith5524244Abstract Architectures and methods are provided for efficiently dividing a processing task into tasks for a programmable real time signal processor (SPROC) and tasks for a decision-making microprocessor. The SPROC is provided with a non-interrupt structure where data flow is through a multiported central memory. The SPROC is also programmed in an environment which requires nothing more than graphic entry of a block diagram of the user's design. In automatically implementing the block diagram into silicon, the SPROC programming/development environment accounts for and provides software connection and interfaces with a host microprocessor. The programming environment preferably includes: a high-level computer screen entry system which permits choosing, entry, parameterization, and connection of a plurality of functional blocks; a functional block cell library which provides source code representing the functional blocks; and a signal processor scheduler/compiler which uses the functional block cell library and the information entered into the high-level entry system to compile a program and to output source program code for a program memory and source data code for the data memory of the (SPROC), as well as a symbol table which provides a memory map which maps SPROC addresses to variable names which the microprocessor will refer to in separately compiling its program. Claims We claim: Description Index of Contents
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0401H Exit boot mode (write f0H) (generate GSP hard reset)
0405H Serial port reset (write)
0406H Global break entry (write) (generate GSP soft reset)
0407H Global break exit (write) (generate GSP soft reset)
0408H GSP1 break entry (write) (generate GSP soft reset)
0409H GSP2 break entry (write) (generate GSP soft reset)
040aH GSP3 break entry (write) (generate GSP soft reset)
040bH GSP4 break entry (write) (generate GSP soft reset)
040cH GSP1 break exit (write) (generate GSP soft reset)
040dH GSP2 break exit (write) (generate GSP soft reset)
040eH GSP3 break exit (write) (generate GSP soft reset)
040fH GSP4 break exit (write) (generate GSP soft reset)
0410H Serial Port 1 internal clock rate select
(write 00 = CK/2048)
(write 01 = CK/1024)
(write 02 = CK/512)
(write 03 = CK/256)
(write 04 = CK/128)
(write 05 = CK/64)
(write 06 = CK/32) (write 07 = CK/16)
where CK is the SPROC clock (50 MHz)
0411H Serial Port 2 internal clock rate select
0412H Serial Port 3 internal clock rate select
0413H Serial Port 4 internal clock rate select
0414H Serial Port 5 internal clock rate select
0415H Serial Port 6 internal clock rate select
0416H Serial Port 7 internal clock rate select
0417H Serial Port 8 internal clock rate select
0440H to
Serial Port 1 (pradd = 0800H)
0447H
0448H to
Serial Port 2 (pradd = 0801H)
044fH
0450H to
Serial Port 3 (pradd = 0802H)
0457H
0458H to
Serial Port 4 (pradd = 0803H)
045fH
0460H to
Serial Port 5 (pradd = 0804H)
0467H
0468H to
Serial Port 6 (pradd = 0805H)
046fH
0470H to
Serial Port 7 (pradd = 0806H)
0477H
0478H to
Serial Port 8 (pradd = 0807H)
047fH
0480H to
DAC (probe) input port (pradd = 0808H)
0487H
0488H to
DAC (probe) serial output port
048fH
04fcH to
Host interface registers
04ffH
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Memory locations 1000 to ffff Hex refers to external address space (e.g. slave SPROCs, other devices, or memory). Of the auxiliary memory locations in the data RAM 100, it should be noted that each GSP is given a break entry and break exit data address. While the embodiment of FIG. 1 causes bus 155 to be connected to the boot/break ROM 190 when a break is implemented such that all GSPs must break together, different circuitry would allow for individual GSP breaks. The eight twenty-four bit locations provided for each serial port are used to configure the serial ports as well as the DFM section associated with each serial port as hereinafter described. Similarly, the eight words of memory assigned the input and output ports of the probe are used to configure the probe, while the eight words of memory assigned the host port are used to configure the host port as described hereinafter. Further, with regard to the memory locations, it is noted that when information is written to any of the serial port locations indicated, another address (pradd), which turns out to be a trigger flag address is generated by the DFM 600 (as discussed in more detail hereinafter) and written to the data RAM bus 125. The writing of particular addresses to the data RAM bus 125 is monitored by decoder 196 which is discussed in more detail in Ser. No. 07/583,508. Turning to FIGS. 3a and 3b, a block diagram of the preferred general signal processor (GSP) 400 of the invention is seen. The GSP is coupled to a program RAM 150 via program RAM bus 155. Because the program RAM 150 is preferably shared by a plurality of GSPs 400, access to the program RAM bus is time division multiplexed as indicated in FIG. 2. The program RAM bus 155 is comprised of a data bus of width twenty-four bits, and an address bus of ten bit width where a 1K program RAM is utilized. Of course, if a larger program RAM is desired, additional bits are required to address the same, and the program RAM bus would be wider. As indicated in FIGS. 3a and 3b, the GSP 400 writes to the address section of the program RAM bus to indicate which instruction (RAM location) is desired. However, under ordinary operating conditions the GSP 400 is not capable of writing data to the program RAM 150. Under ordinary operating conditions, data is written into the program RAM 150 only via the host or access ports shown in FIG. 1 which are also coupled to the program RAM bus 155 in a time division multiplexed manner. The GSP 400 is also coupled to the multiported data RAM 100 via a data RAM bus 125. Because the data RAM 100 is central to the processor architecture, and because non-arbitrated access to the data RAM 100 is desired, the data RAM 100 must either be a true multiported data RAM, or access to the data RAM 100 via the data RAM bus 125 must be time division multiplexed so as to effectively create a multiported RAM. The data RAM bus preferably comprises a data RAM address bus of sixteen bit width, an a data RAM data bus of twenty-four bit width. As indicated in FIGS. 3a, 3b and 4, the GSP may write to the address section of the program RAM 100. Also, the GSP may both read and write to the data section of the data RAM bus. The GSP is substantially described by the details and functioning of six sections: a block controller 410; a program control logic block 420; a multiplier block 430; an ALU block 450; a flag block 460; and a data RAM address generator block 470. Coupling all six sections, as well as a break register 492, a data access register 494, and a temporary register 496 is an internal twenty-four bit bus 490. All access from any of the sections or from the registers 492, 494, or 496 onto the internal bus 490 is via tristate drivers 429, 449a, 449b, 459, 469, 489, and 499. Block controller 410 is comprised of instruction decoder 412, and sequencer 414. The instruction decoder 412, when enabled, takes fourteen bits (nine bits of opcode, and five bits of operand) off of the data portion of the program RAM bus. Six of the nine opcode bits are used to indicate the operation (instruction) which the GSP is to perform (e.g. add, shift, jump, etc.), with up to sixty-four instructions being accommodated. In the preferred embodiment an additional three bits of opcode are utilized to specify the addressing mode the GSP is to use. In particular, in the "absolute" mode (code 000), the fifteen bits in the O register 472 of the address generator block 470 are used to select an address in the data RAM 100, and the data in that address of data RAM is used for the operation. In the "register" mode (code 001), the five operand bits obtained by the instruction decoder 412 are used to specify which register of the numerous registers of the GSP is to place its contents onto the internal bus 490. In the "immediate left" mode (code 010), the fifteen bits of data in the O register are to be put into the fifteen msb slots of the internal bus 490, while in the "immediate fight" mode (code 011), the fifteen bits are put into the fifteen lsb slots of the internal bus. In the remaining four modes, "BL indexed" (code 100), "B indexed" (code 101), "FL indexed" (code 110), and "F indexed" (code 111), as described in more detail hereinafter, values in base registers B or F are added to the value of the fifteen bit operand stored in the O register and, where appropriate, to the value in the L (loop) register, and are output onto the data RAM bus 125. Instruction decoder 412 is not only coupled to the program RAM bus, but to the numerous multiplexers, tristate drivers, registers, etc. of the GSP via lines 416. Based on the instruction which is decoded by instruction decoder 412, various of those lines 416 are enabled in a sequence as determined by the sequencer 414. In effect, instruction decoder 412, and sequencer 414 are simply look-up charts, with instruction decoder 412 looking up which lines 416 must be enabled based on the code found in the nine bits of opcode, and sequencer 414 looking up the sequence to which the enabled lines must subscribe. While instruction decoder 412 decodes whatever instruction is on the program RAM bus 155 when the GSP 400 is granted access to that bus, the instruction which is on the bus is generated and dictated by the program logic block 420. Program control logic block 420 is comprised of a tristate driver 422, a program address value register 424 (also called the "P" register), an incrementer 425, an increment (I) register 426, a jump (J) register 428, a multiplexer 430, and a branch logic block 432. The P register 424 contains the location of the program RAM 150 which contains the microinstructions which are to be used by the GSP 400. P register 424 writes that address onto the program RAM bus 155 by sending it to tristate driver 422 which acts as the bus interface. Updating of the P register 424 is accomplished via muxP 430 which chooses one of the twelve bit addresses stored in the I register 426 or the J register 428 based on information from branch logic block 432. The address stored in the I register is simply the next numerical address after the address stored in the P register, as a value of one is added at incrementer 425 to the value stored in P register 424. In most situations, muxP 430 will permit the P register 424 to be updated by the I register, and the sequential addressing of the program RAM will continue. However, in some situations, such as where a jump in the routine is desired, the multiplexer 430 will permit the address in the J register 428 to be loaded into the P register 424. The decision to jump is made by the branch logic block 432 which reads the status of a plurality of status flags as is hereinafter discussed. The address to which the jump is made is obtained by the J reg 428 from the internal bus 490, which may obtain the address from any of the sections of the GSP 400 (or from the data RAM 100). Coupled to the program control logic block 420 is a break register 492 in which upon the execution of a break instruction is loaded status flag information as well as the value of the P register plus one. The status flag and P register information is stored in the break register 492 which is coupled to internal bus 490 via tristate driver 429 because it is otherwise not available for placement on to the internal bus 490. A program break is typically executed when an information dump is desired by the system user, and is accomplished by putting an instruction in the program RAM 150 which causes the GSP 400 to write to a certain address (e.g. 0406H) of the data RAM 100. A decoder (not shown) on the data RAM bus 125 is used to determine that the program break is to be executed (based on the location to be written to), and a control signal is provided by the decoder to the break register 492. The program break instruction in the program RAM 150 causes instructions in a boot/break ROM 190 (shown in FIG. 1 ) which is coupled to the program RAM bus 155 to be accessed by the program control logic block 420. The instruction code in the boot/break ROM 190 in turn causes the values of each of the registers in the GSP 400 to be written into desired locations in the data RAM 100. Then the GSP 400 is kept waiting until the wait flag stored in its wait flag register (discussed below) is cleared. During the wait period, if desired, the user can change the values of data in the data RAM as described in more detail below with reference to the access port 900. Then, when the wait cycle is terminated, the instructions in the boot/break ROM 190 causes the values in the data RAM, including any new values, to be written back to their appropriate registers in the GSP. The location of the next desired microinstruction contained in a program RAM 150 location is loaded into the P register, so that the GSP can continue in its normal fashion. The multiplier block 430 and the ALU block 450 of the GSP perform the numerical computations for the GSP. The multiplier block 430 is comprised of two input registers Xreg 432 and Yreg 434, a multiplexer 436 which is coupled to the internal bus 490 via tristate driver 449a, a multiplier 438 with a post Xreg 439, and a multiplier control 441, a summer 442, an output register Mreg 444, and a second multiplexer 446 which selects which of six words is to be output onto internal bus 490 via tristate driver 449b. Typically, the multiplicand is loaded into Xreg 432. Then the multiplier is loaded into Yreg 434 while the multiplicand is loaded into post Xreg 439. The multiplier control 441 permits the multiplier 438 to function over several machine clock cycles (e.g. three clock cycles totaling 300 nanoseconds=fifteen internal GSP cycles). If in multiplying, the multiplier overflows, a status flag M is set, and this information is conveyed to the branch logic block 432 of the program logic section 420. Regardless, the product of the multiplier and multipicand is forwarded to summer 442 which, in a multiply with accumulate mode, adds the new product to the sum of previous products and forwards the sum to the multiply register M 444. In a pure multiply mode, the contents of the summer are cleared so that the product is forwarded through the summer which adds zero and send the product to the M register. The contents of the M register 444 are available to the internal bus 490. However, because the M register can accommodate a fifty-six bit word, and the internal bus 490 is a twenty-four bit bus, only a portion of the M register word may be placed on the bus at one time. Thus, multiplexer 446 is provided to either select the twenty-four least significant bits (lsb's) in the M register, the twenty-four next lsb's in the M register, or the eight most significant bits (msb's) in the M register. If the eight msb's are chosen, the eight msb's are placed in the eight lsb slots of the internal bus 490, and the msb of the eight bits is extended through to the msb slot on the bus (e.g. if the msb is a "1", the first seventeen msb's on the bus will be "1"). The multiplexer 446 is also capable of selecting a left shifted by two (zero filling the right) twenty-four or eight bit word. Thus, in all, multiplexer 446 can provide six different outputs based on the product in the M register 444. The ALU block 450 of the processor is basically a standard ALU, having an arithmetic-logic unit 452 with input register 454, and an output accumulator register 456. The arithmetic-logic unit 452 is capable of the standard functions of similar units, such as adding, subtracting, etc., and produces values for Areg 456, as well as status flags including carry (C), overflow (O), sign bit (S), and zero (Z). The status flags are used by the branch logic block 432 of the program logic block 420 to determine whether a conditional jump in the microcode program should be executed. The Areg contents are output onto internal bus 490 via tristate driver 459. Wait flag block 460 is comprised of two wait flag registers WFreg 462 and DFreg 464, a multiplexer 466, and OR gate 468. The bits of the wait flag registers may be set (i.e. written to) by data sent over the internal bus 490. Also, registers WFreg 462 and DFreg 464 are coupled to a flag bus 198 which is written to each time predetermined locations in the data RAM 125 are addressed as hereinbefore described with reference to FIGS. 2 and 13. In this manner, each bit of the wait flag registers 462 and 464 may be selectively cleared. When all of the bits in register WFreg 462 have been cleared due to the occurrences of specified events (e.g. the data RAM has received all the information which is required for another computation), OR gate 468 is used to provide a status flag W which indicates the same. Status flag W is read by the branch logic block 432. In this manner, "jump on wait flag" commands may be executed. The DFreg 464 of the wait flag block 460 functions similarly to the the WFreg 462, except that no signals indicating the presence of all zeros (or ones) are output by the DFreg. In order to check the contents of the DFreg (or the WFreg, if all values in the WFreg are not zero), the register must be selected to put its contents on the internal bus 490. The selection of one of the registers is made by the instruction decode 412 and sequencer 414, and the contents are forwarded via multiplexer 466 and the tristate driver 469. An easy manner of determining whether the DFreg 464 has all zeros is to forward the contents of the DFreg 464 to the ALU 452, which will provide a status flag Z if the contents are zero. The final large block of the general signal processor is the data RAM address generator block 470 which includes bus wide OR gate 471, registers Oreg 472, Dreg 473, Lreg 474, Breg 476, Freg 477, adders 481, 482, and 483, multiplexers muxBFL 484, muxL 485, muxA 486, muxBF 487, muxO 488, and an address access block 489. As previously indicated, the Oreg 472 obtains the fifteen least significant bits of the instruction on the program RAM bus. If "absolute" addressing is desired, i.e. the address to be written onto the data RAM bus is included in the program RAM microinstruction itself, the address is written into the Oreg 472, and then forwarded to the data RAM bus (a sixteenth bit having been added by a zero extender, not shown) via muxA 486 and the address access block 489. The sixteen bit address is then placed on the data RAM bus at the appropriate time. All other situations constitute "indexed" addressing, where the address to be put out on the data RAM bus is generated internally by the data RAM address generator block 470. Addresses are generated by adding the values in the various registers. In particular, and as indicated in FIG. 4, the Oreg 472 is the offset register, the Dreg 473 is a decrement register, the Lreg 474 is a loop register which sets the length of a loop, the Breg 476 is a base address register, and the Freg 477 is a frame address register which acts as a second base address register. The O register obtains its data off of the program RAM bus, while registers D, L, B and F obtain their data from the internal bus 490. If it is desired to add some offset value to the value in the base or frame register (i.e. the "B indexed mode" or "F indexed mode") in order to generate an address, muxBF 487 selects appropriately the Breg 476 or the Freg 477, muxBFL 484 selects the value coming from muxBF 487, and the Breg or Freg value is added to the offset value of the Oreg by the adder 483. That value is then selected by muxA 486 for output over the data RAM bus via the address access block 489. Similarly, if it is desired to add some offset value and some loop value to the value in the base or frame register (i.e. the "BL indexed mode" or the "FL indexed mode "), the value in the L register is added to the value in the B or F registers at adder 482, and the sum is passed via muxBFL 484 to adder 483 which adds the value to the value in the O register. By providing adder 481, and by coupling the decrement register Dreg and the loop register Lreg to the adder 481, registers an address loop is effectuated. In particular, the Lreg sets the length of the loop, while the Dreg sets the value by which the loop is decremented. Each time the Dreg is subtracted from the Lreg 475 at adder 481, the new value is fed back into the Lreg 475 via muxL 485. Thus, each time a DJNE instruction is executed (as discussed below), the resulting value in the Lreg is decreased by the value of the Dreg. If added to the Breg or Freg, by adder 482, the address generated is a sequentially decrementing address where the value in the Dreg is positive, and a sequentially incrementing address where the value in the Dreg is negative. The ability to loop is utilized not only to provide a decrementing (or incrementing) address for the data RAM bus, but is also utilized to effect changes in the program RAM address generation by providing a "decrement and jump on not equal" (DJNE) ability. The output from the adder 481 is read by OR gate 471 which provides a status flag L (loop) to branch logic block 432. The status flag L maintains its value until the L register has looped around enough times to be decremented to the value zero. Before that point, when the Lreg is not zero, the next instruction of the GSP is dictated by the instruction indicated by the Jreg 428. In other words, the program jumps to the location of the Jreg instruction instead of continuing with the next instruction located in the I register. However, when the Lreg does decrement to the value zero, the OR gate 471 goes low and toggles flag L. On the next DJNE instruction, since the "not equal" state does not exist (i.e. the Lreg is zero), branch logic 432 causes muxP 430 of the program logic block 420 to return to obtaining values from the Ireg 426 instead of from the Jreg 428, and the program continues. The values of any of the O, D, L, B, or F registers may be placed on the internal bus 490, by having muxO 488 (and where appropriate mux BF 487) select the appropriate register and forward its contents via tristate driver 489 to the internal bus. Coupled to the internal bus 490, and interfacing the internal bus 490 with the data slots on the data RAM bus is the data access port 494. The data access port 494 is capable of reading data from and writing data to the data RAM and is given access to the data RAM in a time division multiplexed manner as previously described. In writing to the data RAM, the data access port 494 and the address access port 489 are activated simultaneously. In reading data from the RAM, the address access port 489 first places on the data RAM bus the data RAM address in which the desired data is stored. The data is then placed on the data RAM bus by the data RAM, and the data access port 494 which is essentially a dual tri-state driver, receives the data and passes it onto the internal bus 490 for storage in the desired GSP register. If desired, additional registers such as Z register 496 may also be coupled to the internal bus 490, and may be used as temporary storage. The contents of Zreg 496 are output onto the internal bus 490 via tristate driver 499. Details of the functioning of the GSP as well as example microcode may be seen with reference to previously incorporated U.S. Ser. No. 07/525,977. Turning to FIGS. 4a, 4b, and 4c, block diagrams of the input and output circuitry of the data flow manager (DFM) 600 of the invention, and an example FIFO related to the DFM are seen. As previously described, the DFM serves the important function of handling the flow of data into and out of the processor apparatus so that GSPs of the processor apparatus need not be interrupted in their processing tasks. In accomplishing this function, the DFM takes data received by the serial port from the "world" outside of the particular processor apparatus and organizes it inside a FIFO such as the FIFO of FIG. 4c which is implemented in desired locations of the data RAM 100 of the SPROC apparatus 10. Also, the DFM 600 takes data in a FIFO, and organizes it for output to a serial output port of the SPROC apparatus. The DFM is also capable of directing data into a FIFO and drawing data from a FIFO at desired speeds so as to accommodate a decimation operation performed by the SPROC. Further, the DFM causes decoder 196 to write flags to the flag bus 198 (and hence to the GSPs 400) of the SPROC apparatus 10 regarding the status of the buffers. The DFM 600 of the SPROC apparatus may either be central to the apparatus, or distributed among the serial input and output ports 700 of the apparatus, with a single DFM serving each port 700. Where distributed, the circuitry seen in block diagram form in FIGS. 4a and 4b is duplicated for each serial input and output port 700 of the SPROC apparatus, although certain circuitry could be common if desired. The circuitry for receiving data from a serial port and organizing it for storage in a FIFO of the data RAM 100 is seen in FIG. 4a. The data flow itself is simple, with the data being sent from the serial port 700, via multiplexer 611 and tri-state driver 613 to the data slots of the data RAM bus 125. Multiplexer 611 permits either data coming from serial port 700a or data generated as hereinafter described to be forwarded to driver 613. Driver 613 is controlled as indicated such that data is only output on the data RAM bus 125 when the DFM 600 is enabled by the system-wide multiplexer clock scheme. The organization of the data for output onto the data RAM bus as a twenty-four bit word is conducted by the serial port 700, as hereinafter described. Besides the data flow circuitry, each DFM is arranged with buffers, counters, gates, etc. to generate data RAM FIFO addresses for the incoming data. As shown in FIG. 4a, the DFM 600 has three registers 620, 622, 624, three counters 630, 632, and 634 associated with the three registers, an adder 636, a divide by two block 637, a multiplexer 638, seven logic gates 641, 642, 643, 644, 645, 646, and 647 (gates 642, 643, 645, and 647 being bus wide gates), and two delay blocks 648 and 649. The three registers are respectively: the start of FIFO register 620 which stores the start location in the data RAM for the FIFO to be addressed by the particular serial port coupled to the particular part of the DFM; the index length register 622 which stores the number of buffers which comprise the FIFO (for the FIFO of FIG. 4c, the index length register would be set at four), and the buffer length register 624 which stores the length of each buffer, i.e. the number of words that may be stored in each buffer (for the FIFO of FIG. 4c, the buffer length register would be set at eight). When a data word (twenty-four bits) is ready for sending to the data RAM for storage in a FIFO, the serial port 700a provides a ready signal which is used as a first input to AND gate 641. The second input to AND gate 641 is a data enable signal which is the time division multiplexed signal which permits the DFM to place a word on the data RAM bus. With the data enable and ready signals high, a high signal is output from the AND gate which causes driver 613 to output the data on the data RAM bus along with an address. The address is that which is computed by the twelve bit adder 636, or a prewired address, as will be described hereinafter. When AND gate 641 provides a high output, the high output is delayed by delay blocks 648 and 649 before being input into clock counters 630 and 634. As a result, counters 630 and 634 increase their counts after an address has been output on the data RAM bus. When counter 630 increases its count, its count is added by the twelve bit adder 636 to the FIFO start location stored in register 620. If selected by multiplexer 638, the generated address will be the next address output in the address slots of the data RAM bus in conjunction with the data provided by driver 613. Thus, as data words continue to be sent by the serial port for storing in the data RAM FIFO, they are sent to incremental addresses of the data RAM, as the counter 630 increasingly sends a higher value which is being added to the FIFO start location. As is hereinafter discussed, the counter 630 continues to increase its count until a clear counter signal is received from circuitry associated with the index length register 622. When the clear counter signal is received, the counter starts counting again from zero. As aforementioned, each time the AND gate 641 provides a high output, the counter 634 associated with the buffer length register 624 is also incremented (after delay). The outputs of the buffer length register 624 and its associated counter 634 are provided to bus wide XNOR gate 643 which compares the values. When the counter 634 reaches the value stored in the buffer length register 624, a buffer in the data RAM FIFO has been filed. As a result, the output of XNOR gate 643 goes high, causing three input OR gate 644 to pass a high signal to the reset of counter 634. The high signal from bus wide XNOR gate 643 is also fed to the counter 632 associated with the index length register 622, to the multiplexer 638, and to the multiplexer 611. As a result of the buffer being filled, multiplexer 638 enables the prewired address to be placed in the address slots of the data RAM bus 125, along with one of two predetermined (or generated) data words which are generated as discussed below. The placement of the prewired address and a data word on the bus at the end of buffer signal occurs upon the next data enable signal received by the DFM, which is before another word is assembled by the serial port 700a for sending to the data RAM 100. Also, the placement of the prewired address and data word is used for signalling purposes, as a decoder 196 (seen in FIG. 1) monitors the data RAM bus 125 for the particular prewired addresses of the DFMs; the triggering of these addresses occurring because of conditions in the DFM, i.e. the filling of buffers. The decoder 196 in turn, can set a flag (the setting of the flag can be dependent on the value of the data accompanying the prewired address) on the trigger bus 198 which signals the GSPs 400 of the SPROC of the occurrence. In this manner, the GSPs 400 can determine that the data required to conduct an operation is available to the GSP, thereby causing the GSP to exit a wait loop. The predetermined or generated data word placed on the bus after a FIFO buffer has been filled preferably uses a "1" as the msb of the data word if the FIFO buffer that has been filled causes the FIFO to be half filled (as described hereinafter), or a "0" as the msb otherwise. The remainder of the data word may be null information. Or, if desired, the data word may include the next location to which the DFM will write (i.e. the location computed by the twelve bit adder 636) which is inserted in appropriate locations of the data word. This predetermined or generated data word is then passed via multiplier 611 to driver 613 which places the data word on the bus at the same time the prewired address is placed on the data RAM bus 125. As aforementioned, when an indication of a full buffer is output by bus wide XNOR gate 643, counter 632 is incremented. Counter 632 therefore tracks the number of the buffer in the FIFO that is being falled. When the number of the FIFO buffer being addressed (as determined by counter 632) is half of the FIFO length (as determined by the length stored in register 622, divided by divide by two block 637), a flag is raised by the DFM via the bus wide XNOR gate 647. The "mid buffer" flag indicates that the buffer in the FIFO being written to is halfway through the FIFO. Hence, if all previous buffers in the FIFO are still full with data, the FIFO is half full. In addition, the mid buffer flag causes the generated data input to multiplexer 611 to be changed, such that the msb of the data is a "1" instead of a zero. Thus, upon filling the buffer which causes the FIFO to be half filled, a slightly differently coded data word is placed in the data slots of the data RAM bus. When the value of counter 632 is incremented to the value stored in the index length register 622, the last location in the FIFO has been addressed. Accordingly, it is desirable to recirculate; i.e. to continue by addressing the first location in the FIFO. With the value of counter 632 equal to the value of register 622, bus wide XNOR gate 645 provides a high signal which is passed through three input OR gate 646. As a result, counters 630, 632, and 634 are reset. As indicated in FIG. 4a, a "clear counter" signal may also be generated by a power up reset (PUR) signal which is generated by applying a signal to a predetermined pin (not shown) of the SPROC, and by a SYNC signal which is generated by writing to address 0405H of the data RAM 100. The SYNC signal permits different DFMs to be synchronized to each other. If desired, the input section of one DFM can be synchronized to the output section of the same or another DFM. This synchronization is accomplished via a pin (not shown) on the SPROC which generates the "en buf" input into OR gate 644. In turn, OR gate 644 provides a high signal which resets counter 634 in synchronization with the resetting of a similar counter in a DFM output section such as described with reference to FIG. 4b. Turning to FIG. 4b, the serial output section of the DFM 600 is seen. The function of the output section of the DFM is to take data in the FIFO, and organize it for output to a serial output port 700b of the SPROC apparatus. The output section of the DFM is preferably comprised of several registers and counters, logic elements including AND gates, comparators, and inverters, divide and add blocks, flip-flops, a buffer and a parallel to serial converter. Basically, the data flow through the serial output section of the DFM is simple. An address generated by the the start address register 652 is added by adder 654 to the value in the offset counter 656, and that address is output onto the address section of the data RAM bus. The data RAM receives the address information and then places the data located at that data RAM address on the data RAM bus. That data is received by the DFM and latched and stored in buffer 694 prior to being forwarded to the serial output port 700b. The remaining circuitry of FIG. 4b serves the functions of not permitting the data to be forwarded to the serial output port 700b unless certain conditions (i.e. triggers) are met, as well as generating synch pulses and error flags depending on internal logic and received signals. In particular, each DFM has a wait register 660 which holds flag information which must be cleared in the wait flag register 662 before a signal will be generated. The bits in the wait flag register are only cleared upon receipt of appropriate trigger bits received from the trigger bus 198. When the appropriate flags are cleared, bus wide NOR gate 664 resets the wait flag register 662 by permitting it to be reloaded from wait register 660. The NOR gate 664 also passes the signal on to divide by N (N=0, 1, . . . , n) block. Upon the divide by N block 666 receiving N pulses from NOR gate 664, it outputs a pulse to AND gate 668. If N is one, no clock decimation occurs. However, if N is greater than one, decimation is effected; i.e. the clock is reduced to match the decimation of data which occurred in the GSP. If the other input to AND gate 668, is also high (which occurs when the DFM is running as hereinafter described), a pulse is sent to offset counter 656 which increases its count. In this manner the address output by adder 654 is changed to the next address. Likewise, when the output of AND gate 668 is high, a pulse is sent to the serial output port 700b which outputs a data signal from the DFM, and to the sample counter 684 which increases its count. The DFM also includes a IE (initiation/error) register 661 which supplies the flag data which must be cleared by the trigger bits to the LF flag register 663. The outputs from IE flag register 663 are fed to bus wide NOR gate 665 which is used in a feedback manner to reset the IE flag register 663 so that it can be reloaded by IE register 661. The output from bus wide NOR gate 665 is also sent as the clock input into a D type flip-flop 667. The data (D) input into the D type flip-flop 667 should be the msb (bit twenty-three) of the data word being input into the DFM's data RAM buffer by the input side of the DFM, which is arranged to be a value "1" only when the word is being taken from the half-full location of the data RAM buffer. The value of the msb input to the D input, is then clocked over to the Q output of the flip-flop which is forwarded as the first of two inputs to each of two AND gates 670 and 672. As will be discussed hereinafter, AND gate 670 is used to set an error flag. AND gate 672, on the other hand, is used to set block 675 which is used to indicate the state of the DFM (i.e. is it presently running). If the DFM is presently causing data to be read from the data RAM and output via the DFM to a serial port, the DFM is in the running mode, and the output from block 675 is already high. As a result, inverter 676 provides a low signal to AND gate 672 which is not affected by the output from flip-flop 667. On the other hand, if the DFM is not running, the output from block 675 is low, and inverter 676 provides a high value to AND gate 672. Thus, if flip-flop 667 provides a low signal (which will happen until the buffer in the data RAM for the DFM has received enough data to be half full), the DFM will not start running. On the other hand, if flip-flop 667 provides a high signal indicating that the data RAM has now been filled halfway, block 675 changes its output and the DFM starts running. It should be noted that when the DFM is not running, the high output from inverter 676 is forwarded via OR gate 677 to the clearing input of offset counter 656, thereby causing the address count to be generated by adder 654 to be initialized upon start-up of the DFM. As aforementioned, AND gate 670 is used to set an error flag. Thus, if D type flip-flop 667 provides a high output while the DFM is running (as indicated by the output from block 675), AND gate 670 passes a high value to AND gate 698, which in turn will generate an error flag if other criteria are met, as hereinafter described. The remaining blocks of the DFM output section include a FIFO length register 680, a buffer length register 682, a sample counter 684, a divide by two block 685, comparators 686 and 687, a bus wide OR gate 689, and a set/reset block 690. The FIFO length register 682 stores the full length of the FIFO. When the value of the offset counter 656 is equal to the FIFO length stored in buffer 680, a sync pulse is generated by bus wide XNOR gate 686 which is used to synchronize the incoming data signal into an input section of a DFM with the outgoing data signal from the described output DFM. The sync pulse generated is received by the input section of the DFM (seen in FIG. 4a) as the signal enbuf1, previously described. In addition the sync pulse may be used to reinitialize the DFM by clearing the offset counter 656 and reloading the registers. When the value in the offset counter 656 is equal to one-half the value of the FIFO length register 680 (as determined by divide by two block 685), comparator 687 provides a pulse to set/reset block 690 which is indicative of the fact that the address placed on the data RAM bus is the address half-way through the data RAM buffer associated with the particular DFM. When the data RAM address is the half-full address, the data being written into the data RAM buffer should not be written into the half-full address (i.e. there should never exist a situation where the address is being written to and read from at the same time). Thus, if D type flip-flop 667 provides a high signal to AND gate 670 while the DFM is running, and the output from set/reset block 690 is also, high, AND gate 698 provides a high output which sets an error flag for the DFM. Finally, with respect to the output side of the DFM, the buffer length register 682 stores a value equal to the length of each buffer in the data RAM FIFO associated with the DFM. The sample counter 684 is a down counter which is preloaded with the buffer length stored in register 682. When a high pulse is received from XNOR gate 687 (i.e. the offset counter is half of the FIFO length), RS flip-flop 690 is set and the down counter of sample counter 684 is enabled. Each time sample counter 684 receives a pulse from AND gate 668, the count is decremented. When the sample count goes to zero, the RS flip-flop 690 is reset. However, while the RS flip-flop 690 is set and outputs a high pulse to AND gate 698, the DFM is looking for an error. If before being reset a high msb value is seen by flip-flop 667, the DFM is apparently attempting to read and write to the same buffer location at the same time. As a result, AND gate 698 provides a high signal which sets an error flag for the DFM. Turning to FIG. 4c, an example of a FIFO associated with the DFM is seen. The FIFOs associated with DFMs are contained in a preferably predetermined portion of the data RAM of the processor apparatus. The FIFO of FIG. 4c, as shown contains four buffers. Also as shown, each buffer contains storage for eight data samples. Thus, as shown, the FIFO of FIG. 4c has storage for thirty-two data samples. Of course, a FIFO can contain a different number of buffers, and the buffers can store different numbers of data samples. The size of the each FIFO associated with a DFM and the size of its buffers is either set automatically by intelligent software which calculates the requirements of the particular DFM, or by the user of the processor system during initial programming of the processor system. Turning to FIG. 5a, a block diagram of the serial input port 700a of the invention is seen. The basic function of the serial input port is to receive any of many forms of serial data and to convert the received serial data into parallel data synchronous with the internals of the SPROC and suitable for receipt by the DFM 600 and for transfer onto the data RAM bus 125. To accomplish the basic function, the serial input port has a logic block 710, a data accumulation register 720, and a latched buffer 730. The logic block 710 and the data register 720 are governed by seven bits of information programmed into the serial input port 700a upon configuration during boot-up of the SPROC 10. The seven bits are defined as follows:
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dw1 dw0
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0 dw0 0 0 24 bits data width
1 dw1 0 1 16 bits data width
1 0 12 bits data width
1 1 8 bits data width
2 High: msb first
Low: lsb first
3 High: short strobe
Low: long strobe
4 High: gated clock
Low: continuous
clock
5 High: internal clock
Low: external clock
6 High: output port
Low: input port
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Bits 0, 1, and 2 are used to govern the logic block 710. If the incoming data is a twenty-four bit word, the logic block takes the bits in a bit by bit fashion and forwards them to the data accumulation register 720. If the incoming data is a sixteen bit, twelve bit, or eight bit word, the logic block takes the bits of the word in a bit by bit fashion and zero fills them to extend them into a twenty-four bit word. Which bit of the received serial data is forwarded into the msb slot of the register 720 is governed by control bit 2. Once the data is properly accumulated in register 720, it is latched into buffer 730 where it is held until it can be forwarded through the input section of the DFM 600 for storage in the multiported RAM 100. The holding of the data in the buffer 730 until the appropriate signal is received effectively causes data which is asynchronous with the SPROC 10 to become synchronized within the SPROC system. Bits 3, 4, and 5 governing logic block 710 are respectively used to control the type of strobe, the type of clock, and the location of clock control for the input port 700, all of which are necessary for the proper communication between the SPROC and an external device. Because port 700 preferably includes the circuitry of both an input port 700a and an output port 700b (described in more detail hereinafter), an extra bit (bit 6) is used to control the functioning of port 700 as one or the other. The serial data output port 700b seen in FIG. 5b is similar to the data input port 700a in many ways, except that its function is the converse. The serial output port 700b includes a buffer 740, an parallel load shift register 750, and controlled multiplexers 760 and 770. The data to be written from the SPROC via the output port 700b is received by the buffer 740 from buffer 694 of the DFM 600. The twenty-four bits received are then loaded in parallel into the parallel load shift register 750 which functions as a parallel to serial converter. The twenty-four bits are then forwarded in a bit serial fashion via multiplexer 760 which receives the control signals dw0 and dw1, and via multiplexer 770 which receives the msb control signal to the transmit data line. Multiplexers 760 and 770 effectively transform the twenty-four bit word received by the parallel load shift register into the desired format for communication with a desired device external the SPROC. The twenty-four bits may be transformed into an eight bit word (e.g. the eight msb's), a twelve bit word, or a sixteen bit word (the eight lsb's being truncated), with either the lsb or the msb being transmitted first. A twenty-four bit word may similarly be sent lsb or msb first. Where the SPROC is communicating with another SPROC (i.e. output port 700b of one SPROC is communicating with the input port 700a of another SPROC), multiplexers 760 and 770 are preferably controlled to send a twenty-four bit word, msb first. Turning to FIG. 6, details of the host port 800 are seen. Under most circumstances the host port 800 serves to interface the SPROC 10 with a host 180 (see FIG. 2), although where the SPROC 10 is a master SPROC which is in boot mode, host port 800 serves to interface the SPROC 10 with an EPROM and with any slave SPROCs which are part of the system. As indicated in FIG. 8, the host port 800 is coupled to the data RAM bus 125 as well as to the program RAM bus 155 on the SPROC side, while on the host side, the host port 800 is coupled to the host bus. The host bus includes three data sections D0-D7, D8-D15, and D16-D23, and three address sections A0-A11, S0-S3, and EA0-EA1. The remaining interfaces shown on the host side are pins (e.g. master/slave, reset, mode) which control the functioning of the SPROC 10 and the host port 800, and the read/write strobes for the host bus 165. In slave mode (master/slave pin 801 set to slave mode), the SPROC 10 appears to other apparatus, including host microprocessors or DSPs as a RAM. Because it is desirable that the SPROC interface with as many different types processors as possible, the host port 800 is a bit parallel port and is arranged to interface with eight, sixteen, twenty-four, and thirty-two bit microprocessors and DSPs. The mode pins 802, 804, and 806 are used to inform the host port 800 as to whether the host processor is an eight, sixteen, twenty-four bit, or thirty-two bit processor, and whether the word being sent first is the most or least significant word. For sending data from the host processor to the SPROC in slave mode, a data multiplexer 810, a data input register 812, and two drivers 815 and 817 are provided. The data multiplexer 810 receives three eight bit data inputs (D0-D7, D8-D15, and D16-D23) from the data bus section of host bus 165 and causes the data to be properly arranged in the data input register 812 according to the control of mode pins 802, 804, and 806. If the host processor is a thirty-two bit processor, the host port 800 of the SPROC takes two sixteen bit words and processes them in a manner described below with reference to a sixteen bit processor. Where the host processor is a twenty-four bit processor as indicated by mode pins 802 and 804, data is passed directly to the data input register 812 without adding bits or dividing bytes into segments. Where the host processor is a sixteen bit processor as indicated by mode pins 802 and 804, the host port takes sequentially takes two sixteen bits from two of the three eight bit data input lines (D0-D7, D8-D15, D16-D23), discards the eight lsb's of the least significant word, and uses the remaining bits to provide a twenty-four bit word to the data RAM bus 125 or the program RAM bus 155 of the SPROC. Where the host processor is an eight bit processor as indicated by mode pins 802 and 804, three eight bit bytes are received over the D0-D7 data input line and are concatenated in the data input register 812 in order to provide the SPROC with a twenty-four bit signal. Regardless of how the data input register 812 is filled, after the data is assembled, the host port 800 awaits an enabling signal from the SPROC timing so that it can write its twenty-four bit word to the data RAM bus 125 via driver 817 or the program RAM bus 155 via driver 815. In this manner, the host port 800 synchronizes data to the SPROC 10 which was received in a manner asynchronous to the SPROC 10. The address to which the data is written is obtained from the twelve bit address section A0-A11 of the host bus 165. The twelve bit address is forwarded from host bus 165 to the address input register 820. When the host port 800 is enabled, if the address contained in the address input register 820 is indicative of a data RAM location, the address is placed via driver 822 on the sixteen bit address section of the data RAM bus 125. Because the address bus is a sixteen bit bus, while the address in address input register 820 is a twelve bit address, four zeros are added as the msbs of the address via driver 824 when the address and data are put on the data RAM bus. If the address contained in the address input register 820 is indicative of a program RAM location (address location 1K and below), the address is placed via driver 826 on the twelve bit address section of the program RAM bus 155. In the slave mode, when the host processor wishes to read information from the SPROC, the host processor causes the read strobe to go low. The address received by the host port over address lines A0-A11 is read by the host port 800 and latched into the address input register 820. When the host port 800 is allowed access to the data or program RAM buses, the address is placed on the appropriate bus, and the twenty-four bit data word located at the data or program RAM address which was placed on the appropriate bus is read and latched either into the program data output register 832 or the output data register 834. That information is then forwarded via multiplexer 836 to data demultiplexer 840 arranges the twenty-four bits of information onto locations D0-D23 of the host bus 165. Demultiplexer 840 serves the opposite function of multiplexer 810. When sending data to the twenty-four bit host processor, the demultiplexer 840 simply takes its twenty-four bits and passes them unchanged. When sending data to a sixteen bit host processor, the SPROC 10 divides its twenty-four bit word into two sixteen bit words (with zero filling as appropriate). Similarly, when sending data to an eight bit host processor, the SPROC 10 divides its twenty-four bit word into three eight bit bytes. In the master mode, on the "host" side of the host port 800 is located either an EPROM or one or more slave SPROCs. In the boot mode of master mode, data from the internal boot ROM 190 of the SPROC is written into the sixteen bit mode register 850 which is used to configure the internals of the host port 800. Then the GSP of the SPROC, which executes the program in the internal boot ROM, writes the sixteen bit addresses of the EPROM it wants to read in order to initialize the SPROC. Each address is received by the address output register 855 of the host port. The host port then sends a read strobe onto the host bus 165 and places via drivers 856 and 858 the address of the EPROM address it wishes to read. If the EPROM is an eight bit EPROM, the desired address is extended by extended address generator 860, and three read strobes are generated by the strobe generator 865 so that three eight bit bytes of the EPROM can be accessed. When the EPROM places its data onto the data locations of the host bus 165, that data is forwarded through data multiplexer 810, and is placed in a master mode receive register 867. The assembled twenty-four bit data word may then be read by the controlling GSP of the SPROC. After the word is read, the entire sequence repeats until all of the desired information stored in the EPROM is read into the SPROC. Where the master SPROC is acting to boot up slave SPROCs as well as itself, the master SPROC follows the same boot-up procedure just described. However, upon the host port 800 receiving information in the master mode receive register 867 which is bound for a slave SPROC as determined from information previously obtained from the EPROM, the master SPROC causes that data to be written to the host bus 165 (via bus 125, GSP 400, bus 125 again, register 834 . . . as previously described) along with a sixteen bit address generated by the GSP 400 and sent to address output register 855 and then onto lines A0-A11, and S0-S3. In this manner, the data is forwarded to the appropriate SPROC so that it may be booted in a slave mode. It will be appreciated by those skilled in the art, that if the EPROM is wide enough to contain data and address information, that information can be written to host bus 165 and read directly by a slave SPROC or other device outside the memory space of the master SPROC. Because external memories vary in speed, the host port 800 is provided with a wait state generator 870 which can lengthen the read or write strobe generated by strobe generator 865. The host port 800 is also provided with a host interface controller 880 which is essentially distributed circuitry which controls the internal timing of the host port 800. A.1 Functional description of The Parallel Port The parallel port (PPORT0) is a 24-bit asynchronous, bidirectional port with a 16-bit (64K) address bus. The port allows for 8-, 16-, or 24-bit parallel data transfers between the SPROC chip and an external controller, memory-mapped peripheral, or external memory. The port has programmable WAIT states to allow for slow memory access. A data acknowledge signal is also generated for this interface. Two operating modes--master and slave--allow the SPROC chip to operate either as a system controller (master mode), or as a memory-mapped peripheral to an external controller (slave mode). An input pin, MASTER, is dedicated to setting master or slave mode operation. In master mode, the SPROC chip automatically up-loads its configuration program from an external 8-bit PROM into internal RAM, at the initiation of boot. In slave mode, the chip relies on an external controller for its configuration. A system using multiple SPROC chips should have a single bus controller. This may be an external controller or a master SPROC chip. All other SPROC chips in the system should be configured in slave mode. The bus controller should individually enable the chip select input, CS, of each slave SPROC chip while the slave chip is being configured. The 16-bit address field (ADDRESS[15:0]) supports up to 16 SPROC chips interconnected in the same system. The external controller, memory-mapped peripheral, or memory may communicate with a SPROC chip in 8-, 16-, or 24-bit format. Format selection is accomplished with the MODE[2:0] pins. In 8- or 16-bit formats, the data may be most significant (msb) or least significant (lsb) byte or word first. In 16- and 24-bit modes, data is preferably always msb-justified within the word being transferred, and the lsb byte is zero-filled for 32-bit data transfer (i.e., in the second 16-bit word). To accommodate 8- and 16-bit modes, two extended address bits are included. These bits (EADDRESS[1:0]) are located at the lsb-end of the address bus. In master mode, these are driven output lines. In slave mode, they are configured as inputs and are driven by the external controller. The following subsections describe data transfers via the parallel port for different sources and destinations. In all types of parallel port data transfers, signal values at the slave SPROC chip's mode (MODE[2:0]) and address (ADDRESS[15:0]) inputs must be stable before the chip select (CS) and read (RD), or chip select and write (WR) request goes LOW. At that time, the address is latched into the slave SPROC chip. Subsequently, after values on the data bus (DATA[23:0]) become valid, data is latched at the destination on the rising edge of the request. To allow asynchronous communication with slow peripherals in master mode, the parallel port supports programmable WAIT states. In a preferred embodiment, a maximum of seven WAIT states are possible, where each state corresponds to one SPROC chip machine cycle, or five master clock pulses. The parallel port also generates a handshaking signal, DTACK (data transfer acknowledge) in slave mode. This normally-HIGH signal goes LOW when the SPROC chip presents valid data in a read operation, or is ready to accept data in a write operation. DTACK is cleared when the external RD or WR strobe goes HIGH. If enabled, a watchdog timer monitors all data transfers, and resets the parallel port if the transaction time is greater than 256 machine cycles. A.2 Master SPROC Chip Read from Slave SPROC Chip or Peripheral A master SPROC chip initiates a read operation from a memory-mapped peripheral or external memory by reading an off-chip memory location. Prior to initiating the READ, the master SPROC chip should set up the communication mode. This includes 8-, 16-, or 24-bit data select, msb/lsb byte order, and number of WAIT states required for the peripheral. The master's internal parallel port mode register controls these options, and therefore should have been previously written to. In master mode, three bits of the parallel port mode register determine number and order of bytes transferred and are output at pins MODE[2:0]. These pins should be connected to the corresponding slave SPROC chip pins, which function as inputs in slave mode, to ensure the slave's communication mode matches the master's. After a read cycle is initiated by the master SPROC chip, no further read or write requests to the parallel port are possible until the current read cycle has been completed. The parallel port will set up a stable address and then drive the RD strobe LOW. The strobe will remain LOW for the number of WAIT states configured in the master's parallel port mode register, and will then be driven HIGH. The data resident on the data bus will be latched into the master SPROC chip on the rising edge of the RD strobe. If the transmission mode is 8- or 16-bit format, the read cycle will be repeated with the next extended address output, as determined by the state of EADDRESS[1:0], until 24 bits of data have been received. The master's parallel port input register is then updated, and the read cycle is complete. The GSP in the master that initiated the read operation must then read the contents of the parallel port input register. With the read cycle completed, the data bus I/O drivers will be reconfigured as output drivers to prevent the data bus from floating. The address bus will be driven with the last address. A.3 Master SPROC Chip Write to Slave SPROC Chip or Peripheral A master SPROC chip initiates a write operation to a memory-mapped peripheral or external memory by writing to an off-chip memory location. Prior to initiating the WRITE, the master SPROC chip should set up the communication mode. This includes 8-, 16-, or 24-bit data select, msb/lsb byte order, and number of WAIT states required for the peripheral. The master's internal parallel port mode register controls these options, and therefore should have been previously written to. In master mode, three bits of the parallel port mode register determine number and order of bytes transferred and are output at pins MODE[2:0]. These pins should be connected to the corresponding slave SPROC chip pins, which function as inputs in this mode, to make the slave's communication mode match the master's. After a write cycle is initiated by the master SPROC chip, in the preferred embodiment no further read or write requests to the parallel port are possible until the current write cycle is complete. The parallel port will output a stable address and then drive the WR strobe LOW. The strobe will remain LOW for the number of WAIT states configured in the master's parallel port mode register. Valid data will be setup on the data bus, and the WR strobe will be driven HIGH after the WAIT interval, latching the data into the slave SPROC chip or peripheral. If the interface is configured in 8- or 16-bit mode, the cycle will be repeated until all bytes have been output. After transmission of the last byte or word, the address bus and data bus will remain driven. A.4 Read from Slave SPROC Chip by an External Controller The external controller will set up address, extended address, and mode inputs, and drive the SPROC chip's chip select input LOW. (If the communication mode will never change, the SPROC chip's MODE[2:0] inputs could be tied to the appropriate logic levels.) The external controller will then drive RD LOW, which will latch the address, extended address (EADDRESS[1:0]), and mode inputs into the slave SPROC chip. The SPROC chip will asynchronously fetch data from the requested internal RAM location. Data will be latched into the external controller when it drives the RD line HIGH again. The controller must ensure that enough time has been given to the slave SPROC chip to fetch the data, given the asynchronous nature of the interface. Alternatively, the SPROC chip drives its normally-high DTACK (data transfer acknowledge) LOW after it has completed the READ, and the controller need only wait for this event before raising X XTO(RD). At that time, the SPROC chip would correspondingly raise DTACK. If the interface is configured for 8- or 16-bit communication, the external controller must set up multiple extended addresses and RD strobes. A.5 Write to Slave SPROC Chip by an External Controller The external controller will set up address, extended address, and mode inputs, and drive the SPROC chip's chip select input LOW. (If the communication mode will never change, the SPROC chip's MODE[2:0] inputs could be tied to the appropriate logic levels.) The external controller will then drive WR LOW, which will latch the address, extended address, and mode inputs into the slave SPROC chip. When the controller returns WR to HIGH, the data present on the data bus will be latched into the SPROC chip. If the interface is configured for 8- or 16-bit communication, the external controller must set up multiple extended addresses and WR strobes. After the final byte or word has been transferred, the data will be asynchronously written to the requested address in SPROC chip RAM. A.6 Data Transfer Modes MODE[0] and MODE[1] determine the number of bytes transferred per RD/WR strobe. MODE[0] distinguishes between a partial word of 8- or 16-bits, and a full 24-bit word. MODE[1] distinguishes between the partial transfers of 8- and 16-bits. All data transfers are aligned with the least significant byte of the data bus. For 16- and 24-bit modes, the most significant byte is left-justified within the data word, with descending order of significance in lower order data bus bytes.
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MODE[1] MODE[0] DATA
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0 0 8-bit
1 0 16-bit
X 1 24-bit
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EADDRESS[1,0], the extended address, specifies which portion of the full 24-bit word is currently being output on the data bus for 8- and 16-bit modes:
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EADDRESS[1] EADDRESS[0] BYTE
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8-BIT MODE, MODE[2]=0
0 0 msb
0 1 mid
1 0 lsb
1 1 unused (write)
O byte (read)
8 BIT MODE, MODE[2]=1
0 O unused (write)
0 byte(read)
0 1 lsb
1 0 mid
1 1 msb
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In receive data mode, the lower byte of the lsb 16-bit word is unused by the SPROC chip. Similarly, in transmit mode, the lower byte of the lsb 16-bit word is filled with zeros. All data is msb-justified. The word ordering for 16-bit data is determined by EADDRESS[1]:
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EADDRESS[1] EADDRESS[0] WORD
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16 BIT MODE, MODE[2]=0
0 X msb
1 X lsb
16 BIT MODE, MODE[21]=1
0 X lsb
1 X msb
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Data transfer in 8- and 16-bit modes is completed when the EADDRESS lines designate the final byte or word, namely, the lsb when MODE[2] is LOW, or the msb when MODE[2] is HIGH. A.7 Boot Mode A SPROC chip enters boot mode when it is configured as a master SPROC chip (its MASTER input is HIGH) and the reset input (RESET) executes a LOW to HIGH transition. During boot, the parallel port is set for 8-bit mode with the maximum number of WAIT states (seven). The master SPROC chip runs an internal program, stored in its control ROM, to upload its configuration from an external 8-bit EPROM into internal RAM. The master SPROC chip will then configure any slave SPROC chips present in the system. The EPROM will be selected by a HIGH on the master SPROC chip's chip select (CS) pin, which is an output in master mode. Slave SPROC chips or memory-mapped peripherals will be selected by a LOW at this signal. In master mode, the value of the CS output is controlled by a bit set in the transmit mode register, which is the second byte of the parallel port mode register. A.8 Watchdog Timer The parallel port incorporates a simple watchdog timer circuit to prevent any undesirable lockup states in the interface. In both master and slave modes, a read or a write flag is set (in the parallel port status register) on the initiation of a read or write operation. This flag is reset on a successful completion of the operation. If, for some reason, the host controller hangs-up in slave mode, or an invalid condition occurs in master mode, the watchdog timer will detect the situation and clear the interface flags, allowing the next operation to be accepted and executed. The watchdog timer is fixed at 256 machine cycles (1280 master clock cycles). The watchdog timer is enabled by setting bit 16 of the parallel port mode register. SPROC reset will disable the watchdog timer. If the watchdog timer is triggered, a flag is set in the parallel port status register. A.9 Multiple I/O Lockout If the parallel port is performing a read or write operation in master mode, and a second write or read operation is initiated before the first I/O operation is completed, the second I/O request is locked out. A lockout flag is set in the parallel port status register. A.10 Input/Output Flags and Lines The RTS and GPIO signals can be used for communication protocols between master and slave SPROC chips. These signals could be used as data-ready signals, requests for data, or microprocessor interrupt requests. RTS[3:0] (request to send) are four pins that function as inputs for a master SPROC chip and as outputs for a slave SPROC chip. The RTS signals of a slave SPROC can be individually set or cleared via the parallel port, as described below. GP[3:0] are four general purpose pins that are individually configurable as either inputs or outputs. During reset, when RESET is LOW, all GPIO signals are set up as inputs. In addition to being subject to internal program control, the configuration of each GP pin, and the value of each GPIO signal configured as an output, are also individually controllable via the parallel pore A.11 Parallel Port Registers The parallel port utilizes five memory-mapped registers for status and control functions. The tables below list the registers and their bit definitions.
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Parallel Port Registers
REGISTER
ADDRESS REGISTER NAME READ/WRITE
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4FB Lockout and watchdog flag
write
clear
4FC Parallel port status register
read
4FD Parallel port input register
read
4FE Parallel port GPIO/RTS
write
control register
4FF Parallel port mode register
write
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Parallel Port Register Bit Definitions
BIT REGISTER 4FC REGISTER 4FE REGISTER 4FF
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0 GP[0] INPUT SETRTS[0]; RX MODE[0]
1 GP[1] INPUT SET RTS[1] RX MODE[1]
2 GP[2] INPUT SET RTS[2] RX MODE[2]
3 GP[3] INPUT SET RTS[3] RX WAIT
STATES [0]
4 MODE[0] CLEAR RTS [0] RX WAIT
STATES [1]
5 MODE[1] CLEAR RTS [1] RX WAIT
STATES [2]
6 MODE[2] CLEAR RTS [2] RX STROBE
DELAY
7 PARALLEL CLEAR RTS[3] PARALLEL
PORT BUSY PORT SOFT
FLAG RESET
8 LOCK OUT SET GPIO[0] CS (master mode
FLAG only)
9 WATCHDOG SET GPIO[1] TX MODE[0]
FLAG
10 READ FLAG SET GPIO[2] TX MODE[1]
11 WRITE FLAG SET GPIO[3] TX MODE[2]
12 RTS[0] INPUT CLEAR GPIO[0] TX WAIT
STATES [0]
13 RTS[1] INPUT CLEAR GPIO[1] TX WAIT
STATES [1]
14 RTS[2] INPUT CLEAR GPIO[2] TX WAIT
STATES [2]
15 RTS[3] INPUT CLEAR GPIO[3] TX STROBE
DELAY
16 N/A OUTPUT GPIO[0]
WATCHDOG
ENABLE
17 N/A OUTPUT GPIO[1]
N/A
18 N/A OUTPUT GPIO[2]
N/A
19 N/A OUTPUT GPIO[3]
N/A
20 NA/ INPUT GPIO[0] N/A
21 N/A INPUT GPIO[1] N/A
22 N/A INPUT GPIO[2] N/A
23 N/A INPUT GPIO[3] N/A
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The parallel port status register, a 16-bit register, contains signal values of selected SPROC chip pins and I/O status flags. This register is updated every machine cycle (5 master clock cycles). Bits 0 through 3 contain the current signal values at the GP pins, which could individually be configured either as inputs or outputs. Similarly, bits 12 through 15 contain the current values at the RTS pins, which are inputs for a master SPROC chip and outputs for a slave. Bits 4 through 6 contain the current value of the MODE configuration. Parallel port status register bit 10 contains the read flag, which is set while the parallel port is performing a read operation. Similarly, bit 11 contains the write flag, which is set during a write operation. (For 8- and 16-bit modes, these flags remain set until the entire 24-bit data word has been transferred.) Bit 7 is set while the parallel port is busy servicing an I/O transaction. Bit 8 is set if the parallel port is busy in master mode and another read or write request is received. The second request will be locked out and the lockout flag set. Bit 9 is set if the watchdog timer is enabled and it detects a timeout out condition. Bits 8 and 9 can only be cleared by a SPROC reset or any write to the lockout and watchdog flag clear register. Any write to the Watchdog/Lockout Flag Clear Register clears watchdog and/or lockout flags set in the parallel port status register. The parallel port input register, a 24-bit register, holds the data word received during a read operation for subsequent storage at the destination address. This register also buffers and assembles the incoming data for 8- and 16-bit modes. This register must be read by a GSP or the access port. The parallel port GPIO/RTS Control register, a 24-bit register, is used to independently configure each GP pin as either an input or an output. It is also used to individually set and clear GP pins that are outputs, and slave SPROC chip RTS pins. Each RTS or GPIO signal has a dedicated 15air of SET and CLEAR bits in the parallel port GPIO/RTS control register. SET and CLEAR bits for RTS signals are in the low byte; SET and CLEAR bits for GPIO signals are in the mid byte. LOW values written to both SET and CLEAR bits results in no change to the associated signal. A HIGH value at the SET bit sets the associated signal HIGH. A HIGH value at the CLEAR bit sets the associated signal LOW. If a HIGH value is written to both SET and CLEAR bits, the CLEAR dominates. Each GPIO signal additionally has a dedicated pair of OUTPUT and INPUT bits in the high byte of the parallel port GPIO/RTS control register to configure the signal as either an output or an input. LOW values written to both OUTPUT and INPUT bits results in no change to the associated signal. A HIGH value at the OUTPUT bit configures the associated GPIO signal as an output. A HIGH value at the INPUT bit configures the associated GPIO signal as an input. If a HIGH value is written to both OUTPUT and INPUT bits, the INPUT dominates. The master SPROC chip's parallel port mode register, a 16-bit register, controls the parallel port mode and timing. When the master SPROC chip is reading from a slave SPROC chip or peripheral, bits 0 through 2 of the parallel port mode register (the RX MODE bits) are output at the master SPROC chip's MODE pins. Register bits 3 through 5 contain the number of WAIT states programmed for the read operation (i.e., they determine the duration of the read strobe LOW level generated by the master SPROC chip). The HIGH level between read strobes is 2 master clock cycles; this duration can be stretched to 5 master clock cycles for slower peripherals by setting bit 6 of the mode register (the RX strobe delay bit). Similarly, when the master SPROC chip is writing to a slave SPROC chip or peripheral, bits 9 through 11 of the parallel port mode register (the TX MODE bits) are output at the master SPROC chip's MODE pins. Register bits 12 through 14 contain the number of WAIT states programmed for the write operation. The HIGH level between write strobes can be stretched for slower peripherals by setting bit 15 of the mode register (the TX strobe delay bit). Bit 8 of the mode register is output at the master SPROC chip's CS pin. A soft reset of the parallel port, which resets the interface flags and RTS lines (but not the GPIO or MODE signals), can be initiated by setting bit 7 of this register.
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Parallel Port Signal Definitions
SIGNAL TYPE* DESCRIPTION
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ADDRESS[15:0]
O(M) I(S)
ADDRESS BUS
BUSGRANT I BUS GRANT causes the SPROC chip to three-state the
address and data buses, and MODE pins, when LOW.
BUSY O PARALLEL PORT BUSY is set LOW when an I/O
operation is occurring, set HIGH when completed. Also
reset HIGH by watchdog timer if a timeout occurs.
CRESET Tied LOW.
CS O(M) I(S)
CHIP SELECT signal. A slave SPROC chip is selected
by setting its CS input LOW. A master SPROC chip
generates this signal as an output, expecting to select a
slave SPROC chip by setting CS LOW, and an external
ROM (containing every slave SPROC chip's
configuration) by setting it HIGH.
DATA[23:0]
I/O PARALLEL PORT DATA BUS--24-bit
input/output/three-statable bidirectional bus.
DTACK O DATA TRANSFER ACKNOWLEDGE. In slave mode,
set LOW by SPROC chip after RD or WR has gone
LOW and the SPROC chip has completed the data
transfer, set HIGH after RD or WR line goes HIGH.
This output is always HIGH for a master SPROC chip.
EADDRESS[1:0]
O(M) I(S)
EXTENDED ADDRESS specifies which portion of the
full 24-bit word is currently being transferred in 8- and
16-bit modes.
GP[3:0] I/O GENERAL PURPOSE I/O lines, individually
configurable as either input or output. Can be used to
interface SPROC chips with each other or with an
external controller as data-ready, microprocessor
interrupt requests, etc. Controlled and configured by a
write to parallel port GPIO/RTS control register.
MASTER I MASTER causes SPROC chip to operate in master mode
when HIGH, and in slave mode when LOW.
MODE[2:0]
O(M) I(S)
MODE[0] differentiates between full 24-bit mode
(HIGH) and partial (8- or 16-bit) modes (LOW).
MODE[1] differentiates between 8-bit mode (HIGH) and
16-bit mode (LOW) for partial data transfers. MODE[2]
specifies whether the first 8- or 16-bit transmission
contains the lsb (HIGH) or the msb (LOW).
RED Tied LOW.
RD O(M) I(S)
READ strobe generated by master SPROC chip or
external controller. A LOW value on RD initiates a
READ operation. RD must remain LOW long enough
to successfully complete the READ; programmed WAIT
states or DTACK handshaking may be utilized for this
purpose. Data latches at the destination when RD
returns HIGH.
RESET I RESET must be held LOW for a minimum of 25 master
clock cycles. after power and clock have stabilized. This
input is a Schmitt trigger type which is suitable for use
with an RC time constant to provide power-on reset.
While RESET is LOW, a master mode SPROC chip
will force address, extended address, and SPROC select
address LOW, while driving CS, RD, and WR
HIGH. Slave SPROC chips connected to the bus will
then be deselected and have driven inputs. MODE[2:0]
will be configured for 8-bit boot mode with msb byte
first and zero WAIT states. The data bus will be driven.
RTS[3:0] I(M) O(S)
REQUEST TO SEND flags. These pins are outputs for
slave SPROC chips and inputs for master SPROC chips.
Can be used to interface slave with master or external
controller as data-ready, microprocessor interrupt
requests, etc. Controlled and configured by write to
parallel port GPIO/RTS control register.
WR O(M) I(S)
WRITE strobe generated by master SPROC chip or
external controller. A LOW value on WR initiates a
WRITE operation. WR must remain LOW long enough
to successfully complete the WRITE; programmed WAIT
states or DTACK handshaking may be utilized for this
purpose. Data latches at the destination when WR
returns HIGH.
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*(M) = master mode, (S) = slave mode, I = input, O = output
While the SPROC 10 aforedescribed with a data RAM 100, a program RAM 150, a boot ROM 190, GSPs 400, DFMs 600, serial ports 700, and a host port 800, is a powerful programmable signal processor in its own right, it is preferable that the SPROC be able to be programmed in a "user friendly" manner. Toward that end, a compiler system which permits a sketch and realize function is provided, as described more particularly with reference to FIG. 12. In addition, an access port 900 and a probe 1000 are provided as tools useful in the development mode of the SPROC device. As aforementioned, the access port 900 permits the user to make changes to the program data stored in RAM 150, and/or changes to other data stored in data RAM 100 while the SPROC is operating. In other words, the access port 900 permits memory contents to be modified while the SPROC is running. In its preferred form, and as seen in FIG. 9, the access port 900 is comprised of a shift register 910, a buffer 920, a decoder 925, and a switch 930 on its input side, and a multiplexer 940 and a parallel load shift register 950 on its output side. On its input side, the access port 900 receives serial data as well as a clock and strobe signal from the development host computer. The data is arranged by the shift register 910 and stored in buffer 920 until the access port is granted time division access to the data RAM bus 125 or the program RAM bus 155. A determination as to which bus the data is to be written is made by decode block 925 which decodes the msbs of the address data stored in buffer 920. The decode block 925 in turn controls switch 930 which connects the buffer 920 to the appropriate bus. The msbs of the address data in the buffer 920 are indicative of which RAM for which the data is destined, as the data RAM and program RAM are given distinct address spaces, as previously described. On the output side, data received via the program RAM bus 155 or the data RAM bus 125 is forwarded via demultiplexer 940 to a shift register 950. The shift register 950 effects a parallel to serial conversion of the data so that serial data may be output together with an appropriate strobe and according to an external clock to a development host computer or the like. By providing the ability to write and read data to the program and data RAMs, the access port 900 has several uses. First, by writing to a particular location (e.g. 406, or 408-40b Hex) in the data RAM, a program break can be initiated. The contents of the various registers of the GSPs which are written into data RAM as a result of the break can than be read. This information is particularly important in the debugging process. Second, if desired, the contents of the registers of the GSPs (as stored in the data RAM) can be modified prior to exiting the break mode by writing data to desired data RAM locations, thus providing an additional tool in the debugging process. Third, if desired, the program (including microinstructions and/or parameters stored as part of microinstructions) stored in the program RAM itself can be altered "on the fly", and can provide the developer with the ability to monitor (in conjunction with the probe 1000 hereinafter described) how a change in a parameter(s) or a change in the program could effect the functioning of the SPROC. The probe 1000 seen in FIG. 8 permits the user to see internal signals generated by the SPROC by monitoring the data RAM bus 125 and capturing the values of data written to one or more data RAM locations. The probe 1000 is generally comprised or a comparator 1010, a DFM 1060 with an input section 1060a and an output section 1060b, and a digital to analog converter 1070. The comparator 1010 is programmable such that any data RAM address may be monitored. The data RAM address is monitored by coupling the comparator 1010 to the data RAM bus 125 and comparing via XNOR gates (not shown) the programmed address to the addresses placed on the bus. When the addresses match, and it is determined that data is being written to the data RAM as opposed to being read from the data RAM, the data is read into the input DFM section 1060a which stores the data until the probe is granted access for writing data to the data RAM 100. At that time, the probe 1000 writes the data to its own buffer in the data RAM. When the probe 1000 is granted access for reading data from the data RAM 100, the output DFM section 1060b of the data probe 1000 pulls the data from its data RAM buffer at the speed set by the output DFM section's divide by N block. The data is then forwarded to the D/A converter 1070 where it is converted into analog format so that it can be viewed on an oscilloscope. In this manner, signals which are being written to any data RAM location may be monitored in real time as desired. By using the access port 900 and the probe 1000 together, the affect of a change of a parameter value entered via the access port 900 may be immediately viewed as an analog signal via probe 1000. Additional details of the probe may be seen with reference to previously incorporated Ser. No. 07/663,395. As seen in FIG. 9, a plurality of SPROC devices 10a, 10b, 10c, . . . may be coupled to together as desired to provide a system of increased signal processing capabilities. Typically, the SPROC devices are coupled and communicate with each other via their serial ports 700, although it is possible for the SPROCs to communicate via their parallel host ports 800. The system of SPROCs can act as a powerful signal processing front end to a logic processor (e.g., microprocessor) 1120, or if desired, can interface directly with electromechanical or electronic components. B. SPROC Development System and Software The above-disclosed SPROC devices 10 are preferably programmed via a development system (SPROClab). The SPROClab development system is a complete set of hardware and software tools for use with a PC to create, test, and debug digital signal processing designs. It was created as a design tool to support the development of code for the SPROC signal processing chip. B.1 Overview The development system provides an interactive design environment to create processing subsystems in graphical form, as signal flow diagrams, and implement those subsystems easily and efficiently on the SPROC chip. Using the system, one can develop efficient signal processing subsystems without having to manually write code or lay out and tune analog circuits. Together with a PC and oscilloscope or other verification equipment, the development system supports the entire development process, including interactive debugging and design verification. Once the designer completes design development, the designer can easily include the signal processing subsystem in the actual application using a SPROC chip and the code generated by the development system. The preferred process of programming a SPROC is as follows. The designer must first define the signal processing application and determine design requirements. The design is then preferably placed by the designer in a signal flow diagram (using a graphic user interface). Parameters for the various blocks of the design are defined by the designer, including parameters of filters (e.g., low-pass or high pass, and cut-off frequency) and, if desired, transfer functions. Once the signal flow diagram and parameters of the blocks in the signal flow diagram are set, the diagram and parameters are automatically converted into code by the software. The development system's SPROCview graphical design interface enables a simple graphical approach to design capture. Capturing the design consists of entering the design as a signal flow diagram. To enter the diagram, the designer arranges and connects icons that represent processing functions into a schematic diagram defining the signal flow of the system. As the designer selects and places the icons, certain variables and parameters must also be entered that define how the functions represented by the icons will operate. For example, if a design includes an amplifier function, its gain value must be specified. Some functions, like filters and transfer functions, are too complex to be defined using simple parameters. For these functions, one must create a separate data file that includes the detailed definition of the function. When using a filter or a transfer function in a diagram, one must enter a parameter to identify the data file that contains the definition of the function. The schematic diagram and its associated definition data files are the representation of the design upon which all other steps of the process build. The designer should consider them the base record of the design, and always make sure they are current. In designs that include filters or transfer functions, the designer must create the data files that specify the definition of the functions. The SPROCfil filter design interface provides an interactive environment for designing filters. The designer must define transfer functions using a text editor. After the designer captures the design and defines any necessary filters or transfer functions, the diagram and definition data files must be convened into code and a configuration file must be generated to run on the chip. The SPROCbuild utility completes this for the designer by automatically convening the diagram and data files into code, scheduling and linking the code, and generating a configuration file for the chip. Each time the designer modifies the diagram or the definition data files, the files must be converted again to produce an up-to-date configuration file. To debug a design, the designer must transfer the configuration file onto the chip and run the design. The SPROCdrive interface (SDI) allows one to write the configuration to the chip and begin design execution. Using SDI, the designer can evaluate design performance by accessing the value of data in chip memory. If the development system is connected to an oscilloscope, one can view the waveforms represented by this data. If the development system is connected to a target analog subsystem, one can see how the design performs in the actual application. To optimize the design, the designer can modify the values of data and observe the corresponding changes in design performance. If the development system is connected to a signal generator, one can simulate various input signals and evaluate how the design reacts. Changes made to design parameters using SDI are temporary. The designer must modify the schematic diagram and/or definition data files, then convert the files again and generate a new configuration file to make design modifications permanent. Once the designer has debugged and optimized the design, modified the diagram, and generated the final configuration fie, the signal processing design can be ported for use in the end application. If the application is to run from a self-booting chip, the configuration file can be used to burn an EPROM, and the chip and its EPROM can be placed on a specific printed circuit board. If the application is to run from a microprocessor, the SPROClink microprocessor interface (SMI) helps the designer develop a microprocessor application that can use the signal processing design. The designer must generate a special version of the configuration file, create the microprocessor application, and memory map the chip into the microprocessor configuration. The development system comprises both hardware and software tools designed to help the designer complete the development process. The tools are designed in parallel with the SPROC chip to extract maximum efficiency and performance from the chip without compromising ease-of-use. The development system includes hardware and software. The hardware components are described as follows: The SPROCboard evaluation board is a printed circuit board with one SPROC chip, digital-to-analog and analog-to-digital converters, and various communications interfaces and additional components and circuitry necessary to evaluate signal processing design performance during development. The designer can connect an oscilloscope, signal generator, or analog subsystem to the evaluation board to verify and evaluate the design. The SPROCbox interface unit provides an I/O connection between the SPROCboard evaluation board and the PC. It also connects the evaluation board to the power supply unit. The power supply unit converts AC power from a standard wall outlet to 5 VDC and 12 VDC power for use by the interface unit and evaluation board. An RS-232 cable connects the PC serial I/O port to the SPROCbox serial I/O port. A special access port cable connects the SPROCbox interface unit to the SPROCboard evaluation board. A security key connects to the PC parallel port. It enables use of the development system software. An integral power cord connects the power supply unit to the AC outlet. A positive-locking DC power cable connects the power supply to the SPROCbox interface unit. An auxiliary DC power cable dai | ||||||