Architecture and methods for a hardware description language source level analysis and debugging system

Abstract

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.

Claims

We claim:

1. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory of the system, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital Gtech circuit representation generator generating a digital Gtech circuit representation stored in the memory, the digital Gtech circuit representation synthesized from the parse data structure and including a Gtech circuit element, the Gtech circuit element referring to the parse node, wherein the parse node also refers to the Gtech circuit element; and

wherein the portion of the text description, related to the Gtech circuit element, can be determined by following the reference from the Gtech circuit element to the parse node and the reference from the parse node to the portion of the text description.

2. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and

wherein the portion of the text description, related to first circuit element, can be determined by following the reference from the first circuit element to the parse node and the reference from the parse node to the portion of the text description.

3. The computer-aided circuit analysis tool of claim 2, wherein said circuit design language is Verilog.

4. The computer-aided circuit analysis tool of claim 2, wherein said circuit design language is VHDL.

5. A computer-aided circuit analysis, tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element;

a numerical physical characteristic of said first circuit element, stored in the memory; and

a computer window generator causing to be displayed a visual object linked to said parse node and having a visual display characteristic determined by said numerical physical characteristic.

6. The computer-aided circuit analysis tool of claim 5,

wherein said first circuit element includes one or more circuit parts, with each circuit part possessing an area, and said numerical physical characteristic is the sum of the areas of said circuit parts.

7. The computer-aided circuit analysis tool of claim 5,

wherein said first circuit element includes a circuit part input pin and a primary input, and said numerical physical characteristic is a time delay from said primary input to said circuit part pin.

8. The computer-aided circuit analysis tool of claim 5,

wherein said visual object is a rectangle having a height, said visual display characteristic being said height.

9. The computer-aided circuit analysis tool of claim 5,

wherein said visual object is a text character said visual display characteristic is a displayed font of said text character.

10. The computer-aided circuit analysis tool of claim 5,

wherein said visual object is a text character and said visual display characteristic is a displayed color of said text character.

11. The computer-aided circuit analysis tool of claim 5, wherein said circuit design language is Verilog.

12. The computer-aided circuit analysis tool of claim 5, wherein said circuit design language is VHDL.

13. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element;

a first display window generator causing to be displayed in a first display window, a first display object linked to said parse node; and

a second display window generator, causing to be displayed in a second display window, a second display object linked to said first circuit element.

14. The computer-aided circuit analysis tool of claim 13,

wherein said first display object includes a sequence of one or more characters from said text description, and

wherein said sequence of characters includes a subsequence of characters related to said parse node in accordance with said circuit description language.

15. The computer-aided circuit analysis tool of claim 14, wherein

said subsequence of characters is displayed with a visual characteristic distinct from the visual characteristic of said sequence of characters not included in said subsequence.

16. The computer-aided circuit analysis tool of claim 13,

wherein said first display object includes a sequence of one or more characters from said text description related to said parse node in accordance with said circuit description language.

17. The computer-aided circuit analysis tool of claim 13, wherein said circuit design language is Verilog.

18. The computer-aided circuit analysis tool of claim 13, wherein said circuit design language is VHDL.

19. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and

an optimizer that optimizes the digital circuit representation, yielding a mapped circuit representation stored in the memory, the mapped digital circuit representation including a second circuit element, the second circuit element referring to one of said parse node or said first circuit element, so that there is a traceable path between the second circuit element and the parse node.

20. The computer-aided circuit analysis tool of claim 19, wherein there is a traceable path between the second circuit element and the first circuit element.

21. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a circuit element, the circuit element referring to the parse node, wherein the parse node also refers to the circuit element; and

a stacked bar graph window display generator causing a stacked bar graph to be displayed on a display screen, the stacked bar graph representing a numerical physical characteristic of the circuit element, stored in the memory.

22. The computer-aided circuit analysis tool of claim 21, wherein the numerical physical characteristic represented by the stacked bar graph is power.

23. The computer-aided circuit analysis tool of claim 21, wherein the numerical physical characteristic represented by the stacked bar graph is area.

24. The computer-aided circuit analysis tool of claim 21, wherein the numerical physical characteristic represented by the stacked bar graph is logic levels.

25. The computer-aided circuit analysis tool of claim 21, further comprising:

a text window display generator causing a portion of the text description that is traceable to the stacked bar graph to be displayed with a different physical property.

26. The computer-aided circuit analysis tool of claim 25, wherein the entire portion of the text description that is traceable to the stacked bar graph is displayed with a predetermined physical property.

27. The computer-aided circuit analysis tool of claim 25, further comprising:

a user input receiver that receives an indication that a user has selected a portion of the stacked bar graph;

wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the stacked bar graph to be displayed with the predetermined physical property in accordance with the user selection.

28. The computer-aided circuit analysis tool of claim 25,

further comprising a user input receiver that receives an indication that a user has selected a portion of the stacked bar graph;

wherein the stacked bar graph window display generator causes a second stacked bar graph to be displayed on a display screen in accordance with the user selection, the second stacked bar graph representing the numerical physical characteristic of a lower hierarchy of said circuit element.

29. The computer-aided circuit analysis tool of claim 21, a user input receiver that receives an indication that a user has selected a portion of the displayed text description;

wherein the stacked bar graph window generator causes to be displayed a stacked bar graph that is traceable to the selected portion of the text description in accordance with the selection of the user.

30. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from the parse data structure and including a plurality of circuit elements, at least one of the plurality of circuit elements referring to the parse node, wherein the parse node also refers to the at least one circuit element; and

a path browser window display generator, causing at least one circuit element, along a first path through a digital circuit representation of the digital system, to be summarized such that only its input and output which are part of the first path are displayed.

31. The computer-aided circuit analysis tool of claim 30, wherein the digital circuit representation is a Gtech circuit representation.

32. The computer-aided circuit analysis tool of claim 30, wherein the digital circuit representation is a gate level circuit representation.

33. The computer-aided circuit analysis tool of claim 30, further comprising:

a text window display generator, causing a portion of the text description that is traceable to the digital circuit representation to be displayed with a predetermined physical property.

34. The computer-aided circuit analysis tool of claim 33, wherein the entire portion of the text description that is traceable to the digital circuit representation is displayed with the predetermined physical property.

35. The computer-aided circuit analysis tool of claim 33, further comprising:

a user input receiver that receives an indication that a user has selected a portion of the path browser summary;

wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the path browser summary to be displayed with a predetermined physical property in accordance with the user selection.

36. The computer-aided circuit analysis tool of claim 35,

a user input receiver that receives an indication that a user has selected a portion of the displayed text description;

wherein the path browser window generator causes to be displayed a path browser summary that is traceable to the selected portion of the text description in accordance with the selection of the user.

37. The computer-aided circuit analysis tool of claim 30,

a user input receiver that receives an indication that a user has selected a portion of the path browser summary;

wherein the text window generator causes to be displayed a text summary that is traceable to the selected portion of the path browser summary in accordance with the selection of the user.

38. The computer-aided circuit analysis tool of claim 30, further comprising:

a user input receiver that receives an indication that a user has indicated a "start/end" path in the circuit representation; and

a text window display generator, causing a portion of the text description that is traceable to the start/end path to be displayed with a predetermined physical property.

39. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory system, in accordance with the text description the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from the parse data structure and including a circuit element, the circuit element referring to the parse node, wherein the parse node also refers to the circuit element; and

a virtual schematic window generator, causing a virtual schematic to be displayed on a display screen, the virtual schematic displaying the text of at least one of a fanin or fanout of a user-selected portion of the text description.

40. The computer-aided circuit analysis tool of claim 39, further comprising:

a text window display generator, causing a portion of the text description that is traceable to one of the fan ins and fanouts of the selection portion of the circuit representation to be displayed with a predetermined physical property.

41. The computer-aided circuit analysis tool of claim 40, wherein the entire portion of the text description that is traceable to the circuit representation is displayed with the predetermined physical property.

42. The computer-aided circuit analysis tool of claim 40, further comprising:

a user input receiver that receives an indication that a user has selected a displayed fanin or fanout;

wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the fanin or fanout to be displayed with a predetermined physical property in accordance with the user selection.

43. The computer-aided circuit analysis tool of claim 40,

a user input receiver that receives an indication that a user has selected a portion of the displayed text description;

wherein the virtual schematic window generator causes to be displayed a portion of the circuit representation, along with its fanins and fanouts that is traceable to the selected portion of the text description in accordance with the selection of the user.

44. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a memory storing;

a parse tree stored in a memory of the system, in accordance with the text description, the parse tree including a parse tree node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

at least one digital circuit representation stored in the memory, the at least one digital circuit representation synthesized from the parse tree and including a circuit element the circuit element referring to the parse tree node, wherein the parse node also refers to the circuit element, the at least one circuit representation being stored in one or more different circuit domains;

a plurality of analysis tools each analysis tool capable of performing analysis on one or more of the circuit domains;

a plurality of display tools, each display tool capable of displaying data from one or more circuit domains;

a domain mapper, capable of mapping between ones of the plurality of circuit domains; and

a selection manager that informs the plurality of display tools when a user has selected a displayed element of the circuit representation within a one of the display tools.

45. The circuit analysis tool of claim 44, wherein one of the plurality of display tools is a display tool capable of displaying data from the at least one of the source domain and the circuit representation domain.

46. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory of the system, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital Gtech circuit representation generator generating a digital Gtech circuit representation stored in the memory, the digital Gtech circuit representation synthesized from the parse data structure and including a Gtech circuit element, the Gtech circuit element referring to the parse node, wherein the parse node also refers to the Gtech circuit element; and

wherein the Gtech circuit element, related to the portion of the text description, can be determined by following the reference from the portion of the text description to the parse node and the reference from the parse node to the Gtech circuit element.

47. A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:

a parse generator generating a parse data structure stored in a memory, in accordance with the text description, the parse data structure including a parse node, wherein a portion of the text description refers to the parse node and the parse node refers to the portion of the text description;

a digital circuit representation generator generating a digital circuit representation stored in the memory, the digital circuit representation synthesized from the parse data structure and including a first circuit element, the first circuit element referring to the parse node, wherein the parse node also refers to the first circuit element; and

wherein the first circuit element, related to the portion of the text description, can be determined by following the reference from the portion of the text description to the parse node and the reference from the parse node to the first circuit element.

48. The computer-aided circuit analysis tool of claim 47, wherein said circuit design language is Verilog.

49. The computer-aided circuit analysis tool of claim 47, wherein said circuit design language is VHDL.

50. The computer-aided circuit analysis tool of claim 47, further comprising:

a numerical physical characteristic of said first circuit element, stored in the memory; and

a computer window generator causing to be displayed a visual object linked to said parse node and having a visual display characteristic determined by said numerical physical characteristic.

51. The computer-aided circuit analysis tool of claim 50,

wherein said first circuit element includes one or more circuit parts, with each circuit part possessing an area, and said numerical physical characteristic is the sum of the areas of said circuit parts.

52. The computer-aided circuit analysis tool of claim 50,

wherein said first circuit element includes a circuit part input pin and a primary input, and said numerical physical characteristic is a time delay from said primary input to said circuit part pin.

53. The computer-aided circuit analysis tool of claim 50,

wherein said visual object is a rectangle having a height, said visual display characteristic being said height.

54. The computer-aided circuit analysis tool of claim 50,

wherein said visual object is a text character said visual display characteristic is a displayed font of said text character.

55. The computer-aided circuit analysis tool of claim 50,

wherein said visual object is a text character and said visual display characteristic is a displayed color of said text character.

56. The computer-aided circuit analysis tool of claim 50, wherein said circuit design language is Verilog.

57. The computer-aided circuit analysis tool of claim 50, wherein said circuit design language is VHDL.

58. The computer-aided circuit analysis tool of claim 47, further comprising:

a first display window generator causing to be displayed in a first display window, a first display object linked to said parse node; and

a second display window generator, causing to be displayed in a second display window, a second display object linked to said first circuit element.

59. The computer-aided circuit analysis tool of claim 58,

wherein said first display object includes a sequence of one or more characters from said text description; and

wherein said sequence of characters includes a subsequence of characters related to said parse node in accordance with said circuit description language.

60. The computer-aided circuit analysis tool of claim 57, wherein

said subsequence of characters is displayed with a visual characteristic distinct from the visual characteristic of said sequence of characters not included in said subsequence.

61. The computer-aided circuit analysis tool of claim 58, wherein said first display object includes a sequence of one or more characters from said text description related to said parse node in accordance with said circuit description language.

62. The computer-aided circuit analysis tool of claim 58, wherein said circuit design language is Verilog.

63. The computer-aided circuit analysis tool of claim 58, wherein said circuit design language is VHDL.

64. The tool of claim 47, further comprising:

an optimizer that optimizes the digital circuit representation, yielding a mapped circuit representation stored in the memory, the mapped digital circuit representation including a second circuit element, the second circuit element referring to one of said parse node or said first circuit element, so that there is a traceable path between the second circuit element and the parse node.

65. The computer-aided circuit analysis tool of claim 64, wherein there is a traceable path between the second circuit element and the first circuit element.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of computer aided design for digital circuits, and particularly to analyzing and debugging digital circuits constructed from HDL source text using logic or behavioral synthesis.

2. Statement of the Related Art

A digital circuit designer needs to ensure that the digital circuit performs the correct function subject to many design constraints. For example, the digital circuit should perform the correct computation in the proper amount of time. The area that the digital circuit occupies on a semiconductor die should remain within certain bounds. The power that the digital circuit consumes while operating should also remain within specified bounds. To be economically manufacturable, the digital circuit should be testable. An economically useful digital circuit should not take too long to design, manufacture, test or use.

The digital circuit design process typically involves translating the designer's sometimes incipient thoughts about the function and constraints into the tooling necessary to produce a working digital circuit. For example, producing a full-custom semiconductor chip requires producing masks that define the deposition of chemicals into a substrate as well as producing test patterns that exercise the final product. As another example of tooling, producing a field programmable gate array requires generating the bit pattern to be downloaded into the chip to specify the configuration of the architecture. Computer Aided Design (CAD) tools facilitate the iterative translation of the designer's developing thoughts into the tooling required to produce a working digital circuit that satisfies the design constraints. The process of iteratively adjusting a design to meet its constraints is called debugging. The process of identifying various properties of different parts of a digital circuit is called analysis. In order to debug a digital circuit, the designer must first analyze the circuit to ascertain where problems occur.

The typical historical model of the digital design process using conventional CAD tools for a semiconductor chip is as follows. The designer first conceives of a particular function to implement, as well as constraints such as timing or area that the implementation must meet. Next, historically, the designer mentally transforms the desired function into a high level generic technology circuit consisting of components such as gates, adders, registers and RAMs.

The designer then chooses a technology provided by a semiconductor vendor from which the circuit components will be chosen. The process of choosing circuit components from a specific technology is called mapping; mapping creates a mapped circuit. To map a circuit, the designer draws a schematic of a mapped circuit that implements the desired function with a CAD schematic capture tool. The mapped circuit includes parts from a software representation of a specific technology library which is supplied by a silicon vendor. The schematic shows how more primitive functional elements, such as gates or transistors, connect together to form more sophisticated functions such as arithmetic logic units. In addition, modern schematic capture tools allow the designer to divide the design hierarchically into interconnected pieces, and then allow the user to specify the details of each of the pieces separately. For example, Design Architect by Mentor Graphics of Wilsonville, Oreg. provides these schematic capture functions.

Conventional CAD tools, such as those indicated above, can then take the connections in the schematic and other information to evaluate the mapped circuit and to specify the tooling necessary to construct the circuit. Such tools evaluate the mapped circuit in many ways. For example, commercial CAD tools often have a simulator that predicts the response of the mapped circuit to designer specified input patterns. QuickSim II by Mentor Graphics of Wilsonville, Oreg. is a commonly used simulator. Another common CAD tool is a path delay analyzer that identifies the longest timing path in a mapped circuit design. DesignTime by Synopsys, Inc. of Mountain View, Calif. is a tool that provides path delay analysis.

There are conventional CAD tools that have the ability to generate the geometric layout of the digital circuit with layout tools. Cell3 Ensemble by Cadence of San Jose, Calif. is an example of this type of tool. Layout tools are required to produce masks to make a semiconductor chip.

There are conventional CAD tools that have the ability to check that the digital circuit meets the design rules, and to identify the location of any errors to the designer. Design rules help ensure that the specified digital circuit will operate once manufactured.

There are conventional CAD tools that are used to determine how testable a mapped circuit is, and to generate test patterns automatically. Showing the designer the parts of the mapped circuit that are not testable allows the designer to make modifications that will increase the probability of making a successful chip or circuit. Generating test patterns automatically allows for more thorough testing of the digital circuit immediately after manufacturing.

As described above, the concept of analyzing a mapped circuit design historically refers to the process by which a digital circuit designer specified a particular implementation with a schematic capture tool, and then used various circuit evaluation tools to verify that the implementation did what the digital circuit designer wanted. For example, the designer would use a simulator to determine if the mapped circuit produced appropriate outputs from specified inputs. The designer could use the path delay analyzer to determine whether the current design was fast enough to meet the timing constraints. The layout tools could inform the designer whether the design meets the area constraints.

When a particular design did not meet the designer's constraints, the designer then modified the design. For example, if the mapped circuit was too slow, the designer identified the part of the mapped circuit that was too slow, and revised it to increase performance. If the mapped circuit was too large, then the designer revised the mapped circuit to use fewer or smaller components. If the mapped circuit did not behave as required, the designer changed the components and the interconnections to produce the correct function. Because the conventional CAD tools began the analysis with the mapped circuit, the timing or area problems could be readily identified to the designer. Because the designer specified the structure of the mapped circuit, the designer could thoughtfully make adjustments. However, the CAD tools were limited in their ability to identify functional problems because the designer had mentally performed the transformation from desired function to mapped circuit. In other words the CAD tools included structural information about the digital circuit, but did not include data concerning the high level functionality of the digital circuit.

Logic synthesis was developed to provide the designer with an automatic mechanism to translate a hardware description language (HDL) description of a desired function to a structural description of a digital circuit that performed the desired function. Logic synthesis begins with the designer describing the desired function using VHDL, Verilog, or any other logic synthesis source language, to specify the behavior. This allows the designer to specify the digital circuit at a higher level, and allows the CAD tools to assist the designer in defining the functionality of the digital circuit. A software translator then converts that description into generic technology structures that directly correspond statement by statement with the designer's description.

In logic synthesis, translation is followed by logic optimization. Optimization involves two steps. First, it replaces the directly translated structure with a functionally equivalent, yet improved structure. Second, the optimization process includes an optional step called mapping the design. Mapping replaces the generic technology structures with structures from a specific technology library. Technology libraries are provided by silicon vendors to specify the types of parts which the vendor can manufacture. Technology libraries include specific information regarding the functionality and physical characteristics such as area and delay of gates which can be built by the silicon vendor. Technology libraries are designed to work with synthesis systems. A synthesis system can use a technology library to choose available gates from which the silicon vendor can fabricate the digital circuit.

Unfortunately, the transformations performed by the logic optimizer usually modify the structure that was present in the pre-optimization circuit. This results in a mapped circuit that is not easily recognized by the designer. The fact that the designer generally can not readily recognize the original function performed by the mapped circuit makes analyzing optimized mapped circuits difficult. Conventional evaluation tools can determine the timing or area problems in the mapped circuit, but the designer often can not relate those problems easily to the HDL source specification. Theoretically, the designer could manually determine what part of the HDL specification caused the problem. With that insight, the designer could make the desired changes at the HDL specification, and resynthesize the entire digital circuit. If the designer's problem occurred in a part of the mapped circuit that passed through the optimizer with few changes, manual backtracking might work. However, the optimization process generally makes many changes, making it either difficult or impossible to backtrack because many points in the original generic technology circuit do not exist in the mapped circuit.

Furthermore, the level of circuit improvement produced by logic optimization is not consistent. Due to the computational complexity of the optimization problem, optimizers must rely upon approximate, rather than optimal algorithms. The effect of the optimizer is, in some senses, random, because a slightly different initial circuit can significantly affect the choices that the optimizer makes. Therefore, it is impossible to predict consistently the percentage improvement that the optimizer will deliver. A small change in the HDL specification may result not only in a substantially different mapped circuit, but may also result in a mapped circuit which is substantially larger or slower.

As one possible solution, the designer can directly modify the mapped circuit produced by the synthesis software. However, this does not allow the designer to resynthesize the design from the HDL specification because the designer's logic changes is overwritten by subsequent translation and optimization steps. This reduces the value gained by using the synthesis approach to design.

One prior system which attempted to link HDL source text to generic technology and mapped circuits was "Source to Gates" which is included as a feature of Design Analyzer by Synopsys Inc., located in Mountain View, Calif. Source to Gates allowed the designer to trace between HDL source and schematics. Source to Gates did not prove useful because its ability to trace post synthesis mapped structures to the HDL source was limited to optimization invariant circuit structures that were present in the HDL source. Although Source to Gates did allow the designer to trace between schematics of the generic technology circuit and the HDL source, this feature was not particularly useful because it required viewing of the generic technology circuit which was not directly meaningful to the designer and no analysis link to the source was provided.

An additional limitation of Source to Gates is that it stores text location in terms of row and column numbers. Thus, when tracing from a schematic to HDL text, Source to Gates only hilights the first character of the appropriate parse node. There is no indication of the range of the parse node. There are two modes in Source to Gates when tracing from text to the schematic. Exact match mode forces the user to place the cursor on the first character of a parse node in order to enable tracing to the schematic. Closest match mode searches forwards and backwards in the text to find the closest traceable character. In this mode, the user does not know exactly what will be traced.

Another method for minimizing the backtracking problem in the analysis of an optimized mapped circuit is to partition the design into hierarchical components, and translate and optimize the smaller pieces. Because the translation and optimization tools generally do not traverse primary inputs and outputs, the HDL description can be correlated with a particular resulting mapped sub-circuit, thus reducing the size of the backtracking problem. However, repartitioning has the disadvantage that the designer may have to rewrite functionally correct, but nonetheless problematic, HDL source code to isolate the troublesome parts of the mapped circuit. In addition, this approach will greatly limit the optimizer's ability to reduce the area and increase the speed of the resulting circuits because the optimizer will be constrained by the designer's partition.

In addition, it is possible for a designer to be mislead by the results obtained by analysis by partitioning. The designer's bug in the circuit might be that it is too slow or too big. Partitioning the HDL source to locate the cause will likely result in a different circuit than the unpartitioned source. Therefore, the problem that the designer is chasing may be affected by the analysis process itself.

Conventionally, using a synthesizer to transform an HDL source specification into a mapped circuit can also cause substantial computational problems if one needs to incorporate minor changes into a design late in the design process. For example, a designer could have the design fairly close to completion when the designer discovers the need to make a small functional change, such as inverting a particular signal. Intuitively, one would expect that such a small change would require only a small change in the digital circuit all the way to the layout level. However, it is quite possible that, with conventional translation and optimization tools, a small change could require substantial changes in the mapped circuit and the circuit layout. With current tools, a designer can often limit this kind of problem by partitioning the design into smaller pieces and thus limiting the effect to the directly implicated pieces. However, as described previously, inappropriate or unduly narrow partitioning can limit the ability of the optimization tools to construct a mapped circuit which meets the design constraints.

A CONVENTIONAL DESIGN AND DEBUGGING PROCESS OVERVIEW

FIG. 1 shows an overview of the conventional process for designing, analyzing, and debugging digital circuits specified with a Hardware Description Language (HDL). The process begins with the designer writing HDL source code 100. A typical language used for specifying digital circuits is VHDL which is described in the IEEE Standard VHDL Language Reference Manual available from the Institute of Electrical and Electronic Engineers in Piscataway, N.J., which is hereby incorporated by reference. VHDL stands for Very high speed integrated circuit Hardware Description Language. Another language used for specifying digital circuits is Verilog that is described in Hardware Modeling with Verilog HDL by Eliezer Sternheim, Rajvir Singh, and Yatin Trivedi, published by Automata Publishing Company, Palo Alto, Calif., 1990, which is hereby incorporated by reference. Verilog is also described in the Verilog Hardware Description Language Reference Manual (LRM), version 1.0, November 1991, which is published by Open Verilog International, and is hereby incorporated by reference. The examples used in this document are in VHDL, but the principles readily apply to other circuit specification languages.

After writing a HDL description of a desired function, the designer then simulates the function 101 embedded in the description with a HDL simulator. An example of a functional simulator is VHDL System Simulator that is available from Synopsys, Inc. of Mountain View, Calif. The functional simulator allows the designer to determine whether the circuit produces correct values in response to inputs without regard to timing, area or power constraints. A functional simulator can perform function-only simulation relatively quickly, thus enabling the designer to determine that the circuit will produce the desired output.

If there is a problem with the function, the designer can fix function problems 102 by examining the simulation output and going back to writing HDL code 100. Functional simulation executes the source specification directly without generating generic technology or mapped circuits. Therefore, problems identified during functional simulation can readily be linked to their cause in the HDL source.

If the designer believes that the digital circuit described by the HDL source provides the correct function, the designer specifies constraints for the synthesis process 103, e.g. maximum clocking periods, total circuit area, and maximum power. This part of the process is described in Design Compiler Family Reference Manual, Version 3.1a, which is available from Synopsys, Inc. of Mountain View, Calif. and is hereby incorporated by reference. Examples of Computer Aided Design software that use constraint specification are Synergy by Cadence, and Autologic by Mentor Graphics, and Design Compiler by Synopsys.

After developing constraints, the designer then proceeds to synthesize 104 a mapped circuit from the HDL description produced in the writing HDL 100 step. This step involves translating the HDL source description into an initial generic technology circuit that corresponds directly with the statements in the source HDL. An example of software that performs this function is described in the VHDL Compiler Reference Manual, Version 3.1a, which is available from Synopsys, and is hereby incorporated by reference. After translation, the initial generic technology circuit is then optimized into a mapped circuit that meets the performance constraints established in step 103. Prior to optimization, it is a straight-forward task to identify which element of the initial generic technology circuit corresponds to what part of the HDL source code. Conventionally, because of the extensive manipulations performed during the optimization process, such identification after optimization becomes almost impossible except at registers and module interface boundaries.

FIG. 2 shows the intermediate data structures involved in the synthesis process 104. The synthesis process begins with HDL source 900. The translator creates a data structure called a parse tree 901 that represents the organizational structure of the HDL. The translator then turns the parse tree into an initial generic technology circuit 902. Russ B. Segal's Master's Thesis, "BDSYN: Logic Design Translator" at the University of California at Berkeley, Memo#UCB/ERL M87/33, describes such a translator, and is hereby incorporated by reference. U.S. patent application 07/632,439, filed on Dec. 21, 1990, entitled "Method and Apparatus for Synthesizing HDL Descriptions with Conditional Assignments" by Gregory et al, and commonly assigned to Synopsys, Inc. also describes such a translator, and is hereby incorporated by reference. An example of a tool that does this is version 3.1a of the HDL compiler available from Synopsys, Inc.

An optimizer is used to produce the mapped circuit 903 from the initial generic technology circuit 902. The optimization process is explained in "Logic Synthesis Through Local Transformations" by J. Darringer, W. Joyner, L. Berman, and L. Trevillyan in the IBM Journal of Research and Development, volume 25, number 4, July 1981, pages 272-280, which is hereby incorporated by reference. It is also explained in "LSS: A System for Production Logic Synthesis" by J. Darringer, D. Brand, J. Gerbi, W. Joyner, and L. Trevillyan in the IBM Journal of Research and Development, volume 28, number 5, September 1984, pages 537-545, which is hereby incorporated by reference. It is also explained in "MIS: A Multiple-Level Logic Optimization System" by R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang in the IEEE Transactions on Computer Aided Design, Volume 6, number 6, November 1987, pages 1062-1081, which is hereby incorporated by reference. It is also explained in the Ph.D. dissertation "Logic Synthesis for VLSI Design" by R. Rudell at the University of California at Berkeley in 1989, which is hereby incorporated by reference. The optimization process is also described in the Design Compiler Family Reference Manual, version 3.1a which is available from Synopsys, and is hereby incorporated by reference. An example of software that performs this function is the Design Compiler available from Synopsys, Inc. Other examples of software that performs optimization include Synergy from Cadence, Inc., and AutoLogic by Mentor Graphics.

One approach to optimization is to group one or more logic elements together, and replace those elements with a functionally equivalent collection of elements that has better characteristics than the collection of elements replaced. This results in an intermediate circuit that is functionally equivalent to the original. This intermediate circuit can then have some or all of its elements grouped for another replacement. The process can be performed on either generic technology or mapped logic circuits. The process is repeated until the optimizer meets the constraints imposed in step 103 of FIG. 1, or is unable to make any further improvement.

The components of the initial generic technology circuit fall into two groups: those components that must be preserved through the optimization process, and those that can be replaced with functional equivalents. For example, a logic optimizer may replace a block of boolean logic with another block so long as function is maintained. Generally, replaceable components can also be eliminated. Examples of components that are generally preserved through the optimization process are primary inputs, primary outputs and registers.

After developing a mapped circuit, the designer can then analyze the mapped circuit 105 using conventional analysis tools, as shown in FIG. 1. For example, the designer could estimate the area that the mapped circuit consumes or what the longest delay path is in the mapped circuit. This analysis can identify problems to the designer. The analysis report 904 is often a text document, as shown in FIG. 1.

After identifying timing, area, testing or power problems with the analysis tools, the designer then adjusts the mapped circuit to fix these problems 108. Ideally, the designer goes back to the HDL where the function is specified and make adjustments there. However, because it is currently hard to identify the specific places in the source HDL that led to the problem, modifying the appropriate part of the HDL is currently not an effective debugging technique. The designer can usually identify which hierarchical module contains some of the problem. The designer can then manually rewrite that module to create more primary inputs and outputs to examine. This is very time consuming and is generally done as a last resort. A method for automatically adding additional primary inputs and outputs is needed to make this approach practical. Alternatively, the designer could adjust the constraints 103 and synthesize the mapped circuit 104 again to see if the problem is alleviated.

After analyzing the mapped circuit 105, the designer then releases the design for fabrication 106.

SYSTEM PERFORMANCE

In addition to the analysis problems presented by the transformations made by the logic synthesis process, there are also difficulties associated with efficiently and economically constructing CAD systems that compute and display analysis results. Conceptually, after specifying a design, analyzing a digital circuit involves having the designer repeatedly (1) determine a particular characteristic or property that the designer wants to know about, such as area, timing or power, (2) identify a kind of analysis that will provide information about that characteristic, (3) instruct the CAD system to perform that analysis, (4) display the results of that analysis, and (5) gain insight into the desired characteristic from the display. The designer is interested in completing these steps as quickly as possible. Digital circuit CAD tools have historically facilitated this goal by making the instruction and display steps computationally efficient. To improve response times, digital circuit CAD tools have often tightly coupled the software that performed the analysis to the software that performed the display function. This was often done by having the display software depend heavily on the data structure used to process or store the results of the analysis.

For example, timing analysis often reveals the portions of the mapped circuit that are too slow. Reviewing this analysis historically has involved examining the schematic and tracing the critical path. However, as described previously, the schematic may have little to do with the designer's HDL source specification of the digital circuit. Thus, the conventional analysis method does not relate the mapped circuit problem to its HDL source. Therefore, it is not easy for the designer to know what HDL to change to meet the design constraints.

BACKGROUND CONCLUSION

Using HDL synthesis can simplify the task of digital circuit design by allowing the designer to specify the required function in an HDL textual description without specifying the details of the mapped circuit implementation, After creating a mapped circuit using synthesis, the designer can use conventional mapped circuit analysis tools to determine characteristics of the mapped circuit. Conventional analysis will describe such things as the area consumed by different parts of the mapped circuit, or what the longest delay path is through the circuit. Using these analysis results, the designer can then identify which portions of the mapped circuit are problematic. However, because the optimization portion of synthesis often transforms the design substantially, it is difficult, if not impossible, except in certain special cases, to relate specific portions of the mapped circuit to the HDL source that generated those portions. This inability to trace the mapped circuit analysis results easily to the HDL source represents a substantial barrier for analyzing circuits efficiently. Thus, there has been a need for a system which allows the designer to analyze a digital circuit design in terms of the source HDL.

SUMMARY OF THE INVENTION

An aspect of the present invention provides a method for displaying the results of synthesized circuit analysis visually near the HDL source specification that generated the circuit. Circuit analysis provides information about the characteristics of each portion of the synthesized circuit. An aspect of the present invention relates the analysis results of each portion of the synthesized circuit to the particular part of the HDL specification that generated that circuit portion. This permits the designer to modify the part of the HDL specification that is responsible for problems identified by circuit analysis.

The synthesis process works by translating HDL source code into an initial circuit. Each point in the initial circuit corresponds directly with a particular construct in the HDL source. A final, more efficient circuit is constructed from the initial circuit by logic optimization. Connecting the results of the analysis to the source requires identifying points in the final circuit that be traced directly to the initial circuit. Circuit analysis results corresponding to these invariant points in the circuit can therefore be directly related to the appropriate part of the HDL source, and thus can be displayed near that part.

Another aspect of the present invention provides a method for introducing additional points in the design that remain traceable through the optimization process without requiring reorganization or modification of the HDL source. The present invention provides these additional points, for example, by artificially injecting primary inputs or outputs into the initial circuit, and noting where in the HDL source these points came from.

In another aspect of the present invention provides a method for linking information gleaned from evaluating and analyzing a synthesized circuit to the source code that produced the circuit. The present invention establishes the link by providing a designer with the ability to mark the synthesis source code in the places that the designer wants to be able to debug. In a current embodiment, the designer marks the source code with a particular text phrase, such as "probe", along with some additional optional information. During translation, the translator generates a circuit the provides the same function as it did without the "probe" statement, but adds additional information or components to the initial circuit that indicate that certain components should not be replaced during optimization. Because those components will not be replaced during optimization, the circuit analysis results corresponding to any unreplaced components that are in the final circuit will be directly and traceably related to those components in the initial circuit. Because those components are traceably related to the source HDL, the results are traceably related to the source HDL, and therefore be displayed near the appropriate portion of the HDL. Allowing for the interjection of unreplaced components by the designer facilitates debugging without rewriting the designer's original hierarchical design or manually backtracking through the optimization process.

In another aspect of the invention, the designer can assign a priority level to each probe to help manage the debugging process. These priority levels could then be used to activate or deactivate selected probes as a group. An activated probe would establish a link through the synthesis process to facilitate debugging. An inactive probe would have no effect on the synthesis process, and would not establish a debugging link. Establishing many links would provide the designer with a large degree of debugging information, but could limit the ability of the synthesis process to provide a good circuit. Establishing too few links may not provide enough guidance to the designer to resolve circuit problems. By selectively activating groups of probes at different times during the debugging process, the designer can analyze different portions of the design without the probes themselves unduly interfering in the process.

By providing a facility for displaying the results of circuit analysis near the HDL that created the circuit, the present invention allows a designer to make more effective use of logic synthesis and reduce the complexity of the circuit debugging process.

An aspect of the present invention provides a method and system for processing requests from designers about the characteristics associated with the HDL synthesis source specifying a circuit, and displaying the results of circuit analysis with a consistent set of display tools that are not intimately tied to the data structure used for the circuit analysis. Designing a chip involves constructing different representations for a circuit. Some of these representations, such as a synthesis description language are relatively compact and contain primarily functional information. Other representations, such as a gate level net list, contain correspondingly more information, such as the specific types of components to be used. Still other representations, such as a layout description, contain even more information, such as the specific location of the components on the chip. The different representations can be partitioned into domains with each domain containing circuit representations with a common structure. Then the tool builder can develop domain dependent display tools for examining the state of the design in that domain. In addition, the tool builder can also develop tools that evaluate or analyze the state of the circuit in a particular domain. Display tools showing the circuit structure in one domain can obtain information related to analysis obtained in another domain by the forward and backward linkages.

The designer can inquire about the characteristics related to a specific part of the design by first examining part of the design in one domain with a display tool. This domain is the inquiry domain. After identifying a relevant portion of the design in the inquiry domain, the designer selects a constituent piece of the design to evaluate, and makes an inquiry about that piece. This information constitutes a query. The display tool forwards the identification of the object in the inquiry domain and an identifier indicating the requested analysis or evaluation to a data manager. The data manager then determines the domain that would contain the relevant analysis results. If those results do not yet exist, the data manager invokes the appropriate analysis tool to compute those results, which then may be cached in the data manager. Using the linkage established with the HDL-debugging method, the data manager locates the related object in the analysis domain. From the related object, the appropriate information is passed back to the display tool where the designer can see it displayed appropriately.

One aspect of the present invention provides display tools that are not dependent on the structure of the domain in which the analysis is actually performed. Another aspect of the invention provides analysis tools that are not dependent on the structure of the display domain. Another aspect of the invention is to allow the different display and analysis tools to remain independent from one another. The display tools can maintain their independence by relaying all of their queries through a central data manager. The central data manager performs both domain mapping and analysis tool selection for each query issued by a display tool. Thus, neither the display tools nor the analysis tools need to be aware of the source or destination of any query.

One aspect of the present invention provides a selection manager which communicates a circuit selection made in one display tool to all of the display tools in the system. The selection manager allows the designer to select a circuit object via a display object in a display tool, and then to view an alternate display of the circuit object in an alternate display tool. For example, a circuit object can be selected using a histogram display, and then that circuit object can be viewed using a text display.

One aspect of the present invention simplifies digital circuit analysis before optimization. The direct relationship between the translated circuit and the HDL text is leveraged to allow the designer to improve the translated circuit by improving the HDL. An aspect of the present invention allows the designer to obtain characterizations of attributes such as area and timing of parts of the translated circuit and then to relate automatically selected translated circuit parts to the source HDL from which they were created.

The HDL Analysis System has several advantages over prior art systems such as Source to Gates. First, the HDL text browser uses the text to parse node links described earlier to draw a box around the entire selected parse node. Such boxes are drawn both when the cursor is moved across the display of the HDL text, as well as when a portion of the text is selected. The boxes around the HDL text are much easier to see, and indicate the entire range of the source for the selected circuit object. Secondly, the HDL Analysis System creates many more links than simply between HDL source and schematics. As described previously, many display and analysis tools can be linked to the HDL source. Additional display and analysis tools allow many different kinds of digital circuit analysis to be performed, rather than simply viewing the schematic.

One aspect of the present invention allows a designer to relate circuit analysis results visually and quickly back to the text that produced the portion of the circuit that was responsible for those results. This is achieved by the maintaining the parse tree generated during the translation portion of synthesis, and establishing a bidirectional relationship between a parse node and the circuit elements synthesized from that parse node. In particular, the present invention provides for storing the parse tree node number with each created circuit element, and storing a list of created circuit elements with each parse node.

One aspect of the present invention allows the designer to display a numerical physical characteristic of a circuit element near a reference to the portion of the source HDL text responsible for that circuit element. This is achieved by maintaining references between the parse nodes derived from the text and the circuit elements synthesized from the parse nodes. Among the kinds of physical characteristics the designer would want to know about are the area used by the circuit, the time delay from an input or a clock edge to a particular pin on a cell, the number of gates forming part of the design, the number of logic levels from an input to a particular net, or the power dissipated by one or more cells. Among the kinds of display techniques supported are a stacked bar graph, a histogram, text, a path display, a logic inspector, a selection inspector, and a virtual schematic. Among the kind of text display techniques supported, are hilighting, different fonts, different colors, and different sizes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1: A flow diagram showing an earlier synthesis-analysis process.

FIG. 2: shows intermediate data structures and domains involved in the synthesis process.

FIG. 3: shows the general design and debugging process in accordance with the present invention.

FIG. 4: shows the relationship between HDL text and the mapped logic which makes up a mapped circuit.

FIG. 5: shows how mapped and GTech circuit structures are related to HDL tokens.

FIG. 6: shows how HDL text is related to mapped and GTech circuit structures.

FIG. 7: shows how probe statements are translated.

FIG. 8: shows how a primary input/primary output pair is created.

FIG. 9: illustrates a parse tree associated with some text.

FIG. 10: illustrates a text representation of the parse tree" using "{" to mark the beginning of a node and "}" to mark the end of a node.

FIG. 11: An example of VHDL source with no probes.

FIG. 12: A parse tree corresponding to the source fragment in FIG. 11.

FIG. 13: shows the HDL source of FIG. 11 as a text array.

FIG. 14: shows the text array of FIG. 13 with embedded brace "{" characters surrounding each portion of the text that forms a parse node.

FIG. 15: shows the annotated text array of FIG. 14 with each left brace "{" numbered.

FIG. 16: The VHDL source in FIG. 11 with a statement probe inserted.

FIG. 17: shows the text of FIG. 16 as a linear array of characters with parse node braces inserted.

FIG. 18: shows the HDL source of FIG. 11 with an improper probe directive.

FIG. 19: shows the brace representation of FIG. 18.

FIG. 20: shows some HDL source with a pair of embedded block probe directives.

FIG. 21: shows the brace representation for the HDL source of FIG. 20.

FIG. 22: Translation of the source in FIG. 16 according to the present invention.

FIG. 23: An alternative method of implementing probes in accordance with the present invention.

FIG. 24: A second alternative method of implementing probes in accordance with the present invention.

FIG. 25: A third alternative method of implementing probes in accordance with the present invention.

FIG. 26: shows a GTech circuit with an optimization invariant circuit structure implemented as a primary output.

FIG. 27: shows the mapped circuit resulting from the GTech circuit of FIG. 26.

FIG. 28: A GTech circuit arising from the conventional translation of the source fragment in FIG. 11.

FIG. 29: An optimized mapped circuit created from the GTech circuit of FIG. 25.

FIG. 30: An optimized mapped circuit derived from the GTech circuit of FIG. 22.

FIG. 31: An example of a display relating information found from analysis of the optimized mapped circuit of FIG. 30 to the source HDL.

FIG. 32: shows some VHDL source without probe directives using two process blocks.

FIG. 33: Conventional translation of the source in FIG. 32 into a GTech circuit.

FIG. 34: An optimized mapped circuit derived from the GTech circuit of FIG. 33.

FIG. 35: An example of a display relating data found from analysis of the optimized mapped circuit of FIG. 30 to the source VHDL showing that information can only be related to the highest level in the description.

FIG. 36: The VHDL source from FIG. 32 with a block probe directive installed.

FIG. 37: A GTech circuit generated by translating the VHDL source of FIG. 36.

FIG. 38: The mapped circuit obtained by optimizing the GTech circuit of FIG. 37.

FIG. 39: An example of a display relating data found from analysis of the optimized mapped circuit of FIG. 38 to the source VHDL showing information related to the block probes.

FIG. 40: shows the components of the HDL Analysis Tool.

FIG. 41: shows how the selection manager processes the selection.

FIG. 42: shows how the Data Manager processes a query.

FIG. 43: shows a stacked bar graph display of mapped circuit information.

FIG. 44: shows a stacked bar graph display of mapped circuit information showing the relative contribution of one of the sub-blocks in FIG. 43.

FIG. 45: shows a stacked bar graph display of mapped circuit information showing the relative contribution of one of the sub-blocks in FIG. 44.

FIG. 46: shows a histogram display of mapped circuit timing information.

FIG. 47: shows a text display of HDL source code and GTech circuit information related to that source code.

FIG. 48: shows a virtual schematic display showing the inputs and outputs associated with a particular part of VHDL source code.

FIG. 49: shows another virtual schematic display tracing the output of the display in FIG. 48.

FIG. 50: shows another virtual schematic display tracing the output of the display in FIG. 49.

FIG. 51: shows the Path Browser window.

FIG. 52: shows the logic inspector displaying a graphical representation of logic created by the logic inspector.

FIG. 53: Display of the transitive fan in trace of a particular signal in the source HDL in accordance with the present invention.

FIG. 54: Display of the primary inputs reached from transitive fan-in trace of a particular signal in the source HDL in accordance with the present invention.

FIG. 55: shows the stacked bar graph displaying component counts for the AMD2910A.

FIG. 56: shows the stacked bar graph displaying component counts for the STACK.sub.-- BLK module of the AMD2910A.

FIG. 57: shows the HDL text browser with the source code for the STACK.sub.-- BLK hilighted.

FIG. 58: shows an example of the relationship between the text description, the parse tree, the circuit and the display of a circuit analysis result in accordance with the present invention.

FIG. 59: shows the details of the circuit used in FIG. 58.

FIG. 60: shows an example of the inter-domain selection relationship.

FIG. 61: shows the communication flow as the designer analyzes a specific design.

DETAILED DESCRIPTION OF THE INVENTION

The present invention comprises a novel method for analyzing a digital circuit using the HDL source description from which the digital circuit was created. The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiment shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

In one embodiment, the present implementation is a software system which is implemented using conventional techniques such as message passing, object oriented design, and opaque data structures. These concepts are described in many books on programming. Two such publications are Fundamentals of Programming Languages by Ellis Harowitz, 2nd Edition, published by Computer Science Press in 1984, ISBN 0-88175-004-2 and Programming in C++ by Stephen Dewhurst and Kathy Stark, published Prentice Hall in 1989, ISBN 0-13-723156-3.

1.0 Digital Circuit Synthesis

HDL Synthesis creates a mapped circuit netlist description from an HDL description of the digital circuit's functionality. The present invention extends an HDL Synthesis tool. The following sections describe the structures created while synthesizing the mapped circuit, and how the mapped circuit is created.

1.1 Domain Definitions

A digital circuit is a physical piece of hardware. The outputs of a digital circuit are a function of its inputs. Thus, a property of a digital circuit is its functionality. Another property of a digital circuit is the area required to build it. Another property of a digital circuit is the amount of time required after a signal has been applied to its inputs for its outputs to contain a valid value. Properties such as area and delay are called constraints. A digital circuit designer specifies constraints during synthesis.

The design of a digital circuit can be represented or specified in different ways within the memory of a computer system. Each type of digital circuit representation is called a domain. Different domains contain different amounts of information regarding the physical structure of a circuit. Domains which contain more information regarding the structure of the circuit require more of the computer's memory and require more of the computer's time to construct and manipulate. In some cases, a representation of a digital circuit is treated as if the representation were the actual digital circuit. Some representations contain enough information to build a version of the digital circuit. This section describes the different representations of digital circuits which are used in CAD systems as a digital circuit is being designed.

Domains are used to store different representations of a digital circuit design in a CAD system. In going through the digital circuit design process, the designer, through the CAD system, manipulates and transforms digital data in one domain into other digital data in a new domain. Many digital circuit analysis tools are designed to work with a specific domain. For example, the timing verifier works in the mapped logic domain. Because more detailed domains are larger and slower to manipulate, it is desirable to manipulate the circuit in less detailed domains where possible. The following paragraphs describe what a domain is and the different domains used in the HDL Digital Circuit Analysis Tool.

A domain is a software representation of digital circuit design data that includes common structural characteristics. Each domain represents a particular level of abstraction of the digital circuit design information. Some common domains include an HDL source domain, a generic technology domain, which is also known Is a GTech domain, a gate domain, a layout domain. In addition, other domains may be possible. The digital circuit design data in one domain can be the result of a transformation of digital circuit design data from another domain using digital circuit design tools, such as a logic synthesizer, and libraries of components. The intermediate data structures shown in FIG. 2 are all members of various domains.

The source domain contains the HDL source files that the designer creates in step 100 of FIG. 1 or step 150 of FIG. 3. Circuit representations in this domain may also be called HDL source. The HDL source 900 is also shown in FIG. 2. The source domain also contains the parse tree 901 and symbol table generated during the translation step of logic synthesis. Although the HDL text and the parse tree are different representations of the circuit, they are in the same domain because they contain the same information about the structure of the digital circuit. However, it is necessary to establish efficient links between the HDL text and the parse tree. A method for accomplishing this will be described later. In the source domain, the digital circuit design representation contains information about the desired function of the digital circuit without reference to digital circuit topology. Although it is possible to explicitly instantiate technology dependent components in the source domain, the source domain generally does not reference a specific technology provided by a silicon vendor.

The generic technology, or GTech, domain contains the initial generic technology circuit 902 that arises from the translation step of the synthesis process, as shown in step 104 of FIG. 1 or step 154 of FIG. 3. Circuit representations in this domain may also be called the GTech circuit. VHDL compiler by Synopsys, Inc. of Mountain View, Calif. is a tool that creates GTech circuits. Data stored in the generic technology domain contains information about the topology of the digital circuit, but does not have information about the specific technology to be used. Thus, GTech circuits do not have exact timing or area data. However, one can characterize the timing and area of a GTech circuit by ascertaining the logic levels and component counts of the GTech circuit respectively. The logic levels of a path in a GTech circuit is the number of 2 input GTech gates used to construct the logic comprising the path. The component count of a GTech circuit is the number of 2 input GTech gates used to construct the GTech circuit.

The gate, or mapped logic, domain contains the mapped circuit 903 that arises after the mapping step of the synthesis process. Circuit representations in this domain may also be called mapped circuits. Design Compiler by Synopsys, Inc. of Mountain View, Calif. is a tool that creates mapped circuits. Like the generic technology domain, the data in the gate domain contains information about how components are connected together. However, in the gate domain, a particular technology from a specific silicon vendor is specified, thus providing information about the physical characteristics of the components used to implement the desired function. It is in this domain that preliminary timing, area, power, testability, and other calculations of step 105 of FIG. 1 and FIG. 3 can be made.

The layout domain contains information about the geometric placement of the components on the chip substrate and the connections between the components. Circuit representations in this domain may also be called the laid out circuit. Cell3 Ensemble by Cadence of San Jose, Calif. creates laid out circuits. The digital circuit design information in the layout domain is obtained from the digital circuit design information in the gate domain by using placement and routing tools.

It is also possible to have additional domains, as shown by other domains. However, the majority of analysis for HDL specified digital circuits occurs in the domains described above.

1.1.1 Objects within a Domain

The digital circuit design information within a domain is a collection of interconnected objects, with the objects and the connections possessing certain characteristics. For example, in the source domain the objects may include the text of the HDL source code or the nodes of the parse tree constructed from the source code or the entries in the symbol table. In the gate domain, the objects may include software representations of the individual gates or other library parts or the connections between them.

Subsequent sections describe how intra-domain relationships are established and maintained. Objects in different domains can be related to each other using links discussed in subsequent sections. For instance, objects in the source domain can be related to objects in the generic technology domain by tracking the parse node which creates each translated gate. The system leverages the intradomain links to allow the designer to perform analysis in one domain and view it in another.

1.2 Digital Circuit Definitions

This section defines some terms used to describe digital circuits. The same terms are also used for software data structures which represent digital circuit components in the various domains.

A digital circuit is an interconnected collection of parts. Parts may also be called cells. The digital circuit receives signals from external sources at points called primary inputs. The digital circuit produces signals for external destinations at points called primary outputs. Each part receives input signals and computes output signals. Each part has one or more pins for receiving input signals and producing output signals. In general, pins have a direction. Most pins are either input pins which are called loads, or output pins, which are called drivers. However, some pins may be bidirectional pins which are both inputs and outputs. Bidirectional pins must be handled specially by algorithms which manipulate digital circuit designs. Usually one of two strategies is used for bidirectional pins; either they are treated as both an input pin and an output pin, or they are disallowed by the algorithm in question. In this case, the algorithm cannot manipulate that part of the circuit.

One or more pins from one or more parts are connected together with a net. Each net establishes an electrical connection among the connected pins, and allows the parts to interact with each other. Pins are also connected to primary inputs and primary outputs with nets. For the sake of simplicity, parts may be said to be "connected" to nets, but it is actually pins on the parts which are connected to the nets.

Pins, cells, nets and ports may all be referred to as circuit elements. One or more circuit elements form a circuit element set.

A digital circuit can be specified hierarchically. Some or all of the parts in the digital circuit may themselves be digital circuits composed of more interconnected parts. When a high level part is specified as a digital circuit of other, lower level parts, the pins of the high level part become the primary inputs and primary outputs for the digital circuit comprising the lower level parts. If a high level part is composed of lower level parts, it is called a level of hierarchy.

In the GTech domain, a hierarchical digital circuit specification must terminate with primitive parts. Primitive parts are not specified as a GTech circuit, but with a fixed definition provided by the GTech specification or model maker. The definition for a primitive part specifies the logical function performed by the part. Typically, these parts are functionally simple, such as nand gates, or gates, inverters, or flip-flops. Some primitive parts perform a more sophisticated function, such as addition. In some cases, the primitive part performs a very sophisticated function, such as a microprocessor. The GTech specification or logic model supplier describes the functionality and characteristics of the primitive parts. This may include, but is not limited to, the logic performed by the primitive part.

As with GTech circuits, mapped circuit specifications must also terminate with primitive parts. In this case, the primitive parts are supplied by a semi-conductor vendor and are stored in a technology library. Each part in a semi-conductor vendor technology library contains a description of its function, as well as physical characteristics such as area, timing and power usage. Primitive parts in both the GTech and mapped domains are also known as cells.

1.3 Synthesis Process Overview

Digital Circuit Synthesis consists of translating an HDL description into a netlist with equivalent functionality and then optimizing that netlist to create an improved mapped circuit with the same functionality. The following sections describe this process in more detail.

1.3.1 Translation Process Overview

The conventional translation portion of the synthesis process first converts the HDL text into a parse tree. This is done using conventional parsing techniques such as those described in Compilers, Principles, Techniques and Tools by Alfred V. Aho, Ravi Sethi and Jeffery D. Ullman. A parse tree represents the functional relationships established by the HDL text. Various nodes on the parse tree correspond to functions. The translator then constructs an initial GTech circuit using the parse tree as the guide to selecting the appropriate primitive parts and establishing nets among the pins of those parts. The initial GTech circuit will also be hierarchically specified as required by the parse tree. Importantly, every character in the HDL text is related to a node in the parse tree, and every parse node is directly related to a net or a part or a primary input or a primary output in the initial GTech circuit. For example, each variable declared in the HDL will correspond to a net in the GTech circuit. Also, registers specified in the HDL will correspond to flip-flops or other memory elements in the GTech circuit.

1.3.2 Generic Optimization Process

The conventional translation process produces initial GTech circuits that, if mapped directly to a technology library and built, would be slow and large. To remedy this, the translation process is followed by an optimization process to create a mapped circuit with superior characteristics than the initial GTech circuit, but that performs the same function as the initial GTech circuit. Using a GTech circuit consisting solely of primitive parts as an example, the conventional optimization process proceeds generally as described below.

Optimizing a GTech circuit includes improving the structure of the initial GTech circuit as well as mapping the logic in the initial GTech circuit into gates available in the specified technology library. Circuit improvement algorithms may function in either the GTech or the mapped logic domains. Therefore, mapping may occur at different points in the optimization process. Conventional logic optimization tools generally perform some logic improvement both before and after the GTech circuit is mapped. The following paragraphs describe a general approach to improving the logic in either a GTech or a mapped circuit. For readability, the following description of the optimization process describes optimizing GTech circuits. However, the same optimization techniques are applied to mapped circuits as well.

First, the optimization process identifies one or more parts in the GTech circuit. This may include identifying all of the parts of the GTech circuit. Those interconnected parts collectively form an identified GTech sub-circuit. The identified GTech sub-circuit has inputs and outputs. An identified GTech sub-circuit output is a net that connects an output pin of a part in the identified GTech sub-circuit to an input pin of a part not in the identified GTech sub-circuit or to a primary output. An identified GTech sub-circuit input is a net that connects a primary input or an output pin of a part not in the identified GTech sub-circuit to an input pin of a part in the identified GTech sub-circuit. The identified GTech sub-circuit therefore computes one or more outputs from one or more inputs.

Second, the optimization process devises a new GTech sub-circuit that performs the same function as the identified GTech sub-circuit. The new GTech sub-circuit has the same inputs and the same outputs as the identified GTech sub-circuit. Generally, the new GTech sub-circuit should be better than the identified GTech sub-circuit in some measurable manner. For example, if the designer is seeking to construct a digital circuit with the smallest area possible, then the new GTech sub-circuit provided by the optimization process should use fewer gates than the identified GTech sub-circuit. If the designer seeks speed, the new GTech sub-circuit should have a faster timing estimate than the identified GTech sub-circuit. In some optimization processes, such as simulated annealing, the identified GTech sub-circuit is sometimes replaced with a new GTech sub-circuit that has worse characteristics than the identified GTech sub-circuit.

Depending on the particular optimization process used, the measurable criterion used may be a surrogate for the actually desired measurement. For example, a designer may want to minimize area of an entire digital circuit being placed on a chip. The optimization process may estimate the actual new GTech sub-circuit area by counting the number of gates, or adding up an area estimate for each GTech part where the area estimate comes from the GTech part library. Obtaining a more accurate measurement generally requires further analysis of the mapped circuit.

Third, the optimization process replaces the identified GTech sub-circuit with the improved GTech sub-circuit. Replacement means deleting the parts associated with the identified GTech sub-circuit. The new GTech sub-circuit's inputs are connected to the same nets that were connected to the identified GTech sub-circuit's inputs. The new GTech sub-circuit's outputs are connected to the same nets as the identified GTech sub-circuit's outputs. This results in an intermediate GTech circuit.

The optimization process then repeats these three steps on the intermediate GTech circuit until an appropriate termination condition arises. For example, the process could terminate when no further improvement was made, or the total number of iterations reached a specified number. If necessary, the GTech circuit is mapped, and the optimization process may be repeated on the mapped circuit.

1.4 Optimization Invariant Digital Circuit Structures

Several kinds of circuit structures have a 1 to 1 correspondence between the GTech and mapped domains. Such parts are referred to as optimization invariant. Relating an analysis result for a particular net or part in a mapped circuit back to source text is straight-forward when that part of the circuit is not changed in the optimization process. The details of how this correspondence is established will be described in a subsequent section. Conversely, it is difficult, if not impossible, to relate a mapped circuit structure back to the HDL if that mapped circuit structure has no corresponding part in the unoptimized GTech circuit. This section describes several different digital circuit features that typical optimization processes leave unchanged during optimization.

First, optimizers generally do not eliminate registers and defined memory elements such as latches and flip-flops. The translation process typically creates a part in the initial GTech circuit for each bit of a register defined by the HDL text. These initial parts have a one-to-one correspondence with final library parts which are chosen by the optimization process. Therefore, partial analysis results associated with the register (such as its area) or nets connected to the register relate directly to those in the initial GTech circuit. Furthermore, the final register can be related back to the HDL which caused it to be created.

Second, optimizers generally do not eliminate primary inputs and primary outputs. Therefore, post optimization primary inputs and outputs can be related back to pre-optimization parts.

Third, optimizers generally do not optimize across levels of hierarchy. If a GTech circuit contains a part that is implemented as another GTech circuit, then the optimization process will optimize the GTech circuit within that lower level part separately from the rest of the GTech circuit at the higher level. Hierarchy is also respected in mapped circuits.

Fourth, the optimizer can be instructed not to "touch" a given cell or net. Thus, such cells and nets will exist in both the pre- and post-optimization circuit. However, such directives limit the ability of the optimizer to improve the GTech or mapped circuit. In one embodiment, this instruction is called "dont.sub.-- touch." In one embodiment, dont.sub.-- touch is a command which refers to a particular cell or net in the GTech or mapped circuit. In another embodiment, dont.sub.-- touch is an attribute in the HDL language which refers to a part which is instantiated in the source HDL. Cells or nets which are labeled dont.sub.-- touch are not changed in any way by the optimizer.

Relating Digital Circuit Structures to HDL Source

The goal of synthesis is to create a mapped circuit netlist description from a high level description of the digital circuit. The mapped circuit must meet a set of design constraints. Typically, an HDL is used to specify the high level description. It is desirable to analyze the final result in terms of the original source description.

Analysis of the digital circuit can be done in many ways. Generally, analysis involves taking a digital circuit and computing a numerical characteristic of that digital circuit or of parts in the GTech or mapped circuit or of nets connecting parts in the GTech or mapped circuit. The intermediate results of that analysis are often associated with parts or nets or both in the GTech or mapped circuit. For example, one way to estimate the area of a mapped circuit is to add up the areas of each of the parts in the mapped circuit. The area of each primitive part can be found in the library of primitive parts provided by the semiconductor vendor. The area of a hierarchical part is obtained by applying this area summing technique recursively.

As another example, the propagation delay through a mapped circuit is determined by first computing the longest delay from the primary inputs to each pin in the mapped circuit. This associates delay information with each pin in the mapped circuit. For a hierarchical part, the information could be consolidated to be the delay from each input of the part to each output of the same part.

Results such as area or propagation delay refer to the optimized mapped circuit. If a problem is discovered in analyzing such results, it is useful to ascertain which portion of the HDL description caused the problematic mapped circuit structure to be synthesized.

It is also useful to analyze the translated GTech circuit. Because generally it is not reliable to depend upon the optimizer for major improvements in circuit performance, it is useful to improve the translated GTech circuit before optimization. As there exists a direct correspondence between the structure of the source HDL and that of the translated GTech circuit, improving the translated GTech circuit is accomplished by modifying the source HDL. Furthermore, it is also possible to characterize the area and delay of the translated GTech circuit. Thus, it is useful to relate the structure and properties of the translated GTech circuit back to the source HDL. Therefore, the relationship between the translated GTech circuit and the source HDL can be used to create an HDL source level digital circuit analysis tool. GTech analysis will be discussed in further detail in a later section.

The following sections describe how the relationships between the source HDL, the parse tree, the translated GTech circuit, and the optimized mapped circuit are created and used. These relationships form the basis for HDL source level digital circuit analysis and debugging. Once these relationships are established, digital circuit analysis tools can be linked to the source HDL to assist the designer in analyzing and modifying the HDL.

1.5 Overview of HDL Source to Mapped Circuit Link

This section provides an overview of how the relationship between the source HDL text and the mapped circuit is established. Each of the links will be described in more detail in subsequent sections.

FIG. 4 shows the relationship between HDL text and the mapped circuit. The HDL text 3610 is the source representation of the digital circuit. The parse tree 3620 is ccreated by parsing 3654 the HDL text in accordance with conventional computer parsing methods. In addition, each node in the parse tree is assigned a unique numerical id called the parse tree node number which is used to identify the node. Both the HDL text and the parse tree belong to the source domain. The generic logic, or GTech domain 3630, representation of the digital circuit is created by translating 3664 the parse tree. The mapped domain 3640 representation of the digital circuit is created by optimizing 3674 the generic logic. Note that each of the software representations of the digital circuit design in HDL Text 3610, parse tree 3620, GTech domain 3630, and mapped domain 3640 are functionally equivalent. The transformations of parsing HDL text 3654, translating 3664, and optimizing 3674 change the way in which the digital circuit is represented, but not its underlying functionality.

Once each of these representations of the digital circuit has been created in the various domains, it is possible to relate components in one representation to components in either the previous or next representation of the digital circuit. It is possible to derive the relationship between components in any two domains by tracing the components through any intermediate representations.

Link 3652 indicates that the HDL text 3610 can be related to the parse tree 3620 by traversing the parse tree to find the node which represents the relevant text.

Link 3656 indicates that the parse tree 3620 can be related to the HDL text 3610. One technique for relating particular pieces of text with corresponding parts of a parse tree is described in a co-pending application by Gregory entitled "Method and Apparatus for Context Sensitive Displays", filed on Jun. 3, 1994 as U.S. application Ser. No. 08/253,453, which is hereby incorporated by reference. Another embodiment for this stores the file offset of the start and end of each parse node. Another embodiment stores the line and column number from the source HDL in the parse node.

Link 3662 indicates that the parse tree 3620 can be related to the GTech domain 3630 by storing a list of cell ids created from each parse node with the representation of that parse node.

Link 3666 indicates that the GTech domain 3630 can be related to the parse tree 3620 by storing the parse tree node number with each cell that is created in translation.

Link 3672 indicates that the GTech domain 3630 can be related to the mapped domain 3640 by relating optimization invariant digital circuit structures. Optimization invariant structures in the GTech domain 3630 have a one to one correspondence with structures in the mapped domain 3640. Therefore, link 3672 can be implemented by searching for a structure of the same type with the same name in the optimized mapped circuit. An alternate embodiment of tracking optimization invariant structures comprises assigning a unique reference number to each translated GTech circuit structure and then retaining this unique reference number in the corresponding optimized mapped circuit structure.

Link 3676 indicates that the mapped domain 3640 can be related to the GTech domain 3630 by relating optimization invariant digital circuit structures. This link is imlemented using the same method as link 3672.

1.6 Method for Relating Mapped Circuit to Source HDL

As described above, structures in the synthesized digital circuit can be related back to the HDL text. Thus, mapped or GTech circuit analysis results can be shown near the related source HDL. Relating an analysis result back to the source HDL is a several step process. First, the partial analysis result is associated with a part or a net in the final mapped circuit. That part or net is related to a part or net in the initial GTech circuit. In circumstances described below, this relationship is easily established because that net or part did not change during the optimization process. In other circumstances, this relationship is very difficult or impossible to establish. Note however that it is always possible to establish the relationship between the GTech circuit and the source HDL.

FIG. 5 shows how a mapped circuit structure can be related to the source HDL. In step 3510, a mapped circuit structure is selected for tracing. In step 3515, the method checks to see if the mapped structure was derived from, and can therefore be traced to, an optimization invariant GTech circuit structure. If that mapped circuit structure is not traceable, then the process terminates. In one embodiment, a message might be issued to the user that the mapped circuit structure is not traceable. If the structure is traceable, step 3520 relates the mapped circuit structure to the pre-optimization GTech circuit structure which created it. As described previously, this is possible because the mapped circuit structure directly corresponds to a pre-optimization GTech structure with link 3676 of FIG. 4. Step 3530 relates the pre-optimization structure to the parse node from which it was translated. This is possible because the pre-optimization structure contains a record of the parse node from which it was created. This relationship is shown link 3666 of FIG. 4. Finally, step 3540 relates the parse node back to the source HDL token(s) using link 3656 shown in FIG. 4. The details of the method for establishing the parse tree to text link are described in a later section.

FIG. 5 shows the method for tracing from mapped circuit structure back to HDL source text. It is also possible to begin the method shown in FIG. 5 at step 3520 when one is tracing from GTech circuit structures rather than from mapped circuit structures.

Furthermore, as shown in FIG. 4, it is possible to trace from HDL text to a GTech or to a mapped circuit structure. The method is the reverse of that shown in FIG. 5, and uses link 3652, link 3662, and link 3672 from FIG. 4. A method for tracing from HDL text to either a GTech or a mapped circuit structure is shown in FIG. 6.

In step 5620, the selected HDL text is related to the appropriate parse node. This is possible by using link 3652 of FIG. 4. Step 5630 relates the parse node to the appropriate GTech part(s). As described previously, this is possible because the parse node is annotated during translation with a record of the GTech part(s) it creates. This annotation is indicated by link 3662 of FIG. 4. In step 5640, the program checks to see whether it is possible to trace from each GTech part to a mapped part. This tracing, as shown by link 3672 of FIG. 4, is possible if the GTech part remains invariant during optimization. If the GTech part remains optimization invariant, then the procedure returns a mapped part for each GTech part. Otherwise it terminates at step 5650.

2.0 Probe Directives

As described previously, it is possible to relate mapped circuit structures back to the HDL if there is a 1 to 1 correspondence to GTech for them. Although several kinds of GTech circuit structures are preserved by typical optimizers, these parts might not exist in sufficient numbers to derive a sufficient correspondence between the source HDL and the optimized mapped circuit in some cases. Furthermore, the distribution of where these parts are located in the mapped circuit might not correspond to the parts of the mapped circuit requiring analysis. Therefore, it might be necessary for the designer to specify additional parts of the HDL which can be traced to the final mapped circuit. An aspect of the present invention uses "probe" directives in the source HDL to specify the creation of additional optimization invariant parts in the GTech circuit.

Probe directives instruct the translator software to construct an initial GTech circuit with certain points in the GTech circuit marked so that those points are preserved during the subsequent optimization process. In addition, the usual optimization invariant structures will also be preserved during optimization. The following sections describe how an HDL description of a digital circuit with probes is synthesized and the resulting mapped circuit is analyzed. An example showing how probes guide the construction of the mapped circuit and allow analysis information to be related to the HDL source text is then provided.

2.1 Probe Directive Usage

It is important that the designer can easily control when and where probe directives cause optimization invariant structures to be inserted into the mapped circuit. The following sections describe different types of probe directives as well as a method for enabling and disabling probe directives without modifying the HDL source text.

2.1.1 Types of Probe Directives

In a presently preferred embodiment, a probe directive is a single text string that is a comment in the HDL language. The probe directive begins with characters that indicate the beginning of a comment. In VHDL, this is a "--". In Verilog, this is "//". The next word is a keyword that indicates to the translator that this comment is a translator directive, and not a mere comment. In one embodiment, this keyword is "Synopsys". After the keyword, comes a probe declaration to indicate what type of probe it is. In one embodiment, a statement probe is indicated with the phrase "probe.sub.-- statement". After the probe declaration comes an optional search string that is used to identify the type of nets in the GTech circuit to insert optimization invariant GTech circuit structures. An example of an optional search string is "all.sub.-- mux.sub.-- controls" indicating that the control lines to any multiplexors should be probed. The search string information will be described later. After the search string comes optional probe strength information. Probe strength is an aspect of the present invention which provides a convenient method of activating or deactivating groups of probes. In one embodiment, probe strength is indicated using a numerical value from 1 to 5. This feature will be described further in a later section.

Thus, a sample probe directive in the VHDL language is:

Synopsys probe.sub.-- statement all.sub.-- mux.sub.-- controls 4

A basic type of probe directive is a statement probe. Statement probes use the syntax described above, but do not include any search string. In one embodiment, a statement probe selects the first parse node following it.

Another type of probe directive is the block probe. A block probe is defined by two text strings. The first text string is the block starting string. Like the statement probe, it begins with a comment starting symbol and a keyword. In one embodiment, the keyword is followed by the phrase "begin.sub.-- block.sub.-- probe". This phrase is followed by an optional search string. This phrase is followed by an optional string with probe strength information. The second text string is the block ending string. In one embodiment, the keyword is followed by the phrase "end.sub.-- block.sub.-- probe". A sample pair of block probe directives in the VHDL language is:

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            Synopsys begin.sub.-- block.sub.-- probe
            <VHDL statements>
            Synopsys end.sub.-- b1ock.sub.-- probe
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            1000if (C and B) then
            1001 -- Synopsys probe.sub.-- statement
            1002Z <= not (A or B);
            1003else
            1004Z <= not B;
            1005end if;
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