Electronic computer with equipment for debugging operative programs3987420Abstract Apparatus is provided for debugging a utility program without material increase in the memory capacity required. Such apparatus performs the debugging functions by using only the input-output devices as the keyboard, the console, the display, the M.C. reader which normally equip the computer. Actuation of a correction key activates the debugging program and interrupts operation of the utility program. The debugging program may be stored in a reserved portion of a ROM, or transferred into a predetermined storage area from magnetic card storage. This area is predetermined not to hold information significant to resumption of the utility program under test. A search is then made of the utility program, e.g., by addresses of the individual instructions, for the erroneous instruction. Upon discovery thereof, a correct instruction is keyed in directly from the keyboard to replace the erroneous instruction. The debugging program records this correct instruction at the approriate addressed location in memory. Claims What I claim is: Description BACKGROUND OF THE INVENTION
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LIST OF ABBREVIATIONS Page 6
GENERAL DESCRIPTION Page 7
CENTRAL UNIT (FIG. 2) Page 9
1. Timer 20 Page 10
2. Execution of microinstructions (TABLE A)
Page 11
3. State register (SO) 27 Page 17
4. Instruction register (RO) 26 Page 19
5. Operative registers 30 (scratch pad)
Page 19
6. Arithmetic unit 35 Page 20
7. Switching elements 40 Page 22
8. Shift network 41 Page 23
9. Input network to the operative registers
Page 24
10. Network providing connection to the RAM 1
Page 24
11. Channel logic 45 Page 27
DETAILED DESCRIPTION OF THE RAM 1 AND THE ROM 2
Page 28
INSTRUCTION INTERPRETING MICROPROGRAM
Page 41
DBG PROGRAMS Page 56
1. Instructions used Page 56
2. Visual display of the instruction in the registers 362 and
Page 61
3. Bar recognition Page 76
4. Program for introduction from magnetic card (Bar S2)
Page 85
5. Read-RAM program (Bar S0) Page 92
6. STOP reservation program (Bar S1)
Page 94
7. Writing-in-RAM program (Bar S6) Page 95
8. Step-by-step execution program (RUN key)
page 96
CONCLUDING REMARKS AND EXAMPLES Page 98
CLAIMS Page 104
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LIST OF ABBREVIATIONS Di = register 40, indicates the eight switching elements Dev = a switching element of the register 40, specified by three bits Crt = character, corresponds to eight memory bits Mem = memory RAM 1 Ind = address Mls = sequence logic matrix 28 Rb = base register P1 = pointer 1 P2 = pointer 2 Cp = program conditions Ci = interrupt code Mi = instruction modification Dbg = debugging Bsd = dbg service byte M.c. = magnetic card Exor = exclusive-OR Ci = interrupt code Ip = program addresser (207) Ai = enable interrupt Psr = program in progress (Register 300 of RAM 1) Ipsr = interrupt program (Register 302 of RAM 1) Opsr = interrupted program (Register 301 of RAM 1) Zrm = reserver zone of RAM 1 Rc = current reference Cc = condition code Cu = central unit 3 Pu = peripheral unit 4 Ir = reentry address (Reg. 327, FIG. 9) Ii = addresses of interrupt program (Register 335 of FIG. 9) Is = stop address (Register 350, FIG. 9) Bsd = debugging service byte (Register 351 of FIG. 9) Rl = working register (Register 352 of FIG. 9) Ab = enable bars Itr = reference Table address register. DESCRIPTION OF PREFERRED EMBODIMENTS A brief description of the processor using the program debugging system according to the invention will now be given with reference to FIGS. 1a and 1b. Of course, reference is made herein to a particular embodiment of the processor without on that account limiting the possibilities of application of the system according to the invention to other types of processor. More particularly, the processor of FIGS. 1a and 1b is of the microprogrammed type. That is, to each instruction of the program there corresponds a microprogram recorded in a permanent memory. The execution of a program instruction is achieved by means of the sequential execution of the microinstructions of the respective microprogram. The processor of FIGS. 1a and 1b comprises a memory RAM 1 adapted to contain the instructions and the data of the program in process of execution, and a memory ROM 2 adapted to contain both the microprograms which implement the instructions of the programs and the programs used by the debugging system according to the invention, as will be better explained hereinafter. The RAM 1 and the ROM 2 may be of any known type on the market and will therefore not be described in detail; it is only made clear that each cell of both of the memories is adapted to contain 16 bits. The RAM 1 and the ROM 2 are connected to a central processing unit 3, which will be described in detail hereinafter and which is connected in turn to a group of peripheral units 4. The peripheral units 4 may be of various kinds according to the particular application for which the processor is intended. In this particular case, there will be described and demonstrated hereinafter only the peripheral units used by the debugging system according to the invention. More particularly, the peripheral units shown are: an alphanumeric keyboard 5, a visual display 6, a control console 7, a printer 8, and a read/write unit 9' adapted to record and read data on a magnetic card 9. The read/write unit 9' is of the type described in U.S. Pat. No. 3,495,222 issued on Feb. 10, 1970 and assigned to the same assignee of this application. There will now be described briefly with reference to FIGS. 1a and 1b the operations which the programmer must carry out during the stage of debugging a program recorded previously in the RAM 1. Of course, these operations will be described in detail later on. Let it now be assumed that the program recorded in the RAM 1 is not being executed correctly by the processor because of errors of various kinds which the programmer may have made during the compilation thereof. At this point, the programmer intends to carry out a check of the instructions of the program which the processor is not able to execute. He presumes that one of them is wrong. To correct this instruction directly in the RAM 1, the programmer acts on the console 7, positioning a key change-over switch 100 (FIG. 1b) from the normal setting to the debugging setting, writes the respective address of the instruction on the numeric part 101 of the keyboard 5 and then actuates a service bar S1 belonging to a group of bars 102. Corresponding to this operation, an interrupt is generated in the program to be corrected (being caused by the switch 100 actuated on the console 7) and one of the debugging programs recorded in the ROM 2 is performed, the program being associated with the particular bar actuated on the keyboard 5. This program, for example, may have the effect of producing a visual display of the instruction corresponding to the address written on the keyboard and halting of processing with enabling of the keyboard 5. In this way, the programmer can enter the instruction he considers correct on the keyboard 5. Thereafter, the operator actuates another service bar S6 with which is associated another debugging program which records the correct instruction in the memory RAM 1 at the address previously entered. The programmer may wish to carry out a debugging program different from those recorded in the ROM 2. If so, he inserts in the reader 9' the magnetic card 9 on which the desired debugging program is recorded, and actuates the service bar S2. This bar calls a special program of the ROM 2 which causes: the reading of the program recorded on the card 9, the transfer thereof to a fixed zone (ZRM) of the RAM 1, and the immediate execution of this program. It is emphasized -- and this is explained in detail hereinafter -- that the fixed zone of the RAM 1 to which the card program is transferred does not contain information significant for the resumption of the program under test. Thus there is no loss of information in performing the debugging program recorded on the magnetic card 9. From what has been said, one of the advantages of the system according to the invention becomes obvious, i.e., the possibility of testing programs simply by actuating a change-over switch and using the same devices (keyboard, display, magnetic card) which are used during normal operation. CENTRAL UNIT (FIG. 2) A detailed description of the central unit 3 will now be given with reference to FIG. 2. The central unit 3 is an assembly of logic circuits which handle and execute the various microprograms contained in the ROM 2. It is composed of the following main blocks: A timer 20 which times the development of the processing of the data inside the control unit 3. This timer is composed of an oscillator 21 and an assembly of signal generating circuits 22. A sequence logic matrix network 25, which staticizes and interprets the codes of the microinstructions read from the ROM 2 and generates the commands necessary for the execution thereof. This network is composed of a microinstruction register (R0) 26, a state register (S0) 27 and a sequence logic matrix (MLS) 28. An operative network which carries out the processing of the data by methods imposed by the sequence logic matrix 28. The operative network comprises: the operative registers 30 (scratch pad) which are divided into two groups RA-31 and RB-32 each of which is composed of sixteen eight-bit registers hereinafter referred to as AO-A15 and BO-B15, respectively; an arithmetic unit 35 which is formed by three blocks UA-36, UB-37, UC-38 with eight-bit parallelism; the switching elements DI-40; a shift network ND-41, an input network to the operative registers which comprises the nodes NA and NB and two registers BA-42, BB-43, and a network providing connection with the RAM 1 and composed of nodes NO and NC; a channel logic 45 which controls the interface providing connection to the peripheral units and monitors the operative simultaneity of the central unit 3. A detailed description of the above-enumerated blocks will now be given. 1. Timer 20 The oscillator 21 generates periodic pulses which define a fixed period of time called the machine cycle which lasts for the time necessary for the execution of an elementary operation (for example: reading of an operative register 30, its incrementing and rewriting in the operative register 30). During the machine cycle, signals are generated by the circuit 22, the duration of which and the positioning of which in the machine cycle are fixed. The function of these signals is predetermined. The fact that they act or do not act on the circuits of the central unit 3 is determined by the conditions generated by the sequence matrix 28 in the manner to be described hereinafter. The working of the central unit 3 is completely synchronous with this timing, as is also the conversation with the peripheral units. Ten signals are generated by the circuit 22 and their use is illustrated hereinafter. The signals are: T0 which acts on the state register 27, T1 which times the reading of the ROM 2, T2 which times the RAM 1, T3a which acts on the register R0-26, T3n which also acts on the register R0-26, T4a which acts on the registers BA42, BB43 and on the switching elements 40, T5 which acts on the operative registers 31 and 32, T6 and T7 which act on the channel logic 45. FIG. 3 is a timing diagram in which the signals mentioned appear. Of course, the oscillator 21 and the circuits 22 are not described in detail, since they are known in the field of circuit design. 2. EXECUTION OF MICROINSTRUCTIONS Before proceeding to the description of the other blocks of the central unit 3, a brief mention will now be made of the microinstructions used by the central unit 3 in the debugging system according to the invention and of the execution thereof. The execution of a microinstruction can be divided into two phases: An interpretive phase, common to all the microinstructions, which reads the address microinstruction from the ROM 2, prearranges the carrying out thereof and increments the addresser of the ROM 2. This phase is obviously independent of the code of the microinstruction read. An execute phase, during which the processing of the data takes place in accordance with the procedures indicated by the microinstruction read in the preceding interpretive phase. The interpretive phase is always performed in a single machine cycle and the configuration of the signals (hereinafter called "commands") is stable within the limits of the cycle. The configuration of these commands defines the operations to be performed and is called the "Interpretive State." The presence of the interpretive state is indentified by a flip-flop S000 of the register 27 (FIG. 4). The execute phase is performed in one or more machine cycles to which there correspond as many states, each defined by a corresponding flip-flop of the register 27. Throughout the execute phase, the code of the microinstruction in question remains stable in the register 26, while the situation of the flip-flops of the register 27 which define the current state develops. Each state defines the next as a function of the code of the microinstruction read. At the end of the execution of each microinstruction a return is made to the interpretive state S000 to read the following microinstruction from the ROM 2. During the two phases, the interpretive phase and the execute phase, the combinatory network 28 (MLS), which has the registers 26 and 27 as inputs, generates commands C which enable given flows of information through the operative network or the other blocks of the central unit 3. The information then flows between the blocks of the central unit 3 through a series of AND gates of various types which are controlled by the commands C generated by the combinatory network 28. In FIG. 2 these gates are symbolically represented divided into three zones. The central zone contains the control signal of the gate generated by the network 28 (MLS). When this command is present, the signals at the input of the gate are transferred to the following block. The pairs of numbers varying from 00 to 15 which are in the top zone and the bottom zone of the gates indicate the number of bits which they allow to pass and more precisely the positions in which these bits are at the input and the output. For example, a gate having the pairs of numbers 07, 00 both input and output is a gate which transfers an eight-bit character in direct parallel. On the other hand, a gate having the pair of numbers 03, 00 in the top zone, that is as input, and the pair of numbers 07, 04 in the bottom zone, that is as output, is a gate which transfers four bits shifting them to the left by four places. If 07, 04 are input and 03, 00 are output, the shifting is by four places to the right. Finally, if the input zone is empty, this signifies that the bits are forced into the gate from outside. There is described hereinafter, with reference to Table A, the set of microinstructions used by the debugging system according to the invention, omitting the other microinstructions which the central unit is capable of carrying into effect. The microinstructions given in Table A have a fixed format of sixteen bits which corresponds to one word of the ROM 2. The format of the microinstructions is as follows: ##SPC1## The fields, each of four bits, have the following significance: F is the operative code of the microinstruction; X indicates the first operand; Y indicates the second operand; Z is an extender of one of the foregoing fields. When the fields X and Y specify as operands the registers A, B or L of the operative registers 30, they will be indicated in the microinstructions by the symbols Ax, Bx, Lx, Ay, By, Ly, respectively. The microinstructions are divided into groups distinguished by the different function code, that is by the different binary configuration of the field F of the microinstruction. The microinstructions having the same function code are executed with the same sequence of states.
TABLE A
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Name
F X Y Z FUNCTION
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LOGICAL ARITHMETIC
ADDB
0110
A B 0101
B.rarw. (A+B)
ANDA
0110
A B 1000
If (A.rarw.A AND B) = 0
ANDB
0110
A B 0100
If (B.rarw.A AND B) = 0
PUTS
AND 0110
A B 0000
if (A AND B) = 0
ORA 0110
A B 1110
If (A.rarw.A OR B) = 0
ORE 0110
A B 0111
If (A EX OR B) = 0
SOT 0110
A B 0010
If (A - B)>0 D00 = 1
TRANSFER
TAB 0101
A B 1100
B.rarw.A
TBA 0101
A B 0011
A.rarw.B
EXCHANGE
SLL 0100
L L 1111
Ax.revreaction.By; Bx.revreaction.Ay
DECREMENT
DCA 1010
A 0100
1010
If (A.rarw.A - 1) = 0 puts D01=1
LOAD SWITCHING ELEMENT
TAD1
1011
A 1110
0111
DI.rarw.A
TBDI
1011
B 1111
0111
DI B
REDI
1011
0 DEV
0110
0110
DEV `0`
SEDI
1011
1 DEV
0110
0110
DEV `1`
SHSB
1011
B 0001
0101
SHIFT B one bit to left
ROTB
1011
B 0001
0110
Exchange semibyte
AZAP
1011
A 0010
0111
Zeroize left semibyte
JUMP
SAI 000 I Unconditional jump IND. I
SAD0
0010 0 DEV I Jump to I if DEV = 0
SADI
0011 0 DEV I " """DEV = 1
.hoarfrost.
WRITE/READ RAM 1
MAD 1100
A I A MEM. IND. I
AMD 1101
A I MEM. IND. I A
AMI 1110
L A 1011
MEM. IND. L A
BMI 1110
L B 0011
MEM. IND. L B
AMIP
1110
L A 1001
MEM. IND. L A; L L + 1
BMIP
1110
L B 0001
MEM.IND.L B; L L + 1
MAIP
1110
L A 1101
A MEM.IND.L; L L + 1
MBIP
1110
L B 0101
B MEM.IND.L; L L + 1
FORCE REGISTERS 30
CRTA
1000
A CRT A.rarw.CRT
CRTB
1001
B CRT B.rarw.CRT
READ ROM 2
ROMA
0111
A 0000
0000
A.rarw.MEM.IND.L2; if bo7 = 0,
put 8 least significant bits,
if bo7 = 1, put 8 most
significant bits.
bo7 = most significant bit of
the register B2. L2 L2 + 1
TCCA
1010
A 1000
1000
A.rarw. CRT FROM CONSOLE
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3. REGISTER S0 (27) The register 27 is formed by eight flip-flops (FIG. 4) which differentiate the various machine cycles. They are: S000-S001-S002-S003-S004-S042-S043-S010. their positioning is controlled by the logic matrix 28 is directly analyzing the field F of the microinstruction present in the register 26 (RO). The changing of the configuration of the register 27 takes place with the leading edge of the signal T0 and this is the first operation which the matrix 28 effects within the limits of a timing cycle. The signals S042, S043, S010 are obtained from the OR function of the following states: S042 = s004 + s002 s043 = s004 + s003 s010 = s000 + s001 fig. 5 shows the timing diagram relating to the state S010 starting from the states S000 and S001. Of course, the states S042 and S043 will be generated in similar manner. It is to be noted, therefore, that the matrix 28 generates only five states, that is to say S000 to S004, while the other three states are derived therefrom. The sequence of the states corresponding to the microinstructions of TABLE A is now given in TABLE B.
TABLE B
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SEQUENCE OF TYPE OF MICRO-
F. EXECUTION INSTRUCTION
______________________________________
000 S001
0010 S001
} JUMP
0011 S001
0100 S002 S003
0101 S002 TRANSFER
0110 S002 ARITHMETICAL AND
LOGICAL
0111 S002 S001 S004 READING
1000 S004 } ROM 2 INTO RA/RB
1001 S004
VARIOUS
1010 S004 .+-. CHECK;/CONSOLE
1010 S004 SHIFT AND OPER. ON
SWITCHING ELEMENTS 40
1100 S004 S002
1101 S004 S002
1110 S004 S002
} MEMORY RAM 1
1110 S004 S003
1111 S004 S003
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It is to be noted, finally, that all the sequences are preceded by the interpretive state S000. The commands generated by the matrix 28 in the individual states will be described in the continuation of the description. 4. MICROINSTRUCTION REGISTER 26 (RO) The register 26 comprises sixteen flip-flops which staticize the code of the microinstruction or the information read from the ROM at the address specified by predetermined operative registers 30. The sixteen flip-flops are divided into two groups of eight; those which are least significant are commanded by the signal T3N, the others by the signal T3A. The generation of the signals T3N and T3A takes place only in the two states in which reading of the ROM is performed. These are the interpretive state S000 for all the microinstructions and the state S001 for the microinstruction ROMA. With the leading edge of the signals T3N and T3A, the sixteen bits read from the ROM 2 are staticized in the register RO-26 and constitute the code of the microinstruction which must be executed. The information remains stable in the register during all the following execute states, as shown in FIG. 6. As has been said, in the state S001 of the microinstruction ROMA a second reading of the ROM takes place. The eight least significant flip-flops of the register 26 are positioned with the signal T3N by the eight most or least significant bits read. This depends on the value of the bit 07 of the register B2 (see Table A). 5. THE OPERATIVE REGISTERS 30 (SCRATCH PAD) The operative registers 30 are arranged in two series, referred to as A and B, of sixteen registers, each register having a capacity of eight bits (FIG. 8). The bits of the same weight of the registers of each of the two series, for example the series A, are arranged in a 4 .times. 4 matrix (FIG. 7). Thus there are eight 4 .times. 4 matrices in which the first bits of each thereof form the register A0, the second bits the register A1, and so on. To select a register, for example the register A15, it is sufficient to send on the eight select wires shown in FIG. 7 eight commands C024 - C031 having the following configuration: 10000001. Of course, the commands C024 - C031 are generated by the sequence matrix 28, which takes account of the fields X and Y of the microinstructions for generating both the select commands (C024 - C031) and the state associated (forced into S0) with one of the two series of registers. More particularly, the state S043 selects one of the registers of the series B, while the state S042 selects a register of the series A. The state S010, on the other hand, is associated with a register having a length of sixteen bits and formed by the like A and B registers, this register being called a "Long Register" and indicated by the letter L. The writing of an item of information in one of the registers 30 with the information already recorded in the registers 42 and 43 is timed, as has been said, by the signal T5 (FIG. 2). At this instant, the commands CT04 - CT07 generated by the logic matrix 28 select the data to be transferred to the registers 31 and 32 at the level of four bits at a time. Thus it is possible to modify one of the registers A or B in one part thereof, leaving the other part unchanged. 6. ARITHMETIC UNIT 35 The arithmetic unit 35 executes arithmetical and logical operations on the contents of the operative registers 30. It comprises two adders UA-36 and UB-37 with eight-bit parallelism and a logic network U-38. The two adders 36 and 37 (UA and UB) are interconnected in such manner as to obtain a single adder with sixteen-bit parallelism. However, only in particular operations, that is when a long register (L) is operated on, are all the sixteen outputs of the adder significant. The network UC-38, which may enter UA as first operand, performs the logical OR, AND and exclusive-OR functions. By means of a decoder 50 (FIG. 2b), the arithmetic unit 35 moreover supplies information on the result of the arithmetical and logical operations which are stored in the switching device D02 as a consequence of the commands CD11 and CD12 generated by the logic matrix MLS-28. This switching device is then sensed by the instructions SAD0 and SADI to effect conditional jumps. There is given hereinafter in Table C a list of the mircoinstructions which concern the arithmetic unit 35, in which appears the symbolic name of the commands CU00-CU09 generated by the MLS-26 which effect the transfer of the data, and the states of validity of the commands.
TABLE C
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Micro- State of
instrn.
CU00
CU01
CU02
CU04
CU05
CU06
CU07
CU08
CU09
Validity
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ADDB 1 0 0 0 1 X X X X S002
DCA 0 0 0 1 0 X X X X S004
AND 1 1 1 1 0 X 0 1 0 S002
ANDA 1 1 1 1 0 X 0 1 0 S002
ANDB 1 1 1 1 0 X 0 1 0 S002
ORA 1 1 1 1 0 X 1 0 0 S002
ORE 1 1 1 1 0 X 0 0 1 S002
ROMA 1 1 0 0 0 0 X X X S001
TAB 1 1 0 1 0 0 X X X S002
TBA 1 1 0 1 0 0 X X X S002
MAIP 1 1 0 0 0 0 X X X S004
AMIP 1 1 0 0 0 0 X X X S004
MBIP 1 1 0 0 0 0 X X X S004
BMIP 1 1 0 0 0 0 X X X S004
MBI 1 1 0 1 0 0 X X X S004
AMI 1 1 0 1 0 0 X X X S004
BMI 1 1 0 1 0 0 X X X S004
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NOTE: X = Immaterial
7. THE SWITCHING ELEMENTS (40) The switching elements 40 comprise eight flip-flops (D00-D07) which staticize events which occur during the execution of some microinstructions. Their contents are tested during the execution of the microprograms to condition the making of address jumps in the addressers of the ROM 2. The logical microinstructions (AND, OR, etc.) affect them automatically for depositing the result of the logical operation carried out. Each individual switching element can moreover be positioned at ZERO or at ONE by the microinstructions REDI and SEDI, respectively, (Table A). In the format of the microinstruction (Table A) the three least significant bits of the field X constitute the binary address (00-07) of the switching element concerned. Some microinstructions (TADI-TBDI-SADI) force the eight bits of the register A or B selected into the eight switching elements (See Table A). Some arithmetical and logical microinstructions (AND, OR, ORE, ADD), on the other hand, position the switching elements with their qualitative result; more particularly, the switching element D0I staticizes the occurrence of a zero result output by the arithmetic unit 35. The switching elements 40 change their state at two different times. The switching elements D00-D03 change over with the signal T4N, while the switching elements D04-D07 change over with the signal T4A. Given hereunder is Table D, which contains the microinstructions concerning the switching elements 40 and the commands enabling the switching elements themselves which are generated by the MLS 28.
TABLE D
______________________________________
MICROINSTRUC-
TION CDRR CU05 CD11 CD13 CD14
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REDI 1 0 0 0 0
DCA 0 0 1 0 0
AND/A/B 0 1 1 0 1
OR/A/B 0 0 1 1 0
ORE 0 0 1 0 1
ADD/A/B 0 1 1 0 0
TADI 0 0 0 1 1
SADI 0 0 0 1 0
TBDI 0 0 0 0 1
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8. SHIFT NETWORK 41 Through this network formed by circuits of the AND-OR type it is possible to open a flow of information among all the possible flows towards the input network (NA, NB) to the operative registers (31, 32). The shift network 41 is formed by a group of eight gates divided into two sub-groups connected to the operative registers RA-31 and RB-32, respectively. Each of these sub-groups is capable of performing a shift or a rotation on the data coming from the operative registers 30, as is shown symbolically in FIG. 2b. Each gate of the two sub-groups is addressed by a combination of three bits of the microinstructions SHSB and ROTB which act on this network. These combinations are indicated symbolically in FIG. 2b by the synbols CZ00-CZ07 while the other two gates of the network 41 are commanded in direct manner and serve to force the conditions of the switching elements or zero. An input to the shift network 41 is moreover constituted by a gate 70 which is connected to the channel logic 45 by means of the data introducing channel D. This gate 70 permits the introduction of the date coming from the peripheral units through the medium of the logic 45 into the operative registers 30 through the nodes NA or NB. 9. INPUT NETWORK TO THE OPERATIVE REGISTERS This is a network to which the operative registers 31 and 32 lead; the network enables the byte which is to be sent to and written in the operative registers 31 and 32 to be selected. This network is formed by the nodes NA and NB and the registers BA-42 and BB-43. The nodes NA and NB are two networks, each with parallelism of eight bits, which select the eight possible flows of information to the operative registers 31 and 32 by means of the commands CA00-CA07 generated by the MLS 28. The information selected may come in fact the following units: the arithmetic unit 35 (two flows), the shift network 41 (ND), the ROM 2, the RAM 1, the console 7 (two flows), the channel logic 45. The registers BA-42 and BB-43 staticize the information present on the nodes NA and NB and selected by one of the commands CA00-CA07 in the presence of the signal T4. The contents of BA-42 and BB-43 may or may not be written in the operative registers 31 and 32 according to whether the commands CT04-CT07 hereinbefore described are activated or not. 10. NETWORK PROVIDING CONNECTION TO THE RAM 1 The central unit 3 is connected to the input of the memory RAM 1 through the medium of a node N0 with parallelism of 16 bits (N000-15). This node is activated during the execution of the microinstructions for writing into the memory and for reading from the memory. In both cases the node N0 supplies the address which it is desired to access; in the writing microinstructions it sends the character (eight bits) to be stored. The output of the RAM 1 comprises a node NC with parallelism of eight bits (NC00-07) and is used only in the case of reading. All the microinstructions which provide for reading from or writing in the RAM 1 are executed in three machine cycles: in the first cycle S000 the interpretive state takes place, in the second cycle S004 the address in the RAM 1 at which the microinstruction operates is sent through the node N0. The registers which can be connected to the node N0 as addressers are the register RO-26, if it is desired to access an address lower than 255 (that is say, the reserved zone of the RAM1), or a pair of registers (AB or BA), if it is desired to access any address whatsoever of the RAM 1. In FIG. 2, the addressing commands of the memory RAM 1 are represented by the commands CM03-CM07. The command CM03 enables the register R0, while the commands CM04 and CM05 enable the registers RA-31 and RB-32. From the state S004 the machine passes to the third cycle which is the state S002 or the state S003, according to the type of microinstruction being worked out. The machine passes to the state S002 for all those microinstructions in which it is a B register which supplies the item of data to be written or receives the information read. It passes to the state S003, on the other hand, when it is an A register which is concerned in the reading or writing. Within the limits of the states S002 and S003 it is necessary to distinguish two different functions: (1) in the writing microinstructions there is sent, accompanied by the signal T2, the item of data to be written in memory (at the address already specified in the state S004) through the medium of the first eight bits (N000-07) of the node N0. The output NC of the memory is not significant and is not used. The information which can be written may come from the registers RA-31, RB-32 or from the peripheral units through the medium of the channel logic 45 when the commands CM04, CM06 and CM07, respectively, are generated by the MLS 28. (2) In the reading microinstructions, on the other hand, the node N0 is not significant and is not used by the RAM1. Instead, the output NC is of value and can be sent to a B register if the state S002 and the command CA05 are present, or to an A register if the state S003 and the command CA05 are present. In Table E are listed the microinstructions using the RAM 1, with the respective commands and states generated by the MLS 28.
TABLE E
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State S004 State S002 State S003
MICRO- COMMANDS COMMANDS COMMANDS
INSTRUCTION
CM03
CM04
CM05
CM04
CM06
CM07
CM04
CM06
CM07
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AMD 1 0 0 1 0 0
MAD 1 0 0 X X X
MAIP 0 1 1 X X X
MBIP 0 1 1 X X X
AMI 0 1 1 1 0 0
AMIP 0 1 1 1 0 0
BMI 0 1 1 0 1 0
BMIP 0 1 1 0 1 0
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All the blocks of the central unit 3 and also all the commands generated by the MLS 28 for controlling the flow of information between the blocks themselves are specifically described in the foregoing description. The MLS 28 has not been described in detail, however; this is nothing but a matrix having as rows the outputs of the registers 26 and 27 and as columns the conductors on which the commands C are generated. The MLS 28 is moreover conditioned by the timer 20 to generate the commands in the desired sequence. For further details on the MLS 28, references should be made to the bood "Microprogramming, Principles and Practices" by Samir S. Husson, published in 1970 by Prentice-Hall Inc., Englewood Cliff, N.J., United States of America. In Chapter 2, the principle on which a sequence of commands adapted to execute microinstructions is generated is explained with reference to concrete examples. 11. CHANNEL LOGIC 45 The channel logic 45 is a complex of circuits adapted to handle and coordinate the exchange of data and commands between the central unit 3 and the peripheral units 4 connected thereto, excluding the console 7, which has direct access to the central unit 3 through the node NA-NB. A detailed description of the channel logic 45 is given in U.S. patent application Ser. No. 454,973 for "Electronic Computer" filed on Mar. 26, 1974 and assigned to the same assignee of this application which is a continuation-in-part of the U.S. patent application Ser. No. 92,777 filed on Nov. 25, 1970 and now abandoned. At the present time it is desired only to make it clear that the channel logic 45 handles the microinstructions among the various priority levels present in the processor on the basis of a predetermined order or priority. The reason for inserting the channel logic 45 is therefore to permit interruption of the microprogram in progress in order to execute an interrupting microprogram having greater priority. In this particular case there are four priority levels of microprograms, that is: The main microprogram or microprogram of priority 4, which normally has the function of interpreting and executing the instructions of the program by processing the data and starting the input and output operations; A microprogram of priority, 3, normally intended for executing operations which do not come within the predetermined time sequence of the program, microprogrammed handling of input-output operations; Microprograms of priorities 2 and 1, normally intended for effecting the transfer of data from a peripheral unit to the memory or vice versa. With each microprogram there is associated an addressing register as shown in FIG. 8. More particularly, level 4 is addressed by the register L00, level 3 by the register L01, level 2 by the register A13 and level 1 by the register A12. The transfer of the data from the peripheral units to the central unit 3 may take place in two modes. The first is handled by the gate 99 which permits direct access to the RAM 1 through the node N0 (FIG. 2c). This gate is controlled by the microinstructions for direct access to the RAM 1 which have already been described hereinbefore. The second mode is handled by the gate 70 of the node ND-41 and permits access to the operative registers 31 and 32 through the nodes NA and NB. The data and commands from the peripheral units which are recorded in the operative registers 30 and 31 are processed directly by the set of microinstructions which work on the registers. DETAILED DESCRIPTION OF THE RAM 1 AND THE ROM 2 A description of the part of RAM 1 used by the DBG programs will not be given with references to FIG. 9. The first zone, called the reserved zone (ZRM), is at the disposal of the interpreter microprogram and the microprograms handling the peripheral units and of the DBG programs. The second zone, on the other hand, is intended for recording the programs to be performed, the data on which these programs operate and the results of the processing operations. Before describing the RAM 1 in detail, it is necessary to mention briefly the operations performed by a special microprogram residing in the ROM 2 and called the interpreter. This microprogram, which will be described in detail hereinafter, performs the following operations: Interprets the current instruction (Phase ALFA); Recognizes the program interrupts; Starts the interrupt program be recognizing whether it is recorded in the RAM 1 or in the ROM 2; Inhibits all interrupts, including that of the program in the starting stage; Enables reading from the RAM 1 or from the ROM 2 according to whether the interrupting program resides in the RAM 1 of in the ROM 2; Carries out the reading of the instruction from the RAM 1 or from the ROM 2; Recognizes the formats of the instructions; Extracts the operands; Carries out the instructions by starting the microprograms associated therewith (Phase BETA). More particularly, the ZRM comprises a register PSR-300 (FIG. 9) which contains the parameters of the program in course of processing and is constituted by the following registers (see Table F): A base register RB-310 which contains the initial address of the memory zone available for normal programs. The register RB-310 is used by the interpreter for computing the addresses of the operands expressed in the instructions. It is modified by suitable instructions during the execution of a program.
TABLE F
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NUMBER
ADDRESS
REG.NO.
NAME ABBREVN
OF BYTES
FROM
TO
__________________________________________________________________________
310 BASE REGISTER RB 2 00B0
00B1
311 POINTER 1 P1 2 00B2
00B3
312 POINTER 2 P2 2 00B4
00B5
313 PROGRAM CONDITIONS
CP 1 00B6
--
314 INTERRUPT RESERVATION
P1 1 00B7
--
315 INSTRUCTION MODIFN.
MI 1 00B8
--
320 BASE REGISTER RB 2 00D0
00D1
321 POINTER 1 P1 2 00D2
00D3
322 POINTER 2 P2 2 00D4
00D5
323 PROGRAM CONDITIONS
CP 1 00D6
--
324 INTERRUPT CODE C1 1 00D7
--
325 INSTRUCTION MODIFN.
MI 1 00D8
--
327 OPSR ADDRESS IR 2 00DA
00DB
333 PROGRAM CONDITIONS
CP 1 00BC
--
334 ENABLE INTERRUPT
AI 1 00BD
--
335 INTERRUPT ADDRESS
II 2 00BE
00BF
350 STOP ADDRESS IS 2 00EC
00ED
351 DBG SERVICE BYTE
BSD 1 00C7
--
352 WORKING REGISTER
RL 8 00A8
00AF
353 REFERENCE TABLE
ITR 3 00D4
00D6
ADDRESS
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Pointer registers P1-311 and P2-312; these are registers used by particular instructions for computing the absolute addresses of the operands. These addresses are obtained by adding P1-311 or P2-312 to RB-310. Their contents can be modified by special instructions. Program conditions byte represented in FIG. 9a has the following significance: The bits 00, 01 are called the condition code (CC) and are compiled by the arithmetical and logical instructions for storing the significant results. These conditions are then sensed by other instructions for executing conditional jumps. The bit 03 is used by the interpreter to establish whether the instruction to be executed is to be read from the RAM 1 (bit 03 =1) or from the ROM 2 (bit 03 =0). This bit is normally at "one" and is put to "zero" only by the interpreter microprogram when this recognizes an interrupt generated by the actuation of the key 100 which calls a DBG program residing in the ROM 2 to indicate that the instructions of this program must be read in the ROM 2. The bit 05 is normally at one and is used to enable interrupts by the programmer because of DBG requests and is put to zero by the interpreter when the interrupt is activated. The bits 02, 04, 06, 07 are not used by the DBG programs and serve to enable other causes of interruption. Interrupt Reservation Byte (PI-314 of FIG. 9). This is used by the interpreter to actuate a request for an interrupt contained therein. An interrupt is actuated if the AND between PI and CP is different from zero, as will be explained hereinafter (interpreter section). This is compiled by the microprograms associated with causes of interruption originating both from the central unit 3 and from the peripheral units 4. More particularly, the bit 05 indicates a DBG interrupt. The manner in which the bit 05 of the interrupt reservation byte is forced to 1 will be described in detail hereinafter in the section concerning the debugging service byte (Table F). Instruction modification byte (MI-315 of FIG. 9). This is used by the interpreter to modify the second byte of the instruction to be executed and can be compiled by the programmer as a function of results of preceding instructions. The bytes 316, 317 and 318 are used for other purposes which do not concern the invention and they are therefore not described. The ZRM moreover comprises another register OPSR-301 which serves to contain the parameters of the interrupted program. The OPSR-301 is compiled by the interpreter by taking the corresponding registers and bytes from the register PSR-300. When the interrupt program terminates, the last instruction is always for resumption of the interrupted program, that is to say it is an instruction which transfers OPSR-301 to PSR-300. More particularly, the register OPSR-301 comprises: The registers RB-320, P1,321, P2-322, CP-323, MI-325, 326, which are compiled with the contents of the corresponding registers 310-316 of PSR-300. The register 324 contains the interrupt code CI (FIG. 9b), that is the code of the cause of interruption in course of processing in the program being executed. It is compiled by the interpreter before the interrupting program is activated. The causes of interruption specified by the CI are divided into five uniform classes each handled by a different microprogram. To each class there corresponds one bit of the CI; more particularly, classes 1 and 2 each correspond to a single cause of interruption and are identified by the bits 01 and 02, respectively. Classes 3, 4, 5 are identified by the bits 05, 06, 07, respectively, and each comprises a plurality of causes of interruption (sixteen causes at the most) identified by the bits 00-03. The reason for recording the CI of the cause of interruption in OPSR-301 is the fact that the resumption or non-resumption of the interrupted program really depends on the type of interrupt. For example, if the cause of interruption is such that the interrupted program cannot be resumed, then the interrupt program ends by calling the operator. Only after intervention by the operator will it be possible for the interrupted program to be resumed. The register IR-327 contains the re-entry address of PSR-300 to which corresponds the instruction which is to be executed at the instant of re-entry. It is compiled by the interpreter by transferring the contents of the operative register L07 (program addresser) at the time of the interrupt. The ZRM moreover comprises a register IPSR-302 which serves to contain the parameters of the interrupt program. The register comprises a byte CP-333 which indicates the program conditions associated therewith. The byte CP has the significance described in FIG. 9a and is transferred to the register CP-313 by the interpreter at the instant of the enabling of the interrupting program. The register IPSR-302 moreover comprises the interrupt program address II-333 (FIG. 9), which is loaded into the register L07 of the registers 30 of FIG. 2b by the interpreter if the interrupt program is recorded in the RAM 1. The register 302 moreover comprises the interrupt enable byte AI-334 represented in FIGS. 9c, in which the bits 01-02-05-06 and 07, if at 1 level, indicate that the programs corresponding to the respective interrupt classes are recorded in the RAM 1, and, if at zero level, that the programs are recorded in the ROM 2. More precisely, the interpreter carries out the logical AND function between the interrupt code CI and the interrupt enable byte AI. If the logical AND is zero, this signifies that the program associated with the interrupt is recorded in the ROM 2; if it is one, the program is recorded in the RAM 1. In the first case, the interpreter forces the contents of the register II-335 into the operative register L07; in the second case it forces therein the address in the ROM 2 of the beginning of the zone B reserved for the DBG programs. The ZRM moreover comprises a register IS-350 shown in FIG. 9 which contains the STOP address at which the operator desires to halt the processing of the program, as mentioned in the initial part hereof and as will be better explained hereinafter. This register is compiled by a DBG program using the data entered on the keyboard by the programmer. The ZRM moreover comprises a DBG service byte (BSD-351). The BSD-351 is represented in detail in FIG. 9d. The bits used are the bit 01, which indicates (as will be better explained in the section on the interpreter) whether the instruction present at the instant of the interrupt is to be executed or not. If this bit is equal to zero, the instruction is executed, otherwise the interrupt program is performed. The bit 02 indicates whether a stop has been reserved; it is compiled by the DBG program associated with the addressed stop. The bit 03 indicates whether the key change-over switch 100 is in the normal position (bit 03 =0) or in the debugging position (bit 03 =1). It is compiled by the microprogram given in Table G using the position of the key 100.
TABLE G
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SYMB.ADDRESS
MICROINSTRN.
CODE
1st OPERAND
2nd OPERAND
__________________________________________________________________________
IDISO C A C 7 MAD A10 CC7
9 2 F 7 CRTB
B02 CF7
6 A 2 8 ANDA
A10 B02
A 8 8 8 TCCA
A08
B 8 E 7 TADI
A08
9 2 0 0 CRTB
B02 C00
2 2 3 6 SADO
D02 IDISA0
9 2 0 8 CRTB
B02 C08
IDISA0 6 A 2 E ORA A10 B02
D A C 7 AMD A10 CC7
C 2 B 7 MAD A02 CB7
9 2 D 0 CRTB
B02 CD0
6 2 2 8 ANDA
A02 B02
B A E 7 TADI
A10
9 2 3 0 CRTB
B02 C20
3 2 4 0 SADI
D02 IDISA1
3 3 4 0 SADI
D03 IDISA1
IDISA1 6 2 2 E ORA A02 B02
D 2 B 7 AMD A02 CB7
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Referring to FIG. 2c, through the medium of the key 100 the console 7 actuates a switch 60 which is connected directly to the node NA through the wire 61 forming part of the channel 62. If the key 100 is in the NORMAL (N) position, the switch 60 is open and therefore the wire 61 is at zero level. As has been said, this corresponds to the normal working of the machine. On the other hand, when the key 100 is in the DEBUGGING (DBG) position, the switch 60 is closed, so that the wire 61 is at one level. The timer 20 generates every 60 milliseconds a signal TM which causes an interrupt in the microprogram of level 4 (that is the interpreter in the microprogram) and executes the microinstruction addressed by the register L01 (addresser of the microprogram of level 3). This microinstruction forms part of a predefined sequence of microinstructions which corresponds to the various external conditions to be checked during the performance of a program. More particularly, at the instant TM there is present in the register L01 the address corresponding to the microprogram IDISO given in Table G. By means of a microinstruction MAD there is loaded into A10 the cell of RAM 1 at the address C7, that is the DBG service byte, BSD-351. Then, by means of a microinstruction CRTB, the number F7 = 11110111 is loaded into the register B02. By means of a microinstruction ANDA, the logical AND between BSD and F7 is transferred to A10, that is in A10 there is the BSD with the bit b03 = 0. Then, by means of a microinstruction TCCA, there is transferred to A08 the byte present on the channel 62 (see FIG. 2). More particularly, if the key 100 is in the DBG position, the wire 61 (which corresponds to the bit 02 of the channel 62) is at 1 level. By means of a microinstruction TADI the byte on the channel 62 is transferred to the switching elements 40. Then, by means of a microinstruction CRTB, the number 00 is forced into the register B02. Thereafter, the logical level of the switching element D02 (on which the condition of the wire 61 corresponding to the DBG position of the key 100 is present) is sensed. If this bit is at 1 level, the number 08 = 00001000 is forced by means of a microinstruction CRTB into the register B02 and the logical OR is then carried out (microinstruction ORA) between the contents of the register A10 and the number 8. It is to be noted that the BSD with the bit b03 = 0 was recorded in the register A10 and therefore the result of the microinstruction ORA is to force the bit b 03 to one. If, on the other hand, the bit on the wire 61 is at zero level, the microinstruction CRTB which forces 00001000 into B02 is not executed, so that the logical OR is carried out between the contents of the register A10 and the number 00000000; this corresponds to leaving the bit 03 of BSD at zero. After these operations, by means of a microinstruction AMD there is rewritten in the location .phi..phi.C7 (BSD-351) the BSD modified in this way. In short, if the key 100 is in the NORMAL position, the bit b03 = 0; if, on the other hand, it is in the DBG position, b03 = 1. The same microprogram moreover provides for compiling the bit 05 of the interrupt reservation byte (PI). By means of a microinstruction MAD, the byte recorded at the address .phi..phi.B7 of the RAM 1, that is the byte PI - 314, is transferred to the register A02. Then, the bit 05 of PI is zeroized by means of the two microinstructions CTRB and ANDA. By means of the two microinstructions TADI, the contents of the register A10, that is the BSD previously modified in accordance with the condition of the console key 100, are transferred to the switching elements 40. The number 20 = 00100000 is then written by means of a microinstruction CRTB in the register B02. Then, by means of two microinstructions SADI, there are sensed the bits b02 and b03 of the BSD which have been previously loaded into the switching elements, and which correspond respectively to having reserved a STOP address and to having actuated the key 100. If at least one of the bits sensed is at 1 level, a microinstruction ORA puts to one the bit b05 of the byte PI, which is rewritten in the RAM 1 by means of a microinstruction AMD. If, on the other hand, both of the bits b02 and b03 of the BSD are at zero level, there is forced into the register B02, by means of a microinstruction CRTB, the number 10 = 00010000, which corresponds to another cause of interruption which does not concern the DBG and is therefore not described. The ZRM moreover comprises an 8-byte register called the working register (RL-352 in FIG. 9), which is used as a work area for accumulating the partial results during the carrying out of some instructions and for supplying, at the end of an instruction, a result which cannot be contained in the registers of the operands (for example, the remainder of a division). The ZRM moreover comprises an eight-byte register 359 called the conditions register RC. Each byte is divided into two semibytes which identify special conditions of the program. In fact, the register 359 is used to collect all the significant conditions of the program which arise during the execution of internal or external instructions and which, in view of their high number, cannot be expressed in the condition code or which it is appropriate to store independently of this. Of all the semibytes there will be explained only the contents of the ninth, since this is used by the DBG programs, as will be explained hereinafter. The ninth semibyte occupies the first four bits of the cell .phi..phi.CB and is used by the introduction-from-keyboard instructions for compiling the code of the bar 102 which has concluded an introduction of data from the keyboard. The ZRM moreover comprises a one-byte register AB-370 which identifies the bars 102 which are enabled by the program. More particularly, the register is compiled, as will be seen hereinafter, by the DBG programs for enabling the bars S0, S1, S2, S6, since these only have significance during the carrying out of the DBG. The ZRM moreover comprises a group of eight registers 360 - 367 (FIG. 9) which are normally used by the programs in the following manner. The registers 360 to 363 are used together with the working register 352 to contain the intermediate results during the operations of multiplication and division and the results which cannot be contained in the registers of the operands. More precisely, the multiplication and division instructions are executed by microprograms which operate on the said registers. It is to be noted that the contents of these registers are not significant at the end of the instruction which has used them inasmuch as all the conditions and the results which are significant are transferred to memory areas outside the ZRM which are addressed by the operands of the specific instructions. The registers 364 and 365 are used by the instructions for EDITING of a register, that is to say they contain all the characters relating to punctuation, the algebraic characters (+, -), the spaces, etc. required during the print-out of an area of memory. They are called by the operands of these instructions and their contents are no longer significant at the end of such an instruction. The registers 366 and 367 are used by the DBG program as an extension of the register OPSR-301. That is to say, they serve to load significant conditions of the interrrupted program which cannot be contained in the register OPSR-301. It is to be noted that while the registers 360 to 365 do not contain significant data at the end of the instruction which uses them, the registers 366 and 367 contain a significant data for the purposes of the resumption of the interrupted program and can therefore be used by the DBG programs only in special cases which will be specified hereinafter. It is to be noted, moreover, that the registers 360 to 367 do not necessarily have to be allocated to the positions in the RAM 1 which are indicated in FIG. 9, but may be in any zone of the memory. One of the characteristics of the invention resides, in fact, in identification in the RAM 1, by means of the respective addresses, of a certain number of registers (eight in our case) which do not contain significant data at the end of the execution of the instructions and in utilization of these registers as backing registers for the debugging programs. All this is naturally done automatically and without the intervention of the programmer, who only has to actuate the key 100 and the bars 102. It is made clear, moreover, that it is not necessarily the registers 360 to 367 that have to be used as backing registers for the DBG programs, but registers reserved exclusively for the DBG programs may be used and may be allocated both in the ZRM and in the free memory or may even be registers outside the memory. The free memory zone, that is the zone immediately following the ZRM, moreover contains a zone called the reference table zone, the location of which is defined by a register of the ZRM. This register ITR-353 is composed of three bytes, the first two of which define the initial address of the table, while the third defines the length of the table itself (at the most 256 bytes). The table of references if addressed by a number of instructions for calculating the addresses of the operands. The free memory zone immediately following the reference table contains sixteen registers, each of eight bytes, which are called privileged registers. These registers, in fact, can be addressed directly by the instructions by citing their reference number in hexadecimal notation. The remaining part of the RAM 1 can moreover be addressed in free fashion. The ROM 2 is divided into two zones A and B (FIG. 9). The zone A comprises all the microprograms required for the working of the processor, the zone B comprises the DBG programs. INSTRUCTION INTERPRETING MICROPROGRAM (INTERPRETER) As has been stated, the programs recorded in the RAM 1 are executed instruction by instruction. Each instruction in turn is executed in two phases: an interpretive phase (Phase ALFA) and an execute phase (Phase BETA). The interpretive phase is common to all the instructions and is executed by a suitable microprogram, called the interpreter, recorded in the zone A of the ROM 2. This phase terminates with the recognition of the format of the instruction which the interpreter microprogram itself has read from the RAM 1 or from the ROM 2 and with the preparation of the operands in the operative registers 30. This microprogram is therefore called at the beginning of each instruction by the microinstruction terminating execution of the instruction just carried out. More particularly, therefore, the execution of any instruction of the program which the processor performs takes place in the following manner: The last microinstruction of the microprogram which has executed the preceding instruction is an unconditional jump microinstruction SAI to the address IALFA (Table H), that is the first microinstruction of the interpeter microprogram. Table H in which the microinstructions corresponding to the interpreter microprogram are listed is given hereinafter. The first column indicates the symbolic names of the jump addresses which will be used as operands in the jump microinstructions.
TABLE H
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SYMB.ADDRESS
MICROINSTRN.
CODE
1st OPERAND
2nd OPERAND
__________________________________________________________________________
IALFA 8 8 0 0 CRTA
A08 C00
D 8 B 8 AMD A08 CB8
IALFAJ C E B 6 MAD A114 CB6
5 E F C TAB A14 B15
C E B 7 MAD A14 CB7
6 E F 0 AND A14 B15
2 1 E 1 SAD0
D01 IINTE
IALFUR C E B 6 MAD A14 CB6
B E E 7 TADI
A14
3 3 1 3 SADI
D03 IALFA1
4 7 2 F SLL L07 L02
7 8 0 0 ROMA
A08
5 8 E C TAB A08 B14
7 8 0 0 ROMA
A08
5 8 F C TAB A08 B15
4 2 7 F SLL L02 L07
0 2 1 5 SAI IALFA2
IALFA1 E 7 E 5 MBIP
M07 B14
E 7 F 5 MBIP
M07 B15
IALFA2 C 8 B 8 MAD A08 CB8
B 0 6 6 REDI
D00
6 8 F 5 ADDB
A08 B15
9 2 0 2 CRTB
B02 C02
5 2 E 3 TBA A02 B14
7 B 0 0 ROMA
A11
7 2 0 0 ROMA
A02
5 B 2 C TAB A11 B02
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The second column gives the microinstruction in hexadecimal code; the third, fourth and fifth columns give the instruction in symbolic form, that is the function performed, the first operand and the second operand, respectively. It is pointed out that if an operand is indicated by the letter C followed by two alphanumeric characters, this means that the operand is the hexadecimal number (one byte) which follows the letter C. Reference will now be made to Table H, FIG. 9 and FIGS. 10a, 10b and 10c. By means of the first two microinstructions CRTA and AMD, the character CRT 00 is forced into the address .phi..phi.B8 of the RAM 1, that is the instruction modification byte (block 200 of FIG. 10a) is put to zero; this is necessary since a new instruction has to be initiated. By means of the following two microinstructions, that is MAD and TAB, the contents of the cell .phi..phi.B6 are transferred to the operative register B15 through the register A14 the said cell containing, as has been said, the program conditions byte CP-313 (block 201). With the microinstruction MAD there are transferred to the register A14 of the group 31 the contents of the cell .phi..phi.B7, in which is recorded the interrupt reservation byte PI-314 (block 201). As has been seen, the interrupt reservation byte PI contains in coded form the causes which may produce an interrupt in the program being executed. The logical AND is then carried out between CP-313 and PI-314 by the microinstruction AND (logical decision 202). As explained hereinbefore (see Table A), the microinstruction AND sends the switching element D01 of the group of switching elements 40 to one if the result of the AND is zero. With the following microinstruction SADO, the contents of the switching element D01 are sensed and, if this is at zero logical level (that is, if an interrupt has been reserved) a jump is carried out to the address given by the symbolical name IINTE (block 250) at which is recorded the first microinstruction of a microprogram which handles the interrupts (see Table J). If, on the other hand, the switching element is at one logical level, the phase ALFA of reading from the RAM 1 is continued. Let us now examine the conditions which determine the jump to IINTE or the continuation of the interpreter microprogram. If the byte PI is 0000 0000, the AND with the byte CP will of course be 0000 0000, so that the switching element D01 is at 1 level and the jump is not therefore carried out. The condition PI 0000 0000 indicates that no interrupt has been reserved. If at least one bit of PI is at one level and the corresponding bit of CP is also at one, that is to say that particular microinterrupt is enabled, then the AND between CP and PI will have at one the bit of the same weight as that of PI. If, for example, an interrupt has been reserved by means of the console key 100 (FIG. 1b), the byte PI, as has been seen, has the configuration 0010 0000. The byte CP, in turn, has been positioned by the programmer with the configuration 1X1X XXXX, since the program in progress provides for enabling the DBG interrupt, so that the AND between CP and PI will be 0010 0000. Consequently, D01 will be forced to zero by the microinstruction AND and therefore the jump to IINTE will be obtained.
TABLE J
__________________________________________________________________________
SYMB.ADDRESS
MICROINSTRN.
CODE
1st OPERAND
2nd OPERAND
__________________________________________________________________________
IINTE 6 E F 4 ANDB
A14 B15
C A C 7 MAD A10 CC7
B F F 7 TEDI
B15
B A E 7 TADI
A10
2 1 6 1 SADO
D01 IINTE1
2 2 6 7 SADO
D02 IINTE2
3 3 6 7 SADI
D03 IINTE2
C 8 E D MAD A08 CED
5 8 8 C TAB A08 B08
C 8 E C MAD A08 CEC
6 8 7 3 ORE A08 B07
2 1 6 1 SADO
D01 IINTE1
6 7 8 3 ORE A07 B08
3 1 6 7 SADI
D01 IINTE2
IINTE1 9 A 0 2 CRTB
B10 C02
6 A A E ORA A10 B10
D A C 7 AMD A10 CC7
C A B 6 MAD A10 CB6
5 A F C TAB A10 B15
0 2 0 7 SAI IALFAR
IINTE2 9 A F D CRTB
B10 CFD
6 A A 8 ANDA
A10 B10
D A C 7 AMD A10 CC7
9 D 0 $ ARTB
B13 C04
IERR01 8 E B 0 CRTA
A14 CB0
9 8 0 0 CRTB
B08 C00
8 8 D 0 CRTA
A08 CD0
8 B 0 A CRTA
A11 C0A
INTER1 E E 9 D MAIP
A14 A09
E 8 9 9 AMIP
M08 A09
A B 4 A DCA A11
2 1 7 4 SADO
D01 INTER1
E 8 7 1 BMIP
M08 B07
E 8 7 B AMI M08 A07
8 8 D 7 CRTA
A08 C07
E 8 D 3 BMI M08 B13
D B B 8 AMD A11 CB8
C 9 B D MAD A09 CBD
5 B D 2 TBA A11 B13
INTER5 6 B 9 0 AND A11 B09
2 1 8 E SADO
D01 INTER2
8 B 0 0 CRTA
A11 C00
INTER4 D B B 6 AMD A11 CB6
INTER4 9 7 1 7 CRTB
B07 C17
8 7 0 0 CRTA
A07 C00
0 2 0 0 SAI IALFA
INTER2 C 9 B C MAD A09 CBC
D 9 B 6 AMD A09 CB6
C 7 B E MAD A07 CBE
5 7 7 C TAB A07 B07
C 7 B F MAD A07 CBF
0 2 0 0 SAI IALFA
__________________________________________________________________________
If there has not been any interrupt, the whole byte CP is transferred to the switching elements 40 by means of the microinstuctions MAD and TADI (block 203). A check is then made by means of a microinstruction SADI whether the switching element D03 is at one level or zero level (logical decision 204). As has been said, the bit 03 of the byte CP indicates whether the reading of the instruction is to be carried out from the RAM 1 or from the ROM 2. If the reading of the instruction is to be carried out from the RAM 1 (case of normal programs), the first and second bytes of the instruction at the address contained in the long register L07 are read by means of the two microinstructions MBIP (block 205). At each reading (MBIP) the register L07 is incremented by one. The two bytes are moreover transferred to the registers B14 and B15 of the operative registers 32. From what has been said, it can be seen how the register L07 acts as a program addresser for the instructions, since it always indicates the address of the following instruction after each reading. Moreover, in the event of the instruction preceding the current one having been a jump instruction, it will have already compiled in the register L07, by means of a suitable microprogram carried out in the BETA phase, the address in the RAM 1 of the instruction to which to jump. To sum up, both as regards sequential addressing and as regards addressing with a jump, the register L07 always contains the address in the RAM 1 of the following instruction. If the current instruction is to be read from the ROM 2 (case of the DBG programs), the bit 03 of the program conditions has been forced to zero, so that the jump to IALFA1 is not executed. However, the microinstruction SLL is executed and exchanges the contents of the register L07 with the contents of the register L02 (block 206). Then, by two successive pairs of instructions ROMA and TAB, the first two bytes of the instruction read are transferred to the two registers B14 and B15 (block 206). It is to be noted that the exchange of L07 and L02 is rendered necessary by the fact that the microinstruction ROMA which executes the reading from the ROM 2 is addressed exclusively by the register L02. It moreover increments the contents of this register by one after each reading. After the reading of the first and second bytes of the instruction, the contents of the register L07 are restored by executing an exchange microinstruction SLL by means of which the register L02 is exchanged with the register L07. It is to be noted, therefore, that in both cases, reading from the RAM 1 and reading from the ROM 2, the two bytes of the instruction to be executed are recorded in the two registers B14 and B15 of the registers 32 and that after such reading the register L07 already contains the address of the following instruction. After this, by means of three microinstructions MAD, REDI, ADDB (block 207 of FIG. 10a), the second byte of the instruction read is modified in accordance with the instruction modification byte (MI) previously recorded in the cell .phi..phi.B6. By means of the microinstructions CRTB and TBA (block 208), the first byte of the instruction is used to calculate an ROM address from which there are written pairs of bytes which correspond to the formats of the instructions (1st semibyte) and the addresses of the execute phases (2nd, 3rd and 4th semibytes) associated with sets of instructions; these pairs of bytes constitute the elements characterising the instruction. Then, by means of two consecutive microinstructions ROMA, the two bytes associated with the instruction are read and are transferred to the operative register L02 (FIG. 8). At this point, the instruction contained in L02 is examined by a microprogram which recognizes one of the seven possible formats given in FIG. 10d. If the instruction recognized is of format 1, it is composed of a function code F, two bits I1 and I2 which indicate whether the respective registers R1 and R2 address the RAM 1 in direct or indirect manner, and two fields R1 and R2 of four bits which indicate two constants. If I1 = I2 = 0, the addresses of the operands are computed by multiplying the constants R1 and R2 by 8 and adding the value of the base register RB-310 to the result. In this way, the RAM 1 can be addressed by registers of eight bytes. If I1 = 1 and I2 = O, R1 indicates one of the sixteen privileged registers of the RAM 1 and R2 has the same foregoing significance. In this case, the first operand is read in the zone of the RAM 1 addressed by the contents of R1, while the second operand is computed as stated hereinbefore. All the cases I1 = 0 and I2 = 1 or I1 = 1 can be deduced from the foregoing ones. If the instruction is of format 2, it is composed of a function code F, a bit I, and two fields R1 and L2. The first operand is computed as in format 1 (I1 = 0, I1 = 1), while the second operand is computed by adding the pointer P1 or P2 specified by the code F to RB. The field L2 contains the number of bytes of the second operand to be read starting from the computed address. If the instruction is of format 3, it is composed of a function code F and two fields L1 and L2. The addresses of the operands are computed like those of the second operand of format 2 and the lengths of the operands are specified by the fields L1 and L2. If the instruction is of format 4, it is composed of two fields. One indicates the function code F and the other a field E, MD, I and L which may assume four different significances on the basis of the contents of F. The code F addresses the two operands by means of the pointers P1 and P2 as for format 3 and moreover specifies the significance of the second field. If the instruction is of format 5, it comprises a function code F in which the first operand is computed as for format 3 and the second operand as for format 1. If the instruction is of format 6, the two bytes of the instruction are used directly in the following BETA phase. If the instruction is of format 7, it is composed of four bytes, whereby it first transfers the bytes 1 and 2 to other registers 30 and then puts the bytes 3 and 4 addressed by the register L07 into B14 and B15. The instruction is composed of a function code F, a field E which indicates the element of the reference table from which to compute the address of the operand, and a field LD which indicates the displacement with respect to the address computed in this way. After these operations, the interpreter ends its task and therefore initiates the execute phase BETA, in which the operands previously computed are processed. The instructions executed by the DBG programs are given in TABLE K, in which the respective formats appear. If, during the phase ALFA, an interrupt is recognized (logical decision 202 of FIG. 10a), the interpreter performs a jump to the address IINTE (Table J and FIG. 10b). The first microinstruction ANDB executes again the AND between CP and PI and preserves the result thereof in the register B15 (block 251). This result is then transferred to the DEV-40 by means of the microinstruction TBDI and the switching elements are tested to recognize the cause of interruption with the exception of those originating from intervention of the programmer on account of DBG requests. In this case, the DBG service byte is read from the RAM 1 by means of the microinstruction MAD and is thereafter transferred to the switching elements 40 by means of the microinstruction TADI (block 256). After this, the switching elements D01, D02 and D03 which contain the bits 01, 02 and 03, respectively, of the BSD are tested. The bit is normally at 0 level, as a result of which a jump is carried out to the address IINTE1 at which this bit is put to 1 and at which a jump is carried out to the address IALFAR. This is done to render the interrupt operative not during the instruction in progress or current instruction, but at the end thereof. Then there is sensed the switching element D03 (block 259), which distinguishes the STOP addressed from all the other DBG programs. The checking of the bit 03 is effected after the bit 02 for the following reasons. Let it be assumed that the programmer reserves a STOP address, that is he wishes the execution of the program to be interrupted at the instruction corresponding to the STOP address. This causes the bit 02 of the BSD to be brought to one together with the bit 05 of the byte PI, as will be better described hereinafter. This bit arrangement conditions the interpreter to jump to the address IINTE (logical decision 202) and from this it arrives at the logical decision 259. The logical decision 259 distinguishes whether, besides the STOP addressed, another DBG program has been requested by the programmer. This eventuality arises if the operator becomes aware, as soon as the STOP request is made, that it is of no use to him and instead wishes, for example, to execute a special DBG program recorded on a magnetic card 9. This eventually corresponds to having the bits 02 and 03 in the BSD at one simultaneously. This causes a jump of the interpreter to IINTE2. It is arranged beforehand that at IINTE2 the STOP addressed will be inhibited and the DBG program selected by the programmer will be executed. In the example given, this program causes the reading and execution of the program recorded on the M.C. 9. In brief, it is clear how the search for a reserved STOP address takes place only if there are not other alternative DBG requests, and it is therefore the DBG program of lower priority; in fact, the bit 02 of the STOP addressed is inhibited by any other DBG request. In the event of the sole DBG request being the STOP addressed, there are executed the microinstructions MAD, TAB, MAD (block 260), by means of which the two bytes of the reserved STOP address removed from the cells .phi..phi.EC and .phi..phi.ED (register IS-350, FIG. 9) are transferred to the register L08 (30 in FIG. 2b). Then, by means of the microinstructions ORE, SADO, ORE, the EX-OR is carried out between the contents of the registers L07 and L08 (30 in FIG. 2b). That is, a comparison is made between the program address and the reserved address. If the two addresses are the same, the microinstruction ORE puts the switching element D01 to one. In this case, the microinstruction SADI causes a jump to IINTE2 (logical decision 262) and, as will be explained hereinafter, visual display of the instruction recorded at the reserved address will take place. In the case of different addresses, the microinstructions CRTB, ORA and AMD are executed and produce the writing in the RAM 1 at the address .phi..phi.C7 of the BSD, in which, however, the bit 01 has been put to 1 level (block 266). Then there are executed the microinstructions MAD and TAB, which restore the byte CP in the register B15 (block 266). A microinstruction SAI is thereafter executed and produces an unconditional jump to the address IALFAR (block 203 of FIG. 10a). In this way, whether the bit 01 of the BSD is at 0 level (logical decision 256) or the addresses are different, the bit 01 of the BSD is put to 1 in each case and interpretation of the instruction is therefore continued with, so that during the following instruction the interpreter again executes a comparison of the addresses. In the event of the addresses being the same or there being a DBG request different from the STOP reservation, a jump is made to the address IINTE2. The microinstructions CRTB and ANDA are executed and zeorize the bit 01 of the BSD (block 270), that is the normal condition of this bit is restored after the interrupt is activated. The BSD modified in this way is then put back in the RAM 1 at the address .phi..phi.C7 by means of the microinstructions AMD and CRTB (block 271). In this way, the reservation of the STOP is cancelled. Then there is executed the microinstruction CRTB, by means of which there is written in the register B13 the byte CI 0000 0100. which indicates that the cause of interruption is a DBG program. Starting from this microinstruction the actual interruption of the program in progress takes place; in fact, the eight microinstructions following those contained at the address IERRO1 in the ROM 2 are executed and produce the transfer of the first ten bytes of the parameters of the program being executed which are recorded in the register 300-PSR to the corresponding cells of the register 301-OPSR (block 273). The contents of the register L07 are then recorded at the addresses .phi..phi.DA and .phi..phi.DB of the RAM 1 by means of the microinstructions BMIP and AMI, that is the program addresser of the interrupted program is preserved in the register OPSR-301. The interrupt code previously compiled is then written by means of the microinstructions CRTA and BMI at the address .phi..phi.D7 (register 324 of FIG. 9). In this way, there are preserved in the register OPSR-301 all the parameters which will allow resumption of the interrupted program at the end of the interrupt program. As will be seen, all the interrupt programs terminate with the restoration of the register OPSR-301 to the register PSR-300. After this phase, the interpreter microprogram compiles the register 300 with the parameters of the interrupt program which is to be executed in substitution for the interrupted program. More particularly, by means of the microinstructions AMD (block 280 of FIG. 10c) it zeroizes the byte MI of the register PSR-300 and by means of the microinstructions MAD and TBA, TAB it transfers to the register B09 the byte AI recorded in the cell .phi..phi.BD of the RAM 1 (register AI-334) and to the register A11 the byte CI previously compiled in the form 00000100 (block 281). As has been said, the byte AI is compiled by the programmer to define whether the interrupt program is resident in the RAM 1 or in the ROM 2. In this particular case, for the reasons explained in the introduction, it has been chosen to record the DBG programs in the ROM 2, but this does not bar the possibility for the user to record his own DBG programs in the RAM 1 in the event of his having the opportunity of doing so. To do this, it is sufficient to activate the bit 03 of AI-334. There is now carried out the logical AND between AI and CI, which makes D01 = 1 if the AND is different from 0000 0000. The microinstruction SADO checks the switching element D01 and, if this is at one level (program recorded in the ROM), it executes two microinstructions CRTA and AMD which zeroize the byte CP of the interrupt program in progress (block 283). In this way it is brought to notice how the interpreter microprogram, having recognized that the cause of interruption is a DBG program, provides for inhibiting any other possible interrupt (CP = 0000 0000), inasmuch as these interrupts would be incompatible with the DBG programs. After this, it executes the microinstructions CRTB and CRTA by means of which it forces the address 17.phi..phi. of the ROM 2 into the register L07 (block 284), then performs an unconditional jump to the symbolic address IALFA (FIG. 10a) to interpret the first instruction of the DBG program. The address 17.phi..phi. corresponds to the beginning of the zone B of the ROM in FIG. 9. It is to be noted that inter alia the interpreter has also forced the bit 03 of CP-313 to zero, so that when a return is made to IALFA the reading of the instructions will be effected from the ROM 2 and not from the RAM 1. It is to be noted, moreover, that the interpreter also zeroizes the bit 05 of CP-313 relating to the instructions for debugging, because otherwise, after starting the DBG program, it would enter a closed circuit. In fact, in executing the first instruction of the DBG program, the interpreter, at logical decision 202 (FIG. 10a), would find the DBG interrupt enabled, inasmuch as PI is not changed and the bit 05 of CP = 1. Consequently, it would jump to IINTE and, through the blocks 250 to 284 (FIGS. 10b and 10c), would jump again to the address IALFA and would not get out of the aforesaid cycle again. Finally, in the event of the interrupt program being recorded in the RAM 1 (logical decision 182), the interpreter executes the microinstructions MAD, AMD, MAD, TAB, MAD (block 285 of FIG. 10c) by means of which it forces the address contained in the third and fourth bytes of the register IPSR-302 into the addressing register L07 of the program in execution and moreover loads the byte CP-333 of the register IPSR-302 into the register CP-313, thus establishing in the register PSR-300 the new conditions of the interrupt program. DEBUGGING PROGRAMS 1. Instructions used. It has been seen hereinbefore that the consequence of the operation of the key 100 or the recognition of a previously reserved STOP address is that the bit 05 of PI-314 and the bit 03 of the BSD are forced to 1 level. It has moreover been seen that if the programmer has recorded the DBG programs in the ROM 2 he has taken care to put the bit 01 of the byte AI-334 of IPSR-302 to 0. Finally, it has been seen how the simultaneous presence of the values of the bits just mentioned conditions the interpreter microprogram to interrupt the processing of the program in progress, preserve its significance parameters and force the address 17.phi..phi. of the ROM 2 into the program addresser L07. This address is the address of the initial instruction of the DBG program stored in the ROM 2. Before proceeding to the description of the DBG program, it is appropriate to explain with reference to Table K the significance of the instructions used thereby. In Table K, the first column indicates for each instruction the format described hereinbefore to which the instruction itself belongs, the second column gives a brief description of the operation effected by the instruction, and the third and fourth columns indicate respectively the symbolic code and the machine code in hexadecimal notation of the instruction itself. Let us now examine briefly the steps to be performed to process any instruction in Table K. As has been seen, the interpreter reads the two bytes of the instruction from the RAM 1 or the ROM 2. On the basis of the contents of these bytes, the interpreter recognizes the format associated with the instruction, computes the address of the operands on the basis of the format, extracts the operands from the RAM 1 and transfers them to the operative registers B14 and B15. At this point, on the basis of the contents of the field F of the instruction, the microprograms which execute the instruction are extracted from the ROM 2. At the end of the execution, the interpreter is called and proceeds to the extraction of the following instruction. Referring to Table K, the symbology used in the columns of the symbolic code and in the machine code of the instructions will now be explained. R1 and R2 indicate one of the sixteen privileged registers of the RAM 1.
TABLE K
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MACHINE CODE
FORMAT
DESCRIPTION SYMB.CODE
1st BYTE
2nd BYTE
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1 R1.rarw.R1 + R2
AR C 00X.sub.1 X.sub.2
R1 R2
1 R1.rarw.R1 - R2
SR .phi. 01X.sub.1 X.sub.2
R1 R2
1 R1.rarw.R2 LR .phi. 10X.sub.1 X.sub.2
R1 R2
1 R2.rarw.WORKING
LAX 6 110 X.sub.2
B R2
REGISTER
2 PACK PK 5 00X.sub.1 1
R1 L2
3 INTR. AND DISPLAY
YOP 6 E L1 L2
VIS. FOR DBG
3 UNPACK AND TRANSC.
YTX D 6 L1 L2
HEXADEC.
4 P1.rarw.P1+(MD+1))
AP, 1 3 C MD
4 P1.rarw. (P1-(MD+1))
SP, 1 3 E MD
4 P2 .rarw. (P2+(MD+1))
AP, 2 3 D MD
4 PS.rarw. (P2-(MD+1))
SP, 2 3 F MD
4 P1.rarw.E Tl, 1 B 8 E
4 P2.rarw.E TL, 2 B 9 E
4 POINT 1.rarw.POINT 2
MVC C 5 L
4 CONST `I`.fwdarw.MEM (P1)
MVI, 1 C 6 I
4 CONST `I`.fwdarw. MEM `MVI, 2
C 7 I
4 COMP. CONST `I`-
CBI, 1 B C 1
POINT 1
4 COMP. CONST `I`-
CBI, 2 B D I
POINT 2
4 ENABLE BARS KES A 7 I
4 AWAIT END OF WAIT A 5 I
OPERATION
5 P1.rarw.R2 TRD, 1 6 110 X.sub.2
.phi. R2
5 P2.rarw.R2 TRD, 2 6 110 X.sub.2
1 R2
5 R2.rarw.P1 LPD, 1 6 110 X.sub.2
2 R2
5 R2.rarw.P2 LPD, 2 6 110 X.sub.2
3 R2
6 IP.rarw.(IP+SD) (SKIP)
F 7 3 00 SD
6 IP.rarw.(IP-SD) (SKIP)
R 7 3 01 SD
6 MOD. BIN. ACCORD.
MDB, 1 9 A 00 SD
TO P1
6 MOD. BIN. ACCORD.
MDB, 2 9 B 00 SD
TO P2
6 EXCHANGE RB.revreaction.P1
YBP, 1 A E .phi. 2
6 EXCHANGE RB.revreaction.P2
YBP, 2 A F .phi. 2
6 EXCHANGE P1.revreaction.P2
TCP 3 8 .phi. 2
6 CONVERT DECIM.
CVB 3 8 .phi. 1
.rarw.BINAR.
6 SEND P.U. COMM.
STIO, 1 A .phi.
M .phi.
ACCORD. TO P1
6 SEND P.U. COMM.
STIO, 2 A 1 M .phi.
ACCORD. TO P2
6 LIGHT "ERROR"
ON KBE E 4 .phi. .phi.
LAMP
6 AND. CONST. K
NI 2 .phi.
P K
(.)POS. P of R.phi.
6 AND. CONST. K
NIC 2 8 P K
(.)POS. P of RC
6 OR. CONST. K OI 2 9 P K
(+)Pos. P of RO
6 OPSR to PSR and
YPS 3 8 .phi. 9
execute
MACHINE CODE
FORMAT
DESCRIPTION SYMB.CODE
1st BYTE
2nd 3rd & 4th
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7 COND. DIR. BD 7 .phi.
E LD
JUMP. F. LONG
7 JUMP ON COND.
BDC F 00CC E LD
CHECK. F. LONG
7 LOAD `P1` DIR.
TLD, 1 F 8 E LD
F. LONG
7 LOAD `P2` DIR.
TLD, 2 F 9 E LD
F. LONG
7 ACTIVATE M.C.
LAC A B E LD
PROGR.
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The address of the first operand R1 or of the second operand R2 is contained in the register indicated in the instruction (direct addressing), if the corresponding bit X1 or X2, respectively, is at zero. If the bit is at one level, the corresponding register addresses a memory zone in which the address of the operand is recorded. L1 and L2 indicate the number of bytes less one of the operands addressed by the pointers P1 and P2. MD is the value less one of the constant which is to be added to, or subtracted from, the value of the pointers P1 and P2. E is the reference number which contains the address to be forced into P1 or P2. I indicates the immediate operand equivalent to the byte to be used in the instruction. SD indicates the value which must be added to, or subtracted from, the program addresser to obtain the jump address (SKIP). 2. Visual display of the instruction present in the registers 362 and 363. The DBG program recorded in the ROM 2 will now be described with reference to Table L and to FIGS. 11a to 11g. The DBG program recorded in the ROM 2 is divided into a plurality of functional blocks B100, B0, B1,B2,B6 the first of which B100 is common to all the others; the following ones B0,B1,B2,B6 on the other hand, are callable selectively by the bars S0,S1,S2,S6 indicated collectively by the references 102 in FIG. 1b. 1b. It is to be made clear that all the bars 102 (S0-S6) are used also when the key 100 is in the NORMAL position. In this case they each assume a special significance assigned to them by the program in course of execution. For example, the bars S0 and S6 may be interpreted by the program as normal end of introduction of data from the keyboard 5 and resumption of the processing using these data. The remaining bars S1-S5, in addition to concluding the normal introduction of data, add to these blocks of data supplementary information determined by the programmer. Of course, the operation of the processer when the key 100 is in the NORMAL position is not described, but, on the other hand, the operations associated with the bars 102 when the key 100 is in the Dbg position will be described. A description of the initial block B100 of the program common to all the other programs will now be given. this functional block preserves other parameters of the interrupted program which are not contained in OPSR-301 and moreover prepares the visual display of the address and of the instruction which was to be executed at the instant of the interrupt. More particularly, by means of the first two instructions TLD,2 and YPB,2 the register RB-310 is brought to .phi.16.phi. (block 400 of FIG. 11a). The contents of the working register 352 are then transferred to the register 366 by means of an instruction LAX (block 410). It is to be noted that the register 366 is addressed by the instruction LAX as the fourth register (identified by the last semibyte of the instruction) starting from the base register RB-310 of PSR-300 which contains the address .phi.16.phi.. The base register RB-310 is zeroized by means of the instructions TL and YBP, 1 (Block 402). Thereafter, by means of the instructions TLD,1, TLD,2 and MVC, there are preserved two bytes of the condition register RC-359 in cells .phi.188 and .phi.189 (block 403), which, as has been said, contain the conditions entered from outside by the operator before the DBG interrupt. These bytes will be put back into the RC-359 by the DRC program in the event of the interrupted program being resumed after the execution of the DBG program.
TABLE L
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DEBUGGING PROGRAMME
ROM 2 SYMBOLIC
ADDRESS
CODE INSTRUCTION
REMARK
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17 .phi..phi.
TLD, 2
F 9 .phi. .phi. .phi. 1 6 .phi.
LOAD .phi.16.phi. into P2
.phi.4
YBP, 2
A F .phi. 2
EXCHANGE P2 with RB
(RB = .phi.16.phi.)
.phi.6
LAX 6 C B 4 DEPOSIT RL IN R4
.phi. | ||||||