Variable address length compiler and processor improved in address management

Abstract

The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.

Claims

What is claimed is:

1. A program converting unit for generating a machine language instruction from a source program for a microprocessor having an address width N and a data width M, N being greater than M, N and M being inputs to the program converting unit as specified by a user, the value of N depending on a program size of the source program, said program converting unit comprising:

parameter holding means for holding a data width M and a pointer width N, said data width M representing the number of bits of data used in the source program, said pointer width N representing the number of bits of an address, said N and M being input by a user during an execution of the program converting unit, the value of N depending on the program size; and

generating means for generating an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating an instruction to manage said pointer width N when a variable operated by said instruction represents the address,

wherein the program converting unit generates a unique set of machine language instructions from the source program for each N specified by the user.

2. The program converting unit of claim 1, wherein said M is 16 and said N is in a range of integers from 17 to 31 inclusive, said N being determined depending on the program size as follows:

N=17, when the program size.ltoreq.128 Kbytes

N=18, when the program size.ltoreq.256 Kbytes

N=19, when the program size.ltoreq.512 Kbytes

N=20, when the program size.ltoreq.1 Mbyte

N=21, when the program size.ltoreq.2 Mbytes

N=22, when the program size.ltoreq.4 Mbytes

N=23, when the program size.ltoreq.8 Mbytes

N=24, when the program size.ltoreq.16 Mbytes

N=25, when the program size.ltoreq.32 Mbytes

N=26, when the program size.ltoreq.64 Mbytes

N=27, when the program size.ltoreq.128 Mbytes

N=28, when the program size.ltoreq.256 Mbytes

N=29, when the program size.ltoreq.512 Mbytes

N=30, when the program size.ltoreq.1 Gbyte

N=31, when the program size.ltoreq.2 Gbytes.

3. The program converting unit of claim 1, wherein said generating means includes:

determining means for determining a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to a memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;

memory managing means for outputting a direction, in case of the (1) instruction, to manage said data width as an effective memory-access width when a variable to be accessed represents the data, and to manage said pointer width as an effective memory-access width when said variable represents the address;

register managing means for outputting a direction, in case of the (2) instruction, to manage said data width as an effective bit-width when a variable to be read/written from/into the register represents the data, and to manage said pointer width as the effective bit-width when said variable represents the address;

immediate managing means for outputting a direction, in case of the (3) instruction, to manage said data width as the effective bit-width when said immediate represents the data, and to manage said pointer width as the effective bit-width when said immediate represents the address; and

code generating means for generating the machine language instruction in accordance with the directions from said memory managing means, said register managing means, and said immediate managing means.

4. The program converting unit of claim 3, wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive.

5. The program converting unit of claim 4, wherein:

said N is 24; and

said code generating means generates an instruction for a 24-bit data operation when said pointer width is greater than 16 bits and less than 24 bits, and generates an instruction for a 16-bit data operation when said pointer width is 16 bits or less.

6. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:

syntax analyzing means for analyzing a syntax of the source program to convert the same into an intermediary language comprising intermediary instructions, and subsequently for judging whether or not each variable contained in said intermediary instructions represents data used in an address;

table generating means for generating a table for each variable in said intermediary instructions, said table holding a name together with a type of each variable, said type representing one of the data and the address;

parameter holding means for holding a data width and a pointer width, said pointer width designated by a user as an input during an execution of the program converting unit, said data width representing the number of bits of the data while said pointer width represents the number of bits of the address; and

generating means for generating an instruction to manage said data width when the variable in said intermediary instruction represents the data, and an instruction to manage said pointer width when said variable represents the address.

7. The program converting unit of claim 6, wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive.

8. The program converting unit of claim 6, wherein said generating means includes:

judging means for judging a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to an memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;

memory managing means for outputting a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective memory-access width depending on the type of a variable to be accessed shown in said table;

register managing means for outputting a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;

immediate managing means for outputting a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and

code generating means for generating the machine language instruction in accordance with the directions from said memory managing means, said register managing means, and said immediate managing means.

9. The program converting unit of claim 8, said M is 16 and said N is an integer in a range of 17 to 31 inclusive.

10. The program converting unit of claim 9, wherein:

said N is 24; and

said code generating means generates an instruction for a 24-bit data operation when said pointer width is greater than 16 bits and less than 24 bits, and generates an instruction for a 16-bit data operation when said pointer width is 16 bits or less.

11. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:

syntax analyzing means for analyzing a syntax of the source program to convert the same into an intermediary language comprising intermediary instructions, and subsequently for judging whether or not each variable contained in said intermediary instructions represents data used in an address;

table generating means for generating a table for each variable in said intermediary instructions, said table holding a name together with a type of each variable, said type representing one of the data and the address;

parameter holding means for holding a data width and a pointer width designated by a user, said data width representing the number of bits of the data while said pointer width representing the number of bits of the address;

judging means for judging a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to an memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;

memory managing means for outputting a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective memory-access width depending on the type of a variable to be accessed shown in said table;

register managing means for outputting a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;

immediate managing means for outputting a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and

code generating means for generating the machine language instruction in accordance with the directions from said memory managing means, said register managing means, and said immediate managing means.

12. The program converting unit of claim 11, wherein said code generating means generates an instruction for a 24-bit data operation when said pointer width is greater than 16 bits and less than 24 bits, and generates an instruction for a 16-bit data operation when said pointer width is 16 bits or less.

13. A program converting unit for generating a machine language instruction from a source program for an embedded microprocessor series that manages an N-bit address while processing M-bit data, N being greater than M, N being an input to the program converting unit depending on a program size, said program converting unit comprising:

parameter holding means for holding a data width M and a pointer width N, said data width M representing the number of bits of data used in the source program, said pointer width N representing the number of bits of an address, said N being input by a user during an execution of the program converting unit, the value of N depending on the program size;

generating means for generating an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating an instruction to manage said pointer width N when a variable operated by said instruction represents the address;

option directing means for holding a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation; and

compensate instruction generating means for generating a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation, said compensation instruction being generated when an effective bit-width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and

prohibition means for prohibiting a generation of a compensation instruction by the compensate instruction generating means when the option directing means is storing an indication denoting not to compensate, wherein the program converting unit converts the source program into one of a plurality of different machine language programs depending on the values of N and M.

14. The program converting unit of claim 13, wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive.

15. The program converting unit of claim 13, wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive.

16. The program converting unit of claim 13, wherein said compensate instruction generating means includes:

instruction judging means for judging an arithmetic operation instruction that will possibly cause an overflow for all the machine language instructions when said option instructing means holds the user's direction for executing the overflow compensation;

variable judging means, with respect to a variable in the arithmetic operation instruction judged by said instruction judging means, for judging an effective bit-width and whether said variable is signed or unsigned by referring to said table;

sign-extension instruction generating means for generating a compensation instruction in case of a signed variable, a logical value of a sign bit being filled into all bits higher than the effective bit-width in a register that is to store said signed variable by said sign-extension compensation instruction; and

zero-extension instruction generating means for generating a zero-extension compensation instruction in case of an unsigned variable, a logical value "0" being filled into all bits higher than the effective bit width in a register that is to store said unsigned variable by said zero-extension compensation instruction.

17. The program converting unit of claim 16, wherein said generating means includes:

determining means for determining a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to a memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;

memory managing means for outputting a direction, in case of the (1) instruction, to manage said data width as an effective memory-access width when a variable to be accessed represents the data, and to manage said pointer width as an effective memory-access width when said variable represents the address;

register managing means for outputting a direction, in case of the (2) instruction, to manage said data width as an effective bit-width when a variable to be read/written from/into the register represents the data, and to manage said pointer width as the effective bit-width when said variable represents the address;

immediate managing means for outputting a direction, in case of the (3) instruction, to manage said data width as the effective bit-width when said immediate represents the data, and to manage said pointer width as the effective bit-width when said immediate represents the address; and

code generating means for generating the machine language instruction in accordance with the directions from said memory managing means, said register managing means, and said immediate managing means.

18. The program converting unit of claim 17, wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive.

19. The program converting unit of claim 17, wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive.

20. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:

syntax analyzing means for analyzing a syntax of the source program to convert the same into an intermediary language comprising intermediate instructions, and subsequently for judging whether or not each variable contained in said intermediary instructions represents data used in an address;

table generating means for generating a table for each variable in said intermediary instructions, said table holding a name together with a type of each variable, said type representing one of the data and the address, and one of signed and unsigned data;

parameter holding means for holding a data width and a pointer width designated by a user during an execution of the program converting unit, said data width representing the number of bits of the data, said pointer width representing the number of bits of the address;

option directing means for holding a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation;

generating means for generating an instruction to manage said data width when the variable in said intermediary instruction represents the data, and an instruction to manage said pointer width when said variable represents the address; and

compensate instruction generating means for generating a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation, said type being judged when said option directing means holds the user's direction for executing the overflow compensation, said compensation instruction being generated when an effective bit-width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and

prohibition means for prohibiting a generation of a compensation instruction by the compensate instruction generating means when the option directing means is storing an indication denoting not to compensate.

21. The program converting unit of claim 20, wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive.

22. The program converting unit of claim 21, wherein said M is 16 and said N is an integer in a range of 17 to 31 inclusive.

23. The program converting unit of claim 21, wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive.

24. The program converting unit of claim 20, wherein said M is 32, and said N is an integer in a range of 33 to 63 inclusive.

25. The program converting unit of claim 20, wherein said compensate instruction generating means includes:

instruction judging means for judging an arithmetic operation instruction that will possibly cause an overflow for all the machine language instructions when said option instructing means holds the user's direction for executing the overflow compensation;

variable judging means, with respect to a variable in the arithmetic operation instruction judged by said instruction judging means, for judging an effective bit-width and whether said variable is signed or unsigned by referring to said table;

sign-extension instruction generating means for generating a compensation instruction in case of a signed variable, a logical value of a sign bit being filled into all bits higher than the effective bit-width in a register that is to store said signed variable by said sign-extension compensation instruction; and

zero-extension instruction generating means for generating a zero-extension compensation instruction in case of an unsigned variable, a logical value "0" being filled into all bits higher than the effective bit width in a register that is to store said unsigned variable by said zero-extension compensation instruction.

26. The program converting unit of claim 25, wherein said generating means includes:

determining means for determining a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to an memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;

memory managing means for outputting a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective memory-access width depending on the type of a variable to be accessed shown in said table;

register managing means for outputting a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;

immediate managing means for outputting a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and

code generating means for generating the machine language instruction in accordance with the directions from said memory managing means, said register managing means, and said immediate managing means.

27. A program converting unit for generating a machine language instruction based on a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, said program converting unit comprising:

syntax analyzing means for analyzing a syntax of the source program to convert the same into an intermediary language comprising intermediary instructions, and subsequently for judging whether or not each variable contained in said intermediary instructions represents data used in an address;

table generating means for generating a table for each variable in said intermediary instructions, said table holding a name together with a type of each variable, said type representing one of the data and the address, and one of signed and unsigned data;

parameter holding means for holding a data width and a pointer width designated by a user during an execution of the program converting unit, said data width representing the number of bits of the data, said pointer width representing the number of bits of the address;

option directing means for holding a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation;

generating means for generating an instruction to manage said data width when the variable in said intermediary instruction represents the data, and an instruction to manage said pointer width when said variable represents the address;

compensate instruction generating means for generating a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation, said type being judged when said option directing means holds the user's direction for executing the overflow compensation, said compensation instruction being generated when an effective bit-width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and

prohibition means for prohibiting a generation of a compensation instruction by the compensate instruction generating means when the option directing means is storing an indication denoting not to compensate, wherein said generating means includes:

determining means for determining a kind of the machine language instruction, the machine language instruction including (1) an instruction to access to a memory, (2) an instruction to use a register, and (3) an instruction to use an immediate;

memory managing means for outputting a direction, in case of the (1) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective memory-access width depending on the type of a variable to be accessed shown in said table;

register managing means for outputting a direction, in case of the (2) instruction, to manage a corresponding bit-width held in said parameter holding means as an effective bit-width depending on the type of a variable to be read/written from/in the register shown in said table;

immediate managing means for outputting a direction, in case of the (3) instruction, to manage a corresponding bit-width held in said parameter holding means for the immediate as an effective bit-width depending on the type of the immediate shown in said table; and

code generating means for generating the machine language instruction in accordance with the directions from said memory managing means, said register managing means, and said immediate managing means, and wherein

said compensate instruction generating means includes:

instruction judging means for judging an arithmetic operation instruction that will possibly cause an overflow for all the machine language instructions when said option instructing means holds the user's direction for executing the overflow compensation;

determining means, with respect to a variable in the arithmetic operation instructions determined by said instruction determining means, for determining an effective bit-width and whether said variable is signed or unsigned by referring to said table;

sign-extension instruction generating means for generating a compensation instruction in case of a signed variable, a logical value of a sign bit being filled into all bits higher than the effective bit-width in a register that is to store said signed variable by said sign-extension compensation instruction; and

zero-extension instruction generating means for generating a zero-extension compensation instruction in case of an unsigned variable, a logical value "0" being filled into all bits higher than the effective bit width in a register that is to store said unsigned variable by said zero-extension compensation instruction.

28. A processor for processing data in accordance with instructions in a program comprising:

register means including a plurality of register groups, each group being identical in bit-width while being different in types;

instruction decoding means for decoding an instruction to output register information indicating a register designated by an operand contained in a data-transfer instruction;

external-access-width control means for outputting the number of effective bits as bit-width information indicating a bit-width of transmission data in accordance with a kind of a register group to which said designated register belongs; and

external-access executing means for executing data transfer between said designated register and an external memory in accordance with said register information and said bit-width information.

29. The processor of claim 28, wherein said register means includes:

an address register group including a plurality of address registers holding addresses; and

a data register group including a plurality of data registers holding data.

30. The processor of claim 29, wherein

said external-access-width control means, as the bit-width information, outputs a bit-width determined in accordance with the effective bit-width of the data used in the program when said register information represents the data registers, and outputs a bit-width determined in accordance with a sufficiently large address space for a program size and data area size of the program when said register information represents the address registers.

31. The processor of claim 29, wherein:

the address registers and data registers in said register means are all 24-bit wide;

said instruction decoding means outputs information that represents one of the address register and the data register as the register information;

said external-access-width control means outputs the bit-width information exhibiting 24 bits when the register information representing the address register, and outputs the bit-width information exhibiting 16 bits when the register information representing the data register; and

the external-access executing means executes the data transfer three times and twice for the 24- and 16-bit-width information respectively for an 8-bit-width external memory, and for twice and once for the 24- and 16-bit-width information respectively for a 16-bit-width external memory.

32. The processor of claim 31, wherein said access executing means includes:

an address generating circuit for holding an address designated by the data-transfer instruction to output one of a byte address and a word address to the external memory;

an output data buffer for holding write data designated by the data-transfer instruction to output the same one of per byte and per word to the external memory;

an input data buffer for holding data from read out from the external memory; and

a sequence circuit for outputting a byte address to said address generating circuit for an 8-bit-width external memory while controlling the number of times for the data-transfer in accordance with the bit-width information via the input/output data buffers with respect to the read/write data, for outputting a word address to said address generating circuit for a 16-bit-width external memory while controlling the number of times for the data-transfer in accordance with the bit-width information via the input/output data buffers with respect to the read/write data.

33. The processor of claim 29, wherein:

the address registers and data registers in said register means are all 32-bit wide;

said instruction decoding means outputs register information indicating whether the instruction uses the address register or data register;

said external-access-width control means outputs the bit-width information exhibiting 24 bits when the register information representing the address register, and outputs the bit-width information exhibiting 16 bits when the register information representing the data register; and

the external-access executing means executes the data transfer three times and twice for the 24- and 16-bit-width information respectively for an 8-bit-width external memory, and for twice and once for the 24- and 16-bit-width information respectively for a 16-bit-width external memory.

34. The processor of claim 33, wherein said access executing means includes:

an address generating circuit for holding an address designated by the data-transfer instruction to output one of a byte address and a word address to the external memory;

an output data buffer for holding write data designated by the data-transfer instruction to output the data one of per byte and per word to the external memory;

an input data buffer for holding data read out from the external memory; and

a sequence circuit for controlling said address generating circuit to output the byte address for an 8-bit-width external memory while controlling the input and output data buffers to input and output the byte data to transfer the read/write data to the external memory in a matching number of times to the bit-width of the external memory, and for controlling said address generating circuit to output the word address for a 16-bit-width external memory while controlling the input and output data buffers to input and output the word data to transfer the read/write data to the external memory in a matching number of times for the bit-width of the external memory.

35. A processor for operating certain data in accordance with an instruction in a program, comprising:

a first register means for holding N-bit data;

a second register means for holding N-bit data;

sign-extending means for extending said M-bit data to N bits by copying an MSB of said M-bit data in a direction of an upper order, M being less than N;

zero-extending means for extending said M-bit data to N bits by copying a value "0" in a direction of an upper order;

operating means for operating an arithmetic operation in accordance with an instruction;

instruction control means for decoding an instruction to zero-extend M-bit immediate data when said M-bit immediate data are to be stored in said first register means by the decoded instruction and to sign-extend said M-bit immediate data when said M-bit immediate data are to be stored in said second register means by the decoded instruction, said zero-extended and sign-extended N-bit immediate data being outputted in one of two methods, one method being to send the extended N-bit immediate data from their respective extending means to their respective register means directly, the other being to send the same via the operating means to their respective register means, with said instruction including an indication for storing in the first register means and said instruction including an indication for storing in the second register means being of two different kinds of instructions, both kinds of instructions having a same operation code but having different destination operands.

36. The processor of claim 35, wherein

said first register means is a group of a plurality of address registers for storing addresses, and

said second register means is a group of a plurality of register means for storing data.

37. The processor of claim 36, wherein said N is 24 and said M is 16.

38. A processor for operating certain data in accordance with an instruction in a program, comprising:

a first register means for holding N-bit data;

a second register means for holding N-bit data;

sign-extending means for extending said M-bit data to N bits by copying an MSB of said M-bit data in a direction of an upper order, M being less than N;

zero-extending means for extending said M-bit data to N bits by copying a value "0" in a direction of an upper order;

operating means for operating an arithmetic operation in accordance with an instruction;

instruction decoding means for decoding an instruction in the program to detect a first type instruction and a second type instruction, said first type instruction including an instruction to store M-bit immediate data into said first register means, said second type instruction including an instruction to store said M-bit immediate data into said second register means; and

control means for outputting said M-bit immediate data to said zero-extending means when the first type instruction is detected, and for outputting said M-bit immediate data to said sign-extending means when the second type instruction is detected, said zero-extended N-bit immediate data and sign-extended N-bit immediate data being outputted in one of two methods, one method being to send the extended N-bit immediate data from their respective extending means to their respective register means directly, the other being to send the same via the operating means to their respective register means, with said first-type instruction and said second-type instruction both having a same operation code but having different destination operands.

39. The processor of claim 38, wherein

said first register means is a group of a plurality of address registers for storing addresses, and

said second register means is a group of a plurality of register means for storing data.

40. The processor of claim 39, wherein

said first type instruction includes a data-transfer instruction to store the M-bit immediate data to said first register means, an add instruction to add a value in said first register and the M-bit immediate data, and a subtract instruction to subtract the M-bit immediate data from a value in said first register, and

said second type instruction includes a data-transfer instruction to store the M-bit immediate data to said second register means, an add instruction to add a value in said second register and the M-bit immediate data, and a subtract instruction to subtract the M-bit immediate data from a value in said second register.

41. The processor of claim 40, wherein said N is 24 and said M is 16.

42. A data processing method for executing an instruction that includes an operation code to store M-bit immediate data in an N-bit first register and an N-bit second register, both M and N being integers, with M being less than N, said method comprising the steps of:

decoding the instruction for selecting one of the first register and second register in accordance with an operand of the decoded instruction;

zero-extending said M-bit immediate data to N bits when said decoded instruction designates the first register, and sign-extending said M-bit immediate data to N bits when said decoded instruction designates the second register; and

storing extended N-bit immediate data to the designated register.

43. The method of claim 42, wherein

said first register means is a group of a plurality of address registers for storing addresses, and

said second register means is a group of a plurality of register means for storing data.

44. The method of claim 43, wherein said N is 24 and said M is 16.

45. A processor being one out of an embedded processor series of processors with different address bit widths, having an address bit width which can be input by a user in accordance with program size, comprising:

memory means for storing a program including an N-bit data arithmetic operation instruction and other instructions operating both N-bit and M-bit data, N being greater than M, as well as for storing a program including conditional branch instructions, transfer instructions for external memory and instructions using immediate data;

a first register means including a plurality of registers for holding N-bit data;

a second register means including a plurality of registers for holding N-bit data;

a program counter for holding an N-bit instruction address to output the same to said memory means;

fetching means for fetching an instruction from an external memory using the instruction address from said program counter;

instruction decoding means for decoding a fetched instruction;

executing means for executing all arithmetic operation instructions at N-bit length and for executing instructions operating both N-bit and M-bit data excluding the arithmetic operation instructions;

a plurality of flag storing means, each for storing a corresponding flag group changed in response to different bit-widths data in accordance with an execution result of said executing means;

flag selecting means for selecting a certain flag group from said plurality of flag storing means in accordance with a conditional branch instruction decoded by said instruction decoding means;

branch judging means for judging whether a branching is taken or not with a reference to a flag group selected by said flag selecting means;

sign-extending means for extending M-bit data to N bits by copying an MSB of said M-bit data in a higher order;

zero-extending means for extending M-bit data to N bits by filling a value "0" in a higher order;

compensation instruction control means for compensating contents of said first register means and said second register means using said sign-extending means and said zero-extending means in accordance with a compensation instruction inserted after a machine language instruction for an arithmetic operation that will possibly cause an overflow, said machine language instruction being decoded by said instruction decoding means;

external-access-width control means for outputting bit-width information for transmission data in accordance with a type of said register means to which a register indicated by register information belongs, said register information indicating one of said first and second register means;

external-access executing means for executing a data transfer between the register and an external memory in accordance with said register information and bit-width information; and

immediate control means for outputting M-bit immediate data to said zero-extending means when a decoded instruction includes an instruction to store said M-bit immediate data in said first register means, and for outputting said M-bit immediate data to said sign-extending means when a decoded instruction includes an instruction to store said M-bit in said second register means, said zero-extended and sign-extended immediate data being sent to said first and second register means respectively in two methods, one being to send the same directly to their respective register means and the other being to send the same via said executing means,

wherein said memory means stores a program of a size which is up to 2.sup.N bytes.

46. The processor of claim 45, wherein said N is 24 and said M is 16.

47. A program converting unit for generating a machine language instruction from a source program, the machine language program being generated for a selected microprocessor in an embedded microprocessor series comprising a plurality of microprocessors, each of the plurality of microprocessors being able to process M-bit data and having a different address bit width N, said program converting unit comprising:

parameter holding means for holding a data width M and a selected pointer width N, N and M being integers greater than zero and N being greater than M,

said data width M representing a bit-width of data used in the source program to be converted,

said pointer width N representing an address bit-width to be used with the converted machine language program and being set by a user, depending on an estimated size of the object program after conversion, in order to identify the selected microprocessor in the embedded microprocessor series; and

generating means for generating an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating an instruction to manage said pointer width N when a variable operated by said instruction represents the address.

48. A program converting unit for generating a machine language instruction from a source program, the machine language program being generated for a selected microprocessor in an embedded microprocessor series comprising a plurality of microprocessors, each of the plurality of microprocessors being able to process M-bit data and having a different address bit width N, said program converting unit comprising:

parameter holding means for holding a data width M and a selected pointer width N, N and M being integers greater than zero and N being greater than M,

said data width M representing a bit-width of data used in the source program to be converted,

said pointer width N representing an address bit-width to be used with the converted machine language program and being set by a user, depending on an estimated size of the object program after conversion, in order to identify the selected microprocessor in the embedded microprocessor series;

generating means for generating an instruction to manage said data width M when a variable operated by said instruction represents the data, and for generating an instruction to manage said pointer width N when a variable operated by said instruction represents the address;

option directing means for holding a user's direction for an overflow compensation, an overflow being possibly caused by an arithmetic operation;

compensate instruction generating means for generating a compensation instruction to compensate an overflow in accordance with a type of a variable used in the arithmetic operation, said compensation instruction being generated when an effective bit width of a variable designated by an operand is shorter than a register of N-bit wide and the arithmetic operation instruction will possibly cause an overflow exceeding said effective bit-width; and

prohibition means for prohibiting a generation of a compensation instruction by the compensate instruction generating means when the option directing means is storing an indication denoting not to compensate.

49. A computer system comprising a processor and a program converting unit, wherein

said processor is one out of a series of embedded-type processors, each processor in the series having a different address bit width N, N being longer than a data width M, the address bit width N of said processor being selected in accordance with a program size,

said program converting unit generates a machine language instruction from a source program for a processor out of an embedded-type custom processor series which has an address width N in accordance with a necessary program size, and

said processor comprises:

memory means for storing a program, the memory means having a minimum storage capacity of 2.sup.N bytes to store the program and having N address lines, the program including an N-bit data arithmetic operation instruction and other instructions operating on both N-bit and M-bit data, N being greater than M; and

a processor core having an address bus of N bits which is equal in size to the number of address lines of the memory means, the processor core being selected from a plurality of processor cores,

wherein the processor core includes:

a program counter for holding an N-bit instruction address to output an instruction at the N-bit address to the memory means, the program counter having an N-bit address length which is equal in size to the number of address lines of the memory means;

fetching means for fetching an instruction from the memory means using an N-bit instruction address from said program counter; and

executing means for executing all N-bit arithmetic operation instructions and for executing other instructions except for arithmetic operation instructions at one of N-bit length and M-bit length, the executing means having N-bit length,

whereby an N-bit address is calculated by the N-bit arithmetic operation independently of a data bit-width, said data bit-width being M, and

said program converting unit comprises:

parameter holding means for holding a data width M and a pointer width N, said data width M representing the number of bits of data used in the source program, said pointer width N representing the number of bits of an address, said N and M being input by a user in accordance with program size; and

generating means for generating an instruction based on the source program to set the data width M as valid when a variable used in a machine language instruction to be generated is a variable showing data, and for generating an instruction to set the address width N as valid when a variable used in a machine language instruction to be generated is a variable representing an address,

wherein the program converting unit generates a unique set of machine language instructions from the source program for each N specified by the user.

50. The computer system of claim 49, wherein the processor further comprises:

an address register group including a plurality of N-bit address registers;

a data register group including a plurality of N-bit data registers,

wherein said executing means executes the N-bit and M-bit data operation instructions using the address registers, while executing the M-bit data operation instruction using data registers.

51. The computer system of claim 50, wherein:

said N is 24 and said M is 16; and

said processor is installed in a 1-chip microcomputer, whereby said 1-chip microcomputer becomes suitable for running a program that utilizes a memory over 64 Kbytes for an operation with 16-bit data.

52. The computer system of claim 51, wherein the processor further comprises:

compensating means for extending an effective bit-width of the data in one of the address registers and the data register to 24 bits,

wherein said compensating means operates in accordance with a compensate instruction entered after a machine language instruction designating an arithmetic operation that will possibly cause an overflow.

53. The computer system of claim 52, wherein said compensating means includes:

a first extending unit for filling a logical value of a sign bit in all bits higher than the effective bit-width in a register; and

a second extending unit for filling a logical value "0" in all bits higher than the effective bit-width in a register.

54. The computer system of claim 50, wherein the processor further comprises:

compensating means for extending an effective bit-width of the data in one of the address registers and the data register to N bits,

wherein said compensating means operates in accordance with a compensate instruction entered after a machine language instruction designating an arithmetic operation that will possibly cause an overflow.

55. The computer system of claim 54, wherein said compensating means includes:

a first extending unit for filling a logical value of a sign bit in all bits higher than the effective bit-width in a register; and

a second extending unit for filling a logical value "0" in all bits higher than the effective bit-width in a register.

56. The computer system of claim 49, wherein the processor further comprises:

an address register group including a plurality of N-bit address registers; and

a data register group including a plurality of M-bit data registers,

wherein said executing means executes one of an N-bit data operation instruction and an M-bit data operation instruction using the address registers, while executing the M-bit data operation instruction using the data registers.

57. The computer system of claim 56, wherein:

said N is 24 and said M is 16; and

said processor is installed in a 1-chip microcomputer, whereby said 1-chip microcomputer becomes suitable for running a program that utilizes a memory over 64 Kbytes for an operation with 16-bit data.

58. The computer system of claim 57, wherein the processor further comprises:

compensating means for extending an effective bit-width of the data in one of the address registers and the data register to 24 bits,

wherein said compensating means operates in accordance with a compensate instruction entered after a machine language instruction designating an arithmetic operation that will possibly cause an overflow.

59. The computer system of claim 58, wherein said compensating means includes:

a first extending unit for filling a logical value of a sign bit in all bits higher than the effective bit-width in a register;

a second extending unit for filling a logical value "0" in all bits higher than the effective bit-width in a register.

60. The computer system of claim 49 wherein the pointer width N and the data width M are input by a user during an execution of the program converting unit.

61. A computer system comprising a central processing unit and a software program compiler, wherein

the central processing unit is one of a series of processing units, each processing unit having a different address length N, N being longer than a data width M, the address length of the processing unit selected based on a size of a source program, the processing unit comprising:

memory means for storing a program, the memory means having a minimum storage capacity of 2.sup.N bytes to store the program and having N address lines, the program including an N-bit data arithmetic operation instruction and other instructions operating on both N-bit and M-bit data, N being greater than M; and

a processor core having an address bus of N bits which is equal in size to the number of address lines of the memory means, the processor core being selected from a plurality of processor cores,

wherein the processor core includes:

a program counter for holding an N-bit instruction address to output an instruction at the N-bit address to the memory means, the program counter having an N-bit address length which is equal in size to the number of address lines of the memory means;

fetching means for fetching an instruction from the memory means using an N-bit instruction address from said program counter; and

executing means for executing all N-bit arithmetic operation instructions and for executing other instructions except for arithmetic operation instructions at one of N-bit length and M-bit length, the executing means having N-bit length,

compensating means for extending an effective bit-width of the data in one of the address registers and the data register to N bits, wherein the compensating means compensates as directed by a compensate instruction which is entered after a machine language arithmetic instruction which may cause an overflow;

whereby an N-bit address is calculated by the N-bit arithmetic operation independently of a data bit-width, said data bit-width being M, and the software compiler comprises:

parameter holding means for holding a data width M and a pointer width N, the data width M representing the number of bits of data used in the source program, the pointer width N representing the number of bits of an address, N and M being inputs to the compiler input by a user during an execution of the compiler, N and M selected by the user based on the size of the source program; and

generating means for generating an instruction based on the source program to set the data width M as valid when a variable used in a machine language instruction to be generated is a variable showing data, and for generating an instruction to set the address width N as valid when a variable used in a machine language instruction to be generated is a variable representing an address,

wherein the program converting unit generates a unique set of machine language instructions from the source program for each N specified by the user.

Description

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a program converting unit for converting a high level language program into a machine language program and a processor for running the converted program, and more particularly, to such a processor improved in address management with various types of register groups including address and data registers.

(2) Description of the Related Art

With the recent advancement in the field of electronic technology, data processors such as a microprocessor and a microcomputer have been used widely. Today's typical data processor can process data of various widths, and a data processor furnished with a 16-bit or 32-bit CPU has been developed to meet the needs for more efficient data processing and advanced functions. Such a processor may be additionally furnished with various types of register groups including an address register and a data register to further upgrade the performance. Also, there is a need for a processor with a more efficient address management function as the data and programs have increased in size in response to the sophistication and enlargement of applications. In the following, five conventional processors will be explained while considering both of their improvements and shortfalls in address management.

FIRST CONVENTIONAL PROCESSOR

Firstly, a 16-bit segment-address processor will be explained. This type of processor is described in, for example, "Hardware for Microprocessor", Iwao Morishita, Iwanami-shoten, Nov. 9, 1984. The processor includes a segment register which stores a high order address including bits beyond 16 bits to secure an address space over 64 (2.sup.16) Kbyte while processing 16-bit data. More precisely, the address space over 64 Kbyte is divided into a set of 64 Kbyte segments to be serially numbered, and the addresses are managed by the segment numbers thus stored in the segment register and an offset, i.e., a distance from the head of each 16-bit segment.

Also, a 32-bit segment-address processor is disclosed in the aforementioned "Hardware for Microprocessor". This processor can secure an address space of 4 Gbyte (2.sup.32) by managing 32-bit addresses while processing 32-bit data.

These segment-address processors run a machine language program translated by a program converting unit such as a compiler.

An address management of a compiler for a 16-bit processor includes two models: one is a large model and the other is a near-far model.

A large model compiler always sets a pointer variable with a segment number and a 16-bit offset in pairs. Thus, the 16-bit processor that runs an object code from the compiler calculates the content of the segment register to update the same each time an address is calculated. Consequently, the performance efficiency is significantly degraded compared with a 16-bit non-segment-address processor.

A near-far model compiler eliminates this problem by designating one of two pointer variables: a near pointer variable and a far pointer variable; the former is used to access an address within one segment and the latter is used to access an address across a segment boundary. The compiler sets the 16-bit offset alone with the near pointer variable while setting a pair of the segment number and 16-bit offset with the far pointer variable. When the 16-bit near-far model compiler uses the near pointer variable, the performance efficiency is enhanced compared with the 16-bit large model compiler. However, on the other hand, programming efficiency is degraded because it is a programmer that selects one of the two pointer variables by checking the segment boundary.

A compiler for a 32-bit processor is advantageous in that it is free of the aforementioned problems. Because this compiler sets a 32-bit address to the pointer variable for a 32-bit data variable, and thus the programmer does not have to check the segment boundary. Naturally, the 32-bit processor runs the compiled program without degrading performance while securing the address space of 4 Gbyte.

However, most of the applications for an embedded-type microcomputer demand neither the 32-bit data nor address space of 4 Gbyte, but demand the 16-bit data and address space over 64 Kbyte. Thus, if the 32-bit processor and compiler are employed, the hardware is not fully utilized, wasting the cost and running electricity. In addition, the 32-bit processor always designates a 32-bit address in a program, and thus increases a program code size undesirably. Also, the performance is degraded when a 16-bit data bus is used to connect the 32-bit processor to a memory compared with a 32-bit data bus.

Therefore, neither 16-bit and 32-bit segment-address processors nor their corresponding compilers developed to date have met the practical needs.

SECOND CONVENTIONAL PROCESSOR

A second conventional processor includes various types of register groups including address registers and data registers, which is described, for example, in "M68000 8/16/32MICROPROCESSOR USER MANUAL", Motorola Inc.

A structure of the second conventional processor is depicted in FIG. 1. The processor comprises a register unit 11 including a plurality of 32-bit address registers and 32-bit data registers, an instruction decoding unit 12 for decoding an instruction, an external storage unit 13, and an external-access executing unit 14 for inputting and outputting data of a designated bit-width with the external storage memory unit 13. The instruction decoding unit 12 sends register information 15 and bit-width information 16 to the external-access executing unit 14; register information 15 and bit-width information 16 indicate a register subject to data transfer and a bit-width of transmission data, respectively. Assume that a 16-Mbyte address space and 16-bit data are used in an application herein.

A format of an instruction to transfer the data from one of the registers in the register unit 11 to the external storage unit 13 is shown in FIG. 2: OP is an operation field designating a kind of instruction; SIZE is a size field designating the bit-width of the transmission data; SRC is a source field identifying a source register; and DEST is a destination field specifying a destination address in the external storage unit 13.

The second conventional processor executes the above data-transfer instruction in the following way.

To begin with, the instruction decoding unit 12 decodes the data-transfer instruction as: OP designates MOVE; SIZE designates 32-bit data; SRC identifies a register A1; and DEST identifies an address stored in a register A2. Accordingly, the decoding unit 12 outputs the register information 15 and bit-width information 16 to the access executing unit 14, which, in response, writes the content in the register A1 into the external storage unit 13 at the address @A2 in the designated 32-bit width.

However, the second conventional processor demands the size field in each data-transfer instruction, which further demands a size-field decoding function and enlarges an instruction code, or increases the code size.

In addition, since the size field designates one of 32-, 16-, and 8-bit data, 32-bit data are always transferred to the address register when the address for the application is 24-bit or less wide. When 16-bit data are transferred, the execution speed will not be decreased if the compiler designates a 16-bit width by the size filed. Some compilers, however, may not judge the effective 16-bit width when the program uses 16-bit data. In this case, the compiler designates a 32-bit width where 16-bit width should have been designated instead. Thus, if the data are transferred to an 8-bit-width memory, the data are transferred four times per 8 bits and the last two 8-bit data transfer are redundant.

THIRD CONVENTIONAL PROCESSOR

A third conventional processor can process data of a plurality of data widths. For example, immediate data, which directly specifies a value in a program instruction, are processed after the immediate data are sign-extended. This type of processor is described, for example, "Microcomputer Series 14 68000 Microcomputer", Yuzo Kida, Maruzen, March, 1983.

A structure of the third conventional processor is depicted in FIG. 3. The processor comprises a group of data registers 31 for storing 32-bit data, a group of address registers 32 for storing 32-bit addresses, a sign-extender 33 for sign-extending the MSB of 16-bit data to output 32-bit data, an instruction decoding unit 34 for decoding an instruction, and a calculator 35 for operating a calculation in accordance with the decoding result.

The above-constructed processor operates in the following way. To begin with, the instruction decoding unit 34 decodes an input instruction from an external unit, and the other components operate differently in two cases according to the decoded instruction.

(1) In case of an instruction to transfer the data between one of the data registers 31 and one of the address registers 32, or to execute an arithmetic operation using the data therein, the calculator 35 receives 32-bit data from both the registers and operates a calculation using the same to store the result of the operation into a designated register.

(2) In case of an instruction to transfer 16-bit immediate data to one of the data registers 31 or address registers 32, or to execute an arithmetic operation using the same, the immediate data are extended to 32-bit data by the sign-extender 33 to be outputted to the calculator 35; the calculator 35 operates a calculation using the sign-extended data and stores the result of the operation into a designated register.

The operation of the sign-extender 33 will be described more in detail by referring to FIGS. 4A, 4B. When the MSB of 16-bit data exhibits "O" as shown in FIG. 4A, the 16-bit data are extended to 32-bit data by filling the zero's in the 32nd bit. On other hand, when the MSB exhibits "1" as shown in FIG. 4B, the 16-bit data are extended to 32-bit data by filling one's in the 32nd bit.

Assume that the immediate data are shorter than the register designated for calculation and data-storage. The operation of the third conventional processor when executing a program with such immediate data will be explained with referring to FIGS. 5, 6, and 7; FIG. 5 shows an example of a program, FIG. 6 details the flow of the operation for running that program, and FIG. 7 shows an address space.

As understood from FIG. 6, the program in FIG. 5 reads: add up the data at sixteen addresses from the addresses H8000to H8100 (H represents hexadecimal and each address is H10 addresses away) and write the result at the address H10000000. However, executing Instructions 2, 5, and 6 does not result as detailed by FIG. 6. Thus, to run the program as detailed by FIG. 6, Instructions 2, 5, and 6 are, in effect, re-written to Instructions 2', 5', and 6', respectively.

For further understanding, the program in FIG. 5 will be explained more in detail.

Instruction 1: Clear a data register D0

Instruction 2: Set 16-bit immediate data H8000 in an address register A0.

Since Instruction 2 uses a notation of the 16-bit immediate data H8000, the immediate data H8000 are sign-extended to 32-bit data HFFFF8000 by the sign-extender 33 to be stored into the address register A0.

Instruction 3: Read out the content stored at an address designated by the address register A0 from the memory to store the same into a data register D1.

Instruction 4: Add the content in the data register D1 to that of the data register D0 to store the result in the data register D0.

Instruction 5: Add immediate data H0010 to the address register A0 to store the result into the address register A0.

The 16-bit immediate data H0010 are extended to 32-bit data HFFFF0010 by the sign-extender 33. Subsequently, the calculator 35 adds the address data HFFFF8000 stored in the address register A0 to the extended data HFFFF0010 to output the data HFFFF8010, which are stored into the address register A0.

Instruction 6: Compare the output data with immediate data H8100.

The immediate data H8100 are also sign-extended to 32-bit data HFFFF8100 by the sign-extender 33 to be outputted to the calculator 35. Accordingly, the calculator 35 compares the same with the address data HFFFF8010 read out from the address register A0.

Instruction 7: Return to Instruction 3 labeled A when the former is greater than the latter; otherwise, proceed to Instruction 8.

The loop of Instructions 3-7 is repeated until the initial value of the address register A0, i.e., HFFFF8000, is incremented up to HFFFF8100 by H00000010. This means that the processor proceeds to Instruction 8 when the result of the sixteen addition operations has been stored into the data register D0.

Instruction 8: Store the content in the data register D0 into the memory at the address H10000000.

With the third conventional processor, the immediate data used for an access to the address register may have a value unexpected by the flowchart shown FIG. 6. This will be explained more in detail. In FIG. 5, the immediate data H8000, H0010, and H8100 are used for the access to the address register by Instructions 2, 5, and 6, respectively. In case of the immediate data H8000, they are sign-extended not to H00008000 but HFFFF8000. This is because the MSB thereof exhibits "1" and the higher order is filled with all one's. Naturally, the immediate data HFFFF8000 is stored into the address register A0, and the data at the address HFFFF8000 are read out by Instruction 3 where the data at the address H00008000 should have been read out instead as shown in FIG. 7. Thus, the data unexpected from FIG. 6, are read out as a result.

Similarly, the immediate data H8100 is extended not to H00008100 but to HFFFF8100 by Instruction 6, causing the processor to output an unexpected value as the operation result.

As has been stated, with the third conventional processor, the sign-extension causes the immediate data to exhibit a value unexpected by a programmer from the flowchart in FIG. 6 while running the program. This occurs only when the immediate data's MSB is addressed with a value "1" in the address space. Therefore, to eliminate this problem, a method using a 32-bit notation for the immediate data designation has been proposed. For example, the immediate data are designated as H00008000 instead of H8000 by Instruction 2. However, this method demands the 32-bit notation even when 16-bit data are designated, and thus extending the instruction size and object code unnecessarily.

Given these circumstances, a method for re-writing the program using the 16-bit immediate data has been proposed to eliminate the above problem, which is shown in FIG. 8.

In the re-written program, original Instruction 2 is carried out by two steps: Instructions 2-1, 2-2. The immediate data H8000 given by Instruction 2-1 are sign-extended to HFFFF8000 first, and then, the extended data HFFFF8000 and H0000FFFF are ANDed to clear the higher 16 bits to zero's by Instruction 2-2, outputting 32-bit data H00008000.

Similarly, original instruction 6 is carried out three steps: Instructions 6-1, 6-2, and 6-3. The immediate data H8100 given by Instruction 6-1 are sign-extended to HFFFF8100 to be stored into the address register A1 first, and then the extended data HFFFF8100 and H0000FFFF are ANDed to clear the higher 16 bits to zero's by Instruction 6-2, outputting 32-bit data H00008100. Finally, the address registers A0 and A1 are compared by Instruction 6-3.

This enables the use of the 16-bit immediate data; however, it increases the number of steps compared with the program in FIG. 5.

Thus, a processor that can access to correct data in the address space efficiently using the immediate data shorter than the address register has not been realized yet.

FOURTH CONVENTIONAL PROCESSOR

A fourth conventional processor is either a CISC (Complex Instruction Set Computer) or a RISC (Reduced Instruction Set Computer) processor. The former, such as TRON or MC68040, can execute a variety of kinds of instructions while the latter, such as SPARC or MIPS, can speed up the operation by limiting the kinds of available instructions. Both the CISC and RISC processors generally employ a plurality of 32-bit register and a 32-bit calculator.

In a 32-bit CISC processor, all the 32-bit registers can handle any of 8-, 16-, and 32-bit data for any arithmetic operation instruction. In response, a compiler for the 32-bit CISC processor generates an operation code in accordance with the data width used at the 32-bit registers. For example, to generate an instruction to store an 8-bit character data variable, or 16-bit short-integer data variable into the 32-bit register, a code such that stores these data variables into the lower 8 and 16 bits in the 32-bit register respectively and to leave the higher 24 and 8 bits intact respectively is generated.

However, the number of the instructions increases considerably in the above way, which demands larger and more sophisticated hardware for the instruction decoding and execution. This problem is eliminated by the RISC processor.

Unlike the CISC processor, the RISC processor limits the kinds of the available instructions and does not generate an instruction such that updates only the lower 8 bits or lower 16 bits of the 32-bit register. Instead, it generates a code to update all the 32 bits in the register, and subsequently generates a code to compensate the higher 24 and 16 bits respectively to adjust the bit widths to adequate ranges set forth below. This is done to compensate an overflow possibly caused by the arithmetic operation for the data variables.

ADEQUATE RANGES

    ______________________________________
    Type of data variable
                     Range (decimal)
    ______________________________________
    singed character -128 to +127 (inclusive)
    unsigned character
                     0 to +255 (inclusive)
    signed short integer
                     -32768 to +32767 (inclusive)
    unsigned short integer
                     0 to +65535 (inclusive)
    ______________________________________

    ______________________________________
    Kind of data variable
                      Compensation Instruction
    ______________________________________
    singed character  left-shift by 24 bits &
                      arithmetic right-shift by
                      24 bits
    unsigned character
                      left-shift by 24 bits &
                      logica1 right-shift by
                      24 bits
    signed short integer
                      left-shift by 16 bits &
                      arithmetic right shift by
                      16 bits
    unsigned short integer
                      left-shift by 16 bits &
                      logical right-shift by
                      16 bits
    ______________________________________

    ______________________________________
    EXTX Dn         ; sign-extend 16 bits to 24 bits
    EXTXU Dn        ; zero-extend 16 bits to 24 bits
    EXTXB Dn        ; sign-extend 8 bits to 24 bits
    EXTXBU Dn       ; zero-extend 8 bits to 24 bits
    ______________________________________

    ______________________________________
    MOVI #imm16, Dn ; sing extend 16-bit immediate data
                    to 24 bits (#imm16.fwdarw.Dn)
    MOVI #imm8, Dn  ; sign-extend 8-bit immediate data
                    to 24 bits (#imm8.fwdarw.Dn)
    MOVI #imm16, An ; zero-extend 16-bit immediate data
                    to 24 bits (#imm16.fwdarw.An)
    MOV Mem, Dn     , sign-extend 16 bits to 24 bits
                    (Mem.fwdarw.Dn)
    MOVB Mem, Dn    ; sign-extend 8 bits to 24 bits
                    (Mem.fwdarw.Dn)
    MOVBU Mem, Dn   ; zero-extend 8 bits to 24 bits
                    (Mem.fwdarw.Dn)
    ______________________________________