Word processing system employing a plurality of general purpose processor circuits

Abstract

A data processing system embodying the present invention includes a plurality of data processing stations. Each station includes a first communications interface connected to a common communication channel and a second communications interface for communicating with one or more associated controlled units. Each station also includes a processor and a memory; the processor and the interfaces being operatively connected to the memory, so that each may access the memory, and to a contention resolving circuit for resolving memory access conflicts. The system also includes a first controlled unit comprising a mass storage device and a controlled unit communications interface connected to the second communications interface of a first one of the plurality of processors; a second controlled unit comprising a keyboard for entering data and a first, single line, display for displaying data and a controlled unit communications interface connected to the second communications interface of a second of the plurality of processors; and a third controlled unit comprising a second, multi-line, display for displaying data and a controlled unit communications interface connected to the second communications interface of a third of a plurality of processors.

Claims

What is claimed is:

1. A data processing system, comprising:

(a) a plurality of data processing stations each having a first communications means for connecting each of said stations to a common communications channel and having a second communications means for communicating with one or more associated controlled units, each of said data processing stations further comprising a processor and a memory, said first communications mean, said second communications means and said processor each operatively connected to said memory, so that each may access said memory, and to contention resolving means, said resolving means being operatively connected to said memory and to each other device operatively connected to said memory, for resolving conflict between said other devices for access to said memory;

(b) said common communications channel operatively connected to said first communications means of each of said plurality of data processing stations, whereby each of said processors may access said memory of any of said processing stations;

(c) a first one of said controlled units further comprising mass storage means for entering data for storage and for retrieving stored data and including a controlled unit communications means for data communications, said first controlled unit communications means coupled to said second communications means of a first one of said plurality of data processing stations, whereby said first controlled unit may communicate with said first station;

(d) a second one of said controlled units further comprising a keyboard for entering data into said system and a first display means for displaying a single line of data and including a controlled unit communications means for data communications, said second controlled unit communications means coupled to said second communications means of a second one of said plurality of data processing stations whereby said second controlled unit may communicate with said second station; and

(e) a third one of said controlled units further comprising second display means for displaying multiple lines of data and including controlled unit communications means for data communications, said third unit communications means coupled to second communication means of a third one of said plurality of data processing stations, whereby said third controlled unit may communicate with said third station.

2. A system as described in claim 1 further comprising a fourth one of said controlled units including means for printing data and controlled unit communications means for data communications, said fourth controlled unit communications means coupled to said second communications means of a fourth one of said plurality of data processing stations, whereby said fourth unit may communicate with said fourth station.

3. A system as described in claim 2 wherein said first display means includes means for displaying a predetermined amount of the most recently entered of the data entered from said keyboard.

4. A system as described in claim 1 wherein said first display means includes means for displaying a predetermined amount of the most recently entered of the data entered from said keyboard.

5. A system as described in claims 1, 2, 3 or 4 wherein said system is a word processing system.

6. A system as described in claims 2 or 4 wherein the data entered from said keyboard comprises character data for display on said first and second display means and control data for controlling the appearance of said displayed character data on said second display means; only said character data appearing on said second display means and a predetermined portion of the most recently entered of both said character data and said control data appearing on said first display means.

7. A system as described in claims 3 or 5 wherein the data entered from said keyboard comprises character data for display on said first and second display means and control data for controlling the appearance of said displayed character data on said second display means; only said character data appearing on said second display means and both the most recently entered of said character data and said control data appearing on said first display means.

8. A system as described in claim 6 includes means for printing said character data substantially as it appears on said second display means.

9. A system as described in claim 8 further comprising at least one additional controlled unit substantially identical to said second controlled unit and an additional one of said processing stations associated therewith in a substantially identical manner.

10. A system as described in claim 9 wherein said second display comprises a CRT.

11. A system as described in claim 8 wherein said second display means comprises a CRT.

12. A system as described in claim 11 wherein said first display means is a plasma display.

13. A system as described in claim 10 wherein said first display means is a plasma display.

Description

FIELD OF THE INVENTION

The present invention relates to word processing systems, and more particularly to a system employing a plurality of general purpose processor circuits.

BACKGROUND OF THE INVENTION

In multiple user systems, that is, systems wherein the word processing system is utilized by several different individuals performing the same or different operations, it is desirable to have flexibility in the systems configuration and the utilization of the computing capability provided. The systems are desirably such that they can be modified to add on additional capability and functions or to subtract capability and functions so that the systems can be configured conveniently to achieve a particular objective. In general, systems have been developed incorporating dual (or a greater number) of displays. Some of these systems have plural display with each display exhibiting identical information, such as in the case of plural CRT monitors coupled to a common signal source.

Examples of various configurations that users may desire involve the number of printers that a system incorporates, the number of data entry stations that the system incorporates, and the manner in which the system shares the resources available for performing various functions. Word processing systems have been developed employing distributed processing. One word processing system employs microcomputers to implement distributed intelligence in multiple station systems.

The previous systems that have been configured for multiple user application have been limited in the flexibility that they provide in terms of systems configuration modification and capability. One example of a multiple user system involves a single central processing unit to which various subsystems are attached. One such example is shown in U.S. Pat. No. 3,654,609 granted to Bluethman et al. This reference discloses an editing system including a CRT display which displays input characters in a proportionally spaced representation. The text character representations are stored in memory and are accessed by a processor. In this system, additional subsystems are attached to operate in conjunction with the single central processing unit. As additional subsystems are attached to the configuration to support additional users, the single processor begins to reach the limit of its capability. The response time for the central processor unit to respond to subsystem requests for data manipulation soon exceeds the time constraints for the additional subsystems. Moreover, should the single central processing unit fail, all of the subsystems are rendered inoperable and the entire system can not be utilized.

The invention disclosed in this cited reference requires the use of a large memory with the single central processing unit. The single central processing unit itself is more expensive and more critical to the operation of the entire system than components used in distributed configurations.

Another approach to the multiple user and subsystem word processing systems involves the dedication of subsystems to each particular function or task. An example of such an approach is shown in U.S. Pat. No. 3,815,104 granted to Goldman. In this system, the subsystems are hard wired and are each dedicated to a particular task. FIG. 1 in this reference, for example, clearly indicates that hardware is associated with each the function such as pagination, justification, clean up hyphen and keyboard interface. Thus, flexibility is very much constrained in terms of the hardware of the system.

The subsystems are connected to each other by means of a communications bus which includes a data bus, a special control and indicator bus, an address bus and a timing bus. Although the system utilizes distributed processing, each subsystem is rigid in that its function is designed into the hardware and it is not capable of being utilized for any other function.

SUMMARY OF THE INVENTION

The present invention relates to a configuration for a word processing system that allows simultaneous and independent processing of functions within separate processors.

In accordance with the present invention the system enables a flexibility in modification so that multiple users can be accommodated. Subsystems can readily be added to or subtracted from a given system configuration to meet a particular user's needs without degregating, in any way, the response time of any subsystem in the configuration. Moreover, if any processor in the system becomes inoperative for any reason, the remaining subsystem can operate normally unless a rare situation occurs during which the failure is not of a localized nature for the particular subsystem but is a failure that affects other subsystems.

A data processing system embodying the present invention includes a plurality of data processing stations. Each station includes a first communications interface connected to a common communications channel and a second communication interface for communicating with one or more associated controlled units. Each station also includes a processor and memory; the processor and the interfaces being operatively connected to the memory, so that each may access the memory, and to a contention resolving circuit for resolving memory access conflict. The system also includes a first controlled unit comprising a mass storage device and a controlled unit communications interface connected to the second communications interface of a first one of the plurality of processing stations; a second controlled unit comprising a keyboard for entering data, a first, single line, display for displaying data and a controlled unit communications interface connected to the second communications interface of a second one of the plurality processors and a third controlled unit comprising a second display means for displaying multiple lines of data and a controlled unit communications interface connected to the second communications interface of a third one of the plurality of processors.

In a preferred embodiment, the data processing systems also includes a fourth controlled unit comprising a printer and a controlled unit communications interface connected to the second communications interface of a fourth of the plurality of processors.

BRIEF DESCRIPTION OF THE DRAWINGS

A complete understanding of the present invention may be obtained by reference to the accompanying drawings, when taken in conjunction with the detailed description thereof and in which:

FIG. 1 is a perspective view of a word processing system in accordance with the present invention;

FIG. 2 is a top view of a keyboard for use in the word processing system shown in FIG. 1;

FIGS. 3, 4 and 5 are block diagrams of three configurations of word processing systems embodied in the present invention;

FIG. 6 is an interconnection diagram of FIGS. 6a through 6f which when taken together are a block diagram of an entire word processing system, in accordance with the present invention, with each of the subsystems shown in block diagram form (the detailed schematic circuit diagrams of which are shown in subsequent figures);

FIG. 7 is a block diagram of a general purpose processor for use in a word processing system employing plural processors, such as shown in the preceding figures;

FIG. 8 is a block diagram of a configuration of a word processing system embodying the present invention;

FIG. 9 is a block diagram helpful in an understanding of the general purpose processor communications via the word processing system back plane bus;

FIG. 10 is a block diagram helpful to an understanding of the means by which the general purpose processor communicates with a peripheral device;

FIGS. 11 and 12, which are interconnection diagrams of FIGS. 11a through 11i and 12a through 12j, respectively, which when taken together are a general purpose processor schematic circuit diagram;

FIGS. 13, 14, 15, 16, and 17, which are interconnection diagrams of FIGS. 13a through 13e, 14a through 14h and 17a through 17h and block diagrams which when taken together are a schematic circuit diagram of a disk controller and a block diagram of a floppy disk DMA controller;

FIGS. 18, 19, 20, and 21, which are interconnection diagrams of FIGS. 18a through 18d, 20a through 20d and 21a through 21c and a diagramatic representation which when taken together are a typewriter remote keyboard display unit controller schematic circuit diagram and a diagramatic representation of a one-line display for use with the typewriter remote keyboard display unit controller;

FIG. 22 is a block diagram of a CRT controller system with its associated general purpose processor;

FIGS. 23, 24, 25, 26, 27, 28, 29 and 30, which are interconnection diagrams of FIGS. 23a through 23c, 24a through 24c, and 29a through 29e and block diagrams which when taken together are schematic circuit diagrams of the CRT1 controller shown in FIG. 22, and a block diagram of a portion of the CRT controller circuitry;

FIGS. 31, 32 and 33, which are interconnection diagrams of FIGS. 31a through 31c and 33a through 33e and a state diagram which when taken together are a schematic circuit diagram of the CRT2 controller shown in FIG. 22, and a diagram helpful in understanding the state sequence for the row counter on the CRT2 controller circuit; and

FIG. 34 which is an interconnection diagram of FIGS. 34a through 34i which when taken together are a schematic circuit diagram of the receive only printer controller.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference is now made to FIG. 1. A word processing system 12 includes a keyboard 14 having a one line display 16. The one line display is employed to exhibit entered alphanumeric data and other command information in the operation of the word processing system 12. A full page CRT display 18 is provided and is operably connected to the keyboard 14. The CRT display 18 and the one line display 16 operate cooperatively as will be explained in detail hereinafter. A floor module 110 is provided with a floppy type disk drive. The floppy disk drive can be a single or dual disk drive and additionally is suitable for use with both single density and double density recorded disk formats. The floppy disk floor module 110 includes a power switch 112, which when actuated initializes the circuits of the word processing system 12. A system reset switch 114 is provided on the floor module 110. The reset switch 114, when activated as explained in greater detail hereinafter, resets the operating system.

A daisy wheel type printing unit, not shown, may be provided for use in the word processing system 12. Alternatively, a configuration, as is explained in greater detail hereinafter, employs a keyboard display typewriter unit. When the keyboard display typewriter unit is employed, the printer is not necessary for inclusion in the system unless special features associated with the printing unit are desired.

Referring now also to FIG. 2, a keyboard 22 is provided for use in the word processing system. The keyboard 22, as previously described, includes a one line display 24. The one line display 24 may be a standard plasma matrix type display. The keyboard 22 includes the general alphanumeric keys associated with standard word processing systems. These keys are alterable depending upon the language to be employed by the user and the particular application. For example, special purpose mathematical, statistical and scientific type keys and associated print elements may be provided.

The keyboard 22 includes certain special purpose function keys which operate in conjunction with the associated circuits as is explained in greater detail hereinafter. The special purpose keys represent frequently used commands and include a PRINT key 26, a MESSAGE key 28, a BACKGROUND key 210, a FIELD key 212, a BOLD key 214, a CENTER key 216, an UNDERSCORE key 218 and a FORMAT key 220. Additional space is provided for auxiliary keys 222, 224, 226 and 228. These keys can include, for example, a DOUBLE UNDERSCORE key.

Additional special purpose keys which have dual functions include a SUPERSCRIPT/SUBSCRIPT key 230, a CALL/SAVE key 232, a ZOOM key 234, a DOCUMENT/PAGE key 236, a REPLACE/AGAIN key 238, a TOP/BOTTOM key 240, an INSERT/APPEND key 242, a DELETE/RECALL key 244 and a NEXT/PREVIOUS key 246. Cursor control keys 248A, 248B, 248C and 248D are also provided.

The above mentioned special purpose function keys 230 through 248D, except for the ZOOM key 234, are dual function keys. These keys are labeled with two colors: black and blue or white and blue. (The cursor control keys 248A through 248D are labeled with only one color.)

These keys are used in conjunction with a blue colored key 249. Dual function keys serve two purposes. To perform the top (black label) function, a dual function key is normally depressed. To perform the bottom (blue label) function, the blue colored key 249 is held down while a dual function key is depressed. In other words, when held down in conjunction with a dual function key, the blue key 249 activates the dual blue engraved function of that key.

In operation, the SUPERSCRIPT/SUBSCRIPT key 230 moves the baseline of text up or down in increments of 1/4 line. The CALL/SAVE key 232 saves a string of text by a phrase name that can be recalled in the document or in another document. The DOCUMENT/PAGE key 236 selects or creates a document, or it selects a specified page in a document. The REPLACE/AGAIN key 238 deletes and replaces a specified string of text. The TOP/BOTTOM key 240 moves the cursor to the top or bottom of the text on the CRT screen. The INSERT/APPEND key 242 inserts text at the cursor position and readjusts the text. When used with the blue colored key 249, the INSERT/APPEND key 242 positions the cursor at the end of the document to append more text to the document. The DELETE/RECALL key 244 deletes and recalls text. The NEXT/PREVIOUS key 246 creates a new page when typing, or provides access to the next page. When used with the blue colored key 249, the NEXT/PREVIOUS key 246 provides access to the previous page.

The cursor control keys include an up arrow, left arrow, right arrow and down arrow key, 248A, 248B, 248C and 248D, respectively. When depressed normally, these keys move the cursor up, left, right and down one character at at time on the CRT screen. When used with the blue colored key 249, they scroll the text on the CRT screen up, to the left, to the right and down, respectively.

Additional keys are provided including a STOP key 250, a CONTINUE key 252, a COMMAND EXECUTE key 254 and an INDEX key 256.

Several of the keys operate in two modes. The mode of operation is determined by whether a visual indicator is actuated. Thus, for example, the BACKGROUND key 210 includes a light emitting diode (LED) 258 which is mounted in the key switch mechanism 210. As is explained hereinafter, the LED 258 is illuminated and/or caused to blink, depending on whether the key 210 is actuated to cause the word processing system to function in a background or in a foreground mode of operation.

One of the features of the present word processing system is the ability to handle several different jobs simultaneously. It is useful to be able to perform background printing and sorting operations while inputting or editing text. Moreover, the system is expandable to allow a number of key stations to be associated with one floor module, as hereafter described. In general, architecture used in prior word processing systems utilizes a single microprocessor with memory on adjacent printed circuit boards. In those systems, the microprocessor is attached via a bus to memory. Other circuitry is provided in those systems to handle input/output (I/O) operations for a floppy disk controller and a typewriter.

While this architecture is sufficient for single-terminal standalone systems, several key stations on one system and foreground/background operations would tax the throughput of even a high power single processor. A multiprocessor environment, with dedicated processors to handle different key stations and background operations, requires novel architecture, as hereafter described.

Referring now also to FIG. 3, in one configuration of the word processing system, three general purpose processors 32, 34 and 36 are interconnected by a backplane bus 38. The general purpose processor 32 is connected to a floppy disk controller 310 and a receive only printer 312. The floppy disk controller 310 is connected to a disk drive unit 314.

General purpose processor 34 is connected to a keyboard display 316. The keyboard display 316 is of the type shown in FIG. 2.

The general purpose processor 36 is connected via a first CRT controller (CRT1) circuit 318 and a second CRT controller (CRT2) circuit 320 to a CRT unit 322.

Referring now also to FIG. 4, two general purpose processors 42 and 44 are provided. The general purpose processors 42 and 44 are interconnected by a back plane bus 46. General purpose processor 42 is connected to a floppy disc controller 48 which, in turn, is connected to a disc drive 410. General processor 44 is connected to a typewriter 412. The typewriter 412 is of the type which includes a keyboard, a one line display and a daisy wheel typewriter printing mechanism.

Referring now also to FIG. 5, a plurality of general purpose processors 52, 54, 56, 58, 510, and 512 is provided. These general purpose processors are interconnected via a back plane bus 514. Although only six general purpose processors are shown in one configuration of the word processing system, up to 16 general purpose processors may be connected to the back plane bus 514. As is explained in greater detail hereinafter, the physical position of each general purpose processor on the back plane bus has significance in operation of the general purpose processor system circuitry.

The general purpose processor 52 is connected to a keyboard display unit 516. The keyboard display unit includes a keyboard and one line display. The general purpose processor 54 is connected via CRT controller (CRT1) and (CRT2) circuits 518 and 520, respectively, to a CRT display unit 522. The general purpose processor 56 is connected to a receive only printer 524. The general purpose processor 58 is connected to a typewriter unit 526. This unit includes the keyboard, a one line display and a typewriter unit printing mechanism. The general purpose processor 510 is connected to an optional communications unit 528 to facilitate communications with remotely located word processing systems or for other suitable systems.

A general purpose processor 512 is shown unconnected to any other unit. This general purpose processor 512 is shown to denote the flexibility of adding functions to the word processing system. The system can be configured to meet the particular needs of a user by connecting additional general purpose processors such as unit 512, to the back plane 514 in conjunction with associated controlled units coupled to the processor.

As can be seen in the present configuration, two data entry stations are provided, one being a keyboard display unit 516 and the other being a typewriter unit 526. The keyboard display unit 516 may have its alphanumeric input information printed out when desired on the receive only printer 524 while the typewriter unit 526 may have its alphanumeric input information printed by its own associated printer.

It should be recognized that a disc drive such as unit 410 shown in FIG. 4 or 314 shown in FIG. 3 could also be provided for the word processing system configuration shown in FIG. 5.

Referring now also to FIG. 6, it should be noted that the detailed schematic circuit diagram of each of the various modules shown therein is described in detail hereinafter. The system includes a plurality of general purpose processors 62, 64 and 66 which are interconnectd via the back plane bus 68. The back plane bus 68 includes an address bus BADD0 through BADD19 610, a databus BDB0 through BDB7 612 and a control bus 614. It should be recognized that additional general purpose processors can be connected to the back plane bus 68.

Each general purpose processor, such as for example general purpose processor 62, includes an Intel 8085A central processing unit (CPU) 616 introduced in 1976 and described in MCS 80/85 Family Users Manual, October 1979, available from the Intel Corp., California, an interprocessor communications (IPC) interface 618 and a USART 620. A random access memory 622 having provision for 32K bytes of memory (plus additional address space, as is described in greater detail hereinafter) is connected via a bus transceiver 624, an internal databus 626 and a bus interface 628 to the central processing unit 616.

The internal databus 626 is connected via an input/output buffer unit 630 and connecting data bus BDB0 through BDB7 632 to the back plane databus 612. Appropriate timing units may be connected to the internal databus 626, as shown in general purpose processor 64. A master request controller 634 is connected to the back plane control bus 614. The CPU 616 is connected via an internal address bus ADD0 through ADD15 636 and the interprocessor communications interface unit 618 to the back plane address bus 610.

General purpose processor 62 is connected to a CRT monitor unit 638 via a CRT1 controller module 640 and a CRT2 controller module 642. The CRT modules 640 and 642 include circuitry which is shown in greater detail hereinafter, for controlling the CRT monitor 638. The CRT1 controller 640 includes line buffers 644, and 646 and DMA logic 648. A character generator address multiplexer 650 as well as vertical timing circuitry 652 and horizontal timing circuitry 654 are coupled to the CRT2 controller 642.

The CRT1 controller 640 further includes a space generator 656, a bus receiver 658 and a control character decoder 660.

The CRT2 controller 642 includes a 38.2788 MHz clock 666 connected to the horizontal timing circuits 654 and to a row counter 682.

Video drivers 668 are coupled to a receiver input unit 670 of the CRT monitor 638.

The CRT2 controller 642 includes a width generator 672, a character generator A 674, a character generator B 676 coupled to a multiplexer 684. An attribute register 678 and the two character generators 674 and 676 are coupled to a serializer 679.

The monitor 638 includes a cathode ray tube (CRT) 686.

A disk controller 688 is coupled to the disk drive general purpose processor 66. The disk controller 688 includes boot PROMs 690 coupled to a data bus 692 which in turn is connected to a data bus interface 694, input/output (I/O) buffers 696, latch drivers 698, and a DMA controller 6100. An address bus ADD0 through ADD15 6102 and a databus D0 through D7 6104 interface the disc controller 688 to the disk drive general purpose processor 66.

A boot control and reset is provided at reference numeral 6106. A disk controller circuit 6108 is coupled to the I/O buffers 696 and is coupled to drivers and receivers 6110 and 6112, respectively, which drivers and receivers are coupled to a disk drive 6114.

The disk drive general purpose processor 66 is also coupled to a receive only (RO) printer controller 6116. The RO printer controller 6116 includes an 8085A microprocessor 6118 coupled via a databus 6120 to input drivers 6122 and 6124 and to output latches 6126, 6128 and 6130, some of which (6126, 6122 and 6128) are connected to an RO printer logic printed circuit board 6132 and the rest of which (6130 and 6124) are connected to a sheet feeder 6134.

The RO printer controller 6116 also includes a USART 6136 coupled to the databus 6120 via databus transceivers 6138. Boot PROMs 6140 and random access memory 6142 are also coupled to the databus 6120 of the RO printer controller 6116.

The keyboard general purpose processor 64 is coupled to a typewriter controller 6144. The typewriter controller 6144 has a microprocessor 6146 coupled via a databus 6148 to a databus interface 6150 and boot PROMs 6152. A USART 6154 is provided to receive data from and transmit data to the keyboard general purpose processor 64. This USART 6154 is coupled to a databus 6156 in the typewriter controller 6144. The databus 6156 is connected to input drivers and output latches shown generally at reference numeral 6158 to control a keyboard 6160, a one line plasma display 6162, an optional printer 6164 and an optional sheet feeder 6166.

Referring to FIG. 7, a number of general purpose processors (GPP) 72 are provided in the system. Each processor 72 has a Model 8085 microprocessor. The processors 72 each have 32K bytes of memory 74 and each processor 72 has several different ports to enable it to perform different kinds of functions. In particular there is a parallel port 76 on each general purpose processor 72 which communicates with different device controllers 78 in the system.

There is also an optional serial port 710 on each general purpose processor 72 which communicates with serial devices 712 such as a keyboard or printer. There are two adjacent ports on each general purpose processor 72: one is an RS232 serial communications port 710 used to handle devices such as communications modems; and the other port is an abbreviated port 714 for handling and driving most common devices such as a typewriter controller, referred to generally as numeral 716.

At the lower end of the general purpose processor 72 board is an interprocessor communications interface (IPC) 722 which allows the processor 72 to communicate with other processors in the system, referred to generally as reference numeral 720.

A universal synchronous/asynchronous receiver/transmitter (USART) 723 is coupled to the 8085 of general purpose processor 72.

Additionally, on each processor board 72 is an optional timer 724 to allow the processor 72 to perform a time out function for disk operations during communications applications. Associated with an external device controller 78 is a direct memory access (DMA) channel to allow the external device controller 78 to read from and write into the memory 74 of external general purpose processors 72 via arbitration logic 726 without processor 72 intervention.

At any time there are several devices that may contend for the memory 74 on the general purpose processor 72. The memory of each processor 72 in the system is shared. That is, any processor 72 in the system can access the 32K bytes of memory 74 of any other processor 72. The several devices that may contend for the memory 74 include device controllers 78, which transfer data in and out of memory 74, the 8085 of the processor 72 itself, and other processors in the system 720, communicating via the internal bus also may access the 32K memory 74.

If several devices wanted access to this memory 74 at the same time, and several different devices were to gain control of the internal bus simultaneously, spurious results would occur. Accordingly, arbitration logic 726 is included to resolve memory contention.

Referring to FIG. 8, a preferred embodiment configuration consists of a keyboard B2 and a full page cathode ray tube CRT 84 is shown. The configuration has three general purpose processors (GPP0, GPP1 and GPP2) 86, 88 and 810. The general purpose processors are each identified by a 4-bit address. Therefore up to 16 processors can run in the system simultaneously. GPP0 86 is coupled to a disk controller 814. All of the input/output associated with the disk controller 812 is coupled to the GPP0 86. GPP1 88 is attached to the keyboard 82; GPP2 810 is attached to CRT boards 816 and 818 and moves text on the CRT screen. The two CRT boards 816 and 818 do not interface the back plane bus 820, but are connected through the device controller port 822 on GPP2 810. An 8085 microprocessor is associated with each of the general purpose processors 86, 88 and 810.

A printer 824 is connected to serial port 826. The key board 82 is also attached through a serial port 828 to GPP1 88. There are, therefore, two serial lines 826 and 828 that are connected to the back of the floor module. One video cable from the CRT2 card 818 is connected to the monitor 84. In this configuration, there are actually five processors in the system. An 8085 microprocessor resides on each of the processor boards 86, 88 and 810, and one resides on the controller for the printer 824 that mounts in the printer card cage. Another 8085 resides on the controller that mounts on the keyboard 82.

Another aspect of this system is that the machine, with the exception of 256 bytes of PROM 832 on the disk controller 814, is all programmable. That is, the program that is executed in each processor is loaded from the disk 812 at the beginning of a session. When power is applied to the system, a reset button on the front of the floor module is actuated. The processor 86 begins executing under the PROM 832 on the disk controller, and it pulls in the first sector on the disk 812. This data is loaded into GPP0's 86 memory 834, and GPP0 86 begins executing from the code which is loaded from the first sector. GPP1 88 and GPP2 810 are both in a reset condition, not running, during that time. The first sector that is loaded from the disk 814 during initialization contains a boot program. The boot operation allows the GPP0 86 to access more information from the disk 814 and load the operating system into its memory 834. At that point it begins transferring information from the disk 814 through the back plane 820 to GPP1 86 and GPP2 88 and loads their memory 836 and 838 with the program. Once this initialization process has occurred, the GPP0 86 releases the other two processors 88 and 810 to begin execution.

A character generator 840 is provided on CRT2 818 which also must be loaded during initialization. The characters visible on the CRT screen of the monitor 84 are soft-loaded characters. That means the character set can be changed, for example, from pica to proportional. The information in the character generator 840 is loaded from the disk 814 and is transferred to GPP2 810. When this processor 810 begins executing its program, the character set is transferred through CRT1 816 into the memory on CRT2 818. Characters are then ready for display on the CRT screen 84.

GENERAL PURPOSE PROCESSOR CONFIGURATION

To execute a particular instruction, the machine may run through several machine cycles. For a simple instruction it may run through only one cycle. A machine cycle consists of machine states called T states. The duration of each T state is one period of a Phi (o.sub.= I) clock. One instruction can be composed of between one and five machine cycles; each machine cycle can be composed of between three and six T states. While the clock is running, the processor runs through T1, T2, T3, T4 and T5 and then back to T1 again. The actual number of executed states depends upon which machine cycle of which instruction it is executing. A combined data bus and address bus are provided. During T1, the processor starts outputting address information. A latch is provided, as hereafter described, to demultiplex the address/data bus.

During T1 and T2 the processor generates address information. Because the address/data bus is time multiplexed, the processor generates address information during states T1 and T2. The signal address latch enable (ALE) is generated in T1. During T3 the actual data transfer takes place.

In the preferred embodiment 200 to 250 nanoseconds are required before data becomes available. By T3 the data should be stable on the bus. If the processor is executing a write instruction it is expected to be latched at T3. If it is executing an input instruction or a memory read it expects to receive data back during T3. This is where the actual memory transfer takes place. During T4, T5 or T6, the execution of the instructions performed.

Referring to FIG. 9, information is transferred between processors as shown. General purpose processors 92 and 94 are connected to each other through the back plane bus 96 for communication. Each processor has 32K bytes of memory 98 and 910 associated with it. The addressing space on the 8085 912, however, is 64K bytes of memory. For one processor 92 to communicate with another 94, data is passed between a particular processor 92 and the memory 910 on the second processor 94.

A master-slave relationship is initiated on the back plane 96. That is, the processor 92 of the transferring device becomes the master. The processor 914 on the slave 94 device is unaware that its memory 910 is being accessed. The device that is going to become the master 92 waits for the bus 96 to become inactive. The SOD output on the 8085 912 runs out to the flip flop 916 through logic that determines whether the bus 96 is busy. If it is busy, then the processor 92 waits for the bus to be released.

If it is not busy, then the processor 92 takes control of the bus 96. Each one of the processors 92 and 94 has a latch 918 associated with it, used to designate the address of the selected slave processor. The master processor executes code to load the latch 918 with a device address other than its own. It loads a four bit address into the latch 918 that corresponds to the device address of the desired slave processor 94. Then it activates the SOD line, monitoring the state of the SID line. When the SID line becomes active it indicates that the bus is ready. The master-slave relationship is then initiated. As soon as the signal called BUS BUSY 920 is inactive, the processor 92 enables the contents of the four bit latch 918 to be driven onto the bus 96. It then activates the bi-directional bus busy (BUS BUSY) line 920. A decoder 922 receives the four bit address from the back plane 96, and detects its address. It also sees that the bus is busy. It recognizes its address and establishes itself as a slave. The output of the decoder 922 generates the signal called SLAVE. This entire operation is transparent to the slave processor 914.

The processor 92 generates an address corresponding to the upper 32K bank 924 in its memory space. The lower 32K bank 98 in the memory space is assigned to its own memory. The upper 32K bank 924 of the memory is assigned to slave memory 910. Once the master-slave relationship is established, location 0 through 7FFF hex are the lower 32K on 92. Locations 8000 hex through FFFF hex are on slave processor 94. For the master processor 92 to write into location 0 on the slave processor's 94 memory, once it has established the master-slave relationship, the master processor 92 reads or writes to location 8000 as though location 8000 were in its own memory. In actuality, logic, not shown, indicates that the processor 92 is communicating with an address at or above location 8000, not on the master processor 92 board. A read or write signal is sent over the bus 96 which is coupled to to the slave board 94. This board 94 recognizes that it has been established as a slave, and sees a read or write signal coming from the bus 96, indicating that another processor is trying to communicate with its memory. If location 8000 has been loaded on the address bus 96, that is translated to the first location of slave processor 94 memory 910 which is location 0. The bus 96 is frozen in that state until the memory location is accessed.

The address bus 96 has 16 lines attached to it and the data bus 96 has an 8 lines attached to it. There is also a 4 bit address bus 96 which has another four lines attached to it. Consequently there are 20 bits of address space. The maximum amount of addressable memory within the system is 2.sup.20.

When the master processor executes a memory read to location 8000, the BUS READ line on bus 96 is activated with other control signals, and the address is loaded onto the address bus 96. The signal is sent to board 94 which recognizes that it is the active slave in the system. It detects the READ line which indicates that there is a processor 92 trying to perform a read. It converts the address from location 8000 to location 0. There is an attempt made to access that location in memory. Memory is capable of being shared by several different devices on a card-shared by the 8085 914, shared by the device controller 926, and also shared by the interprocessor communications (IPC) bus 928. Also, because the memory on the card is dynamic, it must be refreshed periodically. The device controller 926, the 8085 914, refresh logic 930, and IPC 928 may be contending for memory. They may not all be contending at once but if two of them make an attempt to try to access memory at the same time, there has to be a way of resolving the contention. For that purpose, arbitration logic 932 is provided.

The IPC 928 has lowest priority in contention arbitration. If any other device is using memory 910 during the current memory cycle, the IPC 928 is not granted access to it. It waits until all other devices are not attempting memory access. The master processor 912 enters a wait state. The master processor 912 makes a memory access request into memory 910 and the control signal is sent back on this processor 912 to lower the READY line until it can gain access to that location 910. Once all the other devices are off the bus the IPC 928 grants the master processor 912 access and the address that waits on the IPC bus is passed to memory 910. Data from the slave processor's memory 910 is passed onto the IPC bus and the ready line on the master processor 912 is released.

An IPC transfer usually takes longer than a regular transfer from its own memory 98. It usually takes two or more T-states depending upon the processing occurring in the slave processor 94. All of this happens invisibly to the slave processor due to the contention resolver 932 and due to the fact that memory is being interleaved among the device controller 926, the 8085 914, the refresh logic 930, and the IPC 928. The slave processor 914 is unaware that a transfer has taken place, and discovers it only if it accesses that location 910, and detects that it is different than it was before.

A flip flop 934 on the disk controller 936 controls the master reset line in the IPC bus 96. When the floor module is initialized, the disk controller 936 generates two signals: a power on signal to the processor 92 to initialize its processor 912 and a signal to the master reset flip-flop 934 on the disk controller 936. When the boot operation is finished, then the master processor 912 executes an output instruction that resets the master reset flip flop 934 to release all of the rest of the processors.

The interprocessor communications bus 96 has 16 address lines, eight data lines, four device address lines, bus write, bus read and the master reset for the non-disk processors running in the system. There is also a trap line and a restart 5.5 line which allows a master processor to signal a slave processor to indicate when a transfer is completed. These lines operate in a manner similar to the above described memory transfer operations. A particular processor establishes itself as master on the bus 96. It selects a slave by performing an output to latch 918. It then sets additional bits to control the trap and restart 5.5 lines in the address bus 96. The slave processor 94 decodes its address lines via the decoder 922. If either the trap or the restart 5.5 lines becomes active on the back plane 96 then it is routed to the slave 8085 914 restart 5.5 and trap inputs. By using these lines, the master processor 92 can request attention from the slave processor 94.

Referring now to FIG. 10, showing the internal portions of a general purpose processor, an 8085 102 communicates with a block of memory 104. An address bus 106 is connected from the 8085 102 to a latch 108. The 8085 102 generates an address to memory 104 and then either reads or writes to memory on the data bus. The peripheral device 1012 could be a DMA controller, a USART, or a counter timer chip. The 8085 102 communicates with such a peripheral device over data bus 106.

The processor 102 usually communicates with a peripheral device 1012 such as a floppy disc controller by generating an address on the address bus 1010. That address is decoded by address decoder 1014 using a predetermined decoding scheme. The output of the decoder 1014 is coupled to the chip select in the peripheral device 1012. When the processor 102 is communicating with the peripheral device 1012 it executes either an input or output instruction. The address bus 1010 has eight lines for input/output operations. That allows up to 256 devices to communicate with the processor 102. The processor 102 executes either a input or output instruction. There is an argument associated with that instruction, from 0 to 256 (FF hex) to indicate which device the processor 102 is communicating with. All of the data movement is handled under the accumulator in the 8085 102. To perform an output with a particular device 1012 the accumulator of 8085 102 is loaded and then an output instruction is generated. The data that is in the accumulator is transferred across the data bus 106 to the peripheral device 1012.

An I/O memory signal is generated by the 8085 102. It is applied to the address decoder 1014 and used to differentiate between access to memory 104 and access to peripheral devices 1012. Read and write signals, not shown, are also decoded to indicate whether the operation is a read or a write.

GENERAL PURPOSE PROCESSOR SCHEMATIC CIRCUIT DIAGRAM OPERATION

Referring to FIG. 11, the general purpose processor includes a crystal oscillator 1131. It operates at 15.2064 megahertz. The circuit below it, including a flip flop 1133, is configured as a divide by three circuit. The output signal from the oscillator 1131 is called high frequency clock, HFCLK. The output of the divide by three circuit runs through buffers 11241 and 11242 and is used to drive the X1 and X2 inputs of the processor 1134. The oscillator 1131 operates at 15.2064 MHz to generate the 5.0688 MHz baud rate clock sent to the USART 1162. The USART 1162 has internal counter circuitry for achieving a particular transmission rate, e.g., 9600 baud or 4800 baud.

An output signal called .0.1OUT is developed at pin 37 of the processor 1134. That is the synchronizing signal for all operations in the 8085 1134. The AD bus is coupled to the processor 1134 on pins 12 through 19. Those pins AD0 through AD7 are coupled to a number of devices. One of the devices to which they are coupled is an octal latch 1155, applied to the D input thereof 1155. The lower seven bits of the address bus, are attached by the latch 1155. An address latch enable (ALE) signal at pin 30 is applied to the gate input on the latch 1155.

The octal latch 1155 also has a tri-state output, which provides a means for removing the latch from the output address bus. The GATE input for this latch 155 is coupled to a signal called CPU acknowledge (CPUACK). CPU acknowledge indicates that the processor 8085 1134 is on the address bus. Whenever CPU acknowledge is active, both sets of drivers, the 1155 and the 1175, become active.

The general purpose processor board is provided with a 50-pin device controller interface 11331. The internal address bus is sent directly off the board without being buffered. The data bus above the AD bus is connected to device 1145. This part 1145 latches data from the data bus. The latch output is applied to the AD pins on the processor 1134 only when necessary, since a conflict with the time multiplexed address lines on the processor may occur unless the data transfer is synchronized.

The AD bus on the processor 1134 is also connected to a set of drivers 1135. When the processor 1135 attempts a write operation or an output operation, it turns on the set of drivers 1135 and the data on the AD bus is passed through the drivers 1135 to the data bus. The data bus AD0 through AD7 is also coupled to the top of the board.

Using four devices, 1145, 1135, 1155 and 1175, the processor 1134 is interfaced to the rest of the logic on the GPP circuit board. These devices 1145, 1135, 1155 and 1175 serve to isolate the processor 1134 from the remaining circuitry.

A 28-pin USART 1162 is provided to allow the processor 1134 to communicate through two serial ports, J2 and J4. Port J2 is an RS232 interface. Besides having the essential signals--transmit data, receive data, clear to send, request to send--it also provides modem control signals, such as carrier detect DCD, data set ready DSR, transmit clock both in and out TXC IN, TXC OUT, and receive clock RXC. These signals are used for synchronous operations in the synchronous mode. In that case the modem provides clocks to the USART 1162 and serial data is shifted out of or in synchronism with the clocks.

Connector J4 is a partial RS232 interface to connect the GPP to a keyboard or to a printer. Connector J4 has 10 pins: transmit data, receive data, request to send, clear to send, data set ready, terminal ready, reset line coupled to a controller such as a typewriter controller or a printer controller, and signal ground.

Also provided is a line called PC, connector J4, pin 6, which is a power control. It is coupled to a +12 volt supply through a 680 ohm resistor. It turns on an external controller, whether the typewriter controller, the printer controller or any other like peripheral controllers. That signal turns on the state switch associated with each one of those devices.

A counter 1132 includes three 16-bit counters that can be made to function in many modes. It is used here as a time out device. When the processor 1134 handles communications protocol, for example, there is often a requirement to be able to expect a response from a transmitting unit within a certain time. If that response does not occur, something may not be operating properly. The timer 1132 is used to time out and give an indication that the system is hung in a particular operation.

Only a portion of this timer is used. The output 0 (pin 10 of 1132) is connected to the processor 1134 and is connected directly to pin 8, restart 6.5. Most of the time when the processor 1134 is processing, restart 6.5 is disabled internally. Otherwise it would be giving a series of continuous interrupts.

Both the USART 1162 and the timer 1132 are connected in parallel to the data bus. That is the method by which the processor 1134 writes into or reads from the internal registers on the USART 1162 and the timer 1132.

On the USART 1162, two signals are provided from pins 15 and 14: transmit ready (TXRDY) and receive ready (RXRDY), respectively. Pins 14 and 15 are connected to each other. USART 1162 is an MOS device, and it is possible to connect pins together to obtain an OR function. They are ORed together and the resultant signal is applied to an inverter 1121 from which the signal is applied to the restart 7.5 input pin 7 on the processor 1134. Restart 6.5 pin 8 is dedicated to the counter 1132; restart 7.5 pin 7 is dedicated to the USART 1162.

RS232 drivers and receivers are referred to generally by reference numeral 1135. The 11351 devices are drivers and the 11352 devices are receivers. They translate the TTL levels from the USART 1162 into RS232 levels. The TTL levels, for example, range from 0 to 5 volts. The RS232 levels are both positive and negative. In this case, the drivers 11351 are tied to plus and minus 12 volts. Consequently the outputs of the drivers 11351 range between plus and minus 12, at one extreme or the other.

Connector J2 has further pins for handling signals used with a range of modem types. The secondary request to send (SRTS) and secondary carrier detect (SCD) signals are of the type employed in a Model 202 type modem which transmits two carriers simultaneously. One carrier is a very low transmission rate carrier used to signal line turn-around. The ring indicator (RI) signal on connector J2, pin 18 is provided for a ring indicator signal. This signal is active every time the line rings. It allows the processor 1134 to establish conditions so that the modem is enabled to answer. Some of these signals, for example clear to send (CTS), are applied through RS232 receivers 11352 to the USART 1162 and also to a driver 1192 which drives data bus line zero (DB0). Similarly secondary carrier detect (SCD) and ring indicator (RI) signals are both applied through RS232 receivers 11101 and into tri-state drivers 11921, driving data bus lines DB1 and DB2. The processor 1134 can interrogate the state of the three RS232 lines CTS pin 9, SCD pin 23 and RI pin 18.

Referring now to the operation of serial communications, USART 1162 converts parallel data from the processor 1134 to a serial bit stream, to pass over the serial communications line. The data is transmitted on transmit data (TXD) pin 3 and data returns over the receiving line (RXD) pin 5. The data is converted from serial to parallel format for the data bus. Several control signals are used to facilitate this operation. One pair is request to send (RTS) pin 7 and clear to send (CTS) pin 9. When a transmitter is ready to make a transmission, the processor 1134 raises the request to send (RTS) signal pin 7. If connected to a modem, the modem signals when it is ready on CTS pin 9 and allows the processor 1134 to transmit. The data carrier detect (DCD) signal pin 15 is applied to an RS232 receiver 11352 and is then applied to the USART 1162. That signal is used for the request side. Unless that signal is active, the USART 1162 can not receive data.

A power on clear (POC) signal connector J1 pin 71 comes from the back plane through a receiver 11103 and is applied to an inverter 111031, providing a reset (IRST) signal. This signal initializes all logic on the printed circuit board, including a latch 1161. Application of the IRST signal during a reset operation forces the Q1 output of latch 1161 (pin 7) to go false. The effect is as if a carrier were present. The Q1 output pin 7 is connected to device 11113. If the input is false, the output is also false and the carrier detect on the USART 1162 (pin 16) is active. To use data carrier detect DCD to load the latch 1161, an input instruction must be executed to the latch 1161.

Referring now to FIG. 12, signals DB0 through DB7 represent the internal data bus. These signals are applied to an octal bi-directional transceiver 1286. The transceiver includes a set of drivers 1286 that operate one way or the other to provide isolation for the 16 memory devices generally referred to as reference numeral 1231. These memory devices 1231 are 16K byte dynamic memories, built in a 16K by 1 shape. One bank of them 12311 is used to generate one 16K by 8 segment of the memory and the other bank 12312 is used to generate a second 16K by 8 segment.

The data bus is applied to the transceiver 1286 into the memory 1231 allowing data to pass in either direction through the transceiver 1286.

Referring again to FIG. 11, a 4-bit synchronous counter 11163 and flip flop 11153 are provided. These parts 11163 and 11153 are part of a refresh counter to the circuit board. The input to the refresh counter is coupled to the output of the synchronizer 11133. Signal .0.1SYNC operates at the same rate as signal .0.1OUT on pin 37 of the processor 1134. The .0.1SYNC signal is applied to the counter 11163 and divides it by 16. The ripple carry output from the counter 11163 is applied to the clock input of the flip flop 11153 which divides it by two again. As a result, the signal is divided by 32. Then the output of the flip flop 11153 is applied to flop flip 11123. The designation for the refresh clock signal is RFCK. When the refresh clock signal becomes active, it makes a bid for memory access. That is, the refresh counter 11163 and 11153 counts and periodically--32 times less frequently than the clock rate--generates a signal initiating a request for a refresh cycle. When the memory 1231 becomes available, the refresh cycle occurs. The refresh circuit must be active in order to keep the memory alive.

Referring now to contention resolving circuitry shown generally at reference numeral 1137, the memory 1231 is interleaved. That is, memory cycles are shared by four devices: the device controller, the refresh circuitry, the 8085 microprocessor 1134, and the interprocessor communications which is described in detail hereafter. All of those devices contend for the memory 1231. The configuration is such that utilization of the memory bandwidth is maximized. Since the processor 1134 operates at 2.5 megahertz, .0.1OUT at pin 37, that is also the effective bandwidth of the memory. One memory cycle (one processor clock--.0.1OUT), can be performed every 400 nanoseconds. The effective bandwidth of memory is therefore 1/400 nanoseconds or 2.5 MHz.

If the processor is connected directly to the memory, however, it is inefficiently utilized. Logic circuitry for use in contention resolving 1137 allows other devices to access the memory 1231 when the processor 1134 does not require access to it. It operates in a manner which is transparent to the processor 1134.

A set of flops 111531, 11123 and 111231 is provided. A CPU request flip flop is designated 111531. The refresh request flip flop is designated 11123. The IPC request flip flop is designated 111231.

The outputs of the flip flops 11123, 111531 and 111231 are connected to a priority encoder or priority resolver 11122. The input, D0, D1, D2, D3 or D4, to the priority resolver 11122 with the highest priority is selected. In this case, D0 has the highest priority. If that signal is active, the output Y0, not shown, becomes active. D1 is coupled to the device controller interface, connector J3, energized by a signal called DMA request (DMARQ) at pin 2 of connector J3. It is applied to a receiver 1139 directly into the D1 input of the priority resolver 11122. If that is true and D0 is false, that is, if the device controller connected to J3 requests a memory cycle and the processor 1134 does not, then the device controller gains priority and has access to the memory 1231. If D0 and D1 are false, the refresh circuitry connected to pin 13 (D2) gains access to the memory 1231. If the three inputs (D0, D1 and D2) are false, the IPC D3 gains control of the memory 1231. If none of these four input signals (D0 through D3) is active, signal Y4 becomes active. Signal Y4 performs a memory disable operation.

The output of the priority resolver 11122 is applied to a flip flop 11112. Flip flop 11112 is a device having six D flip flops connected internally, all with a common clock. The signals from the priority resolver 11122 are latched into the flip flop 11112 to determine which device has access to the memory 1231 for the next memory cycle. The memory cycle is defined by the active edge of the .0.1SYNC clock signal. The .0.1SYNC signal is applied to 11112.

In operation, a particular device makes a request through the set of request flip flops 111531, 11123 and 111231. In the case of the device controller connector J3, the controller runs directly into terminal D1, pin 12, as there is a flip flop on the device controller. Then the outputs of those flip flops 111531, 11123 and 111231, as well as the device controller drive the priority resolver 11122. The priority resolver 11122 determines which device has the highest priority of those making the request for the next cycle. That information is latched into the flip flop 11112, which determines which one device gains access to the memory 1231.

The signals from the flip flop 11112 are the memory acknowlege signals. The uppermost signal is called CPU acknowledge (CPUACK) pin 5. The next signal pin 12 of flip flop 11112 is connected to pin 23 connector J3 and is called DMA acknowledge (DMAACK). It has second priority. The third signal is called refresh acknowledge (RFACK) pin 10 and has third priority. The fourth (lowermost) signal is called IPC acknowledge (IPCACK), pin 7, having lowest priority.

The CPUACK signal energizes the address bus drivers 1175, 1155 and 1135 on the output of the processor 1134. When the processor 1134 requests the bus, CPUACK enables these drivers 1175, 1155 and 1135 and the processor 1134 drives the memory 1231, or the I/O device. A signal called address latch enable (ALE) pin 30 of 1134 latches the lower eight bits of the address bus. It also drives the CPU request flip flop 111531. By the time the processor 1134 gains access to the bus (that is, when a CPUACK signal is received by pin 5 of flip flop 11112), the processor 1134 expects to be on the bus. This is all done in synchronism with the .0.1SYNC signal.

The CPU request flip flop 111531 is reset when the CPU Ready (CPURDY) signal tied to the K input pin 12 of flip flop 111531 is active. CPURDY is connected to the ready (RDY) line pin 35 on the processor 1134. The ready line, when deactivated, places the processor 1134 in a wait state. CPURDY is derived from a number of different sources. It is connected to device 1151 used as an OR gate with inverted inputs from three different sources. One of the sources is the ready line pin 1 on connector J3 coupled to the device controller. The second source is a signal called IPC ready (IPCRDY) discussed hereafter. The third signal, I/O ready (IORDY), is coupled to pin 2 of flip flop 11112; it is not associated with priority resolution. If any of the signals IORDY, IPCRDY or RDY from the device controller becomes active, it can place the processor 1134 in the wait state. It is only when all of them are inactive that the CPURDY signal occurs. If the processor 1134 executes an I/O instruction or if an IPC transfer is pending (that is, the processor 1134 is the master and is attempting to communicate with the slave), then IPCRDY is false until the transfer has taken place. That lowers the RDY signal and freezes the processor 1134.

The device controller may be operated to suspend the processor 1134 for some reason. For example, the disk controller may have a very slow I/O device coupled to it. Whenever the processor 1134 tries to execute an input or output instruction to such a device controller, it lowers the ready line at pin 1 of connector J3.

The RDY signal is propogated through device 1151 and is applied to pin 35 of the processor 1134. The CPURDY signal is not generated and the CPURQ signal from flip flop 111531 remains active until such device controller is ready to communicate with the processor 1134.

The DMA device has a higher priority than refresh because the processor card is designed for use with the CRT controller. Since the CRT controller has a very wide bandwidth, the DMA device also requires a wide memory bandwidth. To display many characters on the screen requires a great deal of accesses to the processor's memory 1231. CRT controllers require enough bandwidth to preclude their being relegated to a lower priority than refresh. The CRT controller is configured so as to not monopolize its memory bandwidth. The CRT's controller's DMA request line is active for alternate memory cycles to allow other devices access to the memory. Otherwise, refresh would be compromised.

A six-stage shift register 11133, used in conjunction with device 11164 and associated driving logic, forms synchronizing circuitry. It performs the function of synchronizing the processor clock output .0.1OUT at pin 37 of processor 1134 with HF clock (HFCLK), a 15 megahertz clock. One of the output signals from the synchronizer 11133 is .0.1SYNC. That signal is used to drive the rest of the logic on the board. All data transfers are synchronized to .0.1SYNC. The synchronizer 11133 generates waveforms necessary for the refresh logic. The dynamic memory units 1231 require row address select memory (RASTM) and column address select memory (CASTM) signals in order to allow them to multiplex the address input to each memory unit.

Each memory cycle is divided into six parts by the six-stage shift register synchronizer 11133. With rspect to synchronizer 11133, the Q1 output is tied to the D2 input; the Q2 output is tied to the D3 input; the Q3 output is tied to the D4 input; and the Q4 output is tied to the D5 input. A signal is thus propogated through the synchronizer 11133. The synchronizer circuitry may be tapped in six different places.

The signal .0.1OUT of the processor 1134 is applied to an inverter 11114. The signal is then applied to the clock input pin 13 of device 11164 and it clocks that device 11164. Then the output of device 11164 is applied to the first stage of the synchronizer 11133. That signal is propogated through the six stages of the synchronizer 11133. It is then applid to M3, pin 11 of the synchronizer 11133. The M3 signal is fed back to the clear input pin 14 on device 11164 via devices 11134 and 11162. Accordingly, the signal from the synchronizer 11133 is a square wave. It is fundamentally important that a square wave is generated here. The 8085 microprocessor 1134 does not generate a square wave of this type with the clock out signal. Its wave form may have a variable duty cycle.

Several of the stages 11143 and 111431 of the synchronizer 11133 are ORed together to generate rast time (RASTM) and cast time (CASTM) signals. These are synchronizing signals to strobe into memory 1231 row address and column address. Logic circuitry shown generally as reference numeral 1141 consists of gates and flip flops that generate a signal called memory I/O (M/IO, IO/M) bar, read (RD) and write (WR). These three signals are used as control signals to peripheral devices such as 1132 and 1162 and to peripheral devices coupled to the device controller via connector J3, to the memory 1231, and to any other peripheral device on the GPP board. These three signals are synchronized to .0.1SYNC and with respect to the processor ready (PRD) and processor write (PWR) signals. These signals are used to gate data to or from the data bus during a read or write operation.

The IOPLS signal from pin 6 of device 11164 is used to synchronize the I/O operations with the processor 1134. It is routed through an address decoder 11124 to the USART 1162 and performs a synchronizing operation.

The drivers for memory I/O, read and write, generally referred to as reference numeral 1122, are tri-state drivers. These tri-state drivers 1122 are gated by a CPU acknowledge (CPUACK) signal. Accordingly, these tri-state drivers are on the bus only when the CPU 1134 is on the bus. There are other devices that can access memory 1231. The tri-state control bus is connected to drivers 1122. If the device controller, for example a floppy disk controller coupled to connector J3, attempts to access memory 1231, it does so by utilizing its DMA controller without using the intervention of the processor 1134. It controls the read, write and memory I/O lines, connector J3 to pins 3, 4 and 34, as they are applied to the memory 1231.

Similarly, the IPC interface can also drive these lines. Another processor has access to the read, write, and memory I/O signals so that it can access the memory 1231 as well. The tri-state bus has several different sources. Three 1K pull-up resistors 121810, 121811 and 12189 are connected to the tri-state bus to prevent drift when the bus is not being used.

Devices 1151, 11152 and half of 11124 are provided. The device at 11124 is a 2-to-4 demultiplexer or decoder. These devices, in conjunction with gate 111521, perform a decoding function. They decode I/O addresses for the I/O devices on the board. For example, the output of device 1151 is active only when its four inputs (ADD12, ADD13, ADD14 and ADD15) are active. Those are the four most significant bits of the address. The next two significant bits of the address ADD10 and ADD11 are routed through the 2-to-4 demultiplexer 11124. If the A and B inputs on the demultiplexer 11124 are zeroes, the input to gate 11152 is zero. The output YO pin 4 of demultiplexer 11124 becomes active. YO generates a chip select zero (CS0) signal. This circuitry provides a means of selecting output devices coupled thereto via signals CS0 through CS3.

Referring again to FIG. 12, the memory is shown at reference numeral 1231. A refresh controller 1284 is coupled to the memory 1231. It has a dual function: it multiplexes the address lines to the memory 1231, and it performs a refresh to the memory 1231 which is volatile and must be refreshed periodically to prevent loss of data.

The refresh controller 1284 has a counter therein. Every time a refresh request is made via the refresh acknowledge (RFACK) signal, the source for which resides on the other GPP circuit board, the refresh controller 1284 gates the output of its seven bit counter on the address lines. It performs the refresh cycle with that particular address. At the end of the refresh cycle it increments the counter in the refresh controller 1284. Accordingly, if a refresh request signal is input to the refresh controller 1284, its counter is stepped through its range. Accesses to the memory through the range of the counter are performed. The other function that the refresh controller 1284 performs is to multiplex the address lines to accommodate the number of memory input lines. The memory devices 1231 are 16K by 1. In order to address one bit of 16,384 possible bits, 14 lines are required.

The left side of the refresh controller 1284 is tied to the address bus, ADD0 through ADD13. The right side of the refresh controller 1284 has seven output address lines, A0 through A6. When a memory access is initiated, an address is input from the left of the refresh controller 1284. At the beginning of the memory cycle, half of that address is available to the memory 1231. In the middle of the cycle, a row address strobe (RASD) signal pin 3 of the refresh controller 1284 becomes active and changes state. It applies the other half of the address to the memory 1231. Timing is such that the first half of the address is strobed into the refresh controller 1284 by the RASD signal. The other half of the address is then available to be applied to the memory 1231.

A set of decoding logic is shown generally at reference numeral 1233. The CASTM and RASTM signals, derived from the synchronizer 11133 (FIG. 11) are input to this decoding logic 1233. These two synchronism clocks strobe address information into the memory 1231. Address lines ADD14 and ADD15 are applied to a 2-to-4 decoder 12124. When the gate input in the decoder 12124 is active, a memory enable (DMEM) signal on pin 15 of the decoder 12124 is generated. When DMEM is active it indicates that a device is attempting to access the memory 1231. The address corresponding to ADD14 and ADD15 determines whether RAS1 or RAS2 from the decoder 12124 becomes active. Those signals RAS1 and RAS2 are used to drive either one 16K byte bank 12311 of the memory 1231 or the other bank 12312.

The RAS1 and RAS2 signals are combined with a refresh acknowledge (RFACK) signal through a set of OR gates 12134 and 121341. The RAS signals are used to refresh both banks 12311 and 12312 of memory 1231 simultaneously as no data is being transferred.

For a memory transfer, logic shown at reference numeral 1233 determines whether the transfer is to the lower 16K bytes of memory 1231 or the upper 16K bytes of memory 1231. It is gated to develop RAS1 and RAS2 signals. The RAS1 and RAS2 signals are ORed at gate 12154, the output of which is used to perform a multiplexing operation with the refresh controller 1284. The active signals into the memory 1231 are RAS1 and RAS2, column address strobe (CAS), and write enable (WE). Write enable (WE) is derived from the tri-state control bus on the GPP board. These four signals are required to drive the memory. AND gates shown generally at 12144 drive all four of these lines RAS1, RAS2, CAS and WE.

One of the first events that occurs during interprocessor communications is that the processor drives an octal D flip flop or latch register 1236 to decide which slave processor can communicate with the system. A device address must be loaded into the latch register 1236 before the bus is acquired. The latch register 1236 has a tri-state output.

The latch register 1236 is coupled to the data bus DB0 through DB6 and to connector J1. The latch register 1236 is part of the interface to the back plane. To the left of the latch register 1236 is a gate input on pin 11 and an output or input on pin 1. The gate signal is derived from a write sync (WRSYNC) signal and a chip select zero (CS0) signal. WRSYNC becomes active when the processor 1134 executes either an output or a memory write instruction.

To load information into the latch register 1236, an output instruction is executed with an address that corresponds to CS0. A signal from latch register 1236 is labeled bus address 15 (BADD15) through bus address 19 (BADD19). The fifth line is an expansion bit used for selecting either the upper or the lower 32K bytes of memory on a slave processor. Since a slave processor does not have 64K of memory, the last bit may be ignored.

The other three lines are bus trap (BTRAP), bus restart 5.5 (BRST 5.5), and bus slave clear (BSLCLR). These three control lines can be used either to reset the slave processor (BSLCLR) or to generate a trap (BTRAP) or a restart 5.5 (BRST 5.5) on the slave processor.

A slave address decoder (comparator) 1225 compares the input lines on the left A0 through A3 with the lines on the right B0 through B3. When these lines are identical, an A=B (SLAVE) signal on pin 6 of the decoder 1225 is generated.

The B signal lines pins 1, 14, 11 and 9 are pulled up to the set resistor pack 12191163 connected to jumpers 1235. The jumpers 1235 provide four bits to configure the circuit board to add a particular slave device address when connected to the system.

The input lines on the A side of the decoder 1225 are connected to bus address 16 through 19 (BADD16 through BADD19) signals. They are connected to connector J1.

A tri-state driver 1266 gates the inputs DB0 through DB7 via a resistor pack 12191164 which serves as pull up resistors, to jumper 1237. Device 1237 is a cluster of eight connectors. This set of jumpers 1237 is used for configuration information on the processor 1134. There are times when the software must detect the hardware configuration. If a special configuration is established in this system, this is one way for the software to be aware of it.

Jumpers 1235 are the slave address jumpers, consisting of four jumpers (connectors), providing a possibility of 16 different addresses (processors) coupled to the system simultaneously. This set of jumpers 1237 is accessed through driver 1266. When the processor executes an input instruction to chip select zero address, driver 1266 is activated and information contained in the jumper configuration 1237 is transferred to the data bus DB0 through DB7. If the processor performs an output to address F0, it loads the latch register 1236; if it performs an input to address F0 it reads the configuration of jumpers 1237 by driver 1266.

A pair of flip flops at locations 1253 and 12531 is provided to generate the restart 5.5 and trap signals to the processor 1134. The input to one flip flop 1253 is coupled to the bus restart 5.5 line and is applied through an AND gate 1243. This input signal is ANDed with the SLAVE signal, which drives the clock input on pin 13 of the flip flop 1253. If a device has been established as a slave and an active edge is present on the bus restart 5.5 pin 55 connector J1, then that condition is latched into the flip flop 1253, and is applied to the restart 5.5 line on the 8085 microprocessor 1134. That indicates to the processor 1134 that another unit is attempting to communicate. A similar circuit 12531 is used for the trap interrupt. It is driven directly by the bus trap signal pin 5, connector J1. It also uses the SLAVE signal via AND gate 12431. It derives a signal called TRAP that is applied to the 8085 processor 1134.

Two conditions can clear the interrupt. One is an I rest (IRST) signal applied to flip flop 1253 via OR gate 1263, and to flip flop 12531 via OR gate 12631. If that becomes active, both flip flops 1253 and 12531 are reset. When the processor 1134 is initialized, the flip flops 1253 and 12531 must not be in a set state. This is due to the fact that when the processor 1134 begins to execute a program, if a trap condition exists, the processor 1134 immediately accesses the interrupt vector. The other two signals that clear either of the flip flops 1253 and 12531 are CLEAR 5.5 1253 and CLEAR TRAP 12531. They are coupled to the outputs of a pair of gates 1173 and 11731 that are driven by data bus 6 (DB6), and data bus 7 (DB7), and a write to chip select one (CS1), 1143 and 1133. if an output instruction is sent to the register corresponding to chip select one via devices 1143 and 1133 and if the appropriate bits were set on the data bus, either of the two flip flops 1253 and 12531 is cleared.

In operation, an external device establishes this processor 1134 as a slave, and then executes a bus trap by activating the bus trap line pin 5 is connected J1. The external device then deactivates it. That sets trap flip flop 12531, the output of which is tied to the trap input of the processor 1134. The processor 1134 executes an interrupt vector and then a service routine program. In the service routine, the processor 1134 generates an output instruction, clear trap (CLRTRAP), which is applied to the clear input, pin 15 of trap flip flop 12531 via device 12631. That signal (CLRTRAP) resets the trap flip flop 12531.

The processor 1134 becomes the bus master as the first step in interprocessor communications. This is accomplished by setting the SOD output pin 4 on the processor 1134. The SOD output is a signal called master request (MASTER RQ). The processor 1134 makes a bid for the bus by generating this signal. When the bus is acquired, a master (MASTER) signal is generated and is applied to the processor 1134 over the SID input line pin 5 of the processor 1134. This indicates that the processor 1134 has acquired the bus.

The master request (MASTER RQ) signal is applied to the J input of flip flop 12142. An inverted MASTER RQ signal is applied to the flip flop 12142 via an inverter 12141. Accordingly, the master request signal is latched into the flip flop 12142. The flip flop 12142 is clocked by a signal called bus clock (BCK) connected to pin 21 of connector J1. The bus clock signal is derived on the disk controller, and is applied to the back plane so all of the devices in the system attempting to access the bus are synchronized with that clock. The Q output of the flip flop 12142 is called master request synchronize (MRRQ SYNC). It is applied to an AND gate 12132. This is accomplished with a signal called bus priority in (BPRIN) on the back plane, connector J1.

One signal does not run the length of the back plane connector J1. The bus priority in (BPRIN) signal is daisy chained and passed from one pin of the GPP to another GPP connected to the back plane. This is a priority chain. The priority signal is applied from bus priority in (BPRIN) pin 14 of connector J1 and is output on bus priority out (BPROUT) pin 64 of connector J1. The source for the priority signal is the disk controller. Consequently, the disk controller must be at one end of the back plane positioned for highest priority. It need not be located in the first board slot, but it must be the first circuit board in a series of boards.

The bus priority in (BPRIN) signal is ANDed in gate 12132 with a master request sync (MRRQ SYNC) signal and a bus busy (BBSY) signal. Bus busy (BBSY) is applied from edge connector J1 pin 73, through a pair of inverters 12103 and 121031. When three conditions are met--bus priority, the bus is not busy, and master request, then the output of gate 12132 becomes active and the signal drives the J input of flip flop 121421.

The clock input on flip flop 121421 is the same as the clock input for the first flip flop 12142. They are both synchronized with respect to bus clock (BCK). The request is transferred to the second flip flop 121421 only when the bus is not busy and when the GPP has priority. If not bus request is pending, the bus priority in (BPRIN) signal is propogated as a bus priority out (BPROUT) signal via device 12113. If this GPP 1134 is not presently attempting to become a master, the bus priority in (BPRIN) signal is applied to the next GPP connected to the back plane. If it is trying to become a master, the bus priority in (BPRIN) signal is not applied to device 12113. This priority scheme is used to prevent contention for bus acquisition.

It is remotely possible that in some particular bus clock period two processors will attempt to access the bus simultaneously. The aforementioned priority scheme prevents them from doing that. The boards that are closer to the disk controller are higher on the priority chain. The one closest to the disk controller is the one that gains access to the bus.

The second flip flop 121421 is the master flip flop. When it is set, it indicates that the processor 1134 is now a master. The master (MASTER) signal is applied to the SID input of processor 1134. The processor 1134 now knows that it has been granted access to the bus. The output signal of the master flip flop 121421 is used to activate a tri-state driver 1293 which activates the bus busy (BBSY) line. Once this processor 1134 becomes a master, it activates the bus busy (BBSY) line and no other processor in the system can have access to the bus. The master device does not relinquish control of the bus until the master request (MRRQ) line becomes inactive (that is, the SOD output from pin 4 of the processor 1134 is deactivated). In this way, one and only one processor captures the bus and does not relinquish it until it has completed its series of transfers.

The master (MASTER) signal is applied to the transmit receive input of transceivers 1265 and 1285. These transceivers 1265 and 1285 either drive or receive information between the internal address bus (ADD) on the processor 1134 and the address bus (BADD) on the back plane. In the case where this processor 1134 has become a master, the master (MASTER) signal becomes active and the transceivers 1265 and 1285 drive the address bus on the back plane. The address on the address bus (ADD) is passed to the back plane (BADD).

Devices 1246 and 1256 are the interface between the internal data bus (DB) on the general purpose processor 1134 and the data bus on the back plane (BDB). In the case where the processor 1134 has become a master and reads data from a slave, the data is actually transferred across the data bus (BDB) on the back plane and is applied through device 1246, then on to the data bus (DB), and into the processor 1134. In the case where the processor 1134 has become a master and writes data into the slave's memory, the information is generated by the processor 1134 along the internal data bus (DB) and is latched into device (latch) 1256. This information remains on the data bus (BDB) until it can be transferred to the slave's memory. This transfer may require some time because the slave's memory may be occupied with other operations at any given time. The aforementioned procedure is used to transfer data to and from the back plane.

A gate 12111 is provided to AND several signals: CPUACK, MASTER, address bus 15 (A15), and a processor memory I/O (PM/IO) bar. If the processor is performing a memory cycle, the PM/IO bar signal is active; if the processor is the master, MASTER is true; if the processor is in the process of performing a transfer, CPUACK is true; and if the processor is in the process of performing a transfer with the most significant address bit set (that is, to access address 8,000 hex or above), A15 is true. If all four of the above conditions prevail, a signal called master operation (MOP) is active. The MOP signal is inverted at inverter 1212, and gated with processor read (PRD) at gate 1283, or processor write (PWR) at gate 12831 to derive the bus read (BRD) and bus write (BWR) signals pin 23 and pin 74 on connector J1 respectively. If the processor 1134 is performing a read operation from slave memory, the bus read (BRD) signal becomes active; if the processor 1134 is performing a write operation to slave memory, the bus write (BWR) signal becomes active.

The MOP signal is ORed with IPCACK via OR gate 12151 and is then ANDed with .0.1SYNC at AND gate 12134 to provide a strobe to the gate input on device 1256. There are two reasons that this device 1256 is used. If the GPP 1134 is a master and a write operation to the slave memory is to be performed, the data is transferred into latch 1256 so that it can be transferred to the slave's memory. The other reason that device 1256 is used is if another master in the system selects this GPP 1134 as the slave and the other master is performing a read from this GPP's 1134 memory 1231.

The master GPP generates an IPC request, a bus read (BRD) or a bus write (BWR) signal. Referring again to FIG. 11, these signals are ORed at device 1133, so that if either one is active and this GPP 1134 is selected as a slave, an IPC request is generated in circuitry at reference numeral 1137. If the GPP 1134 is selected as a slave, and a bus read (BRD) or a bus write (BWR) signal is generated, a signal called slave operation (SLOP) 1173 is developed. The SLOP signal clocks a flip flop 111231. This generates an IPC request. An IPC acknowledge (IPACK) signal becomes active in the contention resolver when none of the other high-priority devices is attempting to access memory. Then the IPC acknowledge (IPCACK) signal is applied to OR gate 12151.

Device (driver) 1246 is activated via gating circuitry shown at reference numeral 1241. There are two reasons for activating the driver 1246. If this GPP 1134 is a master and is attempting to perform a read operation from the slave's memory (MOP and BRD are active), the signal on pin 6 of circuit 1241 that activates the set of drivers 1246 is generated. The other condition is if this GPP 1134 is a slave and another master is attempting to write into this GPP's 1134 memory 1231 (IPCACK and BWR are active). In that case, the set of drivers 1246 is activated and data from the master is applied via BDB 1246 and DB. The data then enters the memory 1231.

Data is transferred from the latch 1256 onto the data bus (BDB) in the following manner. The latch 1256 has a set of internal tri-state drivers. To activate these tri-state drivers, the output enable (OE) line on pin 1 of latch 1256 must be activated. That is activated when logic involving circuitry at reference numeral 1243 is satisfied. This circuitry 1243 is part of the same device as is circuit 1241. There are two conditions under which data is output from the latch 1256. If the GPP 1134 is a master and a master operation is being performed (MOP is active), a bus write (BWR) signal is generated. If the bus write (BWR) signal is active and the MOP signal is active, then the contents of latch 1256 is gated onto the bus. The other condition is if the GPP 1134 is a slave and the master processor is trying to read the memory 1231 from this GPP 1134. The slave (SLAVE) signal is active, and the bus read (BRD) signal from the back plane also becomes active. That also gates information from the latch 1256 onto the bus.

Hand-shaking is provided to indicate to the master processor that the slave has completed the transfer. When the master is ready to perform a transfer, it activates the MOP line coupled to device 1212. The slave processor may not be able to respond immediately. It may be engaged in other operations. It is therefore necessary to place the processor in a wait state for the slave to transfer data. The MOP signal is ORed in device 12832 with a bus ready (BRDY) signal at pin 24 of connector J1. The output of OR gate 12832 is a signal called IPC ready (IPCRDY). When IPC ready (IPCRDY) becomes false, it lowers the processor's ready line (CPURDY). That places the processor 1134 in the wait state in which it remains until the bus ready (BRDY) signal returns from the slave. Bus ready (BRDY) then goes true, activating IPC ready (IPCRDY). The ready input (CPURDY) on the processor 1134 goes true to allow the processor 1134 to begin processing again.

For any particular transfer, the master establishes the proper mode by activating MOP. It accesses the upper 8,000 hex bytes of memory, sets bus ready (BRD) or bus write (BWR), depending upon whether a read or a write operation is being performed, and then enters the wait state and waits for the bus ready (BRDY) signal to return from the slave, indicating that the transfer is complete. When the bus ready (BRDY) signal returns, the processor 1134 begins processing again.

A flip flop 12121 is used to drive the bus ready (BRDY) line when the GPP 1134 is a slave. A driver 1293 on the bus ready (BRDY) line is activated by the slave (SLAVE) signal. The input of that driver 1293 is attached to the flip flop 12121. The flip flop 12121 is set when IPC acknowledge (IPCACK) is applied to pin 3 of flip flop 12121.

If another master is on the system and this processor 1134 is a slave, the master makes an IPC request, and when the IPC has priority, it generates an IPC acknowledge (IPCACK) signal, which sets flip flop 12121 and generates the bus ready (BRDY) signal at pin 24 of connector J1. This signal propogates to the master and releases the master so it can process. The K input pin 2 on flip flop 12121 is coupled to the SLOP signal. The bus ready (BRDY) signal is normally true; when the master begins an operation, it activates bus read (BRD) or bus write (BWR). That generates the SLOP signal, which causes the bus ready (BRDY) signal to go false. It stays false until the IPC acknowledge (IPCACK) signal returns (that is, until the transfer actually occurs).

Referring to FIG. 11, the power on clear (PWRONCLR) line into the processor 1134 is attached to a set of jumpers. When the GPP 1134 is a disk processor, the source of the power on signal is the disk controller, tied through the device controller interface. When the GPP 1134 is a non-disk processor, this jumper is established such that the source for the signal is the power on clear (PWRONCLR) signal on the back plane. This line then holds the processor 1134 in a reset condition until the initialization sequence is accomplished.

DISK CONTROLLER

Referring now to FIGS. 13, 14, 15, 16 and 17 and more particularly FIG. 14, a processor interface is shown, including address lines A0 through A15 and data lines D0 through D7 as part of connector J3, coupled to a GPP. All of these lines are connected to transceivers. Lines A0 through A7 are coupled to transceiver 1441; lines A8 through A15 are coupled to transceiver 1451; and lines D0 through D7 are coupled to transceiver 1421. These transceivers 1421, 1441 and 1451 are used to communicate with the GPP.

Read (RD) and write (WRT) control signals can be driven by the tri-state control bus (FIG. 11), which the processor or the DMA device can drive.

Memory I/O is the third control line at device 1432. The read and write lines are bi-directional. They are also coupled to device 1412. Sometimes the processor performs read and write operations to the registers on this controller. Sometimes the DMA controller on this circuit manipulates the read and write lines and performs the transfers into GPP memory.

An interrupt output signal from device 14220 is used to drive the processor's interrupt signal. Device controllers manipulate the interrupt line to generate an interrupt. When the processor is prepared to process the interrupt, an interrupt acknowledge (INTA) line is activated by the processor and applied to device 1433. At this point, the data on a set of drivers 1422, 14221 and 14222 is transferred to the data bus D3, D4 and D5. The other lines on the data bus D0, D1, D2, D6 and D7 are pulled up with resistors shown generally at reference numeral 1411. That corresponds to a restart instruction. During an interrupt acknowledge (INTA), a restart one instruction is applied to the data bus D3, D4 and D5.

Another signal derived on the disk controller is a signal called BOOT at 14223. The boot line has the effect of disabling the random access memory (RAM) on the processor. When the BOOT signal is active, the boot PROM on the disk controller is active. The processor begins executing instructions from the boot PROM in the disk controller. When the boot operation is finished, the BOOT signal goes inactive and the PROM on the disk controller vanishes from the system.

The lower eight bits of the address bus are applied directly into the address pins on the boot PROMs 1442 and 1432. The output of the PROMs 1442 and 1432 is applied to the data bus D0 through D7. The chip selects on 1442 and 1432 are tied to signals called BOOT and memory read (MEMRD). Both signals must be active in order for the PROMs to be accessed. A boot operation, while the processor is performing a memory read operation, results in output information from the PROMs 1442 and 1432. In the absence of these signals, the PROMs 1442 and 1432 are decoupled from the data bus. The PROMs contain instructions therein for the boot operation. When the procesor fetches instructions during the boot operation, it reads the instructions from these PROMs, 1442 and 1432.

An eight input NAND gate 1443 decodes the address lines A0 through A7. When the lower eight bits of the address bus are all set at one, the output of that gate 1443 becomes active. That corresponds to address FF hex. The output of gate 1443 is ANDed in gate 1466 with a memory read (MEMRD) signal and drives the D input to a flip flop 1456. In conjunction with flip flop 14561 and AND gate 14661, the output of 1456 is used to produce a pulse which is one .0. period wide. .female.1 is the clock for flip flops 1456 and 14561. The output of the AND gate 14661 drives the K input on the boot flip flop 1476. It performs the function of resetting the boot flip flop 1176. When a memory read to location FF instruction is executed, the boot flip flop 1476 is reset.

In the boot PROM program, the last step is a jump to location FD. Location FD has a jump instruction to location 0. The jump instruction requires three bytes: jump at FD, the destination address, FE and FF. When the processor executes the instruction fetch at address FF, the boot flip flop 1476 is reset, which operates without intervention of the boot PROM. It then executes that jump instruction. It goes down to location 0, but now finds that location 0 is not the vanished PROM, but the RAM on its associated GPP. The boot flip flop 1476 is initialized by one of two conditions: a power on condition, or depression of the reset switch 14104.

A one-shot 1465 output is used to drive the boot flip-flop 1476. When the system is quiescent, without power, a capacitor 1493 discharges. It has 0 voltage across it. As power is applied, the voltage builds and the one-shot 1465 fires. Gradually the capacitor 1493 charges through a resistor network shown generally at reference numeral 1421. As a result, one trigger pulse from pin 12 of 1465 is generated by the one-shot 1465 setting the boot flip flop 1476. This signal from pin 12 of the one-shot 1465 also sets a master reset flip flop 14761. It also drives a signal called power on clear (POC) via device 1433 to the processor through connector J1.

An I/O decoder shown generally at reference numeral 1431 decodes addresses for the different peripheral devices and registers that are part of this controller. Device 1444 is a three-line to eight-line decoder. A, B and C inputs are applied and the decoder 1444 activates one of its eight outputs, depending upon the code applied to the A, B and C inputs. To activate device 1444, all three enable inputs are required. Two of them are inverting pins 4 and 5 of decoder 1444, and one of them is non-inverting pin 6 of decoder 1444. The outputs of the decoder 1444 are labeled 3, 4, 5 and 6. The three outputs, for example, correspond to a 011 on the C, B and A inputs respectively. B and A must be true and C must be false to activate the three outputs. Also, all of the enables must be active.

The two inverting enables are coupled via buffer 1433 to the memory I/O (M/IO) bar signal in the processor. When the processor is executing an I/O instruction, the M/IO bar signal at buffer 1433 goes false. Device 1433 is a non-inverting buffer. Accordingly, the enable inputs on the decoder 1444 go false when the processor executes an I/O instruction. The other enable input is connected to address line A7 (the most significant bit of the least significant half of the address bus). Seven bits of the address must be utilized to decode I/O instructions because there are 256 possible I/O addresses. When the enable bit is set and when C is 0, B is 1 and A is 1, and the processor is executing an I/O instruction, the number three output is active. That goes false.

The output from decoder 1444 is input to an AND gate 1435 and is ANDed via device 1434 with an IOWRT and .0.1 signal. The output of AND gate 1435 is applied to the K input of the master reset flip flop 14761. If the processor executes an output instruction, to address B0, the master reset flip flop 14761 is reset. The master reset output is applied via the back plane to all of the processor boards. The disk controller processor board ignores this signal, but all the rest of the processor boards use it to active their reset lines. Accordingly, if the disk controller processor performs an output operation with any device on the data bus, the master reset flip flop 14761 is reset, and all the processors are started. This occurs at the end of a boot operation. After all of the processors are loaded with useful code, an output instruction is executed to enable the system processors.

The other outputs of the decoder 1444 are connected as follows. The four output pin 11, which corresponds to register address CX (where X equals not applicable, N/A) is connected to two AND gates 14351 and 1446. They perform an AND function. AND gate 14351 is used to drive the strobe for the mode control register (MCRSTB) 1471 on the controller. When an output to register C0 occurs, the contents of the accumulator is transferred to the mode control register 1471. The gate input pin 11 of the mode control register 1471 is the mode control register strobe. The D inputs on the octal D latch are connected to the data bus D0 through D7.

The signal at AND gate 1446 is ANDed with the I/O read (IORD) signal. An I/O read to address C0 generates a status register strobe (SRSTB) signal. The SRSTB signal is applied to the status register 1461. The inputs to this status register 1461 are tied to different points on the drive and points internal to the controller card: write protect (WP), interrupt request (INTRQ), head load (HLD), and three signals that come back from the drive: TWO-SIDED, DRIVE PRESENT and DISK CHANGE.

The TWO-SIDED signal is used to determine whether a single sided or a double sided drive is being used. The DRIVE PRESENT signal indicates that a drive is connected with a particular drive address. The DISK CHANGE indicates that the disk drive door has been opened and closed, thereby indicating that another disk may have been inserted. This information is used to alert the operator.

An I/O write instruction to address C0 results in data being transferred from the processor to the mode control register 1471. This is accomplished by decoding an I/O instruction to address C0 as above and then ANDing the result with the IOWRT and .0.1 signals in devices 1434 and 14351.

Referring again to the output of the mode control register 1471, the least significant bit is marked double density (DDEN) at pin 9 of mode control register 1471. The bit determines whether the system is writing single density or double density. The next line pin 14 of connector J2 is marked SIDE. It is used for double sided drives. One head or the other can be selected with that signal. The next four lines, pins 26, 28, 30, 32 of connector J2 are also coupled to the drive. They are the drive select lines, DS0 through DS3. Only one of those lines is active at one time. The lines DS0 through DS3 select one of four drives connected to the system.

Another decoder 1423 has read (RD) and write (WRT) inputs from the processor 1134. The C input of decoder 1423 is tied to the memory I/O (M/IO) line. There are three enable inputs on decoder 1423, each designated E on decoder 1423. One enable input at pin 6 is energized and is always active. The other two are tied to a signal called AEN, which is derived on the DMA controller, discussed hereafter. The system differentiates the drivers of the read (RD) and write (WRT) lines. The decoder 1423 is enabled only when the processor 1134 is providing the signals, not when the DMA controller is providing them. When the DMA controller is active, it assumes the function of the processor, driving the memory read and write lines. When the processor 1134 is driving the RD and WRT lines, the AEN signal is false and the decoder 1423 is enabled.

The output of the decoder 1423 includes three signals: memory read (MEMRD), I/O write (IOWRT), and I/O read (IORD). The IOWRT and IORD signals are used when the processor 1134 is performing input or output type operations.

Output 6 (pin 9) of device 1444 is applied to an inverter 1464 and drives a signal called controller chip select (CONCS). This output becomes active whenever the processor executes an I/O instruction to location EX hex, where X equals not applicable, N/A. The CONCS signal is applied to the disk controller 1392 and is used to indicate that the processor 1134 is performing a read or write operation to the disk controller. The controller chip select (CONCS) line drives the J input on flip flop 1454. The Q output of flip flop 1454 is coupled to the K input. As a result, an output signal from pin 6, which is one clock pulse .0.1 wide, is generated. The output of this flip flop 1454 is coupled via amplifier 14223 to the ready (READY) line of the processor 1134. Since the disk controller 1392 is a relatively slow device for I/O, the processor is operated by using the READY signal to delay its operation while waiting for information from the disk controller 1392.

Another output, output 5, from the decoder 1444 at pin 10 provides the signal called DMA chip select (DMACS) that directly drives the chip select on the DMA controller 1353. This signal is active when the processor executes an I/O instruction to address DX hex, where X equals not applicable, N/A.

The OR gate at location 1445 receives all of the output signals from the decoder 1444. It performs a logical OR function on the output signals and generates a signal called disk controller I/O (DCIO), used to enable the data bus driver transceiver 1421 in the processor interface under certain circumstances. In the case where the processor 1134 is performing an I/O read operation, this transceiver 1421 drives data back into the processor 1134. The DCIO signal is an indication to the control circuitry shown generally at reference numeral 1433 for this transceiver 1421 that the processor 1134 is executing the I/O instruction. The transceiver 1421 drives the processor 1134 in accordance with a signal from logic circuitry 1433. If an interrupt acknowledge (INTA) signal occurs or if the processor 1134 is performing an I/O read (IORD) operation or if the boot flip flop 1476 (BOOT) is active and the processor 1134 is performing a memory read (MEMRD) operation or if a write into memory (WRT) is occurring and this is a DMA access (AEN), then the transceiver 1421 is operated to drive the processor 1134.

There are two conditions under which the disk controller 1392 interrupts the processor 1134: one is to indicate that the controller has completed an operation (that is, after a read, write or abort operation); the other condition for interrupting the processor 1134 is when the byte counter in the DMA controller has exhausted itself. That is, if the disk controller is conditioned such that it has additional functions to perform, the processor 1134 can be apprized that the operation is terminated. The terminal account (TC) input to flip flop 1454 comes from the DMA controller. It indicates that the byte count is exhausted. The flip flop 1454 is set when TC goes active and is reset when the processor 1134 performs an I/O read operation to the DMA controller. Two signals, I/O read (IORD) and DMA chip select (DMACS), are applied to the K input of flip flop 1454 via AND gate 1435. The output of flip flop 1454 is ORed in device 1466 with a signal called interupt request (INTRQ). The INTRQ signal is generated by the floppy disk controller device 1392.

Referring now to FIG. 15, the DMA controller 152 is used to transfer information from the disk controller 1392 to the processor's memory without processor intervention. The disk processor can perform other operations while these transfers are taking place. It is not occupied with taking a byte from the disk controller 1392 and transferring it into memory, because if it were, that is all it would have time to do. The DMA controller 152 resides on the disk controller 1392 to handle these transfers for the processor.

The floppy disk DMA controller 152 has a bidirectional data bus 154 D0 through D7 connected to the data bus on the processor 1134 through a set of transceivers shown in greater detail on FIG. 14. It also has a bidirectional address bus 156 A0 through A7. That address bus is connected to a latch 158.

When the DMA controller 152 performs a memory access operation, it follows a multiplexing scheme, similar to the processor's. It loads an address on its bus which is latched. Then the least significant byte of the address is loaded directly on the bidirectional bus. There are bidirectional control lines, I/O read (IORD) and I/O write (IOWRT), memory read (MEMRD) and memory write (MEMWRT). These correspond to the control lines that are derived from the processor.

These four control signals must be distinguished. When the DMA controller 152 performs a transfer operation from the floppy disk controller into memory, it performs an I/O read and then a memory write operation. The two operations must overlap, since the data is to be transferred in a single memory cycle. For data transfers from memory to the disk controller 1392, data is temporarily stored in latch 1331. The DMA controller 152 performs a memory read operation to retrieve information from the memory and overlaps that with an I/O write operation to the disk controller 1392.

In order to monitor the status of the DMA operation, there is provided a 16-bit address counter 1510. The counter 1510 points to the next location in memory. There is also provided a 14-bit byte counter 1512. This counter 1512 allows the transfer of up to 16K bytes of data. The upper two bits 1514 of the counter 1512 are used for control applications to determine whether a memory read or a memory write operation is being performed or whether a verification operation is being performed during which no transfers take place. The two bits 1514 differentiate between a write and a read operation.

The DMA controller 152 has four sets of registers and can handle four channels simultaneously, although only a single channel is used to the disk controller.

A data request (DRQ) signal 1518 is applied to indicate that the disk controller is attempting to transfer a byte of data to memory. There is also provided a control register 1516. The processor 1134 accesses any of these registers by executing an output or an input instruction to the DMA controller 152. Those signals, IORD, IOWRT, MEMRD, and MEMWRT, share the same pins that the DMA controller 152 uses to control the I/O operations. Accordingly, these signal lines are bidirectional. When the processor 1134 attempts to write into one of these registers, it activates the I/O write (IOWRT) line, and it loads an address on the lower byte of the address bus 156. That points to one of the registers on the DMA controller 152 and data is input from the bus 154.

The two registers 1510 and 1512 are 16 bits wide. Consequently, two output instructions are required to load them for a read operation. Control register 1516 is an input control register, used to enable any one of the four channels. Device 1512 is operated on channel two. Accordingly, the signal on line 1518 is designated DRQ2, representing channel two in the DMA controller 152. The DMA controller 152 has an auto chain feature to allow the processor 1134 to move onto the next operation. A series of DMA operations can be performed; the processor 1134 need not be apprized of the termination of each one.

If the DMA controller 152 detects an appropriate data request and if one of the four channels has been enabled by a bit being set in the control register 1516, when the controller 152 moves in accordance with the following sequence. The DMA controller 152 sends a signal to the processor 1134 on a line called hold request (HRQ) 1520. The hold request line 1520 goes active. That makes the processor 1134 become transparent to the system busses. It stops it from processing only for the period of the transfer taking place, which is on the order of 2 to 2.5 microseconds. These transfers take place at the disk rate which is 32 microseconds between transfers for single density or 16 microseconds between transfers for double density recording format disks. Every 16 or 32 microseconds, the processor enters the hold state and remains in that state for 2 to 2.5 microseconds.

The DMA controller 152 has T-states (processor memory cycles) associated with it. Four or five T-states are required to make the transfers. When the controller 152 is prepared to perform the transfer, a signal from the processor 1134 called hold acknowledge (HLDA) on line 1522 indicates that the processor 1134 is in the hold state now and the transfer can be performed. The transfer takes place on the IORD and IOWRT signals. The memory signals MEMRD and MEMWRT are activated at the proper time. The transfer is completed. The DRQ signal on line 1518 is disabled. The controller 152 drops the hold request (HRQ) line 1520 and then the processor 1134 starts processing again. The byte counter 1512 is decremented. The address counter 1510 is incremented. Consequently, consecutive locations in memory are utilized.

The byte counter 1512 operates until it reaches zero, at which point a terminal counter (TC) signal on line 1524 is generated to indicate completion of the write operation.

Referring now to FIG. 16, there is shown a disk controller 1392. A bi-directional data bus D0 through D7 is shown at reference numeral 162. Address lines A0 at reference numeral 164 and A1 at reference numeral 166 are used to address internal registers on the disk controller 1392. A chip select (CS) line 168 indicates selection of the disk controller 1392 chip. Read enable (RE) 1610 and write enable (WE) 1612 signals indicate whether the operation to the disk controller 1392 is a read or write operation respectively.

The disk controller 1392 is provided with four write registers 1614 and four read registers 1616. The write registers 1614 include a command register 16141, a track register 16142, a sector register 16143, and a data register 16144. The read registers 1616 include a status register 16161, a track register 16162, a sector register 16163, and a data register 16164.

Disk controller 1392 provides an interface to the disk drives. Data is serialized and deserialized from the drive. The eight bit data transmitted over data bus 162 is serialized for transmission to the disk. The disk controller 1392 also operates in the reverse manner, converting a serial data stream from the disk for transmission on the data bus 162 into a parallel format. A read data (RDATA) line 1618 carries a serial data stream from the drives, which is converted to parallel format and sent via data bus 162 to the associated GPP. Data from data bus 162 is serialized and output over a write data (WD) line 1620 to the disk.

The disk controller 1392 does not merely transfer data to and from the disk in raw form, but controls the timing for recording on the proper position of the disk. The read data (RDATA) line 1618 is continually monitored by the disk controller 1392 to determine where the read/write head is positioned relative to the rotating disk.

In normal operation, the track 16142 and sector 16143 registers of the write registers 1614 are loaded with the destination location of the position on the disk to which data is to be written. The data transfer is then accomplished. To appropriately position the read/write head on the disk, the disk controller is provided with output control lines, step (STEP) 1622 and direction (DIR) 1624. These signals, STEP and DIR, are used to control the movement of the head. Once the specified track is located and the head is appropriately positioned, a head load (HLD) signal 1626 is output from the disk controller 1392.

A write gate (WG) signal 1628 is output from the disk controller 1392 to indicate when the data on the write data line 1620 is to be written onto the disk. This prevents overwriting of the format and other information residing on the disk.

A data request (DRQ) signal 1630 is generated by the disk controller 1392 to indicate to the DMA controller that data is to be transferred thereto. Operations that can be performed by the disk controller 1392 include the following: STEP, SEEK, READ SECTOR, WRITE SECTOR, READ TRACK, WRITE TRACK, READ ADDRESS, FORMAT, and READ FORMAT.

The STEP operation is a discrete operation, moving the head incrementally in or out.

The SEEK operation occurs when the head is over a particular track on the disk, but must be moved to another track. To initialize this operation, the data register 16144 is loaded with the address of the destination track on the disk. The track register 16142 contains information as to the current track location above which the head is located. A SEEK command steps the head over the appropriate number of tracks until both the track and data registers 16142 and 16144 contain identical information.

A double density (DDEN) signal 1632 indicates to the disk controller 1392 whether the disk is formatted in single density or double density recording format. To initiate a READ SECTOR operation, the disk controller 1392 considers the information loaded in the sector register 16143 to determine whether the destination sector matches the sector specified in the next identification (ID) header. Once the sector has been found, the disk controller 1392 begins to transfer information through the data register 16144. If the appropriate sector cannot be found after 15 rotations, the status register 16161 in the disk controller 1392 is set with a flag. An interrupt request (INTRQ) signal 1634 is generated by the disk controller 1392 to the processor.

A READ TRACK operation instructs the disk controller 1392 to read all sectors on a given track, such as the one loaded in the track register 16142. A similar operation occurs when the disk controller 1392 is instructed to perform a WRITE TRACK operation.

A READ ADDRESS operation occurs when the head is positioned above the disk at an indeterminable location. The head is instructed to read data from the disk until it reaches an identification (ID) header on the disk. The track and sector information obtained from the ID header is loaded in the track and sector read registers 16162 and 16163 of the disk controller 1392.

The FORMAT operation allows the disk controller 1392 to reformat a disk by writing an image from memory continuously onto the disk.

The READ FORMAT operation allows the disk controller 1392 to read every bit of information on the disk for the current track.

Referring now also to FIG. 13, the DMA controller is shown at 1353. The disk controller is shown at 1392. To perform a DMA transfer, the DMA controller 1353 must output the most significant half of the address on the data bus D0 through D7 which is latched into device 1352.

The address strobe (ADSTB) signal at pin 8 of the DMA controller 1353 is applied to the enable gate (EG) pin 11 of latch 1352. A .0.ISYNC signal is applied from the processor via driver 1333 to clock input (CLK) pin 12 of the DMA controller 1353. All of the operations are synchronized with respect to the .0.SYNC signal.

The reset input (RESET) pin 13 is used to initialize the DMA controller 1353. The hold request (HRQ) output at pin 10 of the DMA controller 1353 is used to initiate a DMA transfer. The hold acknowledge (HOLDA) signal at pin 7, applied via driver 13331, acknowledges that the processor has entered the hold condition. The lower half of the address bus A0 through A7 is a bi-directional bus. Four bi-directional control signal lines IORD, IOWRT, MEMRD and MEMWRT are provided. The same function is performed on the DMA controller 1353 that is performed on the processor.

The READY signal is provided at pin 6 of the DMA controller 1353 to introduce wait states in the transfer. When the DMA controller 1353 is communicating with a slower memory, for example, it is slowed until the READY line is asserted. In this configuration, one wait state is introduced for each data transfer.

The data request (DRQ2) signal at pin 17 of the DMA controller 1353 is coupled to disk controller 1392. When disk controller 1392 is ready to transfer data, it activates the DRQ2 signal to inform the DMA controller 1353. The AEN signal at pin 9 of the DMA controller 1353 indicates that the transfer is in the process of taking place.

The AEN output signal is coupled to a buffer 13332 to an OR gate 13113, to the chip select (CS) on the disk controller 1392. When AEN is active, a transfer is taking place to or from the disk controller 1392. This indicates to the disk controller 1392, by means of the CS input, that communication between it and the DMA controller 1353 is occurring, and establishes appropriate conditions in 1392. The AEN signal is also applied to another pair of OR gates 131131 and 131132 that drive inputs on the disk controller 1392. If both of those inputs A0 and A1 are activated and chip select (CS) is also activated, the input or output register three in the disk controller 1392 is addressed. When AEN goes active, the data registers of the disk controller 1392 are activated.

A state counter 1393 monitors DMA cycles. The DMA controller 1353 goes through four to six states to effect a DMA transfer. The counter 1393 monitors the current state. Drivers and receivers are activated depending upon the state of the DMA controller 1353. Logic shown generally at reference numeral 1383 generates a signal called DMA request (DMAREQ). This DMAREQ signal is applied to the general purpose processor 1134 to indicate that a request is being initiated. Because the processor 1134 is in the hold state, it is not on the bus. The next highest priority device is the disk controller 1392. A DMA acknowledge (DMAACK) signal is returned from the processor 1134 on the next clock cycle once the DMA request (DMAREQ) signal is activated.

The combinations of signals that drive the DMAREQ signal are the signal from output 3 (pin 12) of the state decoder 13103 that corresponds to the wait state and a write (WRT) signal, or state 3 from output 2 (pin 13) of the state decoder 13103 and a memory read (RD) signal. The DMA request (DMAREQ) signal is activated depending upon whether the operation is a read from or a write to memory.

A data bus D0 through D7 is coupled to the floppy disk controller 1392 via parallel connected inverting buffers 1362 and 1372. These inverting buffers 1362 and 1372 interface the disk controller 1392 to the data bus D0 through D7.

An octal latch 1331 is coupled to the data bus D0 through D7. When a data transfer occurs from memory to the disk controller 1392, the information must be stored first in the octal latch 1331 due to timing of the various components. Data is taken from memory and is stored in the latch 1331. It is then transferred to the disk controller 1392. Inputs A0 and A1 to the disk controller 1392 are connected to OR gates 131131 and 131132. Inputs A0 and A1 allow addressing of different registers in the disk controller 1392.

Four signals are input by the disk controller 1392 from the disk drive: ready (READY), track zero (TRK 00), index (INDEX), and write protect (WRITE PROT). Each of these signals is applied to the disk controller 1392 via buffers 1382, 13101, 131011 and 131012. Those are status signals that are generated by the drive. The READY signal indicates that the drive is ready to perform an operation--power is applied, a disk is loaded, and the disk drive door is closed. Track zero (TRK 00) indicates that the read/write head is positioned over track zero. The index (INDEX) signal indicates that the physical hole in the disk is aligned with the physical hole in the envelope encasing the disk. The write protect (WRITE PROT) signal indicates that the disk is write protected.

Raw read (RAW READ) and read clock (RCLK) are applied to the disk controller 1392.

A signal called read gate (RD) from the disk controller 1392 pin 25 indicates that the read head is properly positioned with respect to the disk to perform a read operation. The interrupt request (INTRQ) output, pin 39 of disk controller 1392, indicates that the disk controller 1392 requires attention from the processor.

A signal called head load (HD LOAD) is output from pin 28 on disk controller 1392 to the disk. This HD LOAD signal drives a one-shot 13131, the output of which is input to the disk controller 1392 on the head load timing (HLT) terminal at pin 23. The one-shot 13131 provides settling time for the head. The one-shot 13131 operates for approximately 50 milliseconds every time the head is loaded. The one-shot 13131 then provides a signal back to the head load timing (HLT) input of 13391 to indicate that the head has been loaded.

A direction (DIRC) output pin 16 indicates the direction the head is to move. A step (STEP) signal pin 15 provides information regarding the number of steps to move the head. The write gate (WG) signal pin 30 turns the write current on only in certain places on the disk to prevent these transitions from disturbing the disk format.

Three signals, write data (WD) pin 31, early (EARLY) pin 17 and late (LATE) pin 18, are used to generate the write data (WRITE DATA) signal to the disk. In single density applications, the EARLY and LATE signals have no significance; but for double density they provide a way of pre-compensating the data for bit shift before it is loaded on the disk. They move data by shifting the bits to help make certain data combinations easier to decode.

Data is output from pin 31 (WD) of the disk controller 1392 and is shifted through a shift register 13111. A multiplexer 13121 applies one of the shift register outputs to its Y output (1Y), pin 7. A shifted or unshifted version of the data is applied to a one-shot 1365. The one-shot 1365 provides a pulse via a buffer 1391 to generate the WRITE DATA signal.

Referring now to FIG. 17, data separator circuitry is provided to synchronize input data. This circuit processes input data (RDDATA) and generates a clock signal (READ CLOCK) which is timed to a read data (READ DATA) signal out. The read clock (READ CLOCK) output signal windows the read data (READ DATA) signal. The READ DATA signal is a pulse approximately 250 nanoseconds wide.

There are two clocks. An oscillator, shown generally at reference numeral 1711 operates at 8 MHz. The oscillator 1711 drives a counter 17123. The counter 17123 divides the 8 MHz frequency into something usable for the different devices. Delta clock (.DELT