Method and apparatus for custom operations of a processor

Abstract

Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e., low cost and chip count, and advantages of a general-purpose processor reprogramability. These custom operations work in a computer system which supplies input data having operand data, performs operations on the operand data, and supplies result data to a destination register. Operations performed may include audio and video processing including clipping or saturation operations. The present invention also performs parallel operations on select operand data from input registers and stores results in the destination register.

Claims

What is claimed is:

1. A computer system comprising:

input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M;

a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set;

a destination register comprising M bits, for storing the result data of N bits as one output of M bits, wherein:

each input data of a respective input register of M bits comprises a first operand data of N bits and a second operand data of N bits;

said processor comprises:

means for adding the first operand data of a first input data to the first operand data of a second input data to produce a first result of N bits and adding the second operand data of the first input data to the second operand data of the second input data to produce a second result of N bits of N bits, and

means for clipping each respective result into a specified range to produce respective clipped results, each clipped result being N bits; and

said destination register stores the respective clipped results together.

2. A computer system comprising:

input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M;

a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set;

a destination register comprising M bits, for storing the result data of N bits as one output of M bits, wherein:

the input data of M bits comprises two operand data of N bits each;

said processor comprises:

means for computing an absolute value of each operand data, each computation producing a respective absolute value of N bits, and

means for clipping each respective absolute value into a specified range to produce respective clipped results, each clipped result being N bits; and

said destination register stores the respective clipped results together.

3. A computer system comprising:

input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M;

a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set;

a destination register comprising M bits, for storing the result data of N bits as one output of M bits, wherein:

the input data of M bits comprises a first operand comprising N bits and a second operand comprising N bits;

said processor comprises:

means for multiplying the first operand data of a first input data to the first operand of a second input data to produce a first product and multiplying the second operand data of the first input data to the second operand data of the second input data to produce a second product, the first and second products each comprising N bits, and

means for clipping each respective product into a specified range to produce respective clipped results, each clipped result comprising N bits; and

said destination register stores the respective clipped results together.

4. A computer system comprising:

input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M;

a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set;

a destination register comprising M bits, for storing the result data of N bits as one output of M bits, wherein:

the input data of M bits comprises a first operand and a second operand, the first and second operands each comprising N bits;

said processor comprises:

means for subtracting the first operand data of a first input data from the first operand of a second input data to produce a first difference and subtracting the second operand data of the first input data from the second operand data of the second input data to produce a second difference, the first and second differences each comprising N bits; and

means for clipping the first difference and the second difference into a specified range to produce respective clipped results, each clipped result comprising N bits; and

said destination register stores the respective clipped results together.

5. A computer system comprising:

input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M;

a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set;

a destination register comprising M bits, for storing the result data of N bits as one output of M bits, wherein:

the input data of M bits comprises P operand data of N bits each, P being at least two;

said processor comprises:

means for adding a respective operand data of a first input data to a respective operand data of a second input data for each operand data of the P operand data, each adding producing a respective sum of N bits, and

means for clipping each respective sum into a specified range to produce P respective clipped results, each clipped result being N bits; and

said destination register stores the P respective clipped results.

6. A computer system comprising:

input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M;

a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set;

a destination register comprising M bits, for storing the result data of N bits as one output of M bits, wherein:

the input data of M bits comprises P operand data of N bits each, P being at least two;

said processor comprises:

means for subtracting a respective operand data of a first input data from a respective operand data of a second input data for each operand data of the P operand data, each subtracting producing a respective difference of N bits, and

means for clipping each respective difference into a specified range to produce P respective clipped results, each clipped result being N bits; and

said destination register stores the P respective clipped results.

7. A computer system comprising:

input registers for supplying input data of M bits, each input data comprising at least two operand data, each operand data comprising N bits, where N is less than M;

a special purpose processor for performing a group of operations in parallel for selected sets of operand data of the input data, each group of operations producing result data of N bits, said processor performing in response to an instruction of an instruction set;

a destination register comprising M bits, for storing the result data of N bits as one output of M bits, wherein:

the input data of M bits comprises P operand data of N bits each, P being at least two;

said processor comprises:

means for multiplying a respective operand data of a first input data to a respective operand data of a second input data for each operand data of the P operand data, each multiplying producing a respective product of N bits, and

means for clipping each respective product into a specified range to produce P respective clipped results, each clipped result being N bits; and

said destination register stores the P respective clipped results.

8. A computer system comprising:

an input register supplying input data of M bits;

a processor of retrieving N bits of data of the input data, N being less than M, for P input data;

a destination register for storing the respective retrieved N bits of data of the P input data, wherein:

a first and a second input data are supplied;

said processor retrieves the most significant bits (msb) of each respective input data, each respective most significant bits being supplied as the most significant bits (mmsb) of the most significant bits and the least significant bits (lmsb) of the most significant bits;

means for packing packs the most significant bits of the most significant bits (mmsb) of the first input data as the most significant bits of a destination register;

said means for packing packs the most significant bits of the most significant bits (mmsb) of the second input data as the next most significant bits of the destination register;

said means for packing packs the least significant bits of the most significant bits (lmsb) of the second input data as the least significant bits of the destination register; and

said means for packing packs the least significant bits of the most significant bits (lmsb) of the first input data as the next least significant bits of the destination register.

9. A computer system comprising:

an input register supplying input data of M bits;

a processor of retrieving N bits of data of the input data, N being less than M, for P input data;

a destination register for storing the respective retrieved N bits of data of the P input data, wherein:

a first and a second input data are supplied;

said processor retrieves the least significant bits (lsb) of each respective input data, each respective least significant bits being supplied as the most significant bits (mlsb) of the least significant bits and the least significant bits (llsb) of the least significant bits;

means for packing packs the most significant bits of the least significant bits (mlsb) of the first input data as the most significant bits of a destination register;

said means for packing packs the most significant bits of the least significant bits (mlsb) of the second input data as the next most significant bits of the destination register;

said means for packing packs the least significant bits of the least significant bits (llsb) of the second input data as the least significant bits of the destination register; and

said means for packing packs the least significant bits of the least significant bits (llsb) of the first input data as the next least significant bits of the destination register.

10. A computer system comprising:

a plurality of input registers, each register storing a concatenation of multiple operands;

processing means for receiving the operands from the input registers and performing a set of operations in parallel on specific operands of the operands in response to an instruction, the operations including first operations performed on a single operand and second operations performed using multiple operands and each operation producing result data, and each respective set of operations producing respective output data and comprising at least one operation; and

a destination register coupled to the processing means for storing the respective output data together.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is custom operations for use in processor systems which perform functions including multimedia functions, such as, for example, a system with an ability to handle high-quality video and audio and for performing specialized, high-function operations.

2. Description of the Related Art

A system may include a general-purpose CPU and additional units to serve as a multi-function PC enhancement vehicle. Typically, a PC must deal with multi-standard video and audio streams, and users desire both decompression and compression, if possible. While the CPU chips used in PCS are becoming capable of low-resolution real-time video decompression, high-quality video decompression and compression are still not possible. Further, users demand that their systems provide live video and audio without sacrificing responsiveness of the system.

For both general-purpose and embedded microprocessor-based applications, programming in a high-level language is desirable. To effectively support optimizing compilers and a simple programming model, certain microprocessor architecture features are needed, such as a large, linear address space, general-purpose registers, and register-to-register operations that directly support manipulation of linear address pointers. A recently common choice in microprocessor architectures is 32-bit linear addresses, 32-bit registers, and 32-bit integer operations although 64 and 128 bit systems are currently in development.

For data manipulation in many algorithms, however, data operations using the entire number of bits (i.e., 32 bits for a 32-bit system) are wasteful of expensive silicon resources. Important multimedia applications, such as decompression of MPEG video streams, spend significant amounts of execution time dealing with eight-bit data items. Using 32-, 64-, 128-, . . . , bit operations to manipulate small data items makes inefficient use of 32-, 64-, 128-, . . . , bit execution hardware in the implementation. Therefore, custom operations may operate on data items simultaneously and improve performance by a significant factor with only a tiny increase in implementation cost.

Although a similar performance increase through other means may be achieved, -e.g., executing a higher number of traditional microprocessor instructions per cycle -- these other means are generally prohibitively expensive for low-cost target applications. Additionally, use of m-bit operations, for example 32-bit operations, to manipulate small data items of n-bits where n<m is an inefficient use of m-bit execution hardware in the implementation.

Logic of conventional dsp or DSP (digital signal processing) operations calculates modulo values. Clipping or saturation operations of the present invention are especially valuable in signal processing applications where the processing generates data that may run beyond physical limits of the registers. Conventionally, when this occurs, data are mapped to the other end of the physically available range. In processing of signals, this cyclical mapping can be disastrous. For example, a very low audio volume would be mapped onto the highest using the conventional scheme. In control applications and in video/audio applications modulo values are not desirable when the control range or intensity range saturates.

SUMMARY OF THE PRESENT INVENTION

The present invention enhances a system, such as a PC system, to provide real-time multimedia capabilities while maintaining advantages of a special-purpose, embedded solution, i.e. low cost and chip count, and advantages of a general-purpose purpose processor-reprogramability. For PC applications, the present invention surpasses the capabilities of fixed-function multimedia chips.

Accordingly, one object of the present invention is to achieve extremely high multimedia performance at a low price.

A further object of the present invention is to increase processing speed in small kernels of applications.

A still further object of the present invention is to achieve full advantage of cache/memory bandwidth while not requiring an inordinate number of byte-manipulation instructions.

Another object of the present invention is to provide specialized, high-function operations to improve performance in multimedia applications.

A further object of the present invention is to provide custom operations which efficiently use specified bit execution hardware in implementation of operations.

A still further object of the present invention is to provide custom operations which may be, for example, tailored to specific applications such as multimedia applications.

Another object of the present invention is to use multiple operand registers storing multiple operands for parallel processing under control of a single instruction. This is particularly advantageous in audio and/or video applications where samples are currently 8 or 16 bits.

An object of the present invention is to use a clipping operation to keep received signals, such as audio or video signals, in the correct side of a truncated range.

The present invention can be used in low-cost, single-purpose purpose systems such as video phones to reprogrammable, multi-purpose purpose plug-in cards for traditional personal computers. Additionally, the present invention may be used in a system which easily implements popular multimedia standards such as MPEG-1 and MPEG-2. Moreover, orientation of the present invention around a powerful general-purpose CPU makes it capable of implementing a variety of multimedia algorithms, whether open or proprietary.

Defining software compatibility at a source-code level has an advantage of providing freedom to strike an optimum balance between cost and performance. Powerful compilers ensure that programmers never need to resort to non-portable assembler programming. The present invention allows programmers to use powerful low level operations from source code with dsp-like operations being invoked with a familiar function-call syntax.

A computer system includes input registers, each for receiving input data, each input data comprising M bits and operand data comprising N bits, where N is less than or equal to M; a processor for performing a set of operations on selected operand data, each set of operations comprising at least one operation and producing result data of N bits; and a destination register for storing the result data from each set of operations. The set of operations may include a clipping or saturation operation. Additionally, the set of operations may be performed in parallel and in response to an instruction of an instruction set.

Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

These objects as well as other objects of the present invention will be apparent from the description of the present invention including the aid of the following drawings:

FIG. 1 is a block diagram of an example system for use with the present invention;

FIG. 2 illustrates an example of CPU register architecture;

FIG. 3(a) illustrates an example of an organization of a matrix in memory;

FIG. 3(b) illustrates a task to be performed in the example;

FIG. 4 illustrates an application for a byte-matrix transposition using custom operations;

FIG. 5(a) and 5(b) illustrate a list of operations to perform the byte-matrix transposition shown in FIG. 4;

FIG. 6 illustrates a dspiadd operation;

FIG. 7 illustrates a dspuadd operation;

FIG. 8 illustrates a dspidualadd operation;

FIG. 9 illustrates a dspuquadaddui operation;

FIG. 10 illustrates a dspimul operation;

FIG. 11 illustrate a dspumul operation;

FIG. 12 illustrates a dspidualmul operation;

FIG. 13 illustrates a dspisub operation;

FIG. 14 illustrates a dspusub operation;

FIG. 15 illustrates a dspidualsub operation;

FIG. 16 illustrates an ifir16 operation;

FIG. 17 illustrates an ifir8ii operation;

FIG. 18 illustrates an ifir8ui operation;

FIG. 19 illustrates an ufir16 operation;

FIG. 20 illustrates an ufir8uu operation;

FIG. 21 illustrates a mergelsb operation;

FIG. 22 illustrates a mergemsb operation;

FIG. 23 illustrates a pack16lsb operation;

FIG. 24 illustrates a pack16msb operation;

FIG. 25 illustrates a packbytes operation;

FIG. 26 illustrates a quadavg operation;

FIG. 27 illustrates a quadumulmsb operation;

FIG. 28 illustrates an ume8ii operation;

FIG. 29 illustrates an ume8uu operation;

FIG. 30 illustrates an iclipi operation;

FIG. 31 illustrates an uclipi operation; and

FIG. 32 illustrates an uclipu operation.

DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 shows a block diagram of an example system for use with the present invention. This system includes a microprocessor, a block of synchronous dynamic RAM (SDRAM), and external circuitry needed to interface to incoming and/or outgoing multimedia data streams.

In this example, a 32-bit CPU forms a VLIW processor core. The CPU implements a 32-bit linear address space and 128 fully general-purpose 32-bit registers. In the present system, the registers are not separated into banks. Instead, any operation can use any register for any operand.

In this system, the CPU uses a VLIW instruction-set architecture allowing up to five simultaneous operations to be issued. These operations can target, in this example, any five of 27 functional units in the CPU, including integer and floating-point arithmetic units and data-parallel dsp-like units.

The operation set of a CPU utilizing the present invention may include traditional microprocessor operations in addition to multimedia-specific operations that dramatically accelerate standard video compression and decompression algorithms. A single special or "custom" operation, one of several operations issued in a single instruction, in this example five operations, can implement up to 11 traditional microprocessor operations. Multimedia-specific operations combined with VLIW, RISC, or other architecture result in tremendous throughput for multimedia applications. The present invention allows use of one register of 32, 64, 128, . . . , bits for data to perform these "multimedia", operations.

FIG. 2 illustrates one example of a CPU register architecture. The CPU of the present embodiment has 128 fully general-purpose 32-bit registers, labeled r0 . . . r127. In this embodiment, registers r0 and r1 are used for special purposes and registers r2 through r127 are true general purpose registers.

In the present system, the processor issues one long instruction every clock cycle. Each such instruction includes several operations (5 operations for the present embodiment). Each operation is comparable to a RISC machine instruction, except that execution of an operation is conditional upon the content of a general purpose register.

Data in the register may be in, for example, integer representation or floating point representation.

Integers may be considered, in the present embodiment, as `unsigned integers` or `signed integers`, as binary and two's complement bit patterns, respectively. Arithmetic on integers does not generate traps. If a result is not representable, the bit pattern returned is operation specific, as defined in the individual operation description section. The typical cases are: wrap around for regular add and subtract type operations, clamping against the minimum or maximum representable value for dsp-type operations or returning the least significant 32-bit value of a 64-bit result (e.g., integer/unsigned multiply).

Since the present embodiment is 32-bit architecture, it does not use floating point representation for values of data used in the multimedia operations. However, clearly for a 64-bit, 128-bit, . . . , architecture, floating point representation could be used for values of data used in the multimedia operations. For example, single precision (32-bit) IEEE-754 floating point arithmetic and/or double precision (64-bit) IEEE-754 floating point could be used to represent data values.

In the architecture of the present invention, all operations are optionally `guarded`. A guarded operation executes conditionally, depending on the value in a `guard` register (rguard). For example, a guarded integer add (iadd) is written as:

IF r23 iadd r14 r10.fwdarw.r13

In this example, "if r23 then r13:l =r14+r10". The `if r23` clause evaluates TRUE or FALSE depending on the LSB of the value in r23. Hence, depending on the LSB of r23, r13 is either unchanged or set to contain an integer sum of r4 and r10. For example, in this embodiment of the present invention, if the LSB is evaluated as 1, a destination register (rdest), in this example r13, is written. Guarding controls effects on programmer visible states of the system, i.e. register values, memory content and device state.

Memory in the present invention is byte addressable. Loads and stores are `naturally aligned`, i.e. a 16-bit load or store targets an address that is a multiple of 2. A 32-bit load or store targets an address that is a multiple of 4. One skilled in the art could easily modify this.

Compute operations are register-to-register operations. A specified operation is performed on one or two source registers and a result is written to a destination register (rdest).

Custom operations are special compute operations and are like normal compute operations; however, these custom operations are not found in general purpose CPUs. The custom operations advantageously allow performance of operations for, for example, multimedia applications. The custom operations of the present invention are specialized, high-function operations designed to dramatically improve performance in important multimedia applications as well as in other applications. When properly incorporated into application source code, custom operations enable an application to take advantage of a highly parallel microprocessor implementation such as a Trimedia TM-1 chip manufactured by Philips Electronics, of the present invention.

For both general-purpose and embedded microprocessor-based applications, programming in a high-level language may be desirable. To effectively support optimizing compilers and a simple programming model, certain microprocessor architecture features are needed, such as a large, linear address space, general-purpose registers, and register-to-register operations that directly support manipulation of linear address pointers.

The present invention allows use of the system's entire resources, such as, for example, 32-bit resources, to operate on two sixteen-bit data items or four eight-bit data items simultaneously. This use improves performance by a significant factor with only a tiny increase in implementation cost. Additionally, this use achieves a high execution rate from standard microprocessor resources.

Some high-function custom operations eliminate conditional branches, which helps a scheduler effectively use five operation slots in each instruction of the present system, for example, the Philips TM-1 chip with TM-1 instructions. Filling up all five slots is especially important in inner loops of computationally intensive multimedia applications. Custom operations help the present invention achieve extremely high multimedia performance at the lowest possible cost.

Table 1 is a listing of custom operations of the present invention. Some custom operations exist in several versions that differ in treatment of respective operands and results. Mnemonics for these different versions attempt to clarify the respective treatment to aid in selection of the appropriate operation, although clearly, different mnemonics or names could be assigned.

                  TABLE 1
    ______________________________________
    Custom operations listed by function type
    Function
           Custom Pop Description
    ______________________________________
    DSP    dspiabs    Clipped signed 32-bit absolute value
    absolute
           dspidualabs
                      Dual clipped absolute values of signed 16-
    value             bit halfwords
    DSP add
           dspiadd    Clipped signed 32-bit add
           dspuadd    Clipped unsigned 32-bit add
           dspidualadd
                      Dual clipped add of signed 16-
                      bit halfwords
           dspuquadaddui
                      Quad clipped add of unsigned/
                      signed bytes
    DSP    dspimul    Clipped signed 32-bit multiply
    multiply
           dspumul    Clipped unsigned 32-bit multiply
           dspidualmul
                      Dual clipped multiply of signed 16-
                      bit halfwords
    DSP    dspisub    Clipped signed 32-bit subtract
    subtract
           dspusub    Clipped unsigned 32-bit substract
           dspidualsub
                      Dual clipped subtract of signed 16-
                      bit halfwords
    Sum of ifir16     Signed sum of products of signed 16-
    products          bit halfwords
           ifir8ii    Signed sum of products of signed bytes
           ifir8ui    Signed sum of products of unsigned/
                      signed bytes
           ufir16     Unsigned sum of products of unsigned 16-
                      bit halfwords
           ufir8uu    Unsigned sum of products of unsigned bytes
    Merge  mergelsb   Merge least-significant bytes
           mergemsb   Merge most-significant bytes
    Pack   pack16lsb  Pack least-significant 16-bit halfwords
           pack16msb  Pack most-significant 16-bit halfwords
           packbytes  Pack least-significant bytes
    Byte   quadavg    Unsigned byte-wise quad average
    averages
    Byte   quadumulmsb
                      Unsigned quad 8-bit multiply most
    multiplies        significant
    Motion ume8ii     Unsigned sum of absolute values of signed
    estimation        8-bit differences
           ume8uu     Unsigned sum of absolute values of unsigned
                      8-bit differences
    Clipping
           iclipi     Clip signed to signed
           uclipi     Clip signed to unsigned
           uclipu     Clip unsigned to unsigned
    ______________________________________

    ______________________________________
            if rguard then {
              if rsrc1> = 0 then
                rdest .rarw. rsrc1
            else if rsrc1 = 0x800000000 then
                rdest .rarw. 0x7fffffff
            else
                rdest .rarw. rsrc1
            }
    ______________________________________

    ______________________________________
    if rguard then {
    temp1 .rarw. sign.sub.-- ext16to32 (rsrc1<15:0>)
    temp2 .rarw. sign.sub.-- ext16to32 (rsrc1<31:16>)
    if temp1 = 0xffff8000 then temp1 .rarw. 0x7fff
    if temp2 = 0xffff8000 then temp2 .rarw. 0x7fff
    if temp1 < 0 then temp1 .rarw. -temp1
    if temp2 < 0 then temp2 .rarw. -temp2
    rdest<31:16> .rarw. temp2<15:0>
    rdest<15:0> .rarw. temp1<15:0>
    ______________________________________

    ______________________________________
    if rguard then {
    temp .rarw. sign.sub.-- ext32to64 (rsrc1) + sgn.sub.-- ext32to64 (rsrc2)
    if temp < 0xffffffff80000000 then
    rdest .rarw. 0x80000000
    else if temp > 0x00000007fffffff then
    rdest .rarw. 0x7fffffff
    else
    rdest .rarw. temp
    ______________________________________

    ______________________________________
    if rguard then {
    temp .rarw. zero.sub.-- ext32to64 (rsrc1) +zero.sub.-- ext32to64 (rsrc2)
    if (unsigned) temp > 0x00000000ffffffff then
    rdest .rarw. 0xffffffff
    else
    rdest .rarw. temp<31:0>
    ______________________________________

    ______________________________________
    if rguard then {
    temp1 .rarw. sign.sub.-- ext16to32 (rsrc1<15:0>) +
    sign.sub.-- ext16to32 (rsrc2<15:0>)
    temp2 .rarw. sign.sub.-- ext16to32 (rsrc1<31:16>) +
    sign.sub.-- ext16to32 (rsrc2<31:16>)
    if temp1 < 0xffff8000 then temp1 .rarw. 0x8000
    if temp2 = 0xffff8000 then temp2 .rarw. 0x8000
    if temp1 > 0x7fff then temp1 .rarw. 0x7fff
    if temp2 < 0x7fff then temp2 .rarw. 0x7fff
    rdest<31:16> .rarw. temp2<15:0>
    rdest<15:0> .rarw. temp1<15:0>
    ______________________________________

    ______________________________________
    if rguard the {
    for (i.rarw.0,m.rarw.31,n.rarw.24;i<4;i.rarw.1+1,m.rarw.m-8,n.rarw.n-8)
            temp .rarw. zero.sub.-- ext8to32 (rsrc1<m:n>)
            +sign.sub.-- ext8to32 (rsrc2<m:n>)
    if temp < 0 then
            rdest<m:n> .rarw. 0
    else if temp > 0xff then
    rdest<m:n> .rarw.0xff
    else rdest<m:n> .rarw. temp<7:0>
    }
    ______________________________________

    ______________________________________
    if rguard then {
    temp .rarw.
    sign.sub.-- ext32to64 (rsrc1) +sign.sub.-- ext32to64 (rsrc2)
    if temp < 0xffffffff800000000 then
    rdest .rarw. 0x80000000
    else if temp > 0x000000007fffffff then
    rdest .rarw. 0x7fffffff
    else
    rdest .rarw. temp<31:0>
    ______________________________________

    ______________________________________
    if rguard then {
    temp .rarw. zero.sub.-- ext32to64 (rsrc1) .times.
              zero.sub.-- ext32to64 (rsrc2)
    if (unsigned) temp > 0x00000000ffffffff then
            rdest .rarw. 0xffffffff
    else
            rdest .rarw. temp<31:0>
    ______________________________________

    ______________________________________
    if rguard then {
    temp1 .rarw. sign.sub.-- ext16to32 (rsrc1<15:0>) .times.
    sign.sub.-- ext16to32 (rsrc2<15:0>)
    temp2 .rarw. sign.sub.-- ext16to32 (rsrc2<31:16>) .times.
    sign.sub.-- ext16to32 (rsrc2<31:16>)
    if temp1 < 0xffff8000 then temp1 .rarw. 0x8000
    if temp2 = 0xffff8000 then temp2 .rarw. 0x8000
    if temp1 > 0x7fff then temp1 .rarw. 0x7fff
    if temp2 < 0x7fff then temp2 .rarw. 0x7fff
    rdest<31:16> .rarw. temp2<15:0>
    rdest<15:0> .rarw. temp1<15:0>
    ______________________________________

    ______________________________________
           if rguard then {
            temp .rarw. sign.sub.-- ext32to64(rsrc1)-
    sign.sub.-- ext32to64(rsrc2)
            if temp < 0xffffffff80000000 then
             rdest .rarw. 08x0000000
            else if temp > 0x000000007fffffff then
             rdest .rarw. 0x7fffffff
            else
             rdest .rarw. temp<31:0>
           }
    ______________________________________

    ______________________________________
           if rguard then {
            temp .rarw. zero.sub.-- ext32to64(rsrc1)-
    zero.sub.-- ext32to64(rsrc2)
            if (signed)temp < 0 then
             rdest .rarw. 0
            else
             rdest .rarw. temp<31:0>
           }
    ______________________________________

    ______________________________________
    if rguard then {
     temp1 .rarw. sign.sub.-- ext16to32(rsrc1<15:0>)-
       sign.sub.-- ext16to32(rsrc2<15:0>)
     temp2 .rarw. sign.sub.-- ext16to32(rsrc1<31:16>)-
       sign.sub.-- ext16to32(rsrc2<31:16>)
     if temp1 < 0xffff8000 then temp1 .rarw. 0x8000
     if temp2 < 0xffff8000 then temp2 .rarw. 0x8000
     if temp1 > 0x7fff then temp1 .rarw. 0x7fff
     if temp2 > 0x7fff then temp2 .rarw. 0x7fff
     rdest<31:16> .rarw. temp2<15:0>
     rdest<15:0> .rarw. temp1<15:0>
    ______________________________________

    ______________________________________
    if rguard then
     rdest .rarw. sign.sub.-- ext16to32(rsrc1<31:16>).times.
      sign.sub.-- ext16to32(rsrc2<31:16>)+
      sign.sub.-- ext16to32(rsrc1<15:0>).times.
      sign.sub.-- ext16to32(rsrc2<15:0>)
    ______________________________________

    ______________________________________
           if rguard then
            rdest .rarw. sign.sub.-- ext8to32(rsrc1<31:24>).times.
             sign.sub.-- ext8to32(rsrc2<31:24>)+
             sign.sub.-- ext8to32(rsrc1<23:16>).times.
             sign.sub.-- ext8to32(rsrc2<23:16>)+
             sign.sub.-- ext8to32(rsrc1<15:8>).times.
             sign.sub.-- ext8to32(rsrc2<15:8>)+
             sign.sub.-- ext8to32(rsrc1<7:0>).times.
             sign.sub.-- ext8to32(rsrc2<7:0>)
    ______________________________________

    ______________________________________
           if rguard then
            rdest .rarw. zero.sub.-- ext8to32(rsrc1<31:24>).times.
             sign.sub.-- ext8to32(rsrc2<31:24>)+
             zero.sub.-- ext8to32(rsrc1<23:16>).times.
             sign.sub.-- ext8to32(rsrc2<23:16>)+
             zero.sub.-- ext8to32(rsrc1<15:8>).times.
             sign.sub.-- ext8to32(rsrc2<15:8>)+
             zero.sub.-- ext8to32(rsrc1<7:0>).times.
             sign.sub.-- ext8to32(rsrc2<7:0>)
    ______________________________________

    ______________________________________
    if rguard then {
     rdest .rarw. (zero.sub.-- ext16to32(rsrc1<31:16>).times.
      zero.sub.-- ext16to32(rsrc2<31:16>)+
      zero.sub.-- ext16to32(rsrc1<15:0>).times.
      zero.sub.-- ext16to32(rsrc2<15:0>)
    ______________________________________

    ______________________________________
           if rguard then {
            rdest .rarw. zero.sub.-- ext8to32(rsrc1<31:24>).times.
             zero.sub.-- ext8to32(rsrc2<31:24>)+
             zero.sub.-- ext8to32(rsrc1<23:16>).times.
             zero.sub.-- ext8to32(rsrc2<23:16>)+
             zero.sub.-- ext8to32(rsrc1<15:8>).times.
             zero.sub.-- ext8to32(rsrc2<15:8>)+
             zero.sub.-- ext8to32(rsrc1<7:0>).times.
             zero.sub.-- ext8to32(rsrc2<7:0>)
    ______________________________________

    ______________________________________
             if rguard then {
              rdest<7:0> .rarw. rsrc2<7:0>
              rdest<15:8> .rarw. rsrc1<7:0>
              rdest<23:16> .rarw. rsrc2<15:8>
              rdest<31:24> .rarw. rsrc1<15:8>
    ______________________________________

    ______________________________________
             if rguard then {
              rdest<7:0> .rarw. rsrc2<23:15>
              rdest<15:8> .rarw. rsrc1<23:15>
              rdest<23:16> .rarw. rsrc2<31:24>
              rdest<31:24> .rarw. rsrc1<31:24>
    ______________________________________

    ______________________________________
             if rguard then {
              rdest<15:0> .rarw. rsrc2<15:0>
              rdest<31:16> .rarw. rsrc1<15:0>
             }
    ______________________________________

    ______________________________________
            if rguard then {
              rdest<15:0> .rarw. rsrc2<31:16>
              rdest<31:16> .rarw. rsrc1<31:16>
            }
    ______________________________________

    ______________________________________
            if rguard then {
              rdest<7:0> .rarw. rsrc2<7:0>
              rdest<15:8> .rarw. rsrc1<7:0>
            }
    ______________________________________

    ______________________________________
    if rguard then {
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<7:0>) +
            zero.sub.-- ext8to32 (rsrc2<7:0>) + 1)/2
    rdest<7:0>.rarw.temp<7:0>
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<15:8>) +
            zero.sub.-- ext8to32 (rsrc2<15:8>) + 1)/2
    rdest<15:8>.rarw.temp<7:0>
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<23:16>) +
            zero.sub.-- ext8to32 (rsrc2<23:16>) + 1)/2
    rdest<23:16>.rarw.temp<7:0>
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<31:24>) +
            zero.sub.-- ext8to32 (rsrc2<31:24>) + 1)/2
    rdest<31:24>.rarw.temp<7:0>
    ______________________________________

    ______________________________________
    if rguard then {
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<7:0>) .times.
            zero.sub.-- ext8to32 (rsrc2<7:0>) )
    rdest<7:0>.rarw.temp<15:8>
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<15:8>) .times.
            zero.sub.-- ext8to32 (rsrc2<15:8>) )
    rdest<15:8>.rarw.temp<15:8>
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<23:16>) .times.
            zero.sub.-- ext8to32 (rsrc2<23:16>) )
    rdest<23:16>.rarw.temp<15:8>
    temp .rarw. (zero.sub.-- ext8to32 (rsrc1<31:24>) .times.
            zero.sub.-- ext8to32 (rsrc2<31:24>) )
    rdest<31:24>.rarw.temp<15:8>
    ______________________________________

    ______________________________________
    if rguard then
    rdest .rarw. abs.sub.-- val (sign.sub.-- ext8to32 (rsrc1<31:24>) -
    sign.sub.-- ext8to32 (rsrc2<31:24>)) +
    abs.sub.-- val (sign.sub.-- ext8to32 (rsrc1<23:16>) -
    sign.sub.-- ext8to32 (rsrc2<23:16>)) +
    abs.sub.-- val (sign.sub.-- ext8to32 (rsrc1<15:8>) -
    sign.sub.-- ext8to32 (rsrc2<15:8>)) +
    abs.sub.-- val (sign.sub.-- ext8to32 (rsrc1<7:0>) -
    sign.sub.-- ext8to32 (rsrc2<7:0>))
    ______________________________________

    ______________________________________
    if rguard then
    rdest .rarw. abs.sub.-- val (zero.sub.-- ext8to32 (rsrc1<31:24>) -
    zero.sub.-- ext8to32 (rsrc2<31:24>)) +
    abs.sub.-- val (zero.sub.-- ext8to32 (rsrc1<23:16>) -
    zero.sub.-- ext8to32 (rsrc2<23:16>)) +
    abs.sub.-- val (zero.sub.-- ext8to32 (rsrc1<15:8>) -
    zero.sub.-- ext8to32 (rsrc2<15:8>)) +
    abs.sub.-- val (zero.sub.-- ext8to32 (rsrc1<7:0>) -
    zero.sub.-- ext8to32 (rsrc2<7:0>))
    ______________________________________

    ______________________________________
    if rguard then
            rdest .rarw. min (max (rsrc1, - rsrc2-1), rsrc2)
    ______________________________________

    ______________________________________
    if rguard then
            rdest .rarw. min (max (rsrc1, 0), rsrc2)
    ______________________________________

    ______________________________________
              if rguard then {
                if rsrc1 > rsrc2 then
                  rdest .rarw. rsrc2
                else
                  rdest.rarw.rsrc1
            }
    ______________________________________

• Inventors
  Slavenburg, Gerrit Ary; van der Meulen, Pieter; Cho, Yong; Mehra, Vijay K.; Lee, Yen C.;
• Assignee
  Philips Electronics North America Corporation (New York, NY)
• Published
  Oct-5-1999
• Current US Classes:
  345/505
  382/304
  708/200
  708/626
  712/22
  712/9
  715/500.1
• Application #
  836852
• International Classes
  G06F 015/16; G06F 015/80; G06F 017/16
• Field of Search
  395/800.09 395/800.23 395/800.24 395/800.36 345/434 345/439 345/505 345/519 364/715.011 364/715.07 364/715.08 364/716.07 364/736.04 364/745.01 364/748.02 364/758 382/166 382/232 382/300 382/304
• Examiner
  An; Meng-Ai T.
• Agent
  Halajian; Dicran
• US Patent References:
  4734850
  4931950
  5103311
  5239654
  5313551
  5392396
  5450556
  5497373
  5509129
  5569869
  5579253
  5692139
  5740340
  5774600
  5798753