Video display controller, user interface and programming structure for such interface5657091Abstract The use of video/audio signal streams such as in the past have been distributed by broadcast over radio frequency bands or by cable distribution, or made available from video recorder/player devices such as cassette recorders or video disc players, or made available from direct, live sources such as cameras, game systems or computers. In accordance with this invention, programs stored in memory devices associated with microcontrollers controlling the display to a user are constructed in a language which uses layered statements, each of which can have a description portion, an action portion, and a unique connecting character. Claims What is claimed is: Description RELATED APPLICATIONS
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Clocks per pixel
five four three two one
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Bits per pixel
four 160 128 96 64 39
eight 80 64 48 32 16
sixteen 40 32 24 16 n/a
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The horizontal fetch end register determines where video fetches end on the line. In principle, this is the value in horizontal display end minus the above constant. However, horizontal fetch begin should be rounded up so that horizontal fetch end register minus the horizontal fetch begin register is a multiple of the above constant. The horizontal vertical sync is identified as wider sync pulses occurring on a number of lines. The width of these pulses is determined by the horizontal vertical sync register which should be programmed as follows: horizontal vertical sync=horizontal period-(vertical sync width.times.clock frequency). The video/memory controller 78 also has a large number of vertical registers: the vertical period register, the vertical sync register, the vertical blanking end register, the vertical blanking begin register, the vertical display begin register, the vertical display end register, the video interrupt register and the light pen registers. The vertical period register specifies the number of video lines per field. The vertical sync register determines the number of lines on which vertical sync is generated. It should be programmed as follows: vertical sync=vertical period-lines of vertical sync. The vertical blanking end register determines how many lines are blanked after a vertical sync. The vertical blanking begin register determines how many lines are blanked before vertical sync. It should be programmed as follows: vertical blanking begin=vertical sync-lines of blanking prior to vertical sync. The vertical display begin register determines the first line of active video. If this register is greater than the vertical blanking end register the lines in-between show the border color. To position the active area in the middle of the screen this register should be programmed as follows: vertical display begin=(vertical blanking end+vertical blanking begin-number of active lines)/2. The vertical display end register determines the last line of active video. If this register is less than the vertical blanking begin register the lines in-between will show the border color. To position the active area in the middle of the screen this register should be programmed as follows: vertical display end=(vertical blanking end+vertical blanking begin+number of active lines)/2. The video interrupt register determines the video line on which a video interrupt is generated. This interrupt may be enabled or disabled through the INT register. The interrupt occurs when the video mechanism stops at the end of the display line. It may be used by the processor to change display modes or to perform beam synchronous animation. The register may be reprogrammed within a field to provide several interrupts per field. The following table provides typical values for the above registers for the various display formats shown. After loading the registers with the below values, the video timing generator is enabled by setting the VIDEN bit in the register MODE2.
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50 Hz PAL
60 Hz NTSC
VGA
320 .times. 256,
320 .times. 220,
640 .times. 480,
8-bits 8-bits 8-bits
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Clock frequency
22.17 MHz 21.48 MHz 25.17 MHz
Horizontal period
1418 1363 790
Horizontal sync
1314 1262 703
Horizontal blanking end
126 103 48
Horizontal blanking begin
1271 1232 688
Horizontal display begin
378 348 48
Horizontal display end
1018 988 688
Horizontal fetch begin
346 316 32
Horizontal fetch end
986 956 672
Horizontal vertical sync
103 89 0
Vertical period
312 262 525
Vertical sync 309 259 524
Vertical blanking end
20 15 34
Vertical blanking begin
307 257 514
Vertical display begin
35 26 34
Vertical display end
291 246 514
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The video/memory controller 78 has three color resolutions available: four bits per pixel, eight bits per pixel, and 16 bits per pixel. In four- and eight-bit modes, the pixel is a logical color that indexes an 18-bit physical color stored in the palette. In 16-bit mode, the pixel is a physical color in which bits zero to four are blue, bits five to ten are green and bits 11 to 15 are red. Because there are six bits of green but only five bits of blue and red, the least significant bits of blue and red output from the chip are always logical ZERO in 16-bit mode. The border color is a 16-bit register which is displayed as a 16-bit pixel. In eight-bit mode, the pixel addresses the whole 256 by 18 palette. In four-bit mode the pixel addresses 16 entries from the palette in which case the top four bits of the addresses are supplied from the index register. Two variations are available in eight-bit mode. In color hold mode if the pixel takes the value zero, then the color of the previous pixel is displayed. This can be used to fill large areas of color simply by setting the left most pixel. In variable resolution mode, the most significant pixel determines whether the pixel is displayed as one seven-bit pixel or two three-bit pixels. If the bit is clear, the pixel is displayed as one seven-bit pixel; if the bit is set then bits zero to two are displayed first followed by bits four to six. In this case, the two high resolution pixels address eight entries from the palette. The top five bits of the address are supplied from the index register. Variable resolution mode is useful for displaying small regions of high resolution text amid a lower resolution, but more colorful, background. This mode is not available in one clock per pixel resolution. In eight-bit mode any of the bits can be sacrificed and used for other purposes. For instance, a bit could be used to identify "hot spots" for collision detection. Alternatively, bits could be used to encode image "depth" so that one image can move in front of or behind another. To sacrifice a bit, the same bit in a masked register is set and that bit will be replaced from the corresponding bit in the index register. There are five widths of pixel: one clock, two clocks, three clocks, four clocks, and five clocks. These correspond to dot clocks of around 24 MHz, 12 MHz, and 6 MHz. The highest dot clock may not be used with the 16 bits per pixel display mode. Two other combinations: one clock 8-bit and two clock 16-bit may only be used if 32-bit DRAM is fitted. If external hardware is fitted as will be in the applications here described, the video processor 39 can gen-lock to an external video source and mix (encrust) local video with external video on a pixel by pixel basis. This is significant with regard to certain display to be generated in accordance with this invention as described more fully hereinafter. The memory map of the screen is not tied to the video display width but is defined independently. The base address of the screen can be anywhere in system memory 45. The width of the screen memory is the power of 2 from 128 to 2048 bytes. The height of the screen is a power of 2 from 32K to 2 megabytes. Video addresses on the same line wrap within the smaller boundary. This arrangement allows the screen to be placed within a larger virtual screen and panned and scrolled within it. Various registers control the video modes discussed above. The video mode register controls the features listed above. Bits zero and one determine the number of bits per pixel. Bits two and three determine the pixel width in clock cycles. Bits four through six determine the first break in the video address and hence the display width in bytes. Bits seven through nine determine the second break in the video address and hence the display height in bytes. Bit ten turns the sync outputs into inputs which can reset the horizontal and vertical timers for rapid locking to an external video source. Bit 11 controls encrustation, which is the overlaying of an external video source using an external video multiplexer. The multiplexer is controlled by the "INC" pin of the NV/CD controller/coprocessor. Selected bits of the color are used to control encrustation. Bit 12 controls border encrustation, which is the same as bit 11 but only applied to border colors. Bit 13 sets a variable resolution mode. Bit 14 sets the color hold mode, in which color 0 is replaced by previous non-zero color in current scan line. Bit 15 enables Pixel clock widths of three and five based on Bits 2, 3, and 15, as shown in the table below.
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Bit 2 Bit 3 Bit 15 Pixel Clock
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0 0 0 Four clock cycles/Pixel
1 0 1 Two Clock Cycles/Pixel
0 1 0 One Clock Cycles/Pixel
1 1 0 Undefined
0 0 1 Three Clock Cycles/Pixel
1 0 1 Five Clock Cycles/Pixel
0 1 1 Undefined
1 1 1 Undefined
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The video/memory controller 78 also has a pixel mask register and a palette index register. For every bit set in the mast register, the corresponding bit in the pixel is replaced by the bit from the index register. The upper bits in the index register form the high part of the palette address for 4-bit pixels. The border color register is a 16-bit register that defines the border color. The color is displayed in the same way as 16-bit pixels: bits zero to four are blue, bits five to ten are green, and bits 11 to 15 are red. The video/memory controller 78 also has two screen address registers that define the 24-bit base address of the screen in system memory 45. This is the address of the top left pixel on the screen. The video/memory controller 78 also has an auxiliary video mode register MODE2 that provides additional control over video and various test logic. Bit zero enables the light-pen registers so that the horizontal and vertical counters can be read. Bit two enables the video timer, bits three and four determine the refresh frequency with one indicating a refresh frequency of clock/128, two indicating a refresh frequency of clock/256, and three indicating a refresh frequency of clock/512. Most DRAMs require a refresh frequency of 64 KHz or above. The refresh controller waits until eight or more refresh cycles are required then requests the SYSTEM' bus and does the required number of CAS before RAS cycles. When bit six is set, the video mode is double buffered and can only change during blanking. The CPU 48 sets this bit for clean mode changes in split screen operation. Bit seven inverts the polarity of vertical sync. Bit eight inverts the polarity of horizontal sync and bit nine is not used. The palate is a 256 by 18 bit block of RAM at F10000H-F103FFH. Each entry contains six bits each of green, red, green and blue. Each entry extends across two words. The blue and green bits appear in the high word. The red bits appear in the low word. Bits two through seven of the high word are blue; bits 10 through 15 of the high are green and bits two through seven of the low word are red. To write to an entry in the palette, the CPU 48 must first write the red bits to the low word, then the green and blue bits to the high word. The CPU 48 should only write to the palette during border or blanking or speckles will appear on the video. The cache 69 is not a cache in the sense that it prefetches instructions for the CPU 48. Rather, the cache 69 is a 512.times.16-bit static RAM located at F14000H to F143FFH that can be used by the CPU 48 for variables, stack, or program code to speed up program execution. It comprises static RAM and is not subject to page faults. Placing data, stack, or program code in the cache 62 allows quicker accesses and fewer page faults. In this embodiment, the cache is small and byte writes are not allowed to the cache area. Interrupt service routines may not push bytes onto the stack. Video/memory controller 78 supports six interrupt sources: video input interrupt, three analog interrupts, CD block decoder interrupt, and a DSP 61 interrupt. The analog interrupts allow simple analog-to-digital converters to be implemented. A monostable vibrator is implemented from a diode, a capacitor, and a potentiometer. The capacitor is discharged by vertical sync and begins charging at a rate dependent on the potentiometer setting. When the voltage on the capacitor reaches the threshold of the input to the video processor 39, an interrupt is generated. The processor can then read the vertical counter to get a measure of how quickly the capacitor charged, an hence the potentiometer setting. The video/memory controller 78 also has an interrupt enable register allowing all six interrupts to be independently enabled or disabled. Writing a logical ONE to any bit in the interrupt acknowledge write register clears the corresponding interrupt. The interrupt read register reflects all pending interrupts. The video/memory controller 78 decodes the 16 megabyte address range of the 80376 CPU 48 into the following memory map: eight megabytes of DRAM0 (0H-7FFFFFH), seven megabytes of DRAM1 (800000H-EFFFFFH), 64 kilobytes of ROM0 (F00000H-FOFFFFH), 64K of internal memory (F10000H-F1FFFFH), and a 896K block of ROM1 (F20000H-FFFFFFH). The 64 kilobytes of internal memory comprises palette RAM, blitter registers, and DSP registers and memory. The palette address range was stated above. The blitter registers extend from the range F10400H to F107FFH. The DSP memory extends from F10800H to F18000H. The on-board screen RAM and system RAM is 512K of DRAM. The on-board DRAM comprising the screen/system RAM may be either 16-bits or 32-bits wide. Suitable DRAM are the TCS14170BJ 256 kilobyte by 16-bit memory chip, manufactured by Toshiba. The size of the DRAM is determined by the video processor 39 during reset but does not directly affect the CPU 48. Instead, it allows the video/memory controller 78 to operate more quickly leaving more bandwidth available to other bus master candidates. Certain display and blitter modes are only possible with 32-bit memory. Two banks of DRAM may be attached, as indicated above. If small amounts of DRAM are attached, then they will be repeated throughout the memory map shown above. The bootstrap ROM is always 16 bits wide. The bootstrap ROM comprises two 27C512 erasable programmable read-only memories, manufactured by numerous manufacturers, thereby giving 128K of bootstrap ROM. Following a reset, the one megabyte window from F20000H to FFFFFFH containing ROM and internal memory is repeated throughout the 16 megabyte address range. This allows for a variety of processors to boot with the video processor 39. The memory map above is adopted the first time with the memory type register is written to by the CPU 48. The video/memory controller 78 performs page mode cycles on the system memory 45 wherever possible. These are quicker than normal memory cycles and occur if successive reads and writes are within the same page. The video/memory controller 78 needs to know the number of columns in the DRAM, which is programmed in the memory type register. In the memory type register, bit 0 and 1 determine the number of columns in the DRAM, with 0 indicating 256 columns, 1 indicating 512, 2 indicating 1024, and 3 indicating 2048. The video/memory controller 78 supports seven types of transfers: a normal DRAM cycle (4 clocks), a page mode DRAM cycle (two clocks), ROM cycles (6 clocks), internal memory (2 clocks), external I/O (6 clocks), interrupt acknowledge (2 clocks), and internal I/O (2 clocks). The CPU 48 will cycle in one more clock cycle than the actual transfer. Internal bus masters can cycle in the transfer time. The video/memory controller 78 uses a crystal oscillator for a crystal that is the 2X (2 times speed) clock for the CPU 48 and is a multiple of the television chrominance (chroma) subcarrier. This crystal clock is buffered and output to the CPU 48. The same clock is put through a divide by two and this is output as the main system clock. This clock is input to the video processor 39 through a separate pin. The reason for outputting and inputting the clock is so that the relative skew between the CPU 2X clock and the main system clock, can be adjusted one way or the other by adding small delays to either path. The crystal frequency also is divided by a programmable divider which can divide the crystal frequency by a number between 1 and 15 and produce an output waveform with an even mark to space ratio. This is used as the television color subcarrier. The chroma divider register is a 4-bit register that defines the ratio of the television color subcarrier (chroma) to the 2X crystal frequency. It should be programmed as follows: chroma=2X crystal frequency/chroma frequency-1. The video/memory controller 78 also has a status register. If the status register bit 0 is set, the video timing should be set up for PAL (European television signal standard). If bit 0 of the status register is clear, then the video timing should be set up for NTSC. If bit 1 of the status register has been set, then there has been a light-pen input in the current field. This bit is set by the light-pen and cleared by the vertical sync. The video/memory controller 78 can be put into a mode during reset after which it only responds to two-word wide I/O locations and 64K memory locations. The actual location of the I/O locations is determined by a chip select input so the locations can be determined externally. This "peephole" mode allows the video processor 39 to occupy only small gaps in the I/O and address memory map of the system 30. The registers are 32-bits wide and must, therefore, be accessed as two 16-bit accesses. To address all the I/O registers within the video processor 39, the regular I/O address of the required register is first written to the lower word (a[1]low) then that register can be read or written at the upper word (a[1]high). To address all the memory inside and outside the video processor 39 the 64K window can be moved to any 64K boundary in the 16M address space normally decoded by the video/memory controller 78 by writing to the bank register. The bank register is an eight-bit register providing the eight most significant bits when addressing memory in peephole mode. For example, to access the palette, formerly at F10000H, the CPU 48 must write 0F1H to the bank register and then read and write at the bottom of the peephole location, determined by the external chip select. The blitter 72 is a graphical coprocessor whose purpose is to perform graphics creation and animation as fast as possible (limited by the memory bandwidth). It executes commands written by the CPU 48 and the DSP 61 into memory. It can perform arbitrarily long sequences of graphics operations by reading new command sets from system memory 45. While it is performing graphics operations, the blitter 72 becomes a SYSTEM' bus master, and denies the CPU 48 any bus activity whatsoever. This is reasonable because the blitter 72 is being used to perform operations that the CPU 48 would otherwise have performed, and is therefore speeding up program operation. This also removes the need for any synchronous control programming for blitting operations and the need for any interrupt generation hardware in the blitter 72. However, to allow real time programming of either of the other two processors (the DSP 61 and the compact disc DMA), the blitter 72 will suspend its operation and grant the SYSTEM' bus to the DSP 61 or the compact disc DMA channels if they require a DMA transfer. It will also suspend itself and give up the SYSTEM' bus to the CPU 48 if an interrupt occurs. During any of these transfers, the current operation is suspended but will restart when the interrupt signal becomes inactive or when the DSP 61 DMA access completes. The operation of the blitter 72 is best viewed as a simple program:
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read command from memory
for n=0 to outer.sub.-- count
read parameters from memory
for m=0 to inner.sub.-- count
if SRCEN then read source from memory
if DSTEN then read destination from memory
write destination to memory
next m
next n
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The commands and operands are written to memory by either the CPU 48 or the DSP 61. The blitter 72 has several registers in the video processor 39 I/O space: (1) two writable blitter program address registers, which share the same I/O address as two readable blitter destination registers, (2) a writable blitter command register, which shares the same I/O address as a first readable blitter source address register, (3) a writable blitter control register, which shares the same I/O address as a second readable blitter source address register, (4) a readable inner count register, (5) a first writable blitter diagnostics register, which shares the same I/O address as a readable blitter outer count register, (6) a second writable blitter diagnostics register, which shares the same I/O address as a readable blitter status register, and (7) a third writable blitter diagnostics register. The blitter 72 may be operated in a variety of modes to perform graphics and block move operations. The blitter 72 has an internal architecture divided into three largely separate blocks: the data path, the address generator, and the sequencer. The data path contains three data registers: the source data register, the destination data register, and the pattern data register. The data path also contains a versatile comparator to allow intelligent blitting operations, and a logic function unit (LFU) to generate the output data. The address generator contains three address registers: these are the program address register used to fetch blitter commands, and the source register and the destination address registers. It also contains an arithmetic logic unit (ALU) with an associated step register to update addresses, and a multiplexer to generate the output address. The sequencer acts in software terms as the program that the blitter 72 runs, with two loops (an inner loop and an outer loop) and a several procedures, as illustrated above with the short simple program. The program is fixed, although various parts of its operation are conditional upon flags in the blitter command register and the loop counts are also part of the command. The data path contains three data registers and two data manipulation blocks: the logic function unit, which can combine the contents of the data registers in a number of useful ways to produce the output data, and the comparator, which can perform certain comparisons on the data to inhibit write operations, and optionally stop blitter operation. The data path can handle data of four sizes: 32-bit, 16-bit, 8-bit, and 4-bit. Long words (32-bits wide) are used when performing fast block moves and fills. Pixels (4-, 8-, or 16-bits wide) may be manipulated using all the blitter modes, such as line-drawing, multiple plane operations, character painting, etc. The majority of the data path is 16-bits wide, which is the maximum screen pixel size. However, the source data register is 32-bits wide, and the top 16-bits of the source data register are used to produce the top 16-bits of the data written in 32-bit mode, regardless of the mode of the logical function unit. Thus, there are two 16-bit wide registers (pattern data and destination data) and one 32-bit wide data register (source data register). The source and destination data registers are loaded from the source and destination addresses in system memory 45 when the corresponding read cycles are enabled in the inner loop. However, all three data registers are loaded at the start of blitter operation with the pattern data, and this may be used as an additional source of data, either in producing the output data or in the comparator. For example, the data in the pattern data register could be a mask, a pattern for writing, or a reference value, for example. The pattern data is loaded into both words of the source data register. The logic function unit generates the output data, which is written to the destination in system memory 45. It can perform any logical combination of the source and destination register pixels. "Source data pixels" may be selected from either of the source data register or the data pattern data register. The LFU selects any of the four Boolean minterms (A & B, A & B, A & B, and A & B) of the two sets of input data from the data registers, and generates the logical OR of the two selected minterms. This allows any logical combination of input data; thus 16 functional possibilities exist. In 32-bit mode, the LFU will normally be set to produce source data, because it is only 16-bits wide. The upper sixteen bits written during a long-word write are always derived from the top sixteen bits of the source register. The comparator can perform a variety of comparisons on the data in the source, destination, and pattern data registers. If its comparison conditions are met, then it generates an inhibit signal. The inhibit signal is used to inhibit a write operation, and optionally, to stop the blitting operation. The comparator may also be used to provide a pixel plane effect, to give transparent colors, for collision detection and system memory 45 search operations, and as an aid to character painting. A multiple plane operation is supported by assigning a plane number to every pixel. This mode is only applicable to 4 and 8-bit pixels. In 8-bit pixel mode, two of the 8 bits (bits 6 & 7) are used giving two or four planes; in 4-bit (nibble) pixel mode, one of the 4 bits (bit 3 & bit 7 of the two-nibble byte) is used giving two planes. The comparator can produce an inhibit output if the plane number of the destination data is not equal to or greater than the plane number of the source data, or any combination of these. This means the data being written onto the screen can be masked by data already present in a different plane. The comparator can produce and inhibit output if the entire source pixel is equal to or not equal to the destination pixel. This may be used, for example, for searching system memory 45 for a particular value and, more importantly, for designating a color to be transparent and holding the transparent color value in a data register. This applies to 16-, 8-, or 4-bit pixels. The blitter 72 also has a comparator bit to pixel expansion mode operation. This comparator operation allows bit to pixel expansion of data, used, for example, for character painting. In this mode, the comparator selects a bit of the source byte based on the value of the inner counter and inhibits the write operation if this bit is a logical ZERO. The blitter 72 makes provision for handling three pixel resolution modes. These are: 16-bit mode where each word corresponds to one pixel, 8-bit mode, where each byte corresponds to one pixel, and 4-bit mode, where each byte corresponds to two pixels. In 8- and 16-bit pixel modes, the data path is handling one pixel at a time, and operation is straight forward. In 4-bit pixel mode, however, only half of the byte that is read from or written to system memory is the current pixel, therefore, certain additional requirements are placed on the data path. In a 4-bit mode write operation, unchanged destination data is written to the half of the data byte that does not correspond to the current pixel. Thus, destination reads must always be enabled in 4-bit mode (set control bit DSTEN). This must be done because there is no provision for writing less than one byte into main memory. It is also possible that the source 4-bit pixel address and the destination 4-bit pixel address point in different halves of the corresponding bytes of RAM. If this is the case, a shifter swaps the two halves of the source data. In 4-bit mode, the two nibbles (half a byte; 4 bits) of the pattern byte should normally be set to the same value. Note that the pixel with program in the blitter 72 does not have to match the display width, and the most efficient way of moving large amounts of data is 32-bit mode. Recall that such mode transfers must be long-word aligned and the system must be fitted with 32-bit RAM. The blitter 72 also has an address generator. The address generator contains three address registers, an increment or step register, an address adder, and an address output multiplexer. The three address registers hold the source address, the destination address, and the program address. Each of these registers is a 24-bit register allowing the blitter 72 to address up to 16 megabytes. In addition, the source and destination address registers contain a nibble bit used in 4-bit pixel mode. The program address register holds the address that the program is fetched from, and is incremented by one word each time a memory cycle is performed using it. This register is always even, thus, bit 0 must always be a logical ZERO. The source and destination address registers are updated after each cycle, and at other times, using an adder that allows them considerable flexibility in the objects to which they refer. All source and destination address updates, may be performed optionally on just the bottom 16 to 19 bits of the address register. This means that the blitter 72 will then effectively operate in 64K, 128K, 256K, or 512K pages. In this mode, if an address overflows within a page, it will wrap and the overflow or underflow will be lost. The blitter 72 also has an address adder, which is a 25-bit wide adder used to update addresses. It allows either a constant value of 0.5, 1, or 2 or a variable stored in one of the step registers, to be added to an address value. It can also subtract the same values. The 25th bit is the nibble part of the addresses, as stated above. An increment of one pixel has a different effect on the address depending on the current setting of the screen resolution. All address registers are updated automatically at the end of the appropriate memory cycles; source read for the source of address register, and destination write for destination address register. Addresses can be made to wrap vertically by using the SWRAP and DWRAP bits in the blitter command, and horizontally by using the SLWRAP and DLWRAP bits in the blitter control register. The address output multiplexer provides the external address to the system memory 45. It provides three types of addresses: source address, destination address, and the program address. These are derived directly from the corresponding address registers. When the blitter 72 is drawing lines, the address registers are used in a different way than normal. The destination address register is used as the line draw address, and the source address register and the step register are used as delta one and delta two respectively. During line drawing delta two is subtracted from delta one, and the borrow output produced is used to determine what is added to the destination address register. For further details, see the section on line drawing below. The blitter 72 also has a sequencer which controls the operation of the blitter 72. The flow of control is best considered at two levels. There is an outer loop governing the overall flow of control and an inner loop which performs the actual blitting or line drawing operation. The three sections within the outer loop: the command read procedure, the parameter read procedure, and the inner loop. The inner loop performs the actual blitting or line drawing operations. An inner loop cycle can contain up to three memory cycles. These are a read from the source address, a read from the destination address, and a write to the destination address. All three cycles are optional. If the loop includes a source read, or a source read and a destination read, then the comparator inhibit mechanism is tested before the destination write occurs. This allows the write cycles to be bypassed when a comparator inhibit condition is met. When the comparator inhibit conditions are met, it is possible to have the current operations cease and control returned to the CPU 48. The program may then examine the address registers to determine where the inhibit has occurred, so that collision detection may be performed. The CPU 48 may then determine whether to resume the operation or abort it. The inner loop performs operations until the inner loop counter reaches zero. The inner loop counter is a 10-bit counter, so the inner loop can iterate any number of times from 1 to 1024. The blitter 72 makes provision for collision detection by allowing operation to stop when a comparator write inhibit occurs. When this happens, control returns to the CPU 48, which may then examine the internal state of the blitter 72 to determine what has caused the collision. At this point, the CPU 48 may choose to allow the blitter 72 to resume the operation it was performing, or may reset it back to its idle state. Either a reset or a resume command must be issued before the blitter 72 may be used for another operation. Note that while the blitter 72 is in the suspended state, a new value may be written to the command register, so that the collision stop mechanism may be disabled. The parameter read procedure is a very straightforward sequence that loads a new set of parameters to the inner loop. It reads from memory, in order, the inner loop counter value, the step register values, and the pattern value, which is used to preset the data registers. The inner count effectively becomes the number of times the inner loop is executed. The step registers are used for address incrementing and the pattern register is used for data manipulation. The parameter read procedure is called as part of a command read procedure at the start of a blitting operation and is also called if required by a blitting operation, as determined by the PARRD control bit. Extra parameter reads occur between passes through the inner loop to allow parameters to be altered, thereby allowing operations such as irregular shape painting and run-length encoded data decompression. The command read procedure is used to start a new blitting operation. The blitter 72 starts in an inactive reset state, which represents the normal inactive state of the blitter 72. From this state a command register write is performed to start the blitter 72, usually preceded by a write to the program address register. A full set of operational parameters is loaded from program count address which is auto-incremented, and control passes out of the command read loop. When a blitting operation is complete, a new command is read from the program count address and if this command leaves the blitter 72 in run mode, then a new set of parameters is loaded and another operation is started. Otherwise the blitter 72 enters its stopped state and returns the SYSTEM' bus to the CPU 48. The above mechanism allows the blitter 72 to perform arbitrarily long sequences of graphics commands without requiring any processor intervention. This is extremely useful because processor I/O write cycles are relatively slow in comparison to blitter memory reads. Normal operation of the outer loop starts on exit from the command read loop. The parameter read loop is then entered to read the first set of parameters and the inner loop is entered with the inner counter being loaded to its initial value before the start of operation. The outer counter is then decremented, and, if it is zero, the command read loop is entered. Then either or both of the source address and destination address registered may be updated with the contents of the step register. The parameter read loop may then be optionally entered to update various inner loop parameters, before the inner loop is entered again. The two loops allow the blitter 72 to perform operations on with two-dimensional screen structures, with the outer loop address register updates moving screen address pointers onto the start of the structure on the next line. The parameter read loop adds flexibility while allowing the screen structure parameters to be altered on a line-by-line basis. The blitter 72 also has a memory interface state machine, which controls the cycle timing generation and the bus arbitration of all memory cycles. The blitter 72 assumes control over the SYSTEM' bus from the CPU 48 for the duration of a blitter command sequence. This is subject to the bus handover latency discussed above, but as soon as the blitter 72 is granted the SYSTEM' bus its operation will start. The memory interface will give up the SYSTEM' bus to the DSP 61 or the compact disc read channel as soon as one of these requests the SYSTEM' bus, pausing only to complete any current memory cycle. Interrupts will also cause the blitter 72 to suspend operation, unless masked in the blitter control register. The blitter 72 detects the state of the interrupt line itself and uses this to suspend operation. Operation will resume as soon as the interrupt line resumes to its prior state, which occurs when the CPU 48 write to the acknowledge port occurs. This may not be necessarily the end of the interrupt service routine, therefore programmers should be wary of stack crawl, and should normally keep interrupts disabled during a service routine. The blitter 72 resumes operation as soon as the interrupt line is cleared without intervention from the CPU 48. The blitter 72 only responds to the internal interrupt sources (the video interrupt the analog input interrupts and compact disk interrupts). Any external CPU interrupt source has no effect on the blitter 72. The blitter 72 has numerous modes of operation. The simplest operations performed by the blitter 72 are those involving copying one block of system memory 45 to another and filling a block of system memory 45 with a predefined value. These operations can be performed on linear parts of system memory 45 and on arbitrary screen rectangles. The destination data register is used as the address of the system memory 45 being modified and the source address register is used as the address of the data being copied, if it is a copy operation. When the operation is to be performed on linear areas of memory, most of the address control bits will be set to zero. The step register is not used, and the only requirement is to determine whether the copy will be made with the address incrementing or decrementing, in setting DSIGN and SSIGN appropriately. Note that the initial value placed in the address register should be the bottom of the area upon which the operation is to be performed if the sign bit is not set and at the top if it is set. In both cases, the first pixel read or written will be the first address. The length of the operation will be placed in the inner counter and the outer counter set to one. If the block being operated upon is very large both the inner loop and outer loop counters may have to be used and the number of pixels operating on will be given by the product of the inter and outer counter values. When either or both of the source and destination data are rectangles rather than linear areas, then the inner loop counter will contain the rectangle width and the outer loop counter the rectangle height. The appropriate step register is set to the address increment from the right-hand side of the rectangle around to the left-hand side on the next line. The SRCUP and DSTUP bits are set according to whether the source or destination are rectangles. In 8- or more bits per pixel mode, neither SRCEN nor DSTEN will be used for memory fill, bit SCRCEN should be set for memory copy. In 4-bit pixel mode, DSTEN must always be set as well, so that a destination read is performed to avoid corrupting the other pixel. Note that using this method will be slower than otherwise. The blitter 72 draws lines based on the well known digital differential analyzer (DDA) algorithm. The basis of this algorithm is that for a given line one of the X address or the Y address is always incremented for every pixel drawn, while the other one is also incremented if a suitable arithmetic condition is met. The algorithm used by the blitter 72 computes the arithmetic condition that causes the conditional increment by repeated subtraction of the smaller of dx or dy from a working value with the larger being added back when underflow occurs, effectively using division to calculate the gradient. The notation "dx" refers to the distance along the X axis that the line corresponds to and is given by .vertline.(X1-X2).vertline. where X1 and X2 are the X coordinates of the 2 points and the vertical bar notation means the magnitude or absolute value of their difference. Thus if a line is being drawn from (X1,Y1) to (X2,Y2), then dx=.vertline.(X1-X2).vertline. and dy=.vertline.(Y1-Y2).vertline.. From these, D1 (referred to as "delta one" above) is given by the larger of dx and Dy, D2 (referred to as "delta two" above) by the smaller. Then, for each pixel drawn, D2 is subtracted from a working value which is initially set to D1/2 and the sign of the result of this subtraction (indicating underflow) is the arithmetic condition for the conditional part of the screen address update. When this underflow occurs, the original value of D1 is added back to the working value. It can be seen that the ratio of dx to dy will give the frequency with which of this underflow and adding back occurs. The ratio between them is of course the gradient of the line. The values used to create a line draw are set in the blitter command as follows: the starting point of the line is the destination address, D1 is placed in bits 10 to 19 of the source address register and D1/2 is placed in bits 0 to 9. D1 is also the inner counter value although D1 plus 1 should be used if both end points of the line are to be drawn. D2 is placed in the destination step register. If DX is greater than DY, then the YFRAC flag is set, otherwise it is cleared. SSIGN gives the sign of the X-address updates, DSIGN gives the sign of the Y-address updates. While drawing lines, all the registers in the address section are occupied in computing the line address; thus the blitter has no ability to move data from somewhere else when drawing lines. Therefore, the data written at the line address has to be given either directly by the pattern data or by combination of the pattern register and the data already there, according to the logical function unit. Consequently, SRCEN should not be set, otherwise the blitter would produce seemingly random data. While drawing lines the inner counter is set to the length of the line, and the outer counter is set to one. In 8 or more bits per pixel mode, DSTEN need not be set, unless used for read-modify-write operations. In 4-bits per pixel mode, DSTEN must always be set so that a destination read is performed to avoid corrupting the other pixel. The blitter 72 also has the ability to paint characters on the screen in a single operation. Character painting as far as the blitter 72 is concerned involves painting a rectangular area up to 8 pixels wide and of arbitrary height. The pixels in this area are either written to or left unchanged according to a bit pattern. This mode is not restricted to character painting, but may also be used to expand any graphics stored as a monochrome bit plane. During character paints, the source register addresses the bit pattern, normally part of the font, where each byte corresponds to one row of the character. Thus, blitter fonts may be up to 8 pixels wide however, wider fonts may be used, but these will require more than 1 blitter paint operation to paint a character. Character painting is essentially a block move from the character font located in system memory 45 to the destination address. The data is arranged with the bit corresponding to the left-most pixel in the least significant bit, and the top of a character at the lowest address. If the data is less than 8 pixels wide, then the least significant bits of the font data are not used. The destination address register is used to address the area of the screen to which the character is to be painted. Normally this area has been cleared to the required background color by a previous blitter operation. The destination address is initialized to the top left-hand corner of the character. The character to be painted is a rectangle, and, therefore, the destination address is programmed correspondingly. The inner counter is sent to the width of the character and the outer counter to its height. The destination step register is set to the screen width less the width of the character. The DSTUP bit is used to allow the destination address to be updated between passes through the inner loop. Inner loop control bits DSTEN and SRCENF are set, character painting being the reason for the existence of SRCENF. This allows the font byte for each row to be read just once. The comparator is used to control the painting of pixels, therefore the CMPBIT control bit is set, to enable its bit to byte expansion mechanism. The color to be painted is set as the pattern, and this will normally be held in the pattern data register. In 4-bit pixel mode, DSTEN will be set, and the destination data register will hold the read values so that the other half of the byte may be written back undisturbed. The source data register holds the font pattern, as mentioned above. The blitter rotate and scaling mode uses the shading ALU, but instead of producing three DDA-based data values, it produces two DDA-based address values, X and Y. Normally, these values are used to traverse a source data field at arbitrary angles and rates so that the destination data corresponds to a scaled and/or rotated version of them. The red value generator gives the X value and the green value generator gives the Y value. The blue value generator is not used, and clearly shading cannot be used in conjunction with this mode. As the rotation requires higher accuracy than shading, four extra integer bits are added to the X and Y values. These are set up in rotate registers zero and one. All calculations are performed to 10 point bit accuracy. As with shading, the delta values are added to X and Y after each pixel is drawn in the inner loop. The step values are added in the outer loop, and both the SRCUP and DSTUP flags must be set for them to be added. The delta and step values may be either positive or negative, and no add or saturation occurs, unlike shading mode. Normally, rotation and scaling are performed by setting the destination address pointer to performing normal raster scan over the destination rectangle, while the source pointer traverses over the source data at a suitable gradient and rate. This ensures that the destination data is contiguous, and that no more blits (blitter operations) than necessary are required. The source data should be surrounded with a suitable transparent color if the target area is not rectangular. A blitter command is given as a table of data in memory. The blitter 72 loads the contents of the table into its registers and performs the specified operation. The blitter 72 will receive successive sets of commands until a STOP instruction is read into the command register. The blitter program address must be set up before the command word is issued. The blitter program address is given by the program address registers, which together form the full 24-bit address. The program must lie on a word boundary. A full table of blitter command data starts with a command word. However, the first blitter command in a sequence has its command word written to the command register by an I/O cycle of the CPU 48; thus, the blitter command starts reading the command data from the second word. Similarly, the last blitter command need consist of no more than a command word with the run bit clear. A blitter command takes the form of numerous command bits and control bits, a 24-bit source address, a 24-bit destination address, a 10-bit outer count value, a 10-bit inner count value, a 12-bit signed source step, a 12-bit signed destination step, and a 15-bit pattern value. If the SHADE bit is set, then 9 additional words are fetched: red, green and blue initial values (6 integer bits and 10 fraction bits), red, green and blue delta values (same) and red, green and blue step values (same). The command bits are as follows. Setting the RUN bit causes the blitter 72 to start operation. It is used when writing to the command register as an I/O port to start the blitter 72 reading a command. If the blitter 72 loads a command with the RUN bit cleared as part of a command read, then operation ceases. Setting the COLST bit causes operation to stop if a collision (write inhibit) occurs. From that point, print operation can be resumed by the CPU 48 or aborted, and various internal registers may be read. Setting the PARRD bit requires the blitter 72 to read a new parameter set from the program counter address, every time the inner loop exits and the outer loop has not reached zero. Setting the SRCUP bit requires the contents of the step register to be added to the source address on exit from the inner loop if the outer count has not reached zero. Setting the DSTUP bit requires the contents of the step register to be added to the destination address on exit from the inner loop if the outer count has not reached zero. Setting the SRCEN bit enables the source address read in the inner loop. This also causes the source address register to be incremented according to the pixel size. Setting the DSTEN bit enables a destination address read in the inner loop. This does not affect the destination address register, which is incremented as part of the destination write cycle. Setting the SRCENF bit causes the source address to be read when the inner loop is first entered, but not subsequently entered. This is a special case of SRCEN and is relevant to the character paint mode, as described above. SRCENF has no affect if SRCEN is set. The two bits PSIZE0 and PSIZE1 select the pixel size, 0 to 3 corresponding to 4, 8, 16, and 32 bits respectively. 32 bits is for data moves in a 32-bit system only, as described above. The 2-bits WIDTH0 and WIDTH1 select the screen width, in bytes, 0 to 3 corresponding to 256, 512, 1024, and 2048 bytes, respectively. Setting LINDR puts the blitter 72 into line-drawing mode. This mode uses both the source and destination address registers to generate the linedraw address, which may be used for both reading and writing. Setting the YFRAC bit indicates to the blitter 72 which of the X and Y addresses have the fractional increment in line-drawing mode. It is set if the Y address has the fractional increment. Setting the PATSEL bit selects the pattern data register to replace the source data register as the source input to the logical function unit. This bit is relevant to character painting, where the source data register will contain the font data, and the pattern data register contains the ink color. Setting the shade bit enables output from the shading ALU as write data. This bit is only valid for 8- and 16-bit pixels. The blitter 72 has several types of control bits: source control bits, destination control bits, logic function unit control bits, and comparator control bits. The blitter 72 has several source control bits. Setting the SWRAP bit causes source address updates to wrap on a programmable boundary, as opposed to running linearly through memory. Bits SWRAP0 and SWRAP1 control the size of the SWRAP function, which makes the source address pointer wrap vertically, with 0 to 3 corresponding to 64K, 128K, 256K, and 512K screens, respectively. Setting the SRCCMP bit selects the source data register as the source input to the comparator. If it is cleared, the pattern data register is used. Setting the SLWRAP register makes the source pointer wrap within the line width for inner loop updates. Setting the SSIGN bit sets the sign used when updating the source address. Setting it causes the source address to be decremented rather than incremented. This bit makes X negative in line-drawing. The blitter 72 also has several destination control bits. Setting the DWRAP bit causes destination address updates to wrap on a programmable boundary, as opposed to running linearly through memory. Bits DWRAP0 and DWRAP1 control the size of the DWRAP function, which makes the source address pointer wrap vertically, with 0 to 3 corresponding to 64K, 128K, 256K, and 512K screens, respectively. Setting the DSTCMP bit selects the source data register as the source input to the comparator. If it is cleared, the pattern data register is used. Setting the DLWRAP register makes the source pointer wrap within the line width for inner loop updates. Setting the DSIGN bit sets the sign used when updating the source address. Setting it causes the source address to be decremented rather than incremented. This bit makes Y negative in line-drawing. The blitter 72 also has logic function unit control bits. The logic function unit controls the data that is written in a destination write cycle. The LFU allows any logical combination of the source and destination data. This is achieved by each of the LFU bits LFU0 through LFU3 selecting one of the minterms, with the output being given by the logical OR of the selected terms. A 0 value corresponds to NOT source and NOT destination, 1 corresponds to NOT source and destination, 2 corresponds to source and NOT destination, and 3 corresponds to source and destination. There are, therefore, sixteen possibilities. The blitter 72 also has several comparator control bits. Setting CMPPLN enables plane mode where the three comparator functions operate on the plane number bits as opposed to the entire pixel. Setting the CMPEQ bit causes the comparator to inhibit an inner loop write, if in plane mode the priority of the destination pixel is equal to the plane priority of the source pixel, or if the entire pixel is the same if not in plane mode. Setting the CMPNE bit causes the comparator to inhibit an inner loop write, if in plane mode the priority of the destination pixel is not equal to the plane priority of the source pixel, or if the entire pixel is not the same if not in plane mode. Setting the CMPGT bit only operates in plane mode, and causes the comparator to inhibit the write if the plane priority of the destination pixel is greater than the plane priority of the source pixel. Setting the CMPBIT gives a bit to byte expansion scheme. It causes the comparator to generate an inhibit by selecting a bit of the source data register using an inner counter, and generating an inhibit if the bit selected is a zero. The selection is given by 8 in the inner counter selecting bit 0, 7 selecting bit 1, 6 bit 2, and so on. The program address register points to the source of blitting operation commands. Data is read from it sequentially upwards through memory. It must always be even (i.e., blitter operations must lie on word boundaries). Register 0 corresponds to address bits 0 through 15 and register 1 to address bits 16 through 23 and bits 0 through 7. Some of the above blitter registers are visible in the I/O space of the CPU 48. In addition, some blitter status and control bits are accessible to the CPU 48. As mentioned above, the blitter 72 has 7 word-wide read registers and 4 word-wide write registers. Any unused bits in the write register should be written with a 0. The I/O registers appear starting from I/O address 40H. These registers are also available in the memory map, principally so the DSP 61 can access them, starting at the same offsets as I/O, but at base address F10400H (i.e., subtract 40H and add F10400H to get the memory address). The first blitter destination register corresponds to bits 0 through 15 of the destination address register. Bits 0 through 7 of the second blitter destination register correspond to bits 16 through 23 of the destination address register. And bit 15 of the second blitter destination register corresponds to the destination address nibble part of the destination address register. The first blitter source register corresponds to the bits 0 through 15 of the source address register. Bits 0 through 7 of the second blitter source register correspond to bits 16 through 23 of the source address register and bit 15 of the second blitter source register correspond to the source address nibble part. Bits 0 through 9 of the blitter inner counter correspond to the inner counter value. Bits 0 through 9 of the blitter outer counter correspond to the outer counter value. The blitter status register gives a variety of blitter status information. Bit 0 indicates that the comparator plane priority greater than condition is met. Bit 1 indicates that the comparator plane priority equal condition is met. Bit 2 indicates that the comparator plane priority not equal condition is met. Bit 3 indicates that the comparator pixel equal condition is met. Bit 4 indicates that the comparator pixel not equal condition is met. Bit 5 indicates that the comparator bit to pixel condition is met. Bit 13 corresponds to the run bit stating that the blitter is currently active, or operation is suspended by a CPU interrupt or a collision stop. Bit 14 indicates that the blitter has stopped for a CPU interrupt. Bit 15 indicates that the blitter has stopped because of a collision detection. The blitter program address register is loaded with bits 0 through 15 of the blitter program address. Recall that bit 0 of the register is always 0 because blitter programs must lie on word boundaries. The second blitter program address register is loaded with bits 16 through 23 of the blitter program address in bits 0 through 7. The other 8 bits are 0. The blitter command register corresponds to word 0 of the blitter command, and is used to set up the command when the blitter is started. Blitter DMA will then start from word one of the command. The blitter control register has three bits: bit 0 which is an interrupt stop mask masks interrupts from the blitter's bus control unit when set, with a result that the blitter will not stop when an interrupt occurs, bit 1 causes the blitter to resume operation after a collision and is used to restart the blitter after a collision has been detected. Recall that a collision is detected when the COLST bit is set. The blitter will resume the operation which it has suspended. Note that it is possible to reprogram the blitter command register while the blitter is in the collision stop state, so the COLST bit among others may be changed, and bit 2 resets the blitter to a quiescent state after collision and is used to abort the operation the blitter was performing when a collision stop has occurred. Note that after a blitter collision stop occurs, either a resume or a reset should be issued to the blitter. The blitter 72 also has three rotate registers. Bits 0 through 3 correspond to the top four bits of the integer part of the X address, the bottom six bits of the 10-bit value are the integer part of the red value. Bits 4 through 7 correspond to the top four bits of the integer part of the X increment, the bottom six bits of this ten-bit value are the integer part are the red integer value. Bits 8 through 11 correspond to the top four bits of the integer part of the X step, the bottom six bits of this ten-bit value are the integer part are the red integer value. With the second rotate register bits 0 through 3 correspond to the top four bits of the integer part of the Y address, the bottom six bits of this ten-bit value are the integer part are the green integer value. Bits 4 through 7 correspond to the top four bits of the integer part of the Y increment, the bottom six bits of the ten-bit value are the integer part of the green integer value. Bits 8 through 11 correspond to the top 4 bits of the integer part of the Y step, the bottom six bits of the ten-bit value are the integer part are the green integer value. In the third rotate register setting bit 0 causes the rotate address to replace the destination. Setting bit 1 causes the rotate address to replace the source address. Setting bit 2 sets rotation mode, as opposed to shading mode. And bits 10 through 15 correspond to the top bits of the rotate address. The DSP 61 audio coprocessor is a general purpose arithmetic coprocessor with sufficient power to implement a high performance music synthesizer. Synchronous serial outputs are provided for a generation of stereo audio signals with 16 bit precision, giving a sound quality normally associated with compact disc technology. The DSP 61 is micro-programmable from the host CPU 48 and the instruction set is sufficiently flexible to enable the user to program the device to fulfill many different functions that are quite different from that of "music synthesizer." Such applications might include algorithmic speech generation, audio analysis using fast Fourier transform techniques, and three-dimensional graphics rotations. The DSP 61 uses Harvard architecture (separate program and data buses) for maximum data throughput. The DSP 61 has an arithmetic logic unit (ALU). The ALU features a hardware 16-bit by 16-bit hardware multiply/accumulate as well as addition, subtraction, and logical functions. There is also a separate serial divide unit, which generates one quotient bit per tick. The carry bit from the adder/subtracter is stored in a separate latch and can be either used to propagate carry for multiple precision arithmetic operations or can be used for conditional instructions. All instructions may be made to be dependent on this bit being set. Data transfers within the device are all 16 bits wide, with the exception of internal transactions within the multiplier/accumulator. The DSP 61 is a very simple, very fast processor intended primarily for sound synthesis, but also capable of other computational tasks as noted above. It executes all instructions in one processor cycle; these instructions are executed at the system clock speed (typically 20 to 33 megahertz). During sound synthesis, the DSP 61 has its timing controlled by timers in an audio digital-to-analog converter (DAC) interface. These DACs are double-buffered, and if a DAC write is about to cause overflow, then operation is suspended until the buffer is empty. So long as the software to executes loops at sample rate, and as long as the average loop time is less than the sample period, then occasional loops can be up to twice as long. Because the loop may contain more instructions than will fit in the program RAM, the DSP 61 has an indexed addressing mode, which allows the same piece of code to act on several voices. The DSP 61 is a Harvard Architecture device, thus the program RAM and the data RAM are separate, with cycles occurring in both RAM blocks at the same time. A one-cycle pipeline is used; therefore, during each clock cycle two events occur: an instruction is fetched, and the data transfer associated with the previous instruction takes place. This has the odd effect that an instruction after a jump is executed. The DSP 61 has two arithmetic logic units (ALUs, not shown): a typical ALU and a multiply/accumulate ALU; several registers: an X operand register, a second operand register, an AZ register, which holds the result from the ALU, and an MZ register, which holds the result from the multiply/accumulate register. The DSP 61 also has a DMA channel and a divider. Operation of the DSP 61 is fairly simple. In the first tick of an execution of an instruction, the opcode is read from the program RAM into the instruction decoder. In the second tick, while the next instruction is read from the program RAM, a data transfer is performed either from system memory 45 to a register or a register to system memory 45, as per the first instruction. The ALU within the DSP 61 is a 16-bit arithmetic logic unit, with the same functions as a Texas instruments 74181, which is well known in the art. Common arithmetic operations are encoded as instructions; uncommon instructions may be performed by directly setting up the ALU mode bits with the general purpose arithmetic instruction (GAI). The DSP 61 also has a multiplier/accumulator, which is a second ALU to perform 16 by 16 signed/unsigned multiplies to yield a 32 bit result. In addition to this, it may also perform multiply/accumulate operations, where the product of the multiply is added to the previous result. A result is accumulated to 36 bits to allow for overflow. Multiplier operations actually take two ticks, although the multiplying instruction itself completes in one tick. This means that the instruction following a multiply or a multiply accumulate may not involve the MZ register or the X register. The DSP 61 also has a divider. The division unit appears as a set of registers in the internal DSP 61 space. It is capable of unsigned division on 16- or 32-bit operands, and produces a quotient and a remainder. The DSP 61 also has a DMA channel. The DMA channel appears as a set of registers in the DSP 61 data memory space. These are two address registers and a data register. A DMA transfer is initiated by writing an address to the first of the two address registers. DMA transfers have a latency period, which must be allowed to elapse before performing further DMA. The DMA state machine is responsible for requesting the SYSTEM' bus, and when it is granted, performing the transfer, after which the SYSTEM' bus is released. In the alternative, a word may be written to the second of the two address registers with a hold bit set. This will request the SYSTEM' bus and retain it until the hold bit is cleared. Such a DMA transfer may be efficient when performing successive multiple transfers, but is generally less efficient for single transfers because the DSP 61 program cannot determine when the SYSTEM' bus is granted, and therefore has to wait the maximum possible latency. DSP 61 memory is generally visible in both the DSP's internal data address base and in the host address base. The DSP 61 has a DSP memory 76 associated with it. The DSP memory 76 comprises program RAM, data RAM, a register/constant table, and a sine ROM (all not shown). The DSP memory 76 in general is accessible in both the DSP's internal address space as well as the address space of the system memory 45. The DSP program RAM is 512 18-bit words. These locations may only be written by the CPU 48, and are program read-only as far as the DSP 61 is concerned. Program RAM does not appear in the DSP internal address space. The program RAM is not accessible to the host when the DSP 61 is running. Each DSP instruction has a 7-bit opcode and an 11-bit address vector. All microcoded instructions (with the exception of multiply or multiply/accumulate operations) are completed in 185 nanosecond cycle. All instructions are system memory 45 to register transfers or register to register transfers; immediate values are not allowed. Thus, if a constant is needed for a given instruction, it is not available in the constant table, a data RAM location must be set aside for the value. The DSP 61 also allows conditional instructions and indexed addressing. If bit 12 of the instruction code is set, then the instruction is executed only if the carry bit in the ALU is also set. If bit 11 in the instruction code is set, then the 9-bit address vector in the instruction code is added to the 9-bit value in the index register to produce the address and data memory operated on by the instruction. The extra two bits are programmed by loading the values into an extra bits register then writing the word into the desired location. The DSP 61 has numerous move commands, which move data from and to memory and registers. Several other commands are available, including adding, subtracting, ANDing, ORing, adding with carry, a NOP, the GAI described above, and an INTRUDE command, which allows the DSP memory 76 to be accessed by the CPU 48. The sine ROM is 256 16-bit words of full sine wave two's complement sine wave values. The data RAM is 512 16-bit words. Data may be transferred between the CPU 48 and the DSP 61 either under control of the DSP 61 or under the control of the host CPU 48. The DMA transfer mechanism is based upon the DSP 61 becoming the bus master on the SYSTEM' bus and accessing the system memory 45. The DSP 61 is one of the highest priority bus masters, and will therefore be granted the SYSTEM' bus by the current bus master as soon as the current bus master is able to give up the SYSTEM' bus. The worst case for giving up the SYSTEM' bus is the situation where the CPU 48 is the bus master, because the 80376 or 80386SX processor can take a considerable amount of time to release the SYSTEM' bus. DMA transfers are started by a write to the first DMA address register, as stated above. Transfer of status information and the high part of the address should already have been written to the second DMA address register; similarly write data should already have been written to the DMA data register in the case of write transfers. When a transfer is initiated, the DSP 61 requests the SYSTEM' bus and when the SYSTEM' bus is granted to the DSP 61, the DSP 61 performs the transfer and then releases the SYSTEM' bus. Completion of this operation may be polled or the programmer may choose to allow the maximum possible latency to elapse before using read data and/or initiating another transfer. A second bus acquisition technique may be performed which uses the hold bit in the second of the two DMA address registers to request the SYSTEM' bus. This may be more efficient if the DSP 61 wishes to perform multiple transfers consecutively, because the SYSTEM' bus is not released between transfers. The hold bit in the second DMA address register must be cleared before the DSP 61 will release the SYSTEM' bus. This mechanism is generally not recommended because the DSP 61 will have control of the SYSTEM' bus for significant periods of time without any activity, which is wasteful of overall memory bus bandwidth and could potentially disturb CD DMA transfers. If using the second technique, the DSP 61 must first request the SYSTEM' bus before performing any DMA transfer. It has no means of detecting that it has gained the SYSTEM' bus, and must therefore wait the maximum number of bus instructions. Once the DSP 61 has acquired ownership of the SYSTEM' bus it may then proceed to perform bus cycles. It may perform an arbitrary sequence of read and/or write cycles and should relinquish control of the SYSTEM' bus at the end of these. Data transfer may also be performed between the CPU 48 and the DSP 61 under host CPU 48 control. All the internal memory of the DSP 61 is mapped into the host address space. When the DSP 61 is in stop mode, the host may write program memory locations just as if they were in normal system memory 45. When the DSP 61 is running, however, the program memory is not available to the host. DSP 61 data memory is only available by the INTRUDE mechanism. To ensure that DSP 61 operations are not disturbed in any way, data transactions can only take place in the data when the DSP 61 is executing INTRUDE instructions. When the DSP 61 is stopped, it may be considered to be effectively executing INTRUDE instructions constantly. CPU 48 to DSP progra | ||||||