Multimedia system for processing a variety of images together with sound

Abstract

A high performance computer includes a CPU, a video display unit, a control unit, an image data extension unit, a video encoder unit responsive to the outputs of the video display unit, the controller unit and the image data extension unit, and a sound data output unit, for processing a variety of image data together with a variety of sound data at high speed. Three types of image data sequence processes can be carried out in the computer. These are an external block sequence, an external dot sequence, and an internal dot sequence.

Claims

I claim:

1. A multimedia system for processing a variety of images with sound, comprising:

a Video RAM (VRAM) for storing image data;

means for writing image data of external-block type to be processed block-by-block into the VRAM;

a video display (VDP) unit, coupled to the VRAM, for processing the image data stored in the VRAM;

an external storage for storing image and sound data, including image data of internal-dot type to be processed dot-by-dot;

a control unit, coupled to the external storage, for reading the image and sound data stored in the external storage, to produce scale-down image data of external-dot type to be processed dot-by-dot;

an image data extension unit, coupled with the control unit, for extending the scaled-down image data of external-dot type;

a video encoder unit, coupled with the video display unit, the control unit, and the image data extension unit, for encoding each image data of the external-block, internal-dot, and external-dot types, respectively;

means, coupled with the video encoder unit, for decoding the encoded image data to produce transferable data; and

a sound data output unit, coupled to the control unit, for processing a variety of sound data.

2. The multimedia system according to claim 1, wherein:

said video encoder unit performs priority processing for the image data supplied from the video display unit, the control unit and the image data extension unit to superimpose a plurality of pieces of image in a predetermined order.

3. The multimedia system according to claim 1, wherein:

said control unit reads sound data from the external storage through an SCSI interface.

4. The multimedia system according to claim 2, wherein:

said image data extension unit processes Inverse Discrete Cosine Transformation (IDCT) data for natural pictures and moving pictures and run-length-encoding for animation pictures.

5. The multimedia system according to claim 1, wherein:

said video display unit is able to process two pictures of sprite and background.

6. The multimedia system according to claim 1, wherein:

said control unit is able to process four background pictures.

7. The multimedia system according to claim 1, wherein said image data extension unit includes:

a scale down data extension means including a reverse discrete cosine transformation (DCT) converter, a Huffman coding and decoding system, and a run-length coding and decoding system.

8. The multimedia system according to claim 1, wherein said external storage is a CD-ROM.

9. The multimedia system according to claim 1, wherein said control unit reads image data, sound data, and program data through a predetermined interface from said external storage and judges priority of the read data dot-by-dot, and in response, transmits a result of the judgement to the video encoder unit, a reduced version of image data to the image data extension unit, and sound data to the sound data output unit.

10. The multimedia system according to claim 9, wherein

said sound data output unit includes an adaptive difference pulse code modulation (ADPCM) extension-reproducing system and a mixer for mixing a pulse code modulation (PCM) output and sound data.

11. The multimedia system of claim 10, wherein said predetermined interface is a SCSI interface.

12. The multimedia system according to claim 1, further comprising:

a display for displaying the data transferred from said decoding means.

13. The multimedia system according to claim 12, wherein

said display comprises a screen divided into an upper screen portion and a lower screen portion, and in which upper and lower pictures for display in the upper and lower screen portions are stored in first and second Background Attribute Tables (BAT's), respectively.

14. The multimedia system according to claim 12, further including:

means for horizontally scrolling a plurality of rasters on said display a number of dots to the right or left of a reference position, and wherein said number of dots is set in a horizontal scroll register of the image data extension unit.

15. The multimedia system according to claim 1, wherein:

said control unit manages a plurality of (BG) screens, in which a main picture and a sub-picture are specified as BG image data, and in which the sub-picture is superimposed on the main picture.

16. The multimedia system according to claim 1, wherein

said video encoder provides a cromakey function (transparency process).

17. A multimedia system for processing a variety of images and sounds, comprising:

a Video RAM (VRAM) for storing image data;

means for writing image data of external-block type to be processed block-by-block into the VRAM;

a video display (VDP) unit, coupled with the VRAM, for processing the image data stored in the VRAM;

an external storage for storing image and sound data, including image data of internal-dot type to be processed dot-by-dot;

a control unit, coupled with the external storage, for reading the image and sound data stored in the external storage, to produce image data of external-dot type to be processed dot-by-dot and managing a plurality of Background (BG) screens, in which a main picture and a sub-picture are specified as BG image data and scrolled independently of each other, and in which the sub-picture is superimposed on the main picture;

an image data extension unit, coupled with the control unit, for extending a scaled-down image data of external-dot type;

a video encoder unit, coupled with the video display unit, the control unit, and the image data extension unit, for encoding each image data of the external-block, internal-dot, and external-dot types, respectively;

means, coupled with the video encoder unit, for decoding the encoded image data to produce transferable data; and

a sound data output unit, coupled with the control unit, for processing a variety of sound data.

18. The multimedia system according to claim 17, wherein:

the sub-picture is scrolled in one of an endless scroll mode and a non-endless scroll media.

Description

BACKGROUND OF THE INVENTION

The present invention is directed to an apparatus for processing sound and image data, and more particularly to a game computer for displaying image information and producing accompanying sound.

A conventional computer will be explained, hereinafter, separately image processing and sound processing.

(1) IMAGE PROCESSING

In a conventional game computer, a background (BG) image and a sprite image moving on the BG are combined on a screen to increase processing speed and to lower cost.

The background image is composed of a plurality character blocks (character screens) each defined by 64 dots of 8-by-8. Therefore, the background image is defined on a CRT display screen by deciding position, color and pattern of the character blocks. The computer has a video-RAM (VRAM) which includes a background attribute table (BAT) and a character generator (CG), as shown in FIG. 1. The background image is defined in accordance with data format of the background attribute table (BAT) and the character generator (CG).

The BAT includes a CG COLOR and a character code whereby position and color for each character are defined on a virtual screen, which is larger in size than the real screen (CRT). The CG stores many actual character patterns corresponding to the character codes in the BAT. The CG is, for example, composed of four character elements CH0 to CH3, and the number of the character elements is defined by color modes. For instance, the CG is composed of two character elements in a four-color mode, and is composed of four character elements in a sixteen-color mode.

The color of each character block is defined dot by dot, each dot color is defined by total bits of all the corresponding dots on each character elements CH0 to CH3, as shown in FIG. 2. Specifically, when the corresponding dots of character elements CH0 to CH3 are indicated by b0, b1, b2 and b3, a color "C" of the dot to be represented is given by an equation "C=b0.times.2.sup.0 +b1.times.2.sup.1 +b2.times.2.sup.2 +b3.times.2.sup.3 ". It can be considered that the color "C" may be treated as a color code directly. However, the conventional game computer uses a color pallet which stores plural color codes to manage colors of the background image so that many colors may be used for displaying one background image. The color pallet is indicated in position by the color codes of the CG.

The character code in the BAT indicates an address in the CG. A color to be displayed is selected from colors in the color pallet in accordance with both the CG COLOR and the color code. That is, first, a color block is selected from the CG in accordance with the CG COLOR, then a color is selected from in the color block in accordance with the color code, as shown in FIG. 3. The CG COLOR is composed of 4 bits, so that sixteen color blocks may be represented thereby. Each color code is composed of 4 bits, whereby sixteen colors may be represented for each character. Ultimately, sixteen colors are selected from among 256 (16.times.16) colors.

When an address of the image data is moved in a horizontal or vertical direction on the virtual screen, the image is scrolled on the CRT display.

Generally, transmission process of image data to the CRT is controlled in accordance with horizontal and vertical synchronizing signals. According to an NTSC system, 525 scanning lines are used to display an image, and odd fields and even fields are scanned alternately.

On the display device for a general game computer, only odd or even fields are scanned. The display system is controlled line by line in synchronization with horizontal synchronizing signals, and is controlled screen by screen in synchronization with vertical synchronizing signals. In the vertical synchronizing signals, there are flyback times longer than those of the horizontal synchronizing signals, whereby it is preferable that the image data are processed in the flyback times of the vertical synchronization. In order to display the BG image on the CRT, a raster scanning position is detected, and then each piece of character information is converted into video signals.

It is possible to realize an image rotation process and a synthesis process of plural images. In the rotation process of the BG screen, a plurality of screens having different display angles are displayed in a predetermined order whereby the BG screen seems as if it is rotated. In the other hand, a plurality of screens having different angles, which are produced by calculation according to a predetermined matrix coordinate, are displayed in the same order. In the synthesis process, a plurality of image data are supplied through different buses to an encoder, and the data are mixed by the encoder.

The conventional computer system includes a fader for giving a 100% brightness to a picture to be displayed, and a 0% brightness to the other pictures.

Most conventional game computers have single screen, that is not changed by another.

(2) SOUND PROCESSING

In general, a computer has a digital sound source in which all of sound signals are indicated as numerals whereby synthesis of waveform is carried out by addition, subtraction, multiplication and division calculations. Most of game computers include programmable sound generators (PSG) each manage a small amount of data. According to the PSG, waveform data in a predetermined period are changed in amplitude, then modulated in frequency and then are processed in order to generate a sound waveform. In the PSG, the sound source (sound waveform) is generated in accordance with a predetermined program.

On another way, analog sound data are converted into digital sound data whereby high quality sound source is generated by a pulse code modulation (PCM) method. According to the PCM, an analog signal is sampled at predetermined intervals, the sampled signal is quantified and is converted into binary number, whereby digital data are generated.

For the game computer, an adaptive-difference pulse code modulation (ADPCM) method is used for generating a digital signal. According to the ADPCM method, the difference between next two sample values is quantified, and the sampling pitch is shortened if the quantified difference value is larger, and is extended if the quantified difference value is smaller, whereby data to be used for a sound source are reduced (scale-down). As a result, sound can be reproduced by using a small amount of data. The PCM data and ADPCM data may be converted to each other in accordance with a scale coefficient and an extension coefficient given by a scale value and a scale level.

In the ADPCM method, high quality sound may be produced when a sampling frequency of a scale rate is large. In the game computer, sampling frequency is determined on the basis of the data amount, the maximum value being about 16 kHz.

In operation, the ADPCM data are read from the memory by the CPU, and the scale value and the scale level of the data are detected by an ADPCM decoder. The ADPCM data are extended to PCM data, whereby sound is reproduced at a reproducing rate corresponding to the sampling frequency. The reproducing rate is controlled by a synchronizing signal generating circuit including a decoder.

Address renewal of the RAM is carried out by the CPU in accordance with a predetermined program. As another way, such address renewal is carried out in accordance with an automatic adding process. For example, if data access is performed for 32 blocks at each time, the first address of the data are specified and then the following addresses are specified by adding predetermined values to the previous address in the same order. Therefore, it is realized that the RAM is accessed continuously or accessed with some interval depending on the added value.

As described above, the conventional game computer uses BG image data generally composed of only external block sequential data, each block being indicated by 8-by-8 dots, the image is displayed by an RGB system. A variety of image data such as a natural picture illustrated with continuous colors, a moving picture and a still picture illustrated by a single color are required to be displayed, however, the conventional game computer can display only a simple image. Especially, according to the conventional technology, it is difficult to display the natural picture when the CPU has a large amount of data have to deal with.

If the conventional computer having a simple RAM deals with data other than block sequential type data, the processing speed becomes low.

The computer is required to deal with a large amount data in order to display the natural picture. When each luminance of the RGB is defined by eight bits on one screen having picture elements of 512.times.512, each color image needs a memory capacity of about 768 k bytes (512.times.512.times.3). Therefore, it is necessary to take full advantage of the RAM in order to keep the processing speed high when a large amount data have to be processed. It is easy to deal with such a large amount data if all the different mode data are arranged in the same manner in the RAM, however, effective use of the RAM can not be realized. If the image data are arranged in accordance with the mode thereof, different data accesses are required for each mode, so that the address process becomes complicated. Therefore, a memory access apparatus which can manage the RAM having a complicated data arrangement is required for the computer.

In the game computer, predetermined data must be processed while tens of images are displayed within a second, and therefore processing must be performed in both horizontal (HSYNC) and vertical synchronizing (VSYNC) periods. For that reason, in the conventional game computer, it is difficult to realize special graphic processes such as rotation, magnification, reduction and the like. Further, the conventional game computer uses a fader to synthesize a plurality of BG images, so that the structure is complicated and the CPU must perform much processing in the case where a variety of image data are processed and large number of BG images are synthesized. Although BG image data may be processed in both the HSYNC and VSYNC periods for single BG image of 8.times.8 blocks, it is difficult to avoid the disadvantages when a variety of image data are processed or large number of BG data are processed.

As for sound data processing, the conventional ADPCM has a sample frequency of 16 kHz maximum, so that sound quality is not always high. If the sample frequency is increased for producing high quality sound, data amount to be processed is increased. As a result, the above mentioned problems, namely, low speed processing and complicated data access become remarkable, if image data are treated together with PSG data and ADPCM data.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a high performance computer for processing a variety of image data together with a variety of sound data at high speed.

It is another object of the present invention to provide a computer by which multi-image synthesizing can be realized easily.

According to the invention, a sound and image processing apparatus, includes;

a central processing unit (CPU) having a memory control function for directly controlling a DRAM via a memory support, and an I/O control function for communicating the CPU through an I/O port to peripheral devices;

a VRAM in which display data are written by the CPU;

a video encoder unit;

a VDP unit for transmitting the display data from the VRAM to the video encoder unit;

an image data extension unit which includes scale-down data extending means including a reverse DCT converter, a reverse quantifying system, a Huffman coding and decoding system, and a run-length coding and decoding system and the like;

a sound data output unit including an ADPCM extension-reproducing system and a mixer for mixing a PCM output, a PSG output and an external sound data; and

a control unit for reading image data, sound data, and program data through a predetermined interface from an external recording device, judging priority of the read data dot-by-dot, transmitting a result of the judgement to the video encoder unit, transmitting a scale-down image data to the image data extension unit, and transmitting sound data to the sound data output unit;

wherein the video encoder unit superimposes a VDP image, natural picture image and moving image supplied from the VDP unit, control unit and image data extension unit, respectively, and performs color pallet reproducing, special effect processing, and D/A conversion processing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an explanatory diagram illustrating structure of BAT and CG used in a conventional computer system.

FIG. 2 is an explanatory diagram showing operation of the conventional computer system.

FIG. 3 is an explanatory diagram illustrating a relation between a color pallet and BAT/CG in the conventional computer system.

FIG. 4 is a structural diagram of BAT in the conventional computer system.

FIG. 5 is a structural diagram of a character used in the conventional computer system.

FIG. 6 is an explanatory diagram illustrating a bit-structure in a RAM in a 4 color mode.

FIG. 7 is an explanatory diagram illustrating a bit-structure in the RAM in a 16-color mode.

FIG. 8 is an explanatory diagram illustrating a bit-structure in the RAM in a 256-color mode.

FIG. 9 is an explanatory diagram illustrating a bit-structure in the RAM in a 64 k-color mode.

FIG. 10 is an explanatory diagram illustrating a bit-structure in the RAM in a 16M-color mode.

FIG. 11 is a block diagram illustrating a computer system of a preferred embodiment according to the invention.

FIG. 12 is a block diagram illustrating a CPU of the preferred embodiment.

FIG. 13 is a memory port map of the CPU shown in FIG. 12.

FIG. 14 is a table showing memory specifications in relation to a DRAM structure for the preferred embodiment.

FIG. 15A is an explanatory diagram illustrating a structure of an MCU used in the preferred embodiment.

FIG. 15B is an explanatory diagram illustrating a structure of a memory specifying register in the MCU shown in FIG. 15A.

FIG. 16 is an explanatory diagram showing an architecture of a refresh timer used in the preferred embodiment.

FIG. 17 is a block diagram illustrating detail of a control unit used in an image processing unit of the preferred embodiment.

FIG. 18 is an explanatory diagram showing "AFFIN" conversion (reverse conversion).

FIGS. 19A and 19B are configuration diagrams for the AFFIN conversion coefficient register and the AFFIN conversion center coordinate register used in the preferred embodiment, respectively.

FIG. 20 is an explanatory diagram showing a process in the case where reduction rate of the image changes for each raster.

FIG. 21 is a flow chart showing the steps of the process shown in FIG. 20.

FIG. 22 is a timing chart showing operational relation between DCK and HSYNC for the preferred embodiment.

FIG. 23A is a diagram showing configuration of a mlcroprogram control register of the preferred embodiment.

FIG. 23B is a diagram showing a configuration of a microprogram load address register of the preferred embodiment.

FIG. 23C is a diagram showing a configuration of a microprogram data register of the preferred embodiment.

FIG. 23D is an area table of a microprogram storage area of the preferred embodiment.

FIG. 24 is a diagram showing an actual configuration of the microprogram data register shown in FIG. 23C.

FIG. 25 is a timing chart showing operation of the microprogram for the preferred embodiment.

FIG. 26 is a time table showing address generating process by the microprogram of the preferred embodiment.

FIG. 27 is a table showing writing operation by the microprogram of the preferred embodiment.

FIG. 28 is an explanatory diagram showing a BG screen of the preferred embodiment.

FIG. 29 is a flow chart showing data access operation of the preferred embodiment.

FIG. 30 is an explanatory diagram showing memory access operation of the preferred embodiment.

FIG. 31 is an explanatory diagram showing coordinate of the BG screen.

FIGS. 32 and 33 are explanatory diagrams each showing a relation between the screen coordinate and main and sub pictures in an endless scroll mode ("Chazutsu" mode).

FIG. 34 is an explanatory diagram showing a relation between the screen coordinate and main and sub pictures in the case where the main picture is in a non-endless scroll mode ("non-Chazutsu" mode) and the sub picture is in the endless scroll mode.

FIG. 35 is an explanatory diagram showing a relation between the screen coordinate and main and sub pictures in the case where the main picture is in the endless scroll mode and the sub picture is in the non-endless scroll mode.

FIG. 36 is an explanatory diagram showing address arrangements the BAT for characters represented on a virtual screen.

FIG. 37 is a diagram showing a configuration of a sub picture endless scroll set register.

FIG. 38 is an explanatory diagram showing a display example of main and subpictures.

FIG. 39 is an explanatory diagram showing a position to be pointed by a start address register of a K-RAM.

FIG. 40 is an explanatory diagram showing operation in the case where the screen is divided into two of upper and lower.

FIG. 41 is a block diagram illustrating an image data extension unit used in the preferred embodiment.

FIG. 42 is an explanatory diagram showing operation of picture, display timing in the preferred embodiment.

FIG. 43A is a diagram showing the configuration of a transfer control register for the image data extension unit.

FIG. 43B is a diagram showing the configuration of data start address register for the image data extension unit.

FIG. 43C is a diagram showing the configuration of a transfer start raster register for the image data extension unit.

FIG. 43D is a diagram showing the configuration of a transfer block number register for the image data extension unit.

FIG. 43E is a diagram showing the configuration of a raster monitoring register for the image data extension unit.

FIG. 44 is an explanatory diagram showing a change of screen in the case where three blocks in sixty-four rasters are horizontally scrolled.

FIG. 45 is a flow chart showing an algorithm for processing horizontal scroll in the preferred embodiment.

FIG. 46 is an explanatory diagram showing a relation between a start address and a transfer start raster in a twenty-three raster up-scroll mode.

FIG. 47 is a block diagram illustrating a video encoder unit used in the image processing apparatus of the preferred embodiment.

FIG. 48 is a diagram showing configurations of a color pallet RAM of the preferred embodiment.

FIG. 49 is a diagram showing a configuration of a color pallet address used for the preferred embodiment.

FIG. 50 is a table showing configurations of color pallet data separated from each other in unit.

FIG. 51 is an explanatory diagram showing a priority process in a 256 dots mode.

FIG. 52 is an explanatory diagram showing a chromakey process in the preferred embodiment.

FIG. 53 is a table showing data chromakey processes of the VDP unit, control unit and image data extension unit.

FIG. 54 is a block diagram showing a cellophane function used in the preferred embodiment.

FIG. 55 is a flow chart showing operation of the cellophane function.

FIG. 56 is an explanatory diagram showing the cellophane function.

FIG. 57 is an explanatory diagram showing a front cellophane function.

FIG. 58 is an explanatory diagram showing a back cellophane function.

FIG. 59 is a diagram showing an image displayed in a non-interlace mode.

FIG. 60 is a diagram showing an image displayed in an interlace mode.

FIG. 61 is a diagram showing an image displayed in the interlace +1/2 dot shift mode.

FIG. 62 is a block diagram showing a sound data output unit used in the preferred embodiment.

FIG. 63 is an explanatory diagram showing a storage configuration of ADPCM data in the memory.

FIG. 64 is a table showing a relation among sampling frequencies, adding amount in data transmission and adding amount in a linear interpolation.

FIG. 65 is an explanatory diagram showing linear interpolation in a 7.87 kHz sampling frequency mode.

FIG. 66 is a flow chart showing a scale-down process of PCM data to ADPCM data.

FIG. 67 is a flow chart showing an extending process of the ADPCM data to the PCM data.

FIG. 68 is a table showing a relation among the ADPCM data, variation values and level changing value.

FIG. 69 is a table showing a relation between scale levels and scale values.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a computer apparatus of a preferred embodiment according to the present invention will be explained in conjunction with appended drawings.

According to the invention, three types of image data sequence processes, "external block sequence," "external dot sequence" and "internal dot sequence," are carried out. In the apparatus, YUV color data are used when the number of colors to be displayed is more than a predetermined number, and a color pallet is used when the number is less than the predetermined number. The three types sequence processes are now explained in accordance with a YUV method.

(1) EXTERNAL BLOCK SEQUENCE PROCESS

FIG. 4 shows a BAT (background attribute table) which is separated by a pallet bank and a character code. The pallet bank stores data corresponding to a bank stored in a video encoder, and the data in pallet bank are used for selecting a color from in a color pallet having 256 colors. The color pallet includes color groups each composed of, for example, 16 colors, the color groups being selected in accordance with data in the pallet bank. The pallet bank is effective in a 4 color mode and 16 color mode only, so that other color modes are neglected to the pallet bank. The character code is used for specifying a CG (character generator), whereby a CG address is defined by the character code and data in a CG address register. Each character pattern is defined by 64 dots of "8.times.8" by the CG. A bits number "n" required for representing each dot is given by the following equation, where "m" colors are used simultaneously to display the dot. The numbers of dots required to define a color for one dot are different depending on the color modes.

n=Log.sub.2 m

When "m" is indicated by 4, 16, 256, 64 k or 16M bits color data, "n" is indicated by 2, 4, 8, 16 and 24 bits data. A RAM is arranged in address by 16 bits (=1 word), so that 2 dots are indicated by 32 bits when "m=16M".

In FIG. 5, "i, j" of P.sub.i,j means a dot position (line, column) of the character and "p" means a pallet number.

FIGS. 6, 7 and 8 show structure of the RAM in 4, 16 and 256 colors modes, respectively. The structures show positions on the color pallet, which are used to specify a color to be displayed. The color pallet has a capacity of 256 colors, so that a color to be displayed may be selected directly in the 256 color mode. In other words, the pallet bank is not required in the 256 color mode.

FIGS. 9 and 10 show structure of the RAM in 64K and 16M color modes, respectively. In these color modes, color data are specified directly without using the color pallet. In the 64K color mode, one dot color data are specified by YUV (Y of 8 bits, U of 4 bits and V of 4 bits). On the other hand, in the 16M color mode, two dots color data are specified by YYUV (Y of 8 bits, Y of 8 bits, U of 8 bits and V of 8 bits). The first "Y" represents brightness of a first dot, the second "Y" represents brightness of a second dot and "U" and "V" represent common color shift of the first and second dots.

On a natural picture, seccessive dots are not very different in color from each other, so that the next dots may be separated by adjusting the brightness thereof. Thus, a character pattern may be defined by small data. As a result, the character pattern may be defined by 64 word data which is the same as that of 64 k color mode.

(2) EXTERNAL DOT SEQUENCE PROCESS

The external dot sequence process is basically equal to the external block sequence process, however, image data are processed dot-by-dot not block-by-block (character-by-character). Therefore, only one line in the tables shown in FIGS. 9 and 10 is used to define the CG. In 16M color mode, two lines are used to define two dots. The external dot sequence process is especially good for using the memory when a color is continuously changed with time or with position on an image. According to the external block sequence process, which uses many color modes, pictures may be displayed as if they are continuously changed in color. In this case, "64.times. (number of CG)" words are required in order to display the image in which each dot has independent color data. On the other hand, according to the external dot sequence process, "2.times. (number of CG)" words are sufficient in the 16M color mode and "1.times. (number of CG)" words are sufficient in the 64K color mode in order to display the image in which each dot has independent color data.

(3) INTERNAL DOT SEQUENCE PROCESS

The internal dot sequence process is different from the external block sequence process (1) and external dot sequence process (2). That is, according to the internal dot sequence process, a natural picture supplied from an image scanner or the like is directly displayed by a bit-map technique. In this process, the image data are not required to be defined by a user, so that the BAT is not required.

In this data system, five color modes of 4, 16, 256, 64K and 16M are used, and colors are defined for each dot in the same manner as the external dot sequence process. In the 16M color mode, two dot data may be defined by two words of YYUV. Therefore, 16M colors can be defined by the CG having a small capacity, and repeatability of the image is not seriously affected by the process. The internal dot sequence process is especially useful for the case where a natural picture is displayed and each dot of the image has independent color data.

FIG. 11 shows an information processing system of the preferred embodiment. The information processing system includes a game-software recording medium 100 such as a CD-ROM, a CPU 102 of 32-bit type, a control unit 104 for mainly controlling transmission of image and sound data and interfacing most devices to each other, an image data extension unit 106, an image data output unit 108, a sound data output unit 110, a video encoder unit 112, a VDP unit 114 and a TV display 116. CPU 102, control unit 104, image data extension unit 106 and VDP unit 114 are provided with their own memories K-RAM, M-RAM, R-RAM and V-RAM, respectively.

CPU 102 directly controls a DRAM via a memory support, and perform communication through an I/O port to peripheral devices, that is, an I/O control function. CPU 102 includes a timer, a parallel I/O port and a interruption control system. VDP unit 114 reads display data which have been written in the VRAM by CPU 102. The display data are transmitted to video encoder unit 112 whereby the data are displayed on the TV display 116. VDP unit 114 has at most two screens each composed of a background image and a sprite image, which are of an external block sequence type of 8.times.8 blocks.

Control unit 104 includes an SCSI controller to which image data and sound data are supplied through an SCSI interface from CD-ROM 100. Data supplied to the SCSI controller is buffered in the K-RAM. Control unit 104 also includes a DRAM controller for reading data which have been buffered in the K-RAM at a predetermined timing. In control unit 104, priority Judgement is carried out dot-by-dot for image data of natural background, and an output signal is transmitted to video encoder unit 112.

Control unit 104 transmits image moving data (full color, pallet), which has been reduced in scale, to image data extension unit 106 whereby the scale-down data are extended. The extended data are transmitted from image data extension unit 106 to video encoder unit 112. Image data extension unit 106 includes a reverse DCT converter, a reverse quantifying means, a Huffman coding and decoding means and a run-length coding and decoding means. That is, the image data extension unit 106 performs DCT transformation for a natural moving picture, and treats scale-down data encoded by the Huffman coding method and run-length scale-down data for moving animation image and the like.

Video encoder unit 112 superimposes VDP image data, natural background image data and moving image data (full color, pallet) transmitted from VDP unit 114, control unit 104 and image data extension unit 108. Video encoder unit 112 performs color pallet reproducing, special effect processing, D/A converting and the like. Output data of video encoder unit 112 are encoded into an NTSC signal by an Image Data Output Unit.

ADPCM sound data recorded in CD-ROM 100 are buffered in the K-RAM and then transmitted to sound data output unit 110 by control unit 104. The sound data are reproduced by sound data output unit 110.

FIG. 12 shows the internal architecture of CPU 102. The architecture includes an instruction fetch unit (IFU) 120, an instruction execution unit (IEU) 122, an I/O control unit (IOU) 124 and a memory control unit (MCU) 126. MCU 126 generates all control signals for a memory port to control the memory port directly connected to the main memory DRAM. This architecture adopts "eight-bit byte addressing architecture," whereby all data are treated for a byte or integral multiples of byte. In this system, one word is indicated by 4 bytes (32 bits).

The DRAM is composed of some memory arrays. The number of words (depth in address direction) in each array is defined by the number of words (depth in address direction in a chip). For example, a DRAM of "256.times.n" has memory arrays each having 256 k words. The number of chips composing the array is defined by the number of data ports of the DRAM.

FIG. 13 shows the DRAM of 256 k-word size.

FIG. 14 shows specifications for different types of DRAMs. In the preferred embodiment, different types of DRAMs 64 k.times.16, 128 k.times.8, 256 k.times.4, 256 k.times.16, 512 k.times.8 and the like may be used. Such memory types may be determined by a memory determination register. These memories are controlled by the CPU as far as the memory system information is supplied to the MCU in advance.

If such a memory system is used in a conventional apparatus, an IC for decoding data is required. The computer system of the preferred embodiment has a register in the memory controller (MCU) whereby the memory may be specified in structure and a refresh timer may be set by a predetermined program. The register may be addressed in accordance with a special register transmitting instruction.

The register is mapped in a special hardware register region (bank 3, address 4-7), as shown in FIG. 15A. A memory specifying register region takes 32 bits (4 bytes) at the address 4 in the bank 3. An area for instructing refresh time is taken at the address 5 in the same bank. The contents of the memory specifying register is shown as follows and in FIG. 15B.

    ______________________________________
    ROW.sub.-- SIZE
    ______________________________________
    000                   8 bits
    001                   9 bits
    010                  10 bits
    011                  11 bits
    100                  12 bits
    ______________________________________
    COL.sub.-- SIZE (column size)
    ______________________________________
    00                   8 bits
    01                   9 bits
    10                  10 bits
    11                  11 bits
    ______________________________________
    ARRAYS (array size)
    ______________________________________
    0                   1 array
    1                   2 arrays
    ______________________________________
    REFRESH.sub.-- EN (refresh enable)
    ______________________________________
    0                 refresh disable
    1                 refresh enable
    ______________________________________

• Inventors
  Itagaki, Fumihiko;
• Assignee
  Hudson Soft Co., Ltd. (Hokkaido, JP)
• Published
  May-13-1997
• Current US Classes:
  345/473
  345/501
  345/522
  345/634
  715/500.1
• Application #
  563779
• International Classes
  G06F 015/00
• Field of Search
  395/162-166 395/152-154 345/113-116 345/121 345/122
• Examiner
  Tung; Kee M.
• Agent
  Lowe, Price, LeBlanc & Becker
• US Patent References:
  4951038
  5089811
  5170154
  5218432
  5254984
  5296938
  5357604