Programmable digital video processing system

Abstract

Programmable apparatus for digital processing of video signals from multiple sources converted to digital format to provide real-time multiple simultaneous special video effects and suitable for direct interface to a conventional microcomputer bus such as an Apple Macintosh II NuBus. The apparatus includes a matrix of multipliers to do real-time video processing permitting special effects such as fading between at least two video image sources, as well as a priority resolver to control display on a pixel by pixel basis of more than ten sources based upon dynamically programmable priority. In addition, a programmable multiple range thresholder, a hardware window generator capable of generating multiple simultaneous windows, a color look up table and optional image capture capabilities are provided. The apparatus also provides for a light pen input, genlocking and a range of special video effects including zooming, mosaicing, panning and blending.

Claims

What is claimed is:

1. A digital video processor for processing video source components from a plurality of video sources, comprising: input means for receiving a plurality of video sources;

source selection means coupled to the input means, for programmably selecting a plurality of video source components from the plurality of video sources to provide a plurality of selected video source components;

blend input means for input of a blend value;

pre-scale multiplier means, coupled to the blend input means, for multiplying the input blend value by a programmable pre-scale constant to provide a pre-scaled blend constant source;

constant selection means, coupled to the pre-scale multiplier means, for programmably selecting a plurality of constants from among a plurality of constant sources including the pre-scaled blend constant source to provide a plurality of selected constants;

multiplier means, coupled to the source selection means and constant selection means, for multiplying each selected source component by a respective selected constant to provide a plurality of multiplier outputs;

summing means, coupled to the multiplier means, for summing the plurality of outputs to provide at least one summed multiplier output.

2. The digital video processor of claim 1 wherein at least one summed multiplier output is coupled back to the source selection means as one of the plurality of video sources.

3. The digital video processor of claim 1 wherein the multiplier means comprises a multiplier array which is comprised of a plurality of multipliers at least one of which is adapted to perform at least two multiplications within a pixel time period.

4. The digital video processor of claim 1 wherein the multiplier means comprises a plurality of multipliers each of which is adapted to perform a plurality of multiplications within a pixel time period.

5. The digital video processor of claim 3 wherein the multiplier array is comprised of a plurality of multiplier arrays each having inputs and outputs, wherein the output of at least one of said plurality of multiplier arrays is coupled to the input of at least one other of said plurality of multiplier arrays.

6. The digital video processor of claim 3 wherein the pre-scale multiplier means and the multiplier means produce fading effects.

7. The digital video processor of claim 3 wherein the pre-scale multiplier means and the multiplier means produce dissolving effects.

8. The digital video processor of claim 1 wherein each video source comprises signals representative of a plurality of pixels, and wherein the blend input means comprises means for input on a pixel by pixel basis of a unique blend value for each pixel.

9. The digital video processor of claim 1 wherein the multiplier means comprises an array of multipliers.

10. The digital video processor of claim 1 wherein the multiplier means comprises a three by three array of multipliers adapted to multiply each of three components of up to three selected video sources by a set of up to nine selected constants to produce up to nine products.

11. The digital video processor of claim 10 wherein the summing means comprises three summing circuits each adapted to sum three products to produce three summed multiplier components, and means for combining the summed multiplier components to form a summed multiplier output.

12. The digital video processor of claim 11 wherein the summing means further comprises means for providing a total sum of the three summed multiplier components and for selecting predetermined most significant bits of the total sum to provide a partial sum multiplier output.

13. The digital video processor of claim 1 wherein the multiplier means comprises a four by four array of multipliers adapted to multiply each of up to four components of up to four selected video sources by a set of up to sixteen selected constants to produce up to sixteen products.

14. The digital video processor of claim 1 wherein the multiplier means comprises an n by m array of multipliers, where n and m are both positive integers, adapted to multiply each of n components of up to m selected video sources by a set of up to nxm selected constants to produce up to nxm products.

15. The digital video processor of claim 14 wherein n equals m.

16. The digital video processor of claim 14 wherein n does not equal m.

17. The digital video processor of claim 14 wherein the summing means comprises n summing circuits each adapted to sum m products to produce n summed multiplier components, and means for combining the summed multiplier components to form a summed multiplier output.

18. The digital video processor of claim 17 wherein the summing means further comprises means for providing a total sum of the m summed multiplier components and for selecting a subset of predetermined most significant bits of the total sum to provide a partial sum multiplier output.

19. The digital video processor of claim 14 wherein the array of multipliers can be configured to perform blending.

20. The digital video processor of claim 14, wherein at least one video source is comprised of multiple video components, and wherein the array of multipliers can be configured to perform matrix transformations using all components of one video source.

21. The digital video processor of claim 20 wherein said video components are comprised of R, G, and B components.

22. The digital video processor of claim 20 wherein said video components are comprised of Y, U, and V components.

23. The digital video processor of claim 20 wherein said video components are comprised of Y, I, and Q components.

24. The digital video processor of claim 14 wherein the array of multipliers is selectively configurable to perform frame averaging.

25. The digital video processor of claim 9 wherein the array of multipliers is selectively configurable to perform filtering using one of said video components of said video source.

26. The digital video processor of claim 25 wherein said filtering is comprised of image processing, comprised of at least one of softening, sharpening, focusing, blurring, edge detecting, and highlighting.

27. The digital video processor of claim 9 wherein the array of multipliers is selectively configurable to perform simultaneous blending and matrix transformations.

28. The digital video processor of claim 9 wherein the array of multipliers is selectively configurable to perform color transformations.

29. The digital video processor of claim 3 wherein at least one video source is comprised of multiple video components, and each of the pixels has associated therewith data for said multiple video components.

30. The digital video processor of claim 29 wherein said multiple video components is comprised of a control component.

31. The digital video processor of claim 30 wherein the control component is used to control the blend input means on a pixel by pixel basis.

32. The digital video processor of claim 30 wherein the control component is used to control the pre-scale multiplier means on a pixel by pixel basis.

33. The digital video processor of claim 30 wherein the control component is used to control the constant selection means on a pixel by pixel basis.

34. The digital video processor of claim 30 wherein the control component is used to control the multiplier means on a pixel by pixel basis.

35. The digital video processor of claim 30 wherein the control component is used to control the summing means on a pixel by pixel basis.

36. The digital video processor of claim 30 wherein the control component is used to control at least one of the tint, contrast, hue, and brightness of the individual pixels.

37. The digital video processor of claim 30 wherein the control component is used to control the expansion of the individual pixels from a single video component other than the control component to all of the multiple video components.

38. The digital video processor of claim 30 wherein the control component controls video processing effects on a pixel by pixel basis.

39. The digital video processor of claim 30 wherein said control component is further comprised of multiple subcomponents.

40. The digital video processor of claim 30 wherein said control component is comprised of control information and non-control data.

41. The digital video processor of claim 1 wherein the blend input means is responsive to a constant generator.

42. The digital video processor of claim 41 wherein the constant generator is comprised of a plurality of constant generators.

43. The digital video processor of claim 41 wherein said constant generator is a pseudo-random generator.

44. The digital video processor of claim 43 wherein the pseudo-random sequence generator produces a linear pseudorandom sequence.

45. The digital video processor of claim 43 wherein the pseudo-random sequence generator produces a gaussian pseudorandom sequence.

46. The digital video processor of claim 41 wherein said constant generator is an external noise source.

47. The digital video processor claim 41 wherein said constant generator provides an output, wherein said output can be used as one of a blend value, a prescale value, and a video source.

48. The digital video processor of claim 1 wherein the multiplier means include overflow and underflow prevention means for substituting predefined limits responsive to detecting a sum outside a range of predefined overflow and underflow conditions.

49. The digital video processor of claim 1 wherein the multiplier means comprises a plurality of multipliers each adapted to perform multiplications at least at a real-time video rate.

50. The digital video processor of claim 1 further comprising: designation means for assigning a priority designation to each of the plurality of sources including the summed multiplier output; and resolver means, coupled to the designation means, for generating a source selection signal in response to the priority designations.

51. The digital video processor of claim 50 wherein the designation is selectively configurable to perform mixing effects.

52. The digital video processor of claim 50 further comprising a threshold means, coupled to the multiplier means, input means and resolver means, for comparing a programmably selected video source including the summed multiplier output to a plurality of programmable threshold ranges, and generating a priority designation for an associated source in response thereto.

53. The digital video processor of claim 52 wherein the threshold means can be programmed to perform wipe effects.

54. The digital video processor of claim 52 further comprising means for allowing a user to modify the programmably selected video sources.

55. The digital video processor of claim 52 further comprising means for allowing a user to modify the programmable threshold ranges.

56. The digital video processor of claim 52 further comprising output means, coupled to the resolver means, input means and the multiplier means, for selecting and coupling one of the video sources to an output in response to the source selection signal.

57. The digital video processor of claim 56 further comprising window means, coupled to the resolver means, for generating a plurality of window source and window priority designations.

58. The digital video processor of claim 57 wherein the resolver means is responsive to the window source and window priority designations for selecting and coupling selected ones of the video sources for output by the output means.

59. The digital video processor of claim 56 further comprising: a color look up table means, responsive to the input means, for providing a video signal output coupled to the output means as a video source, and for providing an associated priority designation coupled to the resolver means.

60. The digital video processor of claim 59 wherein the source selection signal generated by the resolver means provides for selection of one of the following sources for output to the output means: the input means, the multiplier means, or the color look up table means.

61. The digital video processor of claim 60 wherein the source selection signal generated by the resolver means can select between any of a plurality of input sources.

62. The digital video processor of claim 59 wherein the color look up table also includes a control component for providing a priority designation coupled to the resolver means.

63. The digital video processor of claim 59 wherein the color look up table means can be configured to perform colorization (also known as false coloring, or pseudo-coloring).

64. The digital video processor of claim 56 wherein each video source is comprised of a plurality of horizontal lines of pixels, and further comprising a programmable line control means for providing a plurality of control signals associated with each horizontal line for programmably altering source selections and multiplier constant selections.

65. The digital video processor of claim 64 further comprising pixel control means for providing, on a pixel by pixel basis, a blend constant value, and control signals for altering threshold ranges, output source selections and programmable threshold ranges.

66. The digital video processor of claim 65 wherein each video source comprises signals representative of a plurality of pixels and at least one associated control component, and wherein the designation means for assigning a priority designation is responsive to the threshold means, line control means, input means, pixel control means, and the control component.

67. The digital video processor of claim 65 wherein the designation means in conjunction with the threshold means and the pixel control means, selectively produces chrominance key effects on a pixel by pixel basis.

68. The digital video processor of claim 65 wherein the designation means in conjunction with the threshold means and the pixel control means selectively produces luminance key effects on a pixel by pixel basis.

69. The digital video processor of claim 56 further comprising frame control means for providing, on a frame by frame basis, a blend constant value, and control signals for altering threshold ranges, output source selections and programmable threshold ranges.

70. The digital video processor of claim 59 wherein the color look up table means is further comprised of multiple color look up table means, each of which is independently and selectively configurable for different video sources, outputs, modes, and priorities.

71. The digital video processor of claim 70 wherein the multiple color look up table is further comprised of a programmable means to select modes.

72. The digital video processor of claim 52 wherein each video source comprises a plurality of pixels and further comprising means for providing control signals for altering threshold modes, selected video sources for output, and programmable threshold ranges on a pixel by pixel basis.

73. The digital video processor of claim 52 wherein the designation means can be used in conjunction with the threshold means to selectively produce at least one of luminance and chrominance key effects.

74. The digital video processor of claim 59 wherein the color look up table means provides for selectively remapping of individual video components responsive to the input video source.

75. The digital video processor of claim 1 further comprising memory means for storing selected video source signals in the form of digital data.

76. The digital video processor of claim 1 wherein the pre-scale multiplier means can perform anti-aliasing of computer text and graphics over a plurality of video sources.

77. A video processing system comprising:

input means for receiving signals from a plurality of video sources;

multiplier the signals from means coupled to the input means, for multiplying at least one programmably selected video source with programmably selected constants to generate a multiplier video source;

designation means for assigning a priority designation to each of of the video sources;

resolver means, coupled to the designation means, for generating a source selection signal in response to the priority designation;

output control means, coupled to the resolver means, input means and multiplier means, for coupling of a selected one of the video sources to an output in response to the source selection signal.

78. The video processing system of claim 77 further comprising threshold means for comparing a programmably selected video source to a plurality of programmable ranges and for generating a priority designation for an associated source in response thereto.

79. The video processing system of claim 78 further comprising window means for generating a plurality of window priority designations and designation of respective associated video sources.

80. The video processing system of claim 78 wherein each video source comprises a plurality of pixels and further comprising means for providing control signals for altering threshold range modes, selected video sources for output, and programmable threshold ranges on a pixel by pixel basis.

81. The video processing system of claim 78 further comprising of a functional look up table means for controlling the designation means, resolver means, and output control means, and responsive to the threshold means.

82. The video processing system of claim 77 further comprising a video bus, wherein a plurality of video processing systems can be connected together via the video bus.

83. The video processing system of claim 82 wherein the video bus is comprised of two, independent bi-directional channels.

84. The video processing system of claim 83 wherein each channel is comprised of four video components.

85. The video processing system of claim 84 wherein the bi-directionality is independent for each component of each channel.

86. The video processing system of claim 82 wherein a plurality of video processing systems are connected to the video bus wherein a first video processing system provides output to the next video processing system responsive to the input means, wherein, thereafter, each next video processing system provides output to its respective output means responsive to the input means and the output from the previous video processing system.

87. The video processing system of claim 82 wherein the video bus is comprised of a plurality of independent bi-directional channels.

88. The video processing system of claim 87 wherein each channel is comprised of a plurality of video components.

89. The video processing system of claim 77 further comprising threshold means for comparing one of a programmably selected video source, portion of a video source, and a control source, to a plurality of programmable ranges and for generating a priority designation in response thereto.

90. The video processing system of claim 77 further comprising color look up table means for providing a video source, and a priority designation for an associated source in response to input of a video source.

91. The video processing system of claim 90 wherein the color look up table means is further comprised of multiple color look up tables, each of which is selectively configurable independently for different video sources.

92. The video processing system of claim 91 wherein the multiple color look up tables are further comprised of a programmable means to reconfigure the multiple tables.

93. The video processing system of claim 92 wherein the multiple reconfigurable color look up tables can be combined into a larger color look up table.

94. The video processing system of claim 77 further comprising capture means for digitizing an analog video source to provide a digital video source and for coupling the digital video source to the input means to provide one of the video sources.

95. The video processing system of claim 94 further comprising memory means for storing selected video source signals in the form of digital data.

96. The video processing system of claim 95 wherein the memory means is capable of storing data representations of the control components associated with the video source signals.

97. The video processing system of claim 95 wherein the memory means can be coupled to the output means to perform zoom effects.

98. The video processing system of claim 95 wherein the memory means can be coupled to the output means to perform panning effects.

99. The video processing system of claim 95 wherein the memory means can be coupled to the output means to perform mosacing effects.

100. The video processing system of claim 77, further comprising memory means comprised of a plurality of memory banks, each of which can be programmably configured to store video source signals from any of a plurality of video sources.

101. The video processing system of claim 100 wherein the plurality of memory banks can be programmably combined to form a plurality of larger memory banks, each consisting of a plurality of memory banks.

102. The video processing system of claim 77 wherein each video source comprises signals representative of a plurality of pixels, and further comprising a blend input means for the input on a pixel by pixel basis of a unique blend value for each pixel.

103. The video processing system of claim 77 wherein video input means include at least one video source is in a 24 frames-per-second film format.

104. The video processing system of claim 77 wherein the input means can receive a plurality of video sources, each in different video formats.

105. The video processing system of claim 77 wherein the input means can receive a plurality of video sources, at least one of which is in an interlaced format.

106. The video processing system of claim 77 wherein the input means can receive a plurality of video sources, at least one of which is in a non-interlaced format.

107. The video processing system of claim 77 wherein at least one video source is responsive to a pseudo-random sequence generator.

108. A method for processing video source components from a plurality of video sources comprising the steps of:

programmably selecting a plurality of video source components from the plurality of video sources to provide a plurality of selected video source components;

providing an input blend value;

multiplying the input blend value by a programmable pre-scale ratio to provide a pre-scaled blend source;

programmably selecting a plurality of constants from among a plurality of constant sources including the prescaled blend source to provide a plurality of selected constants;

multiplying each selected source component by a respective selected constant to provide a plurality of multiplier outputs;

summing the plurality of outputs to provide at least one summed multiplier output.

109. The method of claim 108 further comprising the step of coupling at least one summed multiplier output back as one of the plurality of video sources for selection of selected video source components.

110. The method of claim 108 further comprising the steps of assigning a priority designation to each of the plurality of sources including the summed multiplier output and generating a source selection signal in response to the priority designation.

111. The method of claim 110 further comprising the steps of comparing programmably selected video sources including the summed multiplier output to a plurality of programmable ranges and generating a priority designation for an associated source in response thereto.

112. The method of claim 111 further comprising the step of selecting and coupling one of the video sources to an output in response to the source selection signal.

113. The method of claim 112 further comprising the step of displaying the output.

114. The method of claim 112 further comprising the step of generating a plurality of window priority designations each associated with a window source.

115. A video processing system comprising:

input means for receiving signals from a plurality of video sources;

multiplier means for multiplying signals from at least one selected video source with selected constants to generate a multiplied video source;

clock means for providing programmable frequency timing signals for the input means and multiplier means comprising means for dividing the frequency of a reference clock signal by a first programmable number to provide a divided reference signal;

means for dividing the frequency of a selected signal by a second programmable number to provide a divided signal;

means for comparing the divided reference signal with the divided signal to generate a control signal dependent upon the difference between the frequencies of divided signals;

voltage controlled oscillator for generating a VCO signal having a frequency controlled by the control signal;

means for selecting the VCO signal as the selected signal and wherein the selected signal is utilized as a timing signal.

116. The system of claim 115 further comprising a chroma divider means for dividing the frequency of the selected signal by a third programmable number to provide a chroma clock signal, and a pixel divider means for dividing the frequency of the selected signal by a fourth programmable number to provide a pixel clock signal.

117. The system of claim 116 wherein the means for selecting further comprises means for programmably selecting between the VCO signal and at least one external clock signal to provide the selected signal.

118. The system of claim 115 further comprising means for providing a variable rate pixel clock which allows variable screen resolutions on a continuously variable range.

119. The video processing system of claim 115 further comprising output gamma correction means as a means for correcting for non-linear response of the video monitor systems.

120. The video processing system to claim 115 wherein the output means can produce a video signal in a plurality of different video formats.

121. The video processing system of claim 115 wherein the output means can produce a video signal in a plurality of different video formats, at least one of which is in an interlaced format.

122. The video processing system of claim 115 wherein the output means can produce a video signal in a plurality of different video formats, at least one of which is in a non-interlaced format.

123. The video processing system of claim 115 wherein the output means can product a signal in a plurality of different screen resolutions.

124. The video processing system of claim 115, further comprised of clock timing circuitry comprising system registers, and which selectively provides for modification of the system registers responsive to a security code key.

Description

BACKGROUND OF THE INVENTION

This invention relates generally to the field of video data processing and more particularly to methods and apparatus for real time digital video image processing of video image data suitable for use with a microprocessor or microcomputer and capable of providing multiple simultaneous special video effects.

In the prior art, various video special effects generating systems are known for use, for example, in broadcast television, computer graphics generation, etc. Video signal manipulation in various video environments is increasingly being carried out on video signals which have been converted to digital form. Available digital systems can individually produce a variety of known special effects. For example, it is often desirable to combine multiple independent sources of video by such known temporal video techniques as fades, wipes, or other key insertions. Other digital video systems are known for producing spatial video effects such as mosaic effects, blurring effects, scaling, or zooming. Still other digital systems generate windows, use color look up tables to provide a large palette of colors, or use specialized graphic circuits to provide computer graphics capabilities.

However, known systems are expensive and since they typically generate only a small set of effects, they do not permit close integration of multiple functions. These systems require multiple units to be combined to get multiple effects which is expensive and often presents incompatibility problems. Because the prior art systems even when coupled together do not permit close coupling of a variety of functions, they cannot generate many combinations of special effects and cannot generate many unique effects that require close integration of multiple functions. Thus, prior art systems cannot produce a wide variety of complex composite special effects where close integration of multiple functions is required.

Typically, prior art special video effects systems are self-contained systems which are designed to operate independently thereby making it difficult to interface them to a conventional microcomputer or to other special effects systems. In addition, video broadcast systems are uniquely designed to optimize video specifications such as sync, chroma burst, etc., while computer graphics systems optimize such computer specific characteristics as bandwidth, pixel definition, etc. Thus, no prior art system simultaneously optimizes both video and computer related features to permit computer control of such features as fading, blending, range thresholding, etc. This also creates incompatibilities when attempting to interface computer and video systems in a microcomputer environment. The ability to interface directly to a microcomputer bus allows video functions to be integrally combined with computer functions. This permits flexible control of video manipulation functions providing increased flexibility and extending computer control capabilities to complex video effects.

In addition, prior art video systems typically can operate in only one or a few specific targeted video environments such as a specific broadcast television market or a computer video graphics environment for a specific computer system. Thus, these prior art systems can only operate within a limited number of video standards (e.g., NTSC, PAL, etc.).

SUMMARY OF THE INVENTION

It is accordingly an object of this invention to provide a novel digital image processing system which economically provides multiple integrated special effects functions in real time.

It is another object of the invention to provide a novel digital processing system controlled by a conventional microcomputer and suitable for direct interface into a conventional microcomputer bus slot while maintaining both video and computer specification compatibility, thereby extending computer control capabilities to complex video effects.

It is another object of the invention to provide a novel digital image processing system having a programmable timing specification enabling conformance with any existing video standard.

It is another object of the invention to provide a novel programmable digital image processing system having a programmable pixel multiplier matrix capable of programmable blending of at least two independent video sources together with a matrix transformation of the video data in real time.

It is another object of the invention to provide a novel programmable digital image processing system having the capability of programmably assigning a priority to each of a plurality of video sources and for resolving the priority to determine the display source on a pixel by pixel basis.

It is another object of the invention to provide a novel programmable digital image processing system providing programmable multiple axis range thresholding of video data and hardware generation of multiple independent windows.

Briefly, according to one embodiment of the invention, a digital video processing system is provided comprising an input means for providing a plurality of multiple component digital video data sources, a multiple element digital multiplier means for real time multiplication of at least two of the digital video data sources and programmable constants to produce a multiplied digital video source. In addition, a threshold circuit is provided for comparing each of multiple components of a selected one of the digital video sources to a respective programmable range and a priority resolving circuit is provided for programmably assigning a priority to each of the video sources and for resolving the priority to select one of the digital video sources for display.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention, together with further objects and advantages thereof, may be understood by reference to the following description taken in conjunction with the accompanying drawings.

FIG. 1 is a generalized block diagram illustrating a specific embodiment of a digital video image processor system according to the invention.

FIG. 2 is a detailed block diagram illustrating a specific embodiment of the interface controller shown in FIG. 1 in accordance with the invention.

FIG. 3 is a block diagram illustrating a specific embodiment of the video system controller shown in FIG. 1 in accordance with the invention.

FIG. 4 is a detailed block diagram illustrating a specific embodiment of the video input interface shown in FIG. 3 in accordance with the invention.

FIG. 5 is a detailed block diagram illustrating a specific embodiment of the alpha buffer control circuit shown in FIG. 3 in accordance with the invention.

FIG. 6 is a detailed block diagram illustrating a specific embodiment of the line buffer control circuit shown in FIG. 3 in accordance with the invention.

FIG. 7 is a detailed block diagram illustrating a specific embodiment of the multiplier circuit shown in FIG. 3 in accordance with the invention.

FIG. 8 is a detailed block diagram illustrating a specific embodiment of the window control circuit shown in FIG. 3 in accordance with the invention.

FIG. 9 is a detailed block diagram illustrating a specific embodiment of the range thresholding circuit shown in FIG. 3 in accordance with the invention.

FIG. 10 is a detailed block diagram illustrating a specific embodiment of the video priority resolver shown in FIG. 3 in accordance with the invention.

FIG. 11 is a detailed block diagram illustrating a specific embodiment of the display multiplexer shown in FIG. 3 in accordance with the invention.

FIG. 12 is a detailed block diagram illustrating a specific embodiment of the color look-up table shown in FIG. 3 in accordance with the invention.

FIG. 13 is a detailed block diagram illustrating a specific embodiment of the master clock generator shown in FIG. 3 in accordance with the invention.

FIG. 14 is a detailed block diagram illustrating a specific embodiment of the absolute timing circuit shown in FIG. 3 in accordance with the invention.

FIG. 15 is a detailed block diagram illustrating a specific embodiment of the relative timing circuit shown in FIG. 3 in accordance with the invention.

FIG. 16 is a detailed block diagram illustrating a specific embodiment of the capture multiplexer shown in FIG. 3 in accordance with the invention.

FIG. 17 is a detailed block diagram illustrating a specific embodiment of the register interface shown in FIG. 3 in accordance with the invention.

FIG. 18 is a generalized block diagram illustrating a specific embodiment of the video bus means shown in FIG. 1 with generalized block diagrams of two possible example interconnections in accordance with the invention.

FIG. 19 is a generalized block diagram illustrating a specific embodiment of the multiplier circuit shown in FIG. 3 in accordance with the invention.

FIG. 20 is a generalized block diagram illustrating a specific embodiment of the multiplier circuit shown in FIG. 3 in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a generalized block diagram illustrating a specific embodiment of a digital video image processing system 10 according to the invention. The system 10 comprises a video system module 20 coupled as shown to a memory module 30 and an input module 40 as well as to a display device 42 and a host control device 50 such as a processor, controller, or microcomputer. In the illustrated embodiment, the video system module 20 comprises a central motherboard on which the optional daughter board memory module 30 may be mounted and in which an optional daughter board input module 40 may be mounted. Alternatively, other configurations may be used, for example, the video processor 20, memory module 30, and input module 40 may comprise a single circuit board.

In the illustrated embodiment, the video system module 20 is configured to fit into a conventional NuBus slot of a host microcomputer via a NuBus connector 28. The host microcomputer 50 may, for example, be a Macintosh II computer marketed by Apple Computer Company as in the illustrated embodiment. Other computers and bus configurations may also be utilized. In addition, other controller circuits, such as a microprocessor or microcontroller, may be used as the host control device 50. The video processor 20 of the illustrated embodiment is also coupled to a display device 42 via a display connector 52 wherein the display device 42 may be any video display device using any video standard including, for example a monochrome or color CRT monitor, an LCD display, an electroluminescent display, etc. The video system module 20 may also be coupled to external video devices or systems including another video system module 20 via a video bus connector 54.

The memory module 30 which provides digital video data memory for the system comprises primarily video memory banks 56 made up of dual port video dynamic random access memory (VDRAM) with 0 to 8 megabytes of VDRAM (e.g., using TC524256 VDRAM chips marketed by Toshiba). The video memory 56 is normally divided into four eight-bit deep video banks ABCD (alpha, red, green and blue (ARGB)) and is used to hold digital video image data. The video memory banks 56 are coupled to an address/data bus 34 via a multiplexed address bus 58 (10 bits in the illustrated embodiment) and a data bus 60 (32 bits in the illustrated embodiment) as shown. The address bus 58 permits addressing the video data and the data bus 60 permits passing data to and from the computer 50 via the video system module 20.

A serial video data bus 36 is coupled from the video memory banks 56 to a programmable video system controller 22 of the video system module 20, as shown. The video system controller 22, currently consisting of two closely coupled custom chips but could be contained in a single custom chip, controls most of the video special effects processing capability of the system 10 and controls the read/write video memory banks 56 on the video data bus 36. In the illustrated embodiment, the serial video data bus 36 is a bi-directional 64 bit bus (two-to-one interleaved 32 bit bus) which provides video data both to and from the video banks 56 which are organized with a two pixel interleaved configuration. A control bus 38 (48 lines in the illustrated embodiment) provides control signals to the video banks 56 from the video system module 20 including row address select, column address select, write enable, read enable, serial clock, and serial enable. A configuration register 39a is coupled to the address/data bus 34 to provide memory configuration information (i.e., amount of memory installed) to the system module 20.

The input module 40 provides for optional input signals including analog to digital capture of analog video at a programmable sampling rate. The input module 40 may accept multiple (three in the illustrated embodiment) analog video inputs (68) which are coupled to an analog input circuit composed of a sync strip circuit 62, a clamp circuit 64 and a shift/scaler circuit 66, as shown. The three inputs, for example, may be three color components Red (R), Green (G), or Blue (B); a luminance component and two chrominance components; or, any other three components of a conventional video format. Four inputs may be used to provide, for example, for input of four components A R G B. The three analog signals are coupled from the shift/scaler circuit 66 to an analog to digital (A/D) converter 70 (e.g., made up of three model CXA1096 converters marketed by Sony) which sample the three analog signals and converts each to digital form (e.g., 8 bits each).

The resulting 24-bit digital data is then coupled from the converter 70 through an isolation buffer 72 to the video system controller 22 of the video system module 20 via a 24 bit data bus 74, as shown. A configuration register 77 is coupled to the bus 74 via the buffer 72 to provide identification configuration information (e.g., sample rate, analog video format) to the video system module 20 during power up. The configuration register 77 in the illustrated embodiment comprises a set of resistors which are read during power up by disabling the isolation buffer output and reading the bus lines coupled to the register 77.

The input module 40 also provides for a set of external inputs 76 including a light pen input, an external trigger input (e.g., light pen trigger), a TTL video sync input, an external video clock input (e.g., for genlock) and a bi-directional serial control/data bus (e.g., to interface to conventional video integrated circuits), as shown. These signals are coupled through driver buffer circuitry 78 to the video system controller 22 via a control signal bus 80. A multiplexer 82 couples a sync signal stripped from the incoming video signal by the sync strip circuit 62 or a black burst sync signal from an input 84 through the control bus 80 to the video system controller 22 under control of a select signal coupled from the video system controller 22 via a control signal bus 86, as shown. The bus 86 also couples control signals from the video system controller 22 to the shift/scaler circuit 66 (i.e., a reference level signal) and clamp circuit 64 (i.e., a clamp window signal) as well as sample clock and reset signals to the converter 70 and isolation buffer 72.

In operation, the sync strip circuit 62 strips off the synchronization signals from the input analog video signals and couples a stripped sync signal to the multiplexer 82. The stripped analog signals are coupled to the clamp circuit 64 which detects the DC level of the video during a time window supplied by the video system controller 22 via the control bus 86. The shift/scaler circuit 66 then level shifts or scales the input analog signals to put the analog signals into the proper range for the A/D converter 70. The analog signals are coupled to the A/D converter 70 and the sample clock signal from the video system controller 22 controls sampling of the analog signal by the A/D converter 70. The resulting digital output from the A/D converter 70 is coupled to the video system controller 22 through the isolation buffer 72 to the video system controller via the data bus 74. The multiplexer 82 couples either the black burst sync signal or the stripped sync signal to the video system controller 22 under control of the controller 22. The controller 22 may then use the selected sync signal or the TTL sync signal in conjunction with the digitized video data.

In addition to the video system controller 22, the video system module 20 includes an interface controller 24, a triple D/A converter 26, a declaration read only memory (ROM) 88, and a line command and shadow memory buffer 90. The ROM 88 and buffer 90 are coupled via the control bus 38 and the data/address bus 34 to the video system controller 22, the interface controller 24 and the D/A converter 26, as shown. In the illustrated embodiment, the declaration ROM 88 is a 256 Kbit, electrically erasable programmable ROM (e.g., X28C256 EEPROM marketed by XICOR) to which are coupled chip select, read enable and write enable control signals from the control bus 38 as well as twenty six address and data lines from the address/data bus 34. The line command buffer and shadow memory buffer (shadow random access memory or SRAM) 90 comprises 128 Kbytes of random access memory (e.g., TC524 256 marketed by Toshiba) to which are coupled clock row and column address select, read enable and write enable control signals from the control bus 38, as well as twelve address and data lines from the address/data bus 34.

The declaration ROM 88 in the illustrated embodiment contains conventional data that is needed on any circuit board which is to be installed in a Macintosh NuBus bus based on the published NuBus protocol. This data contains information setting video modes, colors and a number of other parameters. The declaration ROM 88 is configured to allow the host Macintosh II computer to read the data at system power up via the interface controller 24. In addition, the EEPROM of the illustrated embodiment permits the data to be erased and reprogrammed under software control. The video system controller 22 in the illustrated embodiment also includes a configuration register 39 which is coupled to the address/data bus 34 to provide system configuration information to the system module 20. In the illustrated embodiment the configuration registers 39a and 39b comprise resistors connected at one end to ground or to the supply voltage and coupled to lines of the bus 34 which are read by the video system controller 20 during power up.

The line command and shadow memory buffers 90 may be loaded with information from the host microcomputer 50. The line command buffer stores commands for line by line control of video. Thus, line commands are used to override various of the current settings affecting operation of the video display on a line of video, after which the settings revert back to the original values. The line command buffer comprises 126 Kbytes in the illustrated embodiment and is organized such that the first 16 commands correspond to the first display line, the next 16 commands correspond to the second display line, etc. The shadow memory comprises 2 Kbytes of random access memory which is used to store the status of system internal latches and registers which are not readable to provide back-up which permits the system to read the last setting of the register.

The video system controller 22 is coupled to the video memory buffers 56 via the video data bus 36, the control bus 38 and the address/data bus 34, as shown. The controller 22 is also coupled to the input module 40 via the control buses 80, 86 and the data bus 74, and to the D/A converter 26 via a control bus 92 and a video data bus 94, as shown. A bi-directional video bus port 54 permits additional digital video sources to be coupled to the controller 22 including another video system module 20. The bi-directional video bus port 54 couples digital video data to and from the video system controller 22 via two bi-directional digital video data buses 96, 98 (e.g, 32 bit buses allowing four 8-bit video components in the illustrated embodiment) and a bi-directional control bus 100 providing clock, horizontal sync, and vertical sync signals. The video system controller 22 also couples a vertical sync signal line 102 and a composite sync signal line 104 to a display output port 52, as shown. The video system controller 22 performs programmable real-time video processing of the various video sources from the memory module 30, input module 40, the interface controller 24 and a video bus port 54 under control of the host computer 50 via the interface controller 24 to produce a wide variety of video effects.

The interface controller 24 which primarily controls the interface between the module 20 and the host computer 50 is coupled to the video system controller 22 via a control bus 106. In addition, the interface controller is coupled to the controller 22, the video memory buffers 56, the ROM 88, and the line command and shadow RAM buffers 90 via the address/data bus 34. The D/A converter 26 is coupled to the interface controller 24 via the address/data bus 34 as well as the read line 108 and write line 110. The interface controller 24 interfaces to the host computer 50 through a bus connector port 28, which is a NuBus connector in the illustrated embodiment. The NuBus connector permits the video system module 20 to fit directly into a NuBus slot of a host Apple Corp. Macintosh computer and thereby permits transfer of data to and from the host computer 50. The NuBus connector 28 is coupled to the interface controller in accordance with the NuBus standard via a multiplexed bi-directional address/data bus 112 (e.g., 32 bits in the illustrated embodiment), a bi-directional control bus 114 (e.g., 12 bits in the illustrated embodiment) and an ID bus 116 (e.g, four bits in the illustrated embodiment). A reset line 113 is also coupled from the NuBus connector to the interface controller 24 and the video system controller 22, as shown.

The D/A converter 26 (e.g., a Bt473 RAMDAC marketed by Brooktree Corp.) converts digital video signals coupled from the video system controller 22 via the video data bus 94. The resulting analog signals are coupled to the display connector 52 and through to the display device 42. The D/A converter 26 in the illustrated embodiment is a 24-bit triple D/A converter which converts three digital video components to three output analog video components (e.g., R,G,B,). Control signals, including sync, blank and clock signals are coupled to the converter 26 via a control bus 92, as shown. Synchronization signals for the video display are also provided by the sync signal lines 102, 104. The Brooktree RAMDAC converter 26 also permits gamma correction to permit compensating for the non-linear signal response of many display devices using look-up tables in the converter 26. Three tables (i.e., registers) are loaded and controlled by the host computer 50 through the interface controller 24 via the address/data bus 34 (e.g., the eleven least significant bits of the bus providing 8 bits of data and 3 bits of address) and read/write lines 108, 110.

Referring now to FIG. 2, there is shown a detailed block diagram of a specific embodiment of the interface controller 24 which receives addresses, data and control signals from the host computer 50 on the address/data bus 112, control bus 114 and ID bus 116. This information is used to generate and pass addresses, data and control signals to load the video memory banks 56, and the various buffers and registers of the programmable video system controller 24 and D/A converter 26 via the address/data bus 34, control bus 38 and control bus 106. In addition, the interface controller provides address, data and control signals to the host computer 50 via the buses 112, 114. Thus, the interface controller primarily controls communications between the host computer 50 (e.g, through the NuBus in the illustrated embodiment) and the video system module 20. The interface controller also implements the loading and reading of the shadow RAM 90 to permit reading of register status, implements an address offset capability, performs a timing register protection function, and generates a programmable refresh signal for refreshing the dynamic RAM of the video memory banks 56.

Address and data information is coupled between the host computers 50 and an address/data processing circuit 118 on the bi-directional address/data bus 112 through the NuBus connector 28. In addition, control signals on the bus 114 and ID signals on the bus 116 are coupled between the host computer 50 and a NuBus control circuit 120 along with a reset signal on the reset line 113, as shown. The processing circuit 118 comprises a data router 122, an address processor 124, and a timing register protection circuit 129. In addition, a set of X and Y address offset registers 126 is coupled to the address processing circuit 118. The register addresses are shown in abbreviated form with x signifying an offset from a base register address (which is $FsF00000 in the illustrated embodiment). This convention will be used hereinafter. All registers within the interface controller 24 are loaded by the address/data processor circuit 118 via a bus 131, as shown. Addresses and data are coupled to and from the data router 122 of the processing circuit 118 to and from the other buffers and registers of the video system module 20 and memory module 30 via the address/data bus 34. In addition, the addresses and data are coupled between the processing circuit 118 and a system memory controller 128 via an address/data bus 130. Decoded operation signals are coupled from the processing circuit 118 to the system memory controller 128 via a bus 132 and a security inhibit signal is coupled to the system memory controller 128 on a control line 134, as shown.

A valid address signal is coupled to the NuBus control circuit 120 on a control line 136 and a store enable signal is coupled from the NuBus control circuit 120 to the processing circuit 118 on an enable line 138, as shown. The NuBus controller 120 also generates a read/write enable signal which is coupled to the system memory controller 128 by an enable line 140 and generates a data available signal to enable a data read or write cycle which is coupled to the controller 128 by a control line 142. In addition, the system memory controller 128 generates an acknowledge signal in response to completion of a data read or write cycle which is coupled to the NuBus controller 120 on a control line 144. The control bus 106 which connects to the video system controller 22 couples an interrupt signal to the NuBus controller 120 on an interrupt line 146 and couples a video RAM transfer request signal to the refresh generator 156 on a control line 148, as shown. In addition, the system memory controller generates a video memory data transfer enable signal and register data enable signal which are coupled to the control bus 106 on enable lines 150 and 152, as shown.

The interface controller 24 primarily synchronizes address and data exchange with the NuBus and controls transfer to and from the video memory 56 and various system registers. Thus, the host computer transfers data by generating an identification code (ID) on the ID bus 116 which identifies to the board its slot in the bus. At the same time, an address is applied by the host computer on the address/data bus 112 followed by data (i.e., bus 112 is time multiplexed between address and data) which is processed by the address processor 124 to determine if it is a valid board address. If it is a valid address, a signal is sent to the NuBus controller 120 on the control line 136 which is used by the NuBus controller in conjunction with the proper ID and the NuBus control signals from the control bus 114 to generate and send a store enable signal to the address/data processor 118 on the enable line 138. In response to the enable signal, the processor 118 stores the incoming address and on the next clock cycle stores the associated data in internal registers with the proper timing as dictated by the NuBus protocol. Thus, the address/data bus 112 is de-multiplexed by the address/data processing circuit 118. The data router 122, comprising primarily a set of gates and multiplexer/demultiplexers, rearranges the address and data and couples them to the proper bus 34, 130 to transfer the data to the addressed video memory bank or system register. The address may also be offset by a predetermined number in either the x or y axis by the data router 122 based upon values stored in the x and y offset registers 126.

Thus, the data router 122 arranges addresses and data to be put on the bus 34 to be stored in the video memory banks 56, or for loading internal registers in the video system module 20. Conversely, the processing circuit 118 may couple data back to the host microcomputer 50 with the data router 122 arranging the data in proper format and multiplexing it on to the bus 112 with the NuBus controller generating the proper control signals in accordance with the NuBus protocol.

To accept data from the host microcomputer NuBus interface, the processing circuit 118 can utilize a pipelining technique in which the data and address are stored after which another cycle of reading and saving data and address information is initiated by an enable signal on enable line 138 at the same time that the previously stored data is transferred to system memory.

To control the transfer of data to system memory, the address processor 124 decodes the address and provides a control signal on the control bus 132 to the system memory controller 128 to identify the addressed segment of system memory (i.e., video memory, EEPROM, system registers, etc.). The NuBus controller 120 generates a data available signal which is coupled on line 140 to the system memory controller 128 to indicate that data and address information is stored and ready to be transferred. In response, the system memory controller 128 generates control signals to control transfer to or from the appropriate system memory location. After the transfer, the system memory controller 128 sends an acknowledge signal to the NuBus controller 120 on control line 144. The system memory controller 128 also generates control signals on the bus 130 to control the multiplexing of the data/address information by the data router 122. Thus, the system memory controller generates the control signals which control the transfer of data to and from the system memory. This process is controlled by data stored in system memory controller register 154 which are loaded with data via the bus 130. The system memory controller 128 also comprises a programmable refresh generator which generates a signal to activate a refresh cycle of the dynamic RAM installed in the system at an interval which is programmable by loading the desired value in the associated one of registers 154.

The transfer of data to registers which control timing of horizontal and vertical control signals is protected by a key code security system 129 incorporated in the address processor 124. If a protected timing register is addressed, the protection circuit 129 inhibits the system memory controller 128 unless a key register 133 coupled to the protection circuit 129 has been loaded with the proper key code on the previous data load cycle. The protection circuit 129 generates an inhibit signal which is coupled to the system memory controller 128 on the control line 134 and which inhibits the controller 128. If the key register 133 is first addressed and loaded with the proper code, the inhibit signal is not generated and the system memory controller 128 can generate the necessary control signals and transfer the data. This protection circuit 129 thus protects against accidental overdriving of the horizontal or vertical circuits of the display device 42.

FIG. 3 is a detailed block diagram of a specific embodiment of the programmable video system controller 22. The video system controller 22 provides the primary capability for video data manipulation and processing of video data from multiple input sources of video data for the system 10. The controller 22 is programmed by the host computer 50 by loading internal registers of the controller 22 through the interface controller 24 via the address/data bus 34. Thus, the address of the register to be loaded and the data to be loaded into the addressed register are coupled on the address/data bus 34 to a register interface 160 of the controller 22. The register interface 160 couples the incoming address and data information and control signals to a bus 162 which couples address data and control signals to all the internal registers associated with the functional blocks of the video system controller 22. The interface register 160 thus controls the loading of the registers internal to the controller 22. The control signals for loading the register are generated utilizing timing signals coupled to the register interface 160 from a relative timing circuit 164 and an absolute timing circuit 166 via timing signal bus 168, as shown. Control signals are also coupled between the register interface 160 and the interface controller 24 via the control bus 106. A reset signal is coupled to the register interface 160 on the reset line 113. The register interface 160 also controls coupling of signals and data back to the host computer 50 through the interface controller 24 via the bus 34.

The absolute timing circuit 166 generates programmable synchronization signals optionally locked to an external synchronization or video source, including horizontal and vertical blanking, and front and back porches. Thus, the absolute timing block can provide a wide variety of programmed or genlocked synchronization and timing signals to generate or synchronize with almost any video standard. These synchronization signals are coupled to the various function circuits of the controller 22 via a sync bus 170, the csync line 104, the vsync line 102 and the control bus 92. In addition, the absolute timing circuit 166 generates timing signals to control capture of video data to the video memory 56 which are coupled to a video capture multiplexer 190 via a control bus 172 and to the input module 40 via the control bus 86, as shown. Programmable line, field, and frame interrupts, as well as light pen interrupts, are also generated by the absolute timing circuit 166. The absolute timing circuit utilizes system and pixel clock signals coupled from a master clock generator 184 on a clock bus 186, external signals coupled on the buses 80, 100, and capture window enable signals coupled on an enable bus 174 to generate synchronization, capture enable and interrupt signals. The absolute timing circuit 166 also generates timing signals which are coupled to the relative timing circuit 164 via a bus 165, and absolute x and y pixel coordinate signals which are coupled to a window control circuit 176, a line control buffer 178 a multiplier 202 and a color look-up table 180 via a bus 182, as shown.

The relative timing circuit 164 is a programmable circuit which controls relative video memory bank configuration to control concatenation of the video memory bank via a control bus 38 to permit the video memory banks to be configured in many arrangements. It also generates control signals to coordinate use of the video bank for capture of video data and couples control signals to the video capture multiplexer 190 via a control bus 188, as shown. The relative timing circuit 164 also processes absolute timing signals coupled from the absolute timing circuit 166 on a line 165 and generates video memory bank addressing to allow for special effects such as panning, zooming, mosaicing, etc. An address translator within the relative timing circuit 164 permits remapping of the addresses provided by the absolute timing section to new addresses. Control signals are also generated to control a video input circuit 192 to control video input from several sources. The relative timing circuit 164 utilizes timing signals coupled from the absolute timing circuit 166, and enable signals from the window control circuit 176, as shown, as well as clock signals coupled from the clock generator 184 via the clock bus 186.

The video input circuit 192 comprises memory decoder and de-multiplexer circuits which process video data coupled from the video memory banks 56 via the video data bus 36, and from the A/D converter 70 of the input module 30 coupled via the data bus 74. Video data may also be coupled to the video input circuit 192 via the digital video data buses 96, 98 from the video port 54. The data from these sources is coupled by the video input circuit 192 to one of several internal video buses including live A/D bus (LADC) 194 (e.g., 24 bits) a live digital video port (LDIG) bus 196 (e.g. 32 bits), a video bus one (DV1) 198 (e.g., 24 bits) and a video bus two (DV2) 200 (e.g., 32 bits), which are coupled to a multiplier circuit 202, a video range thresholding circuit 204, the color look up tables 180, a display multiplexer 206 and the video capture multiplexer 190, as shown. The video input circuit 192 also performs parallel to serial conversions of video data for display of single, double and quad bit data, as well as parallel expansion of word data. A decoding function provides the capability for interpreting and decoding compressed image formats. Control signals for controlling the video data input and output are coupled from the relative timing circuit 164 via a control bus 173, as shown. In addition, the video input circuit 192 couples alpha buffer data to an alpha buffer control circuit 212 via a data bus 214 and control signals to the color look up table 180 via a control line 216.

The alpha buffer control circuit 212 interprets pixel values from the alpha buffer of the video memory 56 (i.e., the first of the four video banks) as commands in several different programmable modes. The alpha pixel commands enable or disable other operations or modes on a pixel by pixel basis enabling pixel by pixel control of the video display. The alpha buffer control circuit 212 utilizes alpha buffer data coupled from the video input circuit 192 via the data bus 214 to generate alpha buffer control data coupled on a control bus 221 to the multiplier 202 and a control bus 296 to other functional circuits of the controller 22 to control functions on a pixel by pixel basis. The alpha buffer control circuit 212 also generates alpha buffer priority data coupled to the video priority resolver 208 via a control bus 220 and control signals which are coupled to a thresholder via a control bus 298.

The line buffer control circuit 178 interprets commands stored in the line command buffer 90 which are coupled to the line buffer control circuit 178 via the address/data line 34. Absolute x pixel coordinates are also coupled to the line buffer control circuit 178 from the absolute timing circuit 166 by bus 182, as shown. The line buffer control circuit reads commands from the line command buffer to enable or disable other modes or operations before scan lines are read from video memory and at programmable absolute x coordinates along a line. Thus line basis which are coupled to the video priority resolver 208 via a control bus 222, and generate control signals on a line basis which are coupled to the multiplier 202 via a bus 224. In addition, control signals are generated which are coupled via a control bus 227 to various functional circuits of the video system controller 22 to enable or disable functions on a line by line basis.

The window control circuit 176 generates control signals to maintain four rectangular window regions in absolute x and y pixel coordinate space utilizing values loaded into internal registers. The x and y pixel coordinates are coupled from the absolute timing circuit 166 via the bus 182. The window control circuit generates window capture signals which are coupled to the timing circuits 164, 166 on the enable bus 174, and generates priority signals based on internal register values for each of the four windows to define window boundaries which are coupled to the video priority resolver 208 on four window priority buses 225, 231, 228, 229. The window priority is arbitrated within the window control circuit; only the highest window priority signal is passed to the priority resolver.

The multiplier circuit 202 comprises primarily a matrix of nine dedicated signed 10.times.9 bit high speed multipliers which can perform a multiplication in less time than required to display one pixel. The multiplier 202 can select from six input video sources which include the live A/D video bus 194, the live digital video port bus 196, the video bus one 198 and the video bus two 200, a color look-up table one (CLUT1) video bus 230 and a color look-up table two (CLUT2) video bus 232. The multipliers typically multiply a video source by a blending or mixing constant. The multiplier circuit can perform a matrix transformation on data from one of the video sources, perform a programmable blend of up to three of the video sources, perform frame averaging of an incoming static video signal and execute spatial filtering on one of the video data sources. The multiplier utilizes control and data signals from the alpha and line buffer control circuits 220, 178, as well as the video sources. The resultant multiplied signal is coupled to a multiplier video bus 234 which couples the resultant signal to the video range thresholding circuit 204, the color look-up table 180, the display multiplexer 206 and the video capture multiplexer 190. In addition, a partial sum is also generated and coupled to a partial sum bus 236 which is coupled to the display multiplexer 206 and the video capture multiplexer 190, as shown. More than nine multipliers may optionally be used, for example, a four by four array of multipliers would be used to permit four sources with four components each to be multiplied by up to sixteen constant values.

The range thresholding circuit 204 compares three sets of upper and lower programmable reference values loaded into internal registers on a pixel by pixel basis to incoming video source data on the buses 194, 196, 198, 200, 230, 232, 234. More than three sets of reference values and comparisons may optionally be provided. Based upon the comparison, priority and source signals are generated and coupled to the video priority resolver 208 on a priority bus 240. The range thresholder may also output a priority and source for those pixels that define a transition or change in the input video source, such that comparisons that result in a change of the thresholder output also result in the generation of a programmable plurality of transition pixel priorities and sources.

The priority resolver 208 examines six priority input signals coupled from the alpha buffer control 212, the line buffer control 178, the range thresholder 204, the video input circuit 192, the window control 176, and the color look-up table 180 of the video system controller 22, each of which has an associated dynamically programmable priority level and video data source designation, and determines for each pixel which video source has the highest priority. The priority resolver outputs an index signal referencing the highest priority video source on a bus 238 which is used by the display multiplexer 206 to output the highest priority video source.

Since the display priority level is programmable, it is possible that two or more video sources could have the same priority level for the same pixel. If this priority level is the highest level at the pixel, then an implicit priority order is used wherein the video data source with the highest implicit priority is selected (e.g., in the illustrated embodiment the implicit order is the order of the inputs to the resolver 208 as follows: buses 220, 222, 225, 231, 228, 229, 201, 203, 181, 183, 240). It is also possible that there may be no contenders of any priority level at a given pixel. In this case, a programmable default video data source is selected to be displayed in the absence of any other. The thresholder circuit 204 also generates control signals which are coupled to the capture multiplexer via a bus 406, as shown.

The display multiplexer 206 selects for display a video source from one of the video buses 194, 196, 198, 200, 230, 232, 234, 236 coupled to it under the control of the select signals from the priority resolver 208 on the select bus 238 and on a default line 239. The selected video source is coupled to the D/A converter 26 via the video data bus 94 for display and to the video capture multiplexer 190 on the data bus 207, as shown.

The video capture multiplexer 190 is a multiplexer and encoder circuit which controls storing of video data arriving at its inputs into the video memory buffers 56 or coupling the data to the digital video port 54, and which encodes the video data into formats suitable for writing to the video memory 56 or the digital video port 54. The input video sources are the video buses 194, 196, 200, 234, 236 and the output data bus 207 of the display multiplexer 206, as shown. Control and timing signals are provided from the absolute timing circuit 166 and the relative timing circuit 164 via control buses 172, 188. The video capture multiplexer 190 also provides serial to parallel conversion of the video data for storage of single, or double byte pixel data. In addition, the video capture multiplexer 190 provides the capability to encode video data in one of two compressed forms: YCc and RGB555 and to store a single component of the video data in any one or all four of the video memory banks 56. The data is output onto the video data bus 36 to the video memory banks 56 or on one of the digital video data buses 96, 98, to the digital video port 54.

The color look-up table (CLUT) 180 is provided to permit remapping of color pixel values, CCC decoding, gamma correction and to provide a hardware cursor mode. The absolute x,y pixel coordinates on the bus 182, CCC bit map signals on the bus 216 and video bus sources 194, 200, 234 are utilized by the CLUT 180. Based on three inputs the CLUT 180 provides output video data to a color look-up table one (CLUT1) video bus 230, a color look up table two (CLUT2) video bus 232, and two color look-up table display priority signals coupled to the video priority resolver 208 on the priority buses 181, 183, as shown.

A color look-up mode permits selection of an output pixel color based on an index value using three color look up tables (one for each of three components). An input value from one of the input video sources is used as an index into all three tables simultaneously. The three values referenced by the index are then used as color components of a pixel which are output on one of the video buses 230, 232. The color look-up table is divided into two somewhat similar halves, but both halves can be joined to provide a color look-up table which is larger. A gamma correction mode permits compensation for non-linear characteristics of video sources at different signal levels. In the gamma correction mode, one half of the table is used as three independent color tables and each of the three color components of the input video source are used as an index into its own color table. The values referenced by the indices are then used as the new color components for the output of the color look-up table 180. Thus, a video source can have its color components individually corrected or remapped. In the hardware cursor mode, the color look-up tables are used to control a small rectangular region of pixels at a programmable continually variable location.

The system module 20 is a programmable and highly flexible digital processing device capable of a wide variety of digital special video effects and video manipulation. The system module 20, in the preferred embodiment, plugs directly into a NuBus slot in, for example, an Apple Macintosh II series computer. The system module 20 supports all standard video display modes permitting it to be configured with virtually any video monitor. The input module 40 supports capture of an image from an external source which may be such sources as an RGB video camera, a time-base corrected video tape or disc player, or virtually any device that can generate a component RGB video signal. The input module 40 also supports a light pen and the system module 20 can retain the last absolute x,y position of the light pen on the displayed image. Most of the operations of the system 10 are accomplished in the digital domain, and therefore, there is no loss of detail as commonly experienced with analog effects. In addition, the effects are accomplished in real time in most cases and utilize static images, animated computer graphics, or real-time video sources.

Due to the programmable timing circuitry 184, 164, 166 of the video system controller 22, the system module 20 provides highly flexible timing which can be configured to match the timing specifications of virtually any video standard such as NTSC, PAL, etc. Timing options include interlace, repeat field, and noninterlace video generation. When generating an interlace video signal, the system module 20 can provide equalization and serration pulses. Data encoded in the vertical blanking intervals such as SMPTE, VIR, or closed caption may normally be blocked but may be optionally passed through. Timing circuity may also be configured to synchronize to an external video source(genlock) or an external synchronization source. The signal generated is in synchronization with the incoming video signal or synch. If the incoming video signal or synch timing is of broadcast standard, the system will produce an output broadcast standard.

Video data can also be output in analog form using a conventional D/A converter 26 to encode the signal into composite analog form. A digital video bus port 54 is provided which permits the exchange of digital video information with other digital video devices coupled to the system. For example, the digital video bus allows direct interconnection of multiple system module 20 circuits or other input or output devices. A wide variety of digital special effects are made possible by the programmable multiplier array 202 and other circuits including mosaicing, pixelization, posterization, solarization, blending, filtering and anti-aliasing. These visual effects are generated in the digital domain and thus many are virtually impossible to do in analog circuitry.

The mosaic effect replaces an image with fewer, but larger "pseudo pixels". This effect may be accomplished in the horizontal or vertical direction. The ratio of the size of the original pixel to the pseudo pixels is highly controllable and programmable. Pixelization is accomplished by mosaicing in both the horizontal and vertical directions. The horizontal and vertical mosaic factors do not need to be identical. This pixelization effect can be used in conjunction with live video mixing to produce the effect commonly used to obscure witness identities or to censor images for television display. Posterization is an effect which restricts the image to a subset of the colors actually present, and sets areas closely related in color or value to the same pixel color and value. This effect is similar to the photographic posterization effect except that the video effect is continuously variable and reversible. This effect may be accomplished by mathematically clipping off less significant bits of the pixels (i.e., truncation). Solarization is an effect that creates a false color or pseudo color effect which is also highly programmable and reversible.

The system module 20 also provides noise generation which produces linear and Gaussian white noise to create a display effect which is similar to that created by a television set which is not tuned to a station. Noise generation is particularly useful for filtering and can be used to control other effects. Since the digital system module 20 provides sharp transitions in an image, some aliasing or image artifacts may appear as a result of the sharp transitions in the image in video formats such as NTSC. This aliasing can be corrected by the real-time anti-aliasing capability of the system module 20 which is capable of performing such functions as fades and mixes while also simultaneously performing anti-aliasing.

Other special effects include traditional video switcher effects and image manipulations including vertical and horizontal scaling, zero order effects and vertical interval manipulations. The system module 20 can independently scale or zoom an image by integer multiplication factors in both horizontal and vertical directions. The appropriate part of the image is replicated along a line in the horizontal direction and the appropriate video lines are repeated as needed. A vertical mirroring effect can be produced by the system module 20 by displaying the top half of the display in reverse vertical order from the bottom half. Any kind of repeating or mirroring in the vertical direction is possible, including vertical reversals or flips and venetian blind effects. Rolling or panning can be performed by displaying different parts of the same image over time. Horizontal and vertical rolling can be performed independent of each other. If an image is being displayed which is much larger than the display area, the image can be "paged through" one display screen at a time.

Conventional video effects such as pulls and pushes can be performed by capturing the video signal and using the appropriate rolling effect. A drop shadow effect can be produced which edges a video image or portion of an image with a selected color or effect. The system can also capture such signals as automated color signals, SMPTE, time code signals and other codes that are inserted into the vertical interval in a video signal and can pass them through or remove them. Some subsets of these codes such as the SMPTE code can be generated or modified as well. The system module 20 is also capable of character generation and can operate in an anti-aliasing character generation mode in which high quality character generation is produced with the number of fonts, faces styles and sizes limited only by the host computer software. The system sill retains the capability to perform such functions as fades and mixes while in this anti-aliasing graphics mode.

Other special video effects such as wipes, fades, video mixing and thresholding are other video effects and functions which may be performed in real time with the system 10. A wipe can be performed from one image source to another with virtually any direction and speed. A fade can be accomplished by mixing a percentage of one image with a percentage of another image. Video mixing allows the video to appear to overlay or go behind other video sources. Multiple windows can also be controlled in real time. Operations such as geometric dissolves, fades, and mixes between two image sources are supported and include square, circular, triangular or other shaped transitions from one image to the next. Any arbitrary shape or shapes can be programmed in switching from one video source to another, and the switch can be hard or soft edged. These effects can be controlled on a frame by frame, line by line, or pixel by pixel basis.

The system module 20 also provides for blending or mixing operations by taking a selected percentage of one image and adding it to a selected percentage of another image. A selected percentage of a third image may be blended in as well. This third image could be used, for example, to add a texture to the blend of the first two. This video mixing is accomplished under the control of a digital fader or level control and noise generation can be used to control blending or mixing of the two images. Thresholding allows a range comparison to be made on a component of color. The result of this comparison can be used, for example, to determine a "key" to control which video source to display at any point on the screen. Multiple thresholders 204 in the system module 20 can be logically combined to create key methods that are currently unavailable, as well as standard types, like "chroma key" and "luma key". Shadowed areas in a chroma key area can be used to alter the luminance of the background graphics, creating a live "pseudo shadow" on top of the graphic image.

Image capture capability is also provided by the input module 20 which involves a digitization of live video signals from an external analog source and recording the data into digital video memory 56. System module 20 in conjunction with the input module 40 is capable of continuously capturing a complete color video frame in real time and processing the digitized data in real-time. For example, a standard NTSC mode frame can be captured 30 times a second with the capture rate flexible enough to be compatible with the characteristics of virtually any incoming video signal. Strobing may be accomplished by repeatedly capturing a video image and holding for short duration before capturing the next image. Selective capture is provided by restricting the capture of live video on a line by line or pixel by pixel basis. The system provides direct support of RGB color space and can be configured to work in YUV, YIQ, and other common color spaces.

The system module 20 supports many computer display modes, including the standard display modes of the Apple Macintosh II series computer. Color look-up table operation modes including the Apple Standards are also supported wherein the display shows a number of user selected colors from a palette of over 16 million colors. In these modes, a reasonable selection of colors is attainable using a smaller amount of memory for the image itself. These modes are commonly called one, two, four and eight bit color look-up table modes. Additionally, the system module 20 supports a nine bit color look-up table format. In the one bit color look-up table mode, a single bit in the image memory determines which of two colors, each specified with 24 bits RGB precision, is to be displayed at that pixel. A 2 bit mode utilizes two bits in the image memory which determine which of four colors, each specified with 24 bit RGB precision, is to be displayed at each pixel. In a 4 bit mode, a group of 4 bits in the image memory determines which of 16 colors, each specified with 24 RGB precision, is to be displayed at each pixel. An 8 bit mode provides a group of 8 bits in the image memory which determine which of 256 colors, each specified with 24 bit RGB precision, is to be displayed at each pixel. The 9 bit mode provides a group of 9 bits in the image memory, which can be used in two different ways: it can determine which of 384 colors each specified with 24 bit precision is to be displayed at each pixel, or it can determine which of 512 colors, the first 256 of which are specified with 24 bit precision and the second 256 of which are specified with 16 bit precision, is to be displayed at each pixel.

In addition, a direct pixel display mode is provided in which millions of colors may be displayed simultaneously with the only limit being the number of pixels on the screen. The direct pixel display is provided in a 16 bit mode in which a group of 16 bits are treated in four parts, 5 bits each for red, green and blue components, and 1 bit which is designated as an alpha bit whose significance varies. This mode is also known as the RGB 555 mode. An RGB 565 mode in which the green component uses six bits (the original five plus the alpha bit) is also provided. A 32 bit mode is also provided in which a group of 32 bits are treated as four parts: 8 bits each for the red, green, and blue components, and the 8 bits left over are designated as an alpha byte, whose meaning is variable. This mode is also designated as the RGB 888 mode. The system 10 can use the eight bit alpha byte for a wide variety of enhanced effects which can be performed on a pixel by pixel basis. Since only 3 sets of 8 bits are being used for color information, this mode is also sometimes referred to as a 24 bit mode. TP Filtering operations are also provided which allow the color at any location on the screen to be affected by the colors around it. Filtering operations can be affected by selected color space components at each location.

Using the memory module 30, the system 10 in the illustrated embodiment can contain up to 8 MegaBytes of video memory in the form of conventional video DRAM. This memory is contiguous in the system address space and is organized such that consecutive raster lines are an equal distance apart in memory. This distance between lines is called rowbytes, and is even. Also video memory can be used for capturing images using the A/D converter 70 of the input module 40.

Video memory is divided into four banks--A, B, C, and D. These banks normally hold images that can be displayed. When displaying from video memory, many different modes are possible. The most straight forward mode contributes the red, green, and blue components from the B, C, and D banks. Other modes may display from just a single bank, or a concatenation or combination of multiple banks. For example, the A and B banks can be treated as independent 8-bit/pixel banks (e.g. eight bit color look up table), or can be combined to act as a single 16-bit/pixel bank (e.g. RGB555). Alternatively, the banks can be concatenated horizontally or vertically. For example, two 1K.times.1K 8-bit banks can be treated as two separate 8-bit banks, as a 1K.times.2K 8-bit bank, as a 2K.times.1K 8-bit bank, or as a 1K.times.1K 16-bit bank. Although the A and B banks were used in this example, these banks would be used for displaying red, green, and blue component data.

In addition, there is great flexibility in the way the bank data can be displayed. The bank data can represent a color look up table (CLUT) image, where each pixel value represents an index to an RGB color. The bank data can be combined into direct pixels, where each pixel has red, green, and blue components which directly represent a color. The banks can also represent YCc (this notation is short for YUV or YIQ), DYUV, or CCC pixels (which are a compressed form of YCc or RGB pixels).

The position and timing for each bank is independently controllable relative to the absolute screen position. Each bank has an associated X and Y offset (this can be used for panning), a horizontal and vertical zoom factor, and a horizontal and vertical mosaic factor for varying the position of the bank and apparent pixel size. The horizontal and vertical zoom and mosaic factors are independent so that the aspect ratio may be altered. The video system controller 22 can manipulate a variety of display sources and control their display on a pixel by pixel basis using display priorities. Thus, at any given pixel, the highest priority display source is selected by the priority resolver 208. For example, if there are two rectangular windows which overlap, the window with the highest display priority is displayed as if it is on top.

There are seven different display sources that the video system controller 22 can control in one of two formats; twenty-four bits RGB, or eight bits gray scale. When an eight bit display source is selected, the eight bits are copied to each of the red, green, and blue components, thus providing a 24 bit grey scale display source. There are three fixed format sources which provide 24 bit data and three fixed format eight bit sources which provide 24 bit gray scale data. The thirteen different display sources are - Live A/D, Live Digital In, Video Bus one, Video Bus two, CLUT 1, CLUT 2, multiplier output, partial sum output, default color one, default color two, Live Digital in alpha channel, Video Bus Two alpha channel, and truncated partial sum output. The first seven of these display sources are the seven dual format sources. The next three of these display sources are the three fixed 24 bit sources. The last three of these display sources are the three fixed eight bit sources.

Analog live video can be fed to the input module 40 and the analog signal may be converted to 24 bits (8 red, 8 green, and 8 blue) by the analog to digital converters 70. These 24 bits are put on the Live A/D video bus 194 (LADC) and can be selected as one of the RGB display sources. The 32-bit digital video port 54 can accept live digital 32 bit data (Live Digital In bus 196-LDIG). This could for example be from the output of another system module 20. The low 24 bits of this can be selected as an RGB display source. The upper eight bits can be used to represent an intensity, and can be selected as an eight bit display source (which is expanded to 24 bits). The video system controller 22 contains two internal video buses: Video Bus One 198, and Video Bus Two 200. Video Bus One is a 24-bit RGB data path and Video Bus Two is a 32 bit ARGB data path. These data paths carry digital video information just as the Live A/D and Live Digital in data paths. However, in this case, the source of the information on the video buses comes from the video memory banks 56.

The video system controller 22 also contains two Color Look Up Tables (CLUT) which expand color indexes to 24-bit RGB data sources 230, 232. In addition, each CLUT can be put in a hardware cursor mode which displays a 16.times.16, or 32.times.32, 24-bit image. These CLUT sources 230, 232 are two of the RGB display sources. The multiplier 202 outputs can also be used as a display sources. In some modes, the upper eight bits of the multiplier array sum 236 may represent a partial sum output and can be used as a gray scale display source. Two additional video sources are provided by two default color registers with each register representing a 24-bit RGB color. Both default colors can be used as display sources.

Referring now to FIG. 4, there is shown a detailed block diagram of a specific embodiment of the video input interface 192 comprising primarily a serial data multiplexer 260 and a video routing multiplexer 262, together with an input driver 264 and an input select circuit 266, as shown. Serial digital video data is coupled to the serial data multiplexer from the video memory 56 via the video data bus 36 made up of four component buses 268, 270, 272, 274 for the alpha red, green and blue components. In addition, a set of control signals is coupled to the serial data multiplexer from the relative timing circuit 164 via the bus 173 and a set of control registers 280 also provide initial values of the DYUV mode. The serial data multiplexer demultiplexes the serial data from the bus 36 and couples it through on a 128 bit video data bus 226 to the video routing multiplexer 262. The control signal bus 173 includes a control line for initializing the DYUV mode and a data bus 228 couples DYUV decoded data from the serial data multiplexer 260 to the video routing multiplexer 262. The control signal bus 173 also couples control signals to the video routing multiplexer 262, as shown.

Also coupled to the video routing multiplexer 262 is a set of control registers 281 which are coupled via a control signal bus 282 to the video routing multiplexer 262. The control registers 281 are the display bank mode control registers which are loaded by the register interface 160 via the bus 162 (see FIG. 3) thereby permitting programmable control of the video input interface 192. The video routing multiplexer 262 decodes video pixel data and couples the video data to the video data bus One (VD1) 198 and the video data bus Two (VD2) 200 depending on the status of the control registers 281. In addition, the video routing multiplexer may generate a display priority and source signal on the priority bus 201 and 203 which are coupled to the video priority resolver 208. The multiplexer 262 also couples the alpha buffer data to the alpha buffer control 212 via the bus 214 and generates a color look-up mode control signal on the bus 216 which is coupled to the color look-up table 180.

An input select circuit 266 is also provided which selects one or both of the video port video data buses 96 and 98 under control of a control register 279. The resulting selected input is coupled to the output live digital video port bus 196, as shown. In addition, the control registers 281 determine a control signal (D8Rate) coupled to the system circuits via the output 286 which determines the color look-up bit mode for each bank independently (i.e., 1, 2, 4, 8 bit mode). In addition, live video data from the A/D converter 70 of the input module 40 is coupled via the bus 74 to an input driver 264 which couples the live input video to the live A/D (LADC) bus 194, as shown.

FIG. 5 is a detailed block diagram of specific embodiment of the alpha buffer control circuit 212 which comprises primarily logic array 288 into which are coupled a set of control registers 290 which provide programmable control information to the alpha control array 288. In addition, the alpha buffer data is coupled from the video input interface 192 to the alpha buffer control array 288 via the bus 214, as shown. The alpha buffer is simply one of the banks of the video memory 56 which can contain image data, or the alpha buffer data can be used as a source of commands. These commands can alter the display on a pixel by pixel basis including control of a blending value for the multiplier 202, control of the inputs to the multiplier 202, control of generation of source and priority values and control of the input to the range thresholder 204. The alpha control array 288 generates control signals on a pixel by pixel basis which are primarily applied to the multiplier 202 via the control bus 221, as shown. In addition, a pixel capture control signal is coupled via a line 292 to the window control circuit 176 and an alpha capture shift clock enable signal is coupled to the relative timing circuit 164 via a control line 294. A set of enable capture signals are coupled to the display multiplexer 206 via a control bus 296 and a set of enable and threshold signals are coupled to the range thresholding circuit 204 via a bus 298. Priority and source signals are also coupled from the alpha control 288 to the priority resolver 208 via the control bus 220.

Referring now to FIG. 6, there is shown a detailed block diagram of a specific embodiment of the line buffer control 178 comprising primarily a command buffer 300, a line control decoder 302, and a set of control registers 306, 312, and a combiner 308, as shown. The command buffer accepts line commands from the line command buffer 90 via the address/data bus 34. The command buffer is dual ported so that while signals are being coupled out of the command buffer 300, additional command information can be read in. Also coupled to the command buffer 300 are control signals pulled from the absolute timing circuit 166 on the control bus 182 which control operation of the buffers. The command buffer 300 couples command signals to the line control decoder 302 via a command bus 310 and the x position of the pixel are coupled to the line control decoder 302 via the bus 182. Also coupled to the line control decoder is a mode control register 306 which is loaded by the register interface 160 via the bus 162 (not shown) and which permit programmability of the line buffer control circuit 178. The line control decoder 302 provides control signals on a line by line basis (i.e., up to sixteen commands per horizontal scan line) to the multiplier 202 via a bus 224, as shown, and several additional prescan command signals which are coupled to the other functional circuits of the video system controller 22 on a bus 227. The line control decoder 302 also generates a source signal which is coupled to a combiner 308 and combined with a priority signal from a line control priority level register 312 to generate a priority and source select signal which is coupled on the priority bus 222 to the video priority resolver 208.

Referring now to FIG. 7, there is shown a detailed block diagram of a specific embodiment of the multiplier matrix circuit 202 which in the illustrated embodiment comprises primarily a three by three array 312 of 10.times.9 bit multipliers (a larger array, e.g., n by m, may be used), a video multiplexer 314, a constants multiplexer 316, a multiplier control circuit 318, a constant pre-scale multiplier 320, and an output multiplexer 322. An 8-bit alpha buffer constant is coupled via the bus 221 from the alpha buffer control 212 to two independent multiplexers, as is a source of white noise data signal. The alpha buffer constant may be changed on a pixel by pixel basis. A blend ration prescale factor is coupled from a BlendRatioScaleFactor register 323 to one of the multiplexers, and the line buffer blend constant is coupled to the other multiplexer via the bus 224. The selection of these two multiplexers is responsive to signals from the multiplier control 318 as well as a signal from the line buffer via the bus 224. The output of the two multiplexers are coupled to the pre-scale mu1tiplier 320 as shown. The pre-scale multiplier 320 may thus perform one of nine functions: it may scale the alpha buffer constant by a register value; it may scale the alpha buffer constant by a random noise value; it may scale the alpha buffer constant by the alpha buffer constant, yielding alpha*alpha; it may scale the line buffer constant by a register value; it may scale the line buffer constant by a random noise value; it may scale the line buffer constant by the alpha buffer constant; it may scale the noise source by the register value; it may scale the noise source by the same noise source, yielding Gaussian noise; and it may scale the noise source by the line buffer constant.

The result of the pre-scale multiplier 320 is coupled to the multiplier control 318 via the bus 325. Typically, the pre-scale register factor is changed on a frame-to-frame basis. The pre-scaled constant is then coupled from the multiplier control 318 to the multiplier constants multiplexer 316 via a bus 335. The multiplier constants multiplexer 316 then uses the pre-scaled constant to override the constants registers 338 as needed under control of control signals coupled on the bus 335 and from the video multiplexer on the bus 334.

Also coupled to the control circuit 318 from the alpha buffer control circuit 212 on the bus 221 are a set of control signals, as shown. Control signals are also coupled to the multiplier control circuit 318 from the absolute timing circuit 166 on the bus 182 and from the line control buffer 178 via the control bus 224. A set of multiplier control registers 324 is also coupled to the multiplexer control circuit 318, as shown, which control multiplier modes, sources and formats. The multiplexer control circuit 318 controls the video multiplexer 314 via a control bus 326 and also controls the multiplier array 312 via a control bus 328 and the output multiplexer 322 via a control bus 330, as shown. Thus, the multiplier controller 318 controls video source and constant selection for the multiplier 312, as well as the form of both the inputs and outputs of the multipliers 312 responsive to the control registers 324 which include MultiplierInputSource registers, Format registers and a ConstantSource register.

Also coupled to the video multiplexer 314 are six video source data buses 194, 196, 198, 200, 230, 232, along with a feedback source which is a feed back of the multiplier output via the bus 343. The video multiplexer under control of the multiplier controller 318 selects any combination of components of the video sources (within timing constraints) to provide up to three complete source signals to be applied to the multiplier array 312 and arranges the data to apply the data in the proper sequence to the multiplier array 312 via a set of data buses 332, as shown. Video multiplexer 314 also generates a white or random noise signal which is coupled via a data bus 334 to the constants multiplexer 316. The constants multiplexer 316 couples constant values (K1 through K9) to the multiplier array 312 via a set of data buses 336. The constant values (K1-K9) may be provided by a set of constant registers 338 (registers for two sets of constants K1-K9 are provided) which are loaded from the register interface controller 160, with the alpha buffer constant coupled from the multiplier controller 318, the line buffer constant coupled from the multiplier controller 318, or may derive the values to be applied to the multiplier array 312 from the white or random noise signal or video source buses 194 and 196, as shown. Thus, the constants may be from the video memory banks (VD2), a live external video source (LDIG), noise, constant registers, the line buffer, or the alpha buffer.

The multiplier matrix 312 of the video system controller 22 performs highly programmable real-time (pixel-rate) video processing. These multipliers may operate in a transformation mode, a blend mode, an 8-bit 2-D filter mode, a 16-bit 2-D filter mode, a transformation blend mode, a blend-transformation mode, and a 16-bit frame accumulator mode. Both filter modes may programmably use a 9 tap or an 18 tap filter mode, The 18 tap filter, blend-transformation, and transformation-blend modes perform two complete multiplication cycles in one pixel period. Each input and the output is specified as signed or unsigned depending on the application. Transformation and gain constants are signed 2's complement 10-bit values. The video signals R, G, B, and Y are unsigned and orthogonal chrominance components (C and c) are signed; all are 8 bit values.

The multiplier array 312 couples the multiplication results to a set of three summing circuits 340 via a set of data buses 342. The control signals coupled from the multiplier controller 318 via the bus 328 control the format (i.e., signed or unsigned) and the bit resolution of the multiplication (i.e., one to nine bits, with greater speed available with lower resolution). The multipliers 312 in the illustrated embodiment multiply the input video source pixel component values of up to three sources by up to nine input constant values, and adds the results of each horizontal row of multipliers in a set of summing circuits 340. Each of the summing circuits 340 sums the result of the three associated multiplier outputs (i.e., sums each horizontal row of three multipliers) and couples that result to the output multiplexer 322 via a set of data buses 344, as shown. An additional summing circuit 346 adds the sums of the summing circuits 340 to provide a matrix total, the sixteen most significant bits of which form a partial sum which is coupled to the partial sum output (PSO) bus 236, as shown. The partial sum output is used to provide the filter mode capability of the Multiplier circuit 202. In addition, the feedback output is provided by combining eight bits of each summed output 340 to provide a 24-bit multiplier feedback video source which is used to perform two multiplication cycles in one pixel period. The output multiplexer 322 under the control of the multiplier controller 318 couples the summed multiplier output onto the multiplier output video bus 234 in the proper format.

In the transformation mode, the multiplier array performs three by three matrix transforms on one video vector to produce another. The multiplier input source registers should all be set to the same video source for transformation modes. Several examples of this are converting a stored YCc (e.g. YIQ or YUV) image to RGB for output display, converting RGB input to YCc for storage (color or B/W) or luma/chroma keying, or color axis rotation of the RGB or YCc vector to RGB' or YCc'.

The multiplier array 202 can blend or mix three images by setting the gain factors appropriately. Each image component is multiplied by a gain factor component (constant) and the three resulting components are added together to produce the new mixed image component. This is done for all three color axes. The gain factors are specified as 3-component K vectors (i.e., K.sub.1, K.sub.4, K.sub.7 ; K.sub.2, K.sub.5, K.sub.8 ; K.sub.3, K.sub.6, K.sub.9) and typically the three multiplier input sources will be set to the same value. The equations for programmable blending are indicated below with K.sub.1 through K.sub.9 representing the nine blend constants within matrix multiplier array.

    ______________________________________
    Red Output    =          K.sub.1 *Red Input 1
                           + K.sub.2 *Red Input 2
                           + K.sub.3 *Red Input 3
    Green Output  =          K.sub.4 *Green Input 1
                           + K.sub.5 *Green Input 2
                           + K.sub.6 *Green Input 3
    Blue Output   =          K.sub.7 *Blue Input 1
                           + K.sub.8 *Blue Input 2
                           + K.sub.9 *Blue Input 3
    ______________________________________