Audio/visual home computer and game apparatus4475172Abstract A home computer system provides a video processor for use with a television receiver. The video processor can selectively perform a variety of modifications to pixel data under the direction of the CPU of the computer system before the pixel data is stored in a random access memory to effectively increase the speed or data handling power of the system. Claims What is claimed is: Description The present invention relates to computers and more particularly to home computers and game apparatus adapted for use with cathode ray tube display apparatus, such as television receivers or monitors.
TABLE 1
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##STR1##
MC1 MC0 Microcycle Data Bus Contents
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0 0 0 A0-A7 from the CPU
0 0 1 A0-A7 from the CPU
0 1 0 A0-A7 from the CPU
0 1 1 A0-A7 from the CPU
1 0 0 A0-A7 from the CPU
1 0 1 A8-A15 from the CPU
1 1 0 D0-D7 from the CPU
1 1 1 D0-D7 to the CPU
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As can be seen above, when the RFSH signal is a logical zero or low state, the microcycler will allow the address bits A0-A7 from the CPU to be conducted through regardless of the state of MC0 or MC1 in order to refresh the RAM. However, when RFSH is a logical 1 (inactive), MC0 and MC1 detemine the contents of the microcycle data bus MXD0-MXD7. The microcycler as well as the interconnection of the various integrated circuit chips of the low resolution mode system are shown in greater detail in FIGS. 10A-C. The microcycler 60 comprises two 8-line to 4-line multiplexers 70 and 72, having four output lines MXD4-MXD7 and MXD0-MXD3, respectively, and each having 4A and 4B input lines, an enable input E and a select input S. The address lines A0-A3 and A8-A11, from a CPU address bus 73 from the CPU 56 are connected to the A and B input lines of the address multiplexer 72, respectively. Similarly, the address bus lines A4-A7 and A12-A15 are connected to the 8 input lines of the address multiplexer 70. The address multiplexers 70 and 72 can selectively conduct either the "low address" bits A0-A7, or the "high address" bits A8-A15, to the microcycle data bus MXD0-MXD7 when enabled. The multiplexers have common industry designation number 74LS257. The microcycler further comprises an 8 line bidirectional data gate 74 having 8 input/output lines connected to a CPU data bus 75 from the CPU 56, 8 input/output lines connected to the microcycle data bus MXD0-MXD7, a direction input DIR and an enable input CD. The data gate 74 can conduct data either from the CPU data bus 75 to the microcycle data bus 66 or from the microcycle data bus 66 to the CPU data bus 75 as determined by the state of the DIR input when enabled. These three logic elements 70, 72, and 74, function as a 24-line to 8-line multiplexer to sequentially conduct groups of address signals and groups of data signals to the microcycle data bus, in response to the control signals MC0 and MC1 and the CPU control signal RFSH. Alternatively, the gate 74, of the microcycler further functions as a gate for conducting data signals from the microcycle data bus to the CPU data bus. The microcycle data bus 66 is connected to the MXD0-MXD7 inputs of the address chip 56, data chip 54 and I/O chip 50. The microcycler 60 had input lines 76, 78, and 80 for the control signals RFSH MC1 and MC0 respectively. The input line 76 operably connects the CPU 56 RFSH output to the inputs of a pair of NAND gates 81 and 82. The output of the NAND gate 81 is inverted by an inverter 84 whose output is connected by a line 85 to the enable `E` of the multiplexers 70 and 72 and is also connected to the input of a NAND gate 86 whose output is connected to the enable input CD of the gate 74. Thus, when the CPU 56 prepares to refresh the RAM, the refresh control signal, RFSH, will go to the low state causing the output of the NAND gate 81 to go high which is inverted by the inverter 84. A low state at the enable input E of the multiplexers 70 and 72 causes these logic elements to be enabled whereby address signals can be conducted to the microcycle data bus 66. A low state on the line 85 also causes the output of the NAND gate 86 to go high which is presented to the enable input CD of the gate logic element 74 causing the gate 74 to be disabled whereby the outputs of the logic gate 74 are forced to an off state. The output of the NAND gate 82 is connected to an inverter 88 having an output line 90 connected to the select inputs S of the multiplexers 70 and 72. Thus, when the refresh multiplexer control signal RFSH is low, the output of the NAND gate 82 is high. Consequently, the output of the inverter 88 is low. A low state presented at the selector input S causes address bits presented at the A inputs to be conducted to the multiplexer data bus. Thus when RFSH is low, the low address A0-A7, is conducted to the microcycle data bus for use in the refresh cycle. The input lines 78 and 80 connect data chip 54 MC1 and MC0 outputs to the inputs of NAND gates 81 and 82, respectively. When the control signal RFSH is high, i.e., a refresh is not being done, the outputs of the NAND gates 81 and 82 are determined by the microcycler control signals MC1 amd MC0 respectively, from the data chip 54. Thus, when the control signal MC1 is in a low state, the output line 85 is also in a low state which enables the multiplexer logic elements 70 and 72 and disables the gate logic element 74 as when the RFSH signal is low. Thus, either the low address or the high address will be conducted onto the microcycler data bus as determined by the control signal MC0. When the control signal `MC0` is in a low state, the output line 90 is also low which causes the low address to be conducted onto the microcycler data bus. If MC0 is at a high state, the high address is conducted to the microcycler data bus. Control signal MC1 (and RFSH ) at a high state results in a high state at control line 85 which disables the mutliplexers 70 and 72 and enables the gate 74. Thus, the data on the data bus 75 for bits D0-D7 from the CPU 56 will be gated onto the microcycler data bus MXD0-MXD7, or the data on the microcycler data bus will be gated onto the data bus of the CPU, depending upon the direction input DIR. The direction input DIR is connected by a line 92 to the output of the NAND gate 82. Thus, the state of the control signal MC0 (with RFSH high) determines the direction that the gate 74 will gate the data. For example, if MC0 is in a low state, the output of the NAND gate 82 will be high resulting in the contents of the data bus D0-D7 being gated onto the microcycler data bus; if MC0 is high, the contents of the microcycler data bus will be gated onto the data bus D0-D7 to the CPU 56. A power supply indicated generally at 93 supplies +15v, +10v, +5 V and -5v to the system. A clock circuit 94 comprising a 14.31818 MHz oscillator 96 and divider stages 98, provides a 7 MHz clock signal 7M, and an inverted 7 MHz clock signal 7M, to the 7M and 7M inputs, respectively, of the data chip 54. A clock signal .PHI. G, generated by the data chip 54 from the 7M and 7M clock signals, is outputted to a buffer 100 having output lines for clock signals .PHI. and .PHI.. The clock signals .PHI.1 and .PHI.2 are connected to the .PHI. and .PHI. inputs of the address, data and I/O chips. The CPU address bus 73 and data bus 75 are connected to the system ROM 48 having inputs A0-A12 and D0-D7 for the address and data bits, respectively. The address bus 73 and data bus 75 are also connected to the cassette ROM 24 (not shown) and the extension plug 77 (for expanding the system). The system ROM chip 48 has a chip select input CS connected to the output of the chip select logic indicated at 79a and b with the cassette ROM chip select input CCS also connected to the output of the chip select logic 79a and b. The outputs of the logic 79a and b are functions of the CPU control signals MEMORY REQUEST (MREQ) and READ (RD), the address bits A13-A15 and the memory disable signals SYSEN, CASEN, AND BUZOFF from the extender plug 77. DATA CHIP The CPU control signal lines MEMORY REQUEST, INPUT/OUTPUT REQUEST, READ, and MACHINE CYCLE 1 are operatively connected to the data chip inputs MREQ, IORQ, RD, and M1, respectively, from the CPU 56. Two more control lines carrying control signals generated by the address chip 56 are connected to the data chip inputs LTCHDO, and WRCTL, respectively. The data chip had VDD input connected to a +5 volts source, a VGG input connected to a +10 volt source, and a DVSS input connected to ground. Two more inputs SERIAL 0 and SERIAL 1 are grounded since they are used in the high resolution mode. The data chip 54 has a plurality of outputs including the memory data inputs and outputs MD0-MD7, connected by a memory data bus 102 to the display RAM 42. The data chip input/output MD0 is operatively connected to the data input, D1, and data output D0, ports of the RAM chip 104a, with other memory data input/outputs, MD1-MD7 of the data chip similarly connected to seven RAM chips 104b-h. The data chip also has analog video outputs R-Y, B-Y, VIDEO and +2.5 volts reference operatively connected to the RF modulator 58 (not shown). The data chip has clock signal outputs, VERTICAL DRIVE (VERT. DR.) and HORIZONTAL DRIVE (HORZ. DR.), connected to the address chip 56. Finally, the data chip has control signal outputs MC0 and MC1 connected to the microcycler (as noted before) and an output DATEN used to generate the write enable signal, WE, for the RAM chips. A schematic block diagram of the data chip 54 is shown in FIGS. 11A-11F. The microcycle generator 106 of FIG. 11A generates the microcycle control signals MC0 and MC1 from the CPU control signals IORQ, MREQ, RD, and M1. Also generated are microcycle decoder control signals LOAD LOW (LDL1) and LOAD HIGH (LDH1) for loading the low and high address bits respectively. A more detailed schematic diagram of the data chip is shown in FIGS. 13A-EE with a composite diagram of these figures shown in FIG. 14. The microcycle generator has an input line 108 for the MREQ control signal and an input line 110 for the IORQ control signal, both of which are connected to the inputs of a NAND gate 112 whose output is connected by an inverter 114 to the inputs of a pair of NOR gates 116 and 118. The microcycle generator has an input line 120 for the CPU control signal RD which is connected to the other input of the NOR gate 116. The output of the NOR gate 116 is connected by an inverter 122 to the input of an AND gate 124. The output of the NOR gate 118 is connected to the input of a NOR gate 126 whose output is connected to the input of a NOR gate 128 with the output of the AND gate 124 connected to the other input of the NOR gate 128. The output of the NOR gate 128 is connected by a gating transistor 130 which acts as a delay to the input of a NOR gate 132. The gate of the transistor 130 is connected to the clock signal line .PHI.2. .PHI.2 is the complement of the clock signal .PHI. and a clock signal .PHI.1 is .PHI. uncomplemented. The output of the NOR gate 132 is connected by a gating transistor 134 (which also acts as a delay) to an inverter 136 having an output line 138. The gate of the "delay" transistor 134 is connected to the clock signal .PHI.1. The output line 138 is connected to the inputs of the AND gate 124 and the NOR gate 126 and is also connected by a delay transistor 140 to the input of a NOR gate 142. The gate of the transistor 140 is connected to the clock signal 7M. The output of the NOR gate 142 is connected by a delay transistor 144 to an inverter 147 having an output line 148. The gate of the transistor 144 is connected to the 7M clock signal. The output line 148 of the inverter 146 is connected to an input of a NOR gate 150 whose output is connected to an inverter 152. A transistor 154 is connected to the voltage source VDD and to ground by a transistor 156. The gate of the transistor 154 is connected to the output of the inverter 152 and the gate of the transistor 156 is connected to the output of the NOR gate 150. The junction of the transistors 154 and 156 at the line 80 carries the microcycle control signal MCO. The E,ovs/MREQ/ and IORQ input lines, 108 and 110, are connected to the input AND gate 160 whose output is connected to a NOR gate 162. The output line 138 of the inverter 136 is also connected to the input of a NOR gate 164 whose output is connected to the input of the NOR gate 162. The output of the NOR gate 162 is connected by a delay transistor 166 to a NOR gate 168. The gate of the transistor 166 is connected to the .PHI.2 clock signal. The output of the NOR gate 168 is connected by a delay transistor 170 to an inverter 172 having an output line 174. The gate of the transistor 170 is connected to the .PHI.1 clock signal. The output line 174 is connected to an input of the AND gate 160 and inputs of the NOR gates 118 and 164 and is also connected by a delay transistor 176 to a NOR gate 178. The gate of the transistor 176 is connected to the 7M clock signal. The output of the NOR gate 178 is connected by a delay transistor 180 to an inverter 182 having an output line 188. The gate of the transistor 180 is connected to the clock signal 7M. The output line 188 of the inverter 182 is connected to a NOR gate 190 whose output is connected to an inverter 192. A gating transistor 194 is connected to the voltage source VDD and to a transistor 196 which is connected to ground. The output of the inverter 192 is connected to the gate of the transistor 194 and the output of the NOR gate 190 is connected to the gate of the transistor 196. The junction of the transistors 194 and 196 at the line 78 carries the microcycle control signal MC1. The state of the control signal MCl is the same as the output of inverter 192 since a high state (logical 1) output of the inverter 192 will turn on the transistor 194 causing the MC1 line 78 to also go high. Similary, a high output from the NOR gate 190 (when inverter 192 is at a low state) causes the transistor 196 to turn on which causes the MC1 control signal line 78 to also go low. The state of the MCO control line 80 is similarly the same as the state of the inverter 152. The microcycle generator has another input 200 for the CPU control signal M1 which is connected to the input of a NOR gate 202 having another input connected to the input line 110 for the CPU control signal IORQ. The output of the NOR gate 202 is connected to the inputs of the NOR gates 168, 132, 178, 142, 190 and 150. The M1 CPU control signal is active when low (logical 0) and indicates that the current machine cycle is an operaton code fetch cycle of an instruction execution. Thus, the M1 control signal is normally high (logical 1) whenever the CPU is accessing a peripheral device such as a video processor. Hence, the NOR gate 202 having a logical 1 presented at the input will output a logical O. This logical O is presented at the inputs of the NOR gates 132, 168, 142, 178, 150 and 190 resulting in these NOR gates operating as inverters whenever the /M1 control signal is high. Similarly, whenever M1 goes low indicating that the current machine cycle is the fetch cycle of an instruction execution, IORQ will normally be high with the same effect upon the above-mentioned NOR gates with an exception. IORQ and M1 will both go low during an "interrupt ackowledge" cycle. With these two control signals both at a low state, the NOR gate 202 will output a high state causing the NOR gate 150 to produce a low state forcing the control signal MC0 to a high state or 1. In a similar fashion, the output of the NOR gate 190 is forced to a low state which also forces the control signal MC1 to a high state. Referring back to the microcycle modes set out in Table I, it is seen that where MC0 and MC1 are both a logical 1, the microcycler will gate data from the microcycler data bus to the CPU data bus. This data was placed on the microcycler data bus by the peripheral device initiating the interrupt and will be used by the CPU in its response to the interrupt signal. The "MEMORY REQUEST" control signal, MREQ, is active when low and indicates that the address bus of the CPU holds a valid address for a memory read or a memory write operation. The "INPUT/OUTPUT REQUEST" control signal IORQ, is also active when low and indicates that the lower half of the address bus holds a valid I/O address for I/O read or write operation. The read control signal, RD, is active when low and indicates that the CPU wishes to read data from the memory or an I/O device. When high, RD indicates the CPU wishes to write data to memory or an I/O device. The generation of the microcycler control signals MC0 and MC1 as a function of the CPU control signals MREQ, IORQ, and RD together with clock signals .PHI.1 and 7M, are illustrated for a plurality of read and write operations in FIGS. 12A-G. An example of MC0 and MC1 as functions of MREQ RD, and the clock signals .PHI.1 and 7M, is shown for a memory write operation in FIG. 12A. A clock state, T, is defined by one complete period of the clock signal .PHI.. At the beginning of the initial clock state T1, the CPU control signals MREQ RD are at the same state as the previous clock state which is a high state with the microcycler control signals MC0 and MC1 also at the same state as the previous clock state which is a low state. During T1, after the clock signal .0. goes low, MREQ goes low which indicates that the CPU address bus holds a valid address for the memory write operation. Referring to FIG. 13, the NAND gate 112 has the control signals MREQ and IORQ presented at its inputs which are both inactive or a logical 1 at the beginning of T1. When MREQ goes low, the output of the NAND gate 112 goes high which is inverted by the inverter 114 presenting a low state to one input of the NOR gate 118 and to one input of the NOR gate 116. the other input of the NOR gate 118 is connected by the line 174 to the output of the inverter 172. Since M1 is at a high state, the NOR gates 142, 178, 150 and 190 function as inverters. Thus the output of the inverter 172 at line 174 is at the same state as the previous MC1 state since there are an even number of "inverters" between the line 174 and the gate of the output transistor 194 (except insofar as the 7M and 7M delay transistors 176 and 180 delay any change in MC1 resulting from a change in the output of the inverter 172 of line 174). Thus since MC1 is at a low state, the line 174 connected to the input of the NOR gate 118 is at a low state with the other input of the NOR gate 118 at a low state, as noted before. This produces a high state at the output of NOR gate 118 which results in a low state at the output of the NOR gate 126. The control signal RD is at a high state indicating a write operation which causes the NOR gate 116 to output a low state which is inverted by the inverter 122 to produce a high state. The line 138 is at the same state (except for a delay) as the previous MCO state (in a manner similar to that for the line 174) which causes the output of the AND gate 124 to be low. The NOR gate 128 thus has a low state presented at both of its inputs which results in a high state produced at its output. This output is connected when the clock signal .PHI. 2 goes high and is inverted by the NOR gate 132. The transistor 134 conducts this output when the clock signal .0.1 goes high resulting in the output of the inverter 136 going high. thus the output of the inverter 136 assumes the same state as the NOR gate 128 on the positive edge 200 (i.e., going from a low state to a high state) of the clock signal .PHI. (FIG. 12A). The high state at the output of the inverter 136 is conducted by the transistor 140 when the clock signal M goes high which is inverted by the NOR gate 142 and conducted by the transistor 144 when the clock signal 7M goes high. The logical 0 is then inverted by the inverter 146, NOR gate 150, and inverter 152 to produce a high state at the output of the inverter 152 which turns on the transistor 154 to produce the high state at the line 86 which is the MCO control signal line. Referring back to FIG. 12A, it is seen that the control signal MCO goes to a high state on the positive edge 202 of the clock signal 7M which follows the positive edge 200 of the clock signal .PHI. occurring after the CPU control Signal MREQ goes low. When MC0 changes from a low state to a high state, the contents of the microcycle data bus changes from the low address, A0-A7, to the high address, A8-A15. Thus the 16 address bits from the CPU are transmitted to the video processor and I/O chip in 2 eight-bit groups or slices. The output of the inverter 136 rising to a high state causes the NOR gate 164 having an input connected to the output line 138 of the inverter 136 to fall to a low state. the output of the AND gate 160 is also low since MREQ is low causing the output of the NOR gate 162 to go high. This high output appears at the output of the inverter 172 at the line 174 on the positive edge 204 (FIG. 12A) of the clock signal .PHI. marking the start of the clock state Tw. The high state then appears at the gate of the transistor 194 on the positive edge 206 of the clock signal 7M (FIG. 12A) causing the control signal MC1 to rise to a logical 1. The RD signal is at a high state (indicating a write operation) which causes the NOR gate 116 to output a "zero" which is inverted by the inverter 122. The output of the inverter 136, which is at a high state, is returned to the AND gate 124 causing the AND gate to output a "one" which causes the NOR gate 128 to output a "zero". This low state appears at the output of the inverter 136 on the positive edge 204 of the clock signal .PHI. (FIG. 12A). The low state then appears at the MC0 control signal line 80 on the positive edge 206 of the 7M clock signal (FIG. 12A). With MC0 at a low state and MC1 at a high state, the contents of the CPU data bus are gated onto the microcycle data bus. Thus data placed on the CPU data bus is transmitted to the peripheral devices on the microcycle data bus. During clock state T3, MREQ returns to a high state. Since MREQ as well as the output of the inverter 172 at line 174 and IORQ are at a high state, the output of the AND gate 160 is high which causes the output of the NOR gate 162 to go low. This low output appears at the line 172 on the positive edge 208 of the .PHI.1 clock signal at clock state T1. The low state at line 172 appears at the gate of the output transistor 194 (with a high state at the gate of the transistor 196) at the positive edge 210 of the clock signal 7M causing the microcycle control signal MC1 to go low. The microcycler is now ready to transmit the low address of the next address presented at its inputs. The relationship of the microcycler control signals MC0 and MC1 to the CPU control signals and system clock signals .PHI. and 7M is shown for a variety of other read and write operations in FIGS. 12B-G. The microcycler further comprises a NOR gate 201 having inputs connected to outputs of the inverters 146 and 182 and to the clock signals .PHI.1. A NOR gate 203 also has inputs connected to the output of the inverter 182, to the output of the inverter 146 by an inverter 205, and to the clock signal input .PHI.. An output line 226 of the NOR gate 201 carries the microcycle decoder control signal LDL1 which is a logical 1 when the outputs of the inverters 146 and 182 are a logical 0 (corresponding to both MC0 and MC1 a logical 0), together with .PHI.1 a logical 0. An output line 228 of the NOR gate 203 carries the signal LDL1 which is a logical 1 when MC0 is a logical 1, MC1 a logical 0 and .PHI.1 a logical 0. Each of the address, data, and I/O chips has a plurality of registers. Each of these registers is individually addressable by the CPU for inputting or outputting data contained in the register. The data chip is shown in FIG. 11B to have microcycle decoder 212 which assembles 11 address bits A0-A10 from the low address bits, A0-A7, and high address bits, A8-A15, transmitted from the microcycle data bus. The microcycle decoder 212 has an eight bit input line connected to all the bits of an eight-bit data chip data bus 66a and a three-bit input line connected to the lower 3 bits of the data bus 66a. The microcycle data bus 66 is connected to the data bus 66a by a tristate buffer 273 (FIG. 11C). (Other buffers shown in the more detailed schematic FIG. 13 are omitted from the FIGS. 11A-F for clarity). The microcycle generator 106 (FIG. 1A) generates control signals LDL1 and LDH1 to signal that the microcycle data bus contains the low address bits or the high address bits, respectively. The microcycle decoder 212 is operatively connected to the microcycle generator to input these control signals such that the decoder latches up the low address bits from the eight bit input lines when LDL1 is high and subsequently the high ddress bits A8-A10 on the three bit input line when the control signal LDH1 is a high. The 11 bits latched in the microcycle decoder are utilized to address the registers on the data chip. The microcycle decoder has an 11 bit output bus A0-A10 which is connected to an address decoder 214 which decodes the address bits to activate one of a plurality of register select lines 216-222. Register select line 216 actually represents eight register select lines for eight different "color" registers 224. In addition to the proper address, the register select lines 216-221 require the concurrence of a data chip generated control signal, OUTPUT, in order to be activated. The eight color register select lines 216 further require a CPU generated control signal IORQ. The register select line 222 requires the concurrence of another data chip generated control signal INOUT, to be activated. The INPUT and OUTPUT signals are functions of z-80 CPU control signals including MREQ, IORQ, RD and M1 and are generated to compensate for any delay caused by the microcycler. The register select lines 216-221 are operatively connected to eight color registers 0-7, an "expand" register, "function generator" register, "vertical blank" register, "horizontal color boundary" and "background color" register and "low/high resolution mode" register, respectively. The line 222 is operatively connected to a multiplexer, which when activated causes the multiplexer to select the output of an "intercept" register. In this manner, the CPU may select any particular register of the data chip by transmitting an address corresponding to the register which is transmitted in two groups, the low and high addresses, by the microcycler to the microcycle decoder which reassembles the address bits into address bits A0-A10. These bits are then decoded and the corresponding register select line is activated which enables the addressed register to input or output data to the CPU via the microcycle data bus. The microcycle decoder 212 and address decoder 214 are shown in greater detail in FIG. 13. The microcycle decoder 212 comprises an 11-bit latch with the eight least significant bits A0-A7 each having an input connected to the D0-D7 lines, respectively, of the data bus 66a. Each of the A0-A7 bits of the latch also have an input connected to the LDL1 control signal line 226 and an input connected the line 226 through an inverter 227. The most significant bits A8-A10 each have an input connected to the D0-D2 lines, respectively, of the dat bus 66a and each has an input connected to the LDH1 control signal input line 228 directly, and an input connected to the line 228 through an iverter 229. The A0 bit has output lines A0 and its complement A0 with the A1 bit having outputs A1, A1, etc. all connected to the address decoder 214. An example of a bit circuit of the latch of the microcycle decoder is shown in FIG. 13. The input of the A0 bit circuit of the latch is connected to a gating transistor 230 whose gate is connected to the LDL1 control signal line 226. The 1 input is also connected to the D0 line of the data bus 66a which carries (among others) address bits A0 and A8. Transistor 230 is connected to an inverter 232 whose output is the A0 output line of the A0 latch which is also connected to an inverter 234 whose output is the A0 output line. The output of the inverter 234 is connected to a gating transistor 236 whose gate is connected to the output of inverter 227 (FIG. 13) which carries LDL1. The output of the transistor 236 is connected to the input of inverter 232. The bit of the D0 line of the data bus 66a is presented to the input of the transistor 230 which is gated by the LDL1 control signal when the D0 line carries the address bit A0. The inverter 232 inverts the address bit A0 and outputs the bit as address bit A0. The output of the ivnerter 232 is inverted by inverter 234 whose output is the address bit A0. The bit A0 is stored in the A0 bit of the latch in this manner. The address decoder is shown in FIG. 13) to comprise a programmed logic array (PLA) having a plurality of input lines A0-A10 and A0-A10 connected to the corresponding output lines of the microcycle decoder 212. A plurality of output lines 217-222 and 238-253 are selectively coupled to the PLA input lines by a plurality of pull-down transistors, each of which is represented by a small circle 254. An example of these pull-down transistors, the transistor coupling the input line A10 to the output line 238 is shown in greater detail in FIG. 16. If the address bit A10 equals 1, i,e., a high state, the A10 address line will cause the pull-down transistor 254 to turn on which "pulls down" the output line 238 to ground. Each output line 217-1222 and 238-253 is connected to the voltage source VDD by a pull-up transistor 260 referring back to FIG. 13. A logical 1 on any address bit input line coupled to an output line will cause that output line to be grounded which is a low state or logical 0. The input lines of the PLA are selectively coupled to the output lines by the pull-down transistors 254 such that a particular output line will produce a logical 1 only when a predetermined address consisting of a predetermined combination of 1's and 0's are presented on the address input lines A0-A10 and AO-A10. The output lines 217-221 are coupled to the OUTPUT control signal line 262 by pull-down transistors 264 so that in addition to the proper address, the OUTPUT control signal must be low in order for one of these control lines to output a logical 1. For example, if the address bits A7, A6, A5, A4, A3, A2, A1 and A0 (A7 being the most significant) have the values 0, 0, 0, 1, 1, 0, 0 and 1, respectively, the control line 217 will be a logical 1, if the OUTPUT control signal is also low. Since the PLA output line 217 is the "expand" register select line, the expand register will be selected if the address bits A7-A0 have the value 00011001 or 19H. Thus 19H is the hexadecimal address of the expand register. If any of the address bits A7-A0 are different from the values just listed, the expand register will not be selected. For example, if the address bit A7 is a 1 instead of a 0, the pull-down transistor 254 associated with the A7 input line and the PLA output line 217 will be turned on which pulls the output line 217 to a logical 0. The output line 222 has an associated address 8H and, as seen in FIG. 11B, is the "intercept" register select line. the intercept register select line 222 is coupled to an INPUT control signal line 266 by a pull-down transistor 268 so that in addition to the address 8H, the INPUT control signal must be low in order for the register select line 222 to be at a logical 1 state which will select the intercept register. The output lines 238 and 239 are connected to the input of a NOR gate 270 whose output is connected to a NOR gate 272. The other inputs of the NOR gate 272 are the control signal line 262 and a IORQ control signal line 270. Thus, either of two hexadecimal addresses, BH or OH, will cause the output of the NOR gate 270 to go low which will cause the output of the inverter 272 to go high if the control signal OUTPUT and the control signal IORQ are both low. The output lines 240 and 241, 242 and 243, etc. are also connected to a plurality of NOR gates 271 which are connected to a plurality of NOR gates 272 which also have inputs connected to the OUTPUT control signal lines 262 and IORQ control signal line 270. The output lines 216 of the NOR gates 272 are the register select lines for the color registers 224, as seen in FIG. 11B. Thus, either the hexadecimal address 8H or BH will select color register 0. There is an extra address for each color register to accomodate a color block transfer operation which will be described in more detail later. Thus, the CPU may address or select a particular register in order to input or output data from or to that register by transmitting the register's associated address together with the proper CPU control signals. The microcycler transmits this address in two groups, the low and high addresses, which are then reassembled by the microcycler decoder 212. The address latched in the microcycler decoder is decoded by the address decoder 214 which activates a register select line. The register select line enables the associated register to input from or output data to the microcycle data bus. The hexadecimal addresses for the input and output ports or registers for the Address, Data and I/O chips are set forth in Table II below:
TABLE II
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OUTPUT INPUT
PORTS PORTS
PORT PORT
ADDRESS
FUNCTION ADDRESS
FUNCTION
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.0.H Color Register .0.
8H Intercept Feedback
1H Color Register 1 Multiplexer
2H Color Register 2 EH Vertical Feedback
3H Color Register 3 Register
4H Color Register 4 FH Horizontal Feedback
5H Color Register 5 Register
6H Color Register 6 1.0.H Player 1 Handle
7H Color Register 7 11H Player 2 Handle
8H Low/High Resolution
12H Player 3 Handle
Register 13H Player 4 Handle
9H Horizontal Color 14H Keypad Column .0.
Boundary Register (right)
Background Color 15H Keypad Column 1
Register 16H Keypad Column 2
AH Vertical Blank 17H Keypad Column 3
Register (left)
BH Color Block Transfer
CH Function Generator
Register
DH Interrupt Feedback
Register
EH Interrupt Enable and
Mode Register
FH Interrupt Line Register
1.0.H Master Oscillator Register
11H Tone A Frequency Register
12H Tone B Frequency Register
13H Tone C Frequency Register
14H Vibrato Register
15H Tone C Volume, Noise Modulation
and MUX registers
16H Tone A Volume and Tone B
Volume Registers
17H Noise Volume Register
18H Sound Block Transfer
19H Expand Register
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The function generator of the video processor can perform a variety of functions or modifications to the pixel data as the data is a written to the display RAM by the CPU from the system or cassette ROM. The function generator is enabled when the address of the data is less then 4,000H (address bit A14 equal to 0). The function generator is contained on the data chip 54 and is shown in FIG. 11C to comprise a 7-bit function generator register 274 which is connected to the data bus 66a by a 7-bit input line 276. The data chip data bus 66a is operatively connected to the microcycler data bus 66 by the tri-state buffer 273 shown in FIG. 13 to comprise 8 units 273a-h. (Buffer unit 273a, typical of the units 273a-h, is shown in greater detail in FIG. 17). The output 1 of each unit is connected to the data bus 66a by a buffer 611 (logically similar to that shown in FIG. 18). The data contents of the register 274 determine how the pixel data is to be modified. The CPU 46 (FIG. 2) may output data to the register 274 by transmitting the address CH to the microcycle decoder 212 and address decoder 214 of FIG. 11B which activates the function generator register select line 218. When the register select line 218 is activated, the function generator register 274 is enabled to input (or latch up) the 7 bits of data transmitted by the CPU. The bits of the data contained within the function generator register 274 relate to different modifications of the pixel data as shown below in Table III:
TABLE III
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Bit 0 Least Significant Bit of Shift Amount
1 Most Significant Bit of Shift Amount
2 Rotate
3 Expand
4 OR
5 Exclusive-OR
6 Flop
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The order in which the functions are performed is as follows: expansion is done first; rotating or shifting; flopping; and logical-OR or exclusive-OR. The video processor performs the modifications in response to the data stored in the function generator register. A logical 0 or 1 in the bits 2-6 determine whether or not the corresponding function is performed. Bits 0 and 1 of the function generator register determine the amount, if any, of the shift. As many as four of thes functions can be used at any one time and any function can be omitted. However, rotate and shift as well as logical-OR and exclusive-OR cannot be done at the same time. The expand function expands the 8 bits contained on the microccyle data bus 66 four bits at a time into 16 bits. It expands a 0 on the microcycle data bus into one 2-bit pixel and a 1 into another 2-bit pixel. Thus, two-color patterns can be stored in the system or cassette ROM in half the memory space. The expand function is performed by an expander indicated generally at 278. During each write operation to the display memory using the expander 278, either the upper half (D4-D7) or the lower half (D0-D3) of the data bus 66a is expanded but the expand function may be bypassed, as will be more fully explained below. The half that is expanded is determined by an expand flip-flop 282 having a reset input connected to the function generator register select line 218 and an output connected to a multiplexer 282. The flip-flop 280 is reset by an output to the function generator register 274 and is toggled after each write operation to the display RAM in which the function generator is utilized. The multiplexer 282 is responsive to the flip-flop to select either the upper half, or lower half, of the bits contained on the data bus 66a and output the selected bits on a 4-bit multiplexer data bus 284 for expansion. The upper half of the data bus 66a is expanded when the flip-flop 280 is at a low or zero state, and the lower half is expanded when the flip-flop toggles to the high state. A 4-bit "expand" register 286 having a 4-bit output line 288 determines the pixel values into which the data contained on the multiplexer data bus 284 can be expanded. A 0 on thwe multiplexer data bus will be expanded by an expand decoder 290 connected to the expand register output bus 288 and multiplexer output bus 284 into the pixel value determined by bits 0 and 1 of the expand register 286. A 1 on the multiplexer data bus will be expanded into the pixel value determined by bits 2 and 3 of the expand register 286. Thus, the pixel data on the multiplexer data bus is encoded at the first level to identify either the 0 and 1 or 2 and 3 bits of the expand register. In this manner, the data from the computer is decoded into pixel data encoded at the second level, i.e., the pixel data stored in the expand register, which is transmitted when the particular bits of the expand register are selected or identified. The second level pixel data is stored in the display RAM after other modifications, if any, are performed. The pixel data stored in the RAM, when read, is utilized together with the left/right bit to select a color register to generate the pixels of the display as explained hereinbefore. The expand register 286 has an address 19H at which the CPU may access the expand register in order to change the contents. The address 19H (together with an OUTPUT signal) transmitted to the address decoder 214 (FIG. 11B) causes the expand register select line 217 to be activated which enables the expand register 286 to receive data on the data bus 66a. In this manner, the pixel data values into which data is expanded may be changed. The expander 278 is shown in greater detail in FIG. 13. The expand flip-flop 280 has a reset input R connected to the function generator register select line 218 so that the flip-flop is reset with each output of data to the function generator register 274. The flip-flop has a clock input C connected to a clock input line 292 and a clock input C also connected to the clock signal input line 292 through an inverter 294. (The line 292 carries a clock signal, SHIFT which will be more fully explained hereinafter.) An output Q is connected to a D input of the flip-flop 280 so that the flip-flop toggles with each clock signal which occurs with each write to the display RAM. The output Q is also connected by a line 296 to the gates of four transistor switches 298a-d of the multiplexer 282. An output Q of the flip-flop is connected by a line 300 to the gates of four transistor switches 302a-d. (The flip-flop 280 is shown in greater detail in FIG. 19). The inputs of the transistor switches 298a-d are connected to the four most significant bits (the upper half) of the data bus 66a with the transistor switches 302a-d connected to the four least significant bits (the lower half) of the data bus 66a. If the state of the expand flip-flop 280 is a logical 1, the transistor switches 302a-d will conduct the lower half of the data bus 66a to the expander. Otherwise, a logical 0 will cause the transistor switches 298a-298d of the multiplexer 282 to conduct the upper half of the data bus 66a. The output of the transistor switches 302d and 298d are connected by an inverter 304 to the gates of a pair of transistor switches 306a and 306b of the expander decoder indicated generally at 290. The output of the inverter 304 is also connected by an inverter 308 to the gates of a pair of transistor switches 310a and 310b. A line 312a is connected to ground by a transistor 314 whose gate is connected to the output of bit 0 of the expand register 286. (The logic design of each bit of the expand register is similar to that of the bit of the latch of the microcycle decoder 212 shown in FIG. 15). The line 312a is connected to the voltage source VDD by the transistor 306a and a pull-up transistor 316. If the state of bit 0 of the expand register 286 is a logical 1, the transistor 314 is turned on which pulls the line 312 to ground or logical 0, otherwise it is a logical 1. Thus the contents of bit 0 of the expand register controls the logic state of the line 312 wherein the logic state of the line 312 is the complement of bit 0 of the expand register 286. In a similar manner, the logic state of a line 312b connected to the transistor switch 306b is the complement of the value of bit 1 of the expand register 286. Also the logic state of a pair of lines 318a and 318b are the complements of the bits 2 and 3, respectively, of expand register 286. The lines 318a and 318b are connected to the transistor switches 310a and 310b, respectively. If the input of the inverter 304 (either bit 0 or bit 4 of data bus 66a, depending upon flip-flop 280) is a logical 0, the transistors 306a and 306b are turned on, which selects the lines 312a and 312b which contain the complemented values of bits 0 and 1 of the expand register. On the other hand, if the input of the inverter 304 is a 1, the transistors 310a and b are turned on which selects the lines 318a and 318b containing the complemented values of the bits 2 and 3. The transistors 306a and 310a are connected to a common output line referred to as expand data bit 0 or EDB0. Similarly, the transistors 306b and 310b are connected to output line EDB1; thus a bit from the multiplexer 280 at inverter 304 is expanded into the logic states of lines ED0 and ED1, or simply bits ED0 and ED1. A 0 is expanded into bits ED0 and ED1 which are defined by the complement of bits 0 and 1 of the expand register and a 1 is expanded into bits ED0 and ED1 defined by the complement of bits 2 and 3 of the expand register 386. In a similar manner, the remaining bits of the lower half of the data bus 66a, (or remaining bits of the upper half if the upper half of the microcycle data bus is selected by the multiplexer 282) are expanded into the expand data bits ED2 and ED3, ED4 and ED5, and ED6 and ED7 which are also defined by the complement of either bits 0 and 1 or 2 and 3 of the expand register. For example, if the expand register bits 0 and 1 contain the values 1 and 0, respectively, the expand register bits 2 and 3 contain the values 0 and 0, respectively, and the half of the microcycler data bus being expanded has the values 0, 1, 1 and 0. These values will be expanded into the pixel values 01, 00, 00 and 01, respectively. A pixel is generally represented by 2 bits so that a byte of pixel data having 8 pixel data bits or PDB7-PDB0, represents four pixels with the first pixel represented by pixel data bits PDB0 and PDB1, the second pixel by PDB2 and PDB1, etc. The pixel data bit PDB6 will be referred to as the low bit of the first pixel with PDB7 as the high bit. Similarly, the second pixel has low and high bits PDB4 and PDB5, etc. The functions shift, rotate, and flop can be thought of as operating on pixels as a whole rather than as individual bits. Accordingly, there is provided a shifter, rotator, and flopper for both of the two bits of data representing pixels. Thus, referring to FIG. 11C, there are provided shifter circuits 320a and b, rotator circuits 322a and b, and flopper circuits 324a and b, for the low pixel data bits (PDB6, PDB4, PDB2 and PDB0) and the high bits (PDB7, PDB5, PDB3 and PDB1), respectively, of a byte of pixel data. The expand function, as with all the other functions, may be bypassed. Accordingly, the expand decoder 290 has a 4-bit output line 326a for the low pixel data bits connected to inputs of a 2-to-1 multiplexer 328a and a four-bit output line 326b for the high pixel data bits connected to inputs of a 2-to-1 multiplexer 328b. The other four inputs of the multiplexer 328a are connected to the low bits (D6, D4, D2 and D0) of the data bus 66a by a 4-bit input line 330a with the other 4 inputs of the multiplexer 328b connected to the high bits D7, D5, D3 and D1 by a line 330b. The output of the function generator register 274 is connected by a 7 bit output line 332 to a latch 334 having a control input line for address bit A14 connected to the address bus 75 of the CPU. When address bit A14 is low, the contents of the function generator register are gated through the latch 334. The output of the latch 334 corresponding to bit 3 of the function generator register is connected to the select inputs of the multiplexers 328a and 328b by a line 336. Thus, bit 3 of the function generator register controls the multiplexers 328a and 328b. if bit 3 is a 0, for example, the multiplexer 328a will conduct the low bits of pixel data from the expand decoder 290 but if bit 3 is a 1, the multiplexer 328a will conduct the low bits of pixel data from the data bus 66a. The multiplexer 328b operates in a similar manner for the high bits of pixel data. In this manner, the expand function may be bypassed by placing a 1 in bit 3 of the function generator register. The output of the multiplexer 328a is connected to the inputs of the shifter 320a and to the inputs of the rotator 322a with the output of the multiplexer 328b connected to the inputs of the shifter 320b and rotator 322b. As noted before, the shift and rotate functions are not performed at the same time. Bits 0 and 1 of the function generator register 274 control the amount of shift, if any, performed by the shifters 320a and b. The outputs of latch 334 corresponding to the bits 0 and 1 are connected to the shifter 320a and 320b by a 2 bit line 338. Bit 2 of the function generator register controls whether a rotate is performed and its corresponding latch output is connected to rotators 322a and 322b by a line 340. The output of the shifter 320a and the rotator 322a are connected to the inputs of the flopper 324a with the output of rotator 322b and shifter 320b connected to the input of flopper 324b. The output of the latch 334 corresponding to bit 6 of the expand register 274 is connected to the floppers 324a and b by a line 342 and controls whether a flop function is performed. The function generator register 274 is shown in FIG. 13 to comprise a 7-bit register having 7 inputs connected to the D6-D0 bits of the data bus 66a. (The logic design of each bit of the register 274 is also similar to the bit of the latch of the microcycle decoder 212 shown in FIG. 15). The latch 334 comprises NOR gates 334a-g each having an input connected to the address bit line A14 and an input connected to an output of bits 6-0, respectively, of the function generator 274. The function generator register select line 218 is connected by a buffer 385, and by an inverter 346, to the function generator register 274. The multiplexer 328b, rotator 322b, shifter 320b and flopper 324b for the high pixel data bits are constructed and operate in a manner similar to the multiplexer 328a, rotator 322a, shifter 320a and flopper 324a, for the low pixel data bits. Therefore, only those modifiers for the low pixel data bits (PDB6, PDB4, PDB2 and PDB0) will be described in detail. The high and low pixel data bits are modified at the same time and reassembled before being written to the display RAM. The output of the NOR gate 334d (corresponding to bit 3 of the function generator register) is connected by line 336 to the select input A of the 4 units 328a0, 328a2, 328a4 and 328a6 of the multiplexer 328a. The line 336 is also connected to the select input B of each multiplexer unit by an inverter 348. One such multiplexer unit, 328a0, is shown in greater detail in FIG. 20. The multiplexer unit 328a0 has an input 1A, connected to the unexpanded MDO bit of the data bus 66a and an input 1B, connected to the bit ED0 of the expand data bus 326a. The ED0 input is connected to a D type flip-flop shown generally at 349 having outputs 4 and 5, by a transistor switch 350 having a gate connected to the line 336 (not shown). The MD0 input is connected to the D flip-flop 348 by a transistor switch 351 whose gate is connnected to the line 336 through the inverter 348 (also not shown). Thus if the line 336 is a logical 1 (which is controlled by bit 3 of the function generator register when the address bit A14 is a logical 0), the ED0 bit from the expander is conducted to the D flip-flop. The output of this D flip-flop defines pixel data bit PDB0. The output of the eight flip-flops of the multiplexer 328a and b for the low and high pixel data bits, respectively, together define PDB7-PDB0. Thus if the line 336 is a logical 1, the pixel data bits PDB7-PDB0 will be determined by expand bits ED7-ED0. But if the line 336 is a 0, the unexpanded bit from the data bus 66a is conducted to the D flip-flop and PDB0 is defined by MD0. In such a manner, bit 3 of the function generator register determines whether the expand function is utilized or whether the pixel data from the microcycle data bus is transferred directly. Each multiplexer unit of multiplexer 328a has an output line 352a-d, respectively, and carries the low pixel data bits PDB0, PDB2, PDB4 and PDB6, respectively. The output line of each multiplexer unit is connected to the shifter for the low pixel data bits, indicated generally at 320a and the rotator for the low bits, indicated generally at 322a in FIG. 13. The shifter 320a comprises a programmed logic array (PLA) 321 having a plurality of input lines selectively coupled to a plurality of output lines 368a-p by a plurality of pull-down transistors 350. The output lines 352a-d of the multiplexer 328a are four of the PLA input lines. The shifter 320a further comprises a register 354a having 4 bits 354a0, 354a2, 354a4 and 354a6 which are connected to the inputs 356a-d of the PLA 321, respectively, (with bit 354a0 shown in greater detail in FIG. 21.) The register 354a stores the 4 low bits of the last pixel data byte from the CPU to be written to the display RAM which may be the previous byte of the sequence of bytes (such as those shown in FIG. 6) to be shifted. The register 354a is also clocked by the signal SHIFT. The NOR gate 344a (corresponding to bit 0 of the function generator register) of the latch 334 is connected by a line 358 to another input of the PLA 321. The line 358 is also connected to an input 359 by an inverter 360. NOR gate 344b (corresponding to bit 1 of the function generator register) of latch 334 is connected by a line 362 to an input of the PLA, with the line 362 also connected to an input 364 by an inverter 366. Bits 0 and 1 of the function generator register define the least and most significant bits of the shift amount performed by the shifter 320a. Each of the output lines 368a-p is connected to the voltage source VDD by one of a plurality of pull-up transistors 370. The actual amount of the shift performed by the shifter 320a is the complement of the bits contained within bits 0 and 1 of the function generator register since the NOR gates 344a and b invert the outputs of bits 0 and 1 when the address bit A14 is low. Thus, if bits 0 and 1 have the value "11", this is complemented to the values "00" resulting in a shift of 0 pixel positions. A shift of 1 position shown in FIG. 6 will be explained to illustrate the operation of the shifter 320a. If the bits 1 and 0 of the function generator register have the value "10", the complement of this is "01" indicating a shift of 1 pixel position. Thus, the line 358 will have the logic value of 1 with the line 362 at a logic value 0. The lines 359 and 364 will, of course, be a logical 0 and 1, respectively. As seen by the placement of the pull-down transistors 350, a logical 1 on the line 358 and the line 364 results in all the output lines being pulled down to logical 0 except output lines 368c, 368g, 368k and 368o since these lines do not have a pull-down transistor coupled to either the input line 358 or 364. The output lines 386c does have a pull-down transistor 350a coupled to the input line 352b which carries pixel data bit PDB2 from the multiplexer 328a. Thus the logic state of the output line 368c is the complement of the logic state of the input line 352b (or PDB2) from the output of the multiplexer unit 328a2. The pixel data bit PDB0 output of the shifter corresponds to output lines 368a-d and the particular value of PDB0 depends upon which of the lines 368a-d are selected by the input lines 358 and 362. Here, output line 368c was selected, therefore the pixel data bit PDB0 output of the shifter is defined by the PDB2 output of the multiplexer (but complemented). Since PDB0 is the low bit of the two bits representing the first pixel of a byte of pixel data and PDB2 is the low bit of the two bits representing the second pixel, it is seen that the pixel data values outputted by the multiplexer have shifted one pixel position. Output lines 368e-h of the shifter correspond to PDB2 with output lines 368i-l and 368m-p corresponding to PDB4 and PDB6 respectively. The output line 368g is coupled by a pull-down transistor 350b to the line 352c which carries the bit PDB4 from the multiplexer. Thus output line 368g (PDB2 of the shifter) has the complement of the logic state of PDB4 from the multiplexer. Output line 368k (PDB4) has the complement of the bit PDB6 from the multiplexer. The output line 368o of the shifter corresponding to PDB6 is coupled by a pull-down transistor 350d to the output bit 354a0 of the register 354a. Register 354a stores the low pixel data bits of the previous pixel data byte from the CPU to be written to memory. Bit 354a0 contains the pixel data bit PDB0 of the previous byte. Thus the logic state of the output line 368o (PDB6) is the complement of the bit PDB0 of the previous byte to be written. Thus, for example, if the output bits PDB6, PDB4, PDB2 and PDB0 of the multiplexer 328a are the low bits of the 8 bits representing the pixel values P7, P6, P5 and P4, respectively, of byte 1 of the sequence of bytes to be shifted shown in FIG. 6, and the output of the register 354a0 is the low bit of the 2 bits representing pixel value P0 of the prior byte of the sequence, it is seen that the low pixel data bits PDB6, PDB4, PDB2 and PDB0 of byte 1 (together with the high pixel data bits PDB7, PDB5, PDB3 and PDB1) represent pixel data values P0, P7, P6 and P5, respectively, after a shift operation of 1 pixel position. It is assumed that the first byte of pixel data of a sequence of bytes to be shifted is the first byte to be written to the display RAM after an output by the CPU to the function generator register. Accordingly, each bit of the register 354a has a reset input connected by a line 372 to the function generator register select line 218 such that the register 354a is reset to 0 with each output to the function generator register. Thus zeros are shifted into the first byte of a sequence as shown in FIG. 6. Each sequence is initialized by an output to the function generator register and therefore data should not be sent to the function generator register in the middle of the sequence. The output pixel data of the shifter are in complemented form (whether shifted or not) and will be recomplemented by the flopper indicated generally at 324a. The NOR gate 344g has an input connected to the A14 address bit and an input connected to bit 6 of the function generator register 274 which determines whether the flop function is performed when A14 is low. The output of the NOR gate 344g is connected by a line 374 to the gates of four transistor switches 376a-d. The logic state of the input line 374 is inverted by an inverter 378 whose output is connected to the gates of transistor switches 380a-d of the flopper 324a. The output lines 368a-p of the shifter 320a are the input lines of the flopper 324a. The flopper 324a also comprises a programmed logic array having output lines 382a-h coupled to the input lines 368a-p by a plurality of pull-down transistors 384. The output lines 382a and b are connected by the switches 376aand 380a, respectively, to a buffer 385 having an output line which is the flopper PDB0 output line 377a. (A typical buffer 385 logic circuit is shown in FIG. 22.) Lines 382c and d are connected by switches 376b and 380b, respectively, to a buffer 385 having the flopper PDB2 output line 377b, with the lines 382e and f connected by switches 376c and 380c, respectively, to a buffer 385 having the PDB4 output line 377C and the output lines 302g and h connected by switches 376d and 380d, respectively, to a buffer 385 having the flopper PDB6 output line 377d. The input line 368c (containing the complemented output pixel data bit PDB0 of the shifter when set for a shift of 1 pixel position) is coupled to the output line 382b by a pull-down transistor 384a and to the output line 382g by a pull-down transistor 384b wherein the logic state of the complemented shifter output bit PDB0 is recomplemented and carried uncomplemented on the flopper output lines 382b and 382g. A logical 1 state of the input line 374 turns on the transistor switch 376d whereby the shifter output bit PDB0 is conducted to the flopper PDB6 output line 377d. Thus, the PDB0 output of the shifter 320a is flopped to the flopper 324a output bit PDB6 when the input line 374 is a logical 1. On the other hand, if the logic state of line 374 is 0, the output of the inverter 378 is a logical 1 which turns on the transistor switch 380awhich conducts the shifter PDB0 bit to the flopper PDB0 line 377a and is not flopped. Thus when the logic state of the input line 374 is 0, the output of the shifter is not flopped. The other inputs of the flopper 324a for the bits PDB2, PDB4 and PDB6 are handled in a similar manner. As an example, if the byte of pixel data being written to the display RAM represents pixel values P7, P6, P5 and P4 as for the byte of original data of FIG. 6 and the shifter is set for zero shifts so that the shifter does not shift the data, then the PDB6, PDB4, PDB2 and PDB0 output bits of the shifter 320a are the low bits of the bits representing pixel values P7, P6, P5 and P4, respectively, (but complemented). When bit 6 of the function generator register is a logical 0, the logic states of the pixel data bits will be recomplemented and flopped so that the PDB6, PDB4, PDB2 and PDB0 output bits of the flopper 324a (together with the PDB7, PDB5, PDB3 and PDB1 output bits of the flopper 324b) represent the pixel data values P4, P5, P6 and P7 after the flop operation as shown in FIG. 6. The rotate function is performed on the low pixel data bits by a rotator indicated generally at 322a and comprises a programmed logic array 386 having 4 input lines connected to the register 354 PDB0, PDB2, PDB4 and PDB6 output lines 356a-d and 12 input lines connected to the 12 outputs of four 3-bit shift registers 388-391. The input of the first bit 388a of the shift register 388 is connected to the PDB0 input line 356a with the inputs of the first bits 389a-391a of register 389-391 connected to the PDB2, PDB4 and PDB6 lines 356b-d, respectively. (A typical bit circuit 388a of the bits of the shift registers 388-391 is shown in greater detail in FIG. 23.) The rotator is used to rotate a four-by-four pixel image 90.degree. in a clockwise direction. The four-by-four pixel image represented in FIG. 7A is shown with the individual pixel data bits PDB0-PDB7 of each of the four data bytes labeled. The rotator is initialized by an output to the function generator register and will reinitialize itself after every 8 writes to the display RAM. To perform a rotation, the following procedure is performed. The top byte or byte 0 of the unrotated image is written to a location in the display RAM. The next byte, byte 1 is written to the first location plus 40, byte 2 to the first location plus 80, and the last byte, byte 3 to the first location plus 120. These four locations correspond to 16 contiguous pixels since 40 bytes represent one line of pixels on the display screen. The process is then repeated with byte 0 rewritten to the first location, byte 1 to the first location plus 40, byte 2 to the first location plus 80 and byte 3 to the first location plus 120. After these 8 writes, the data will appear in the display RAM and (subsequently) the image on the screen rotated 90.degree. from the original as shown in FIG. 7B. The low 4-bit rotator 322a further comprises a 3-bit counter 394 for counting the 8 writes completed in a rotate sequence. (The logic circuitry of the bits 0-3 is shown in greater detail in FIG. 24 with bit 3 excluding that portion shown in phantom.) The counter 394 has a "clear" input, 2, connected to the function generator register select line 218 so that the counter is initialized to 0 with each output to the function generator register 274. A NOR gate 400 having a "DATEN" control signal input and an address bit A14 input is connected by series connected inverters 396 and 398 to the toggle input of the counter 394. The DATEN control signal is generated by a memory control circuit (FIG. 11F) of the data chip and is activated during memory write cycles. The NOR gate 400 has the input connected to the address bit A14 so that the counter is toggled only during memory write cycles in which the data written is to be modified by the function generator. The output of the third bit (bit 2) of the counter 394 is connected to the input of a NOR gate 402 which also has an input connected to the output of the inverter 396. The output signal of NOR gate 402, SHIFT is connected to the shift inputs of the shift registers 388-391 and clock inputs of register 354 (as well as flip-flop 280 of the expander). During the first four memory writes of a rotate sequence, the third bit of the counter 394 is 0 (since the counter counts from 000 to 011) therefore, the NOR gate 402 performs as an inverter wherein the DATEN signal from the inverter 396 generates a shift signal at the output of the NOR gate 402 with each of the first four writes to the display RAM of a rotate sequence. With the next or fifth write, however, the third bit of the counter 394 goes to a logical 1 which drives the output of the inverter 402 low for the last four memory writes of a rotate sequence. The SHIFT clock signal is activated with each write to the display RAM (except for the last four writes of a rotate operation) whether or not the rotate function is utilized in a write of data to the display RAM. Thus the SHIFT signal is also used to clock the Expand flip-flop 280 so that the flip-flop 280 toggles with each write operation to the display RAM. Each low bit of the first three bytes of a rotate sequence are shifted into the shift registers 388-391 of the low bit rotator 322a. Shift register 388 stores the pixel data bit PDB0 of pixels P0, P4 and P8 of the first three bytes, respectively, of the rotate sequence of FIG. 7A. Similarly, shift register 389 contains the low pixel data bit PDB2 of pixels P1, P5 and P9 after the first four memory writes of the rotate operation. The particular pixel data bits for each of the registers 388-391 are shown in FIG. 40. The programmed logic array 386 of the rotator 322a further has inputs 404a-404c connected to the outputs of bits 388a-388c, respectively, of the shift register 388. The output of bits 389a-c of the shift register 389 are connected to the input lines 406a-c with the output of bits 390a-c and 391a-c of the shift registers 390 and 391 connected to the input lines 408a-c and 410a-c, respectively. The input lines 356a-d from the register 354 are coupled to output lines 412a-d, respectively, by four pull-down transistors 414. The output lines 412a-d are connected by four transistor switches 416a-d to the voltage source VDD by a pull-up transistor 418 and also to a common output line 420 which carries the pixel data bit PDB6 output of the rotator in complemented form. The input lines 404a, 406a, 408a and 410a (from the LSB of the shift registers 388-391) are coupled to output lines 422a-d, respectively, by four pull-down transistors 424. The output lines 422a-d are connected by four transistors switches 426a-d, respectively, to a common output line 428 and to voltage source VDD by a pull-up transistor 430. The output line 428 carries the pixel data bit PDB4 output of the rotator in complemented form. The input lines 404b, 406b, 408b and 410b and input lines 404c, 406c, 408c and 410c are coupled to output lines 432a-d and output lines 434a-d, respectively, by pull-down transistors 436 and 438 respectively. The output lines 432a-d are connected by four transistor switches 440a-d to a common output line 422 (for pixel data output bit PDB2) and to the voltage VDD by a pull-up transistor 444. The output lines 434a-d are connected by four transistor switches 446a-d to a common output line 448 (for pixel data output bit PDB0) and to voltage source VDD by a pull-up transistor 450. The rotator 322a has a second programmed logic array 452 having four output lines 454-457 which controls the transistor switches 416, 426, 440 and 446. The output line 457 is connected to the gates of the transistor switches 416a, 426a, 440a, and 446a with the output line 456 connected to the gates of the transistor switches 416b, 426b, 440b and 446b, etc. The program logic array 452 has an input line 460 connected to the output Q of the third bit of the counter 394. The input line 460 is coupled to each of the output lines 454-457 by four pull-down transistors 462. Thus, when the third bit of the counter 394 is a logical 0 (i.e., during the first four writes to the display RAM of the rotate sequence) the output Q of the third bit is a logical 1 which pulls down the four output lines 454-457 of the PLA 452 which turns off the transistor switches 416a-d, 422a-d, etc. These switches are turned off since during the first four writes, the four shift registers 388-391 are being loaded with the proper pixel data bits of the first four writes. The PLA 452 has an input line 463 connected by an inverter 464 to the output of the NOR gate 344c of the latch 344. The input line 463 is coupled to the output lines 454-457 by four pull-down transistors 466, respectively. If bit 3 of the function generator register 274 is a logical 1, the logic state at the input line 463 will also be a logical 1 which pulls down the output lines 454-457 to a logical 0 turning off the transistor switches 416a-d, 426a-d, etc. of the programmed logic array 386. The rotate function may be bypassed in this manner. The PLA 452 has inputs 468 and 470 connected to the Q outputs first and second bits, respectively, of the three-bit counter 394. The input line 468 is connected to a second input line 469 by an inverter 472. The input line 470 is connected to still another input line 471 by an inverter 474. The input lines 468-471 are coupled to the output lines 454-457 by a plurality of pull-down transistors 476 such that as the counter 394 counts from 4 (100 Binary or B) to 7 (111 B) the output lines 454-457 are successively activated. Thus, when bits 1 and 2 of counter 394 are both 0, the output line 454 is enabled and with bits 1 and 0 equal to 01, respectively, output line 455 is enabled, etc. As noted before, during the first writes of the rotate sequence, the shift registers 388-391 are loaded with their respective bits of the first three bytes of the rotate sequence of data with the last byte being stored in register 384. This corresponds to counts 0-3 of the counter 394. For counts 4-7 data is no longer shifted into the registers while the CPU re-transmits the four pixel data bytes of the sequence to be rotated. At count (100 B) in which byte 0 is transmitted, the output line 454 is enabled which turns on the transistor switches 416d, 426d, 440d and 446d. Since output line 412d is coupled to input line 456d from register 384, pixel data bit PDB6 of the previous (at last) data byte of the sequence (i.e., byte 3), appears on the output line 420 (PDB6) of the rotator in complemented form. The pixel data bit PDB6 of byte 3 of the sequence is the lower bit of the pixel value represented by P15. The lower pixel data bit representing the pixel data value P11 stored in the 391a bit of the shift register 391 connected by the input line 410a is complemented by a pull-down transistor 424 and conducted by the transistor switch 426d to the PDB4 output line 428 of the rotator 322a. In a similar manner, the low pixel data bits representing pixel data values P7 and P3 stored in the shift register 391 appear on the rotator 322a pixel data outputs PDB2 and PDB0, respectively, since the transistor switches 440d and 446d, respectively, are turned on. Thus, although the CPU transmits byte 0 at count 100 B, the byte representing pixel data values P15, P11, P7 and P3 is actually written to the display RAM at the first location as shown in FIG. 7B. On the next write to the display RAM, the count of the counter 394 changes to 101 B wherein the PLA 452 in turn causes the transistor switches 416b, 426b, 440b, and 446b to turn on. The low pixel data bit representing pixel data value P14 carried by input line 356c from the register 354 appears in complemented form on the rotator 322a output PDB6 line 420. Also, the low pixel data bits representing pixel data values P10, P6 and P2 stored in the register 390 appear in complemented form on the rotator 322a PDB4, PDB2 and PDB0 output lines 428, 442 and 448, respectively, and are stored in the first memory location plus 40, as indicated in FIG. 7B. After the last two writes, the low pixel data bits (as well as the high pizel data bits from the rotator 322d) representing the pixel data values will appear in the display RAM as shown in FIG. 7B. The flopper 324a recomplements the pixel data bits from the rotator 322a so that the pixel data bits are stored in uncomplemented form in the display RAM. Thus, the pixel data that will be written to the display RAM is transmitted by the CPU in the first four "writes" to the display RAM of the four bytes of the rotate sequence and is latched up in the registers 388-391 and 354. The rotate sequence is then re-transmitted (but any data could actually be sent) to the same four addresses of the display RAM with the pixel data latched up in the registers 354 and 388-391 actually being written to those four display RAM addresses represented in FIG. 7B. The rotator, shifter and flopper circuits for the high pixel data bits (PDB7, PDB5, PDB3 and PDB1) are indicated generally at 322b, 320b and 324b, respectively, in FIG. 13. The modifications to the high pixel data bits PDB7, PDB5, PDB3 and PDB1 are performed by the rotator 322b, the shifter 320b and the flopper 324b simultaneously with the modifications performed on the low pixel data bits. Each pixel data value, represented by a high and a low pixel data bit, can be shifted, flopped, or rotated as shown in FIGS. 6 and 7a and b. The OR and exclusive-OR functions are performed by an OR/exclusive-OR circuit 480 shown in FIG. 11C to have a four bit input line 482a connected to the output of the low pixel data bit flopper 324a and a four bit input line 482b connected to the output of the high pixel data bit flopper 324b. The OR/exclusive-OR circuit 480 has two further inputs connected by a two-bit input line 484 to the latch 334 which latches the complement of bits 4 and 5 of the function generator register 274 when the address bit A14 is low. These bits determine whether or not the OR or exclusive-OR functions, respectively, are performed. These functions can be thought of as operating on a byte of pixel data as 8 bits rather than as 4 pixels. When the OR function is used in writing data to the display RAM, the input to the OR/exclusive-OR circuit is ORed with the contents of the display RAM location being accessed by the addressed chip. Accordingly, the OR/exclusive-OR circuit 480 has 8 inputs connected by an 8-bit input line 486 to a tri-state buffer 488 which is connected to an 8-bit memory data bus 490 from the display RAM which carries the memory data bits MDO-MD7. Pixel data that was stored in the display RAM which is to be used in an OR or exclusive-OR operation, is latched up in the OR/exclusive-OR circuit 480. The OR/exclusive-OR circuit 480 has an 8bit output line 492 connected to the tri-state buffer 488 on which the resultant pixel data is carried to be stored at the display RAM location from which the pixel data was accessed. The OR/exclusive-OR circuit 480 is shown in greater detail in FIG. 13 and comprises 8 units 480a-h. Each OR/exclusive-OR unit can perform an OR or exclusive-OR (as determined by bits 4 and 5 of the function generator register 274) on a pixel data bit from the flopper and from the display RAM and can store the resultant pixel data bit in the display RAM. A typical unit 480a is shown in greater detail in FIG. 25. The unit 480a has an input connected to the output line 377a (which is one of the input lines 482a in FIG. 11C) which carries the pixel data bit PDB0 output of the flopper 324a and an input 486a which carries the pixel data bit PDB0 from the display RAM. The unit has an input 484a connected to the output of the NOR gate 344e of the latch 334 associated with bit 4 of the function generator register 274. Bit 4 determines whether or not the OR function is performed. The input line 484a is also connected to an inverter (not shown) having an output connected to an input 494. The unit has an input 484b connected to the output of the NOR gate 344f associated with bit 5 of the expand register which controls whether or not the exclusive-OR function is performed. The input line 384b is also connected to an input line 496 by an inverter 498. The input line 377a (the PDB0 bit from the flopper) is connected by an inverter 500 which is connected to a line 502. The input line 486a (for the PDB0 bit from the display RAM) is connected to a latch indicated generally at 504 which latches up the pixel data bit from the display RAM until the pixel data bit from the flopper arrives for the OR or exclusive-OR function. The latch 504 has an output line 506 which is connected to a line 508 by an inverter 510. The unit 480a further comprises a programmed logic array indicated generally at 512 which performs either the OR function or exclusive-OR function (or neither) as determined by bits 4 and 5 of the function generator register. The PLA 512 has output lines 514a-e selectively coupled by a plurality of pull-down transistors 516 to the lines 500, 502, 508, 377a, 494a, 494, 484b, and 496. The lines 514a-e are connected to a NOR gate 516 having an output connected to an inverter 518 which has an output 492a (of lines 492 FIG. 11C). To illustrate the operation of the unit 480a, it will be assumed that bits 4 and 5 of the function generator register have the values 0 and 1, respectively, which indicates an OR function is to be performed. When bit 4 is a logical 0, line 484a is a logical 1 which pulls-down the lines 514a, 514b and 514d to a logical 0. The PDB0 bit from the flopper carried on the line 377a is inverted by the inverter 500 and recomplemented by the pull-down transistor 516a so that line 514c carries the PDB0 bit from the flopper in the uncomplemented form. The PDB0 bit from the display RAM is complemented by the inverter 510 and recomplemented by the pull-down transistor 516b so that the line 514e carries the PDB0 bit from the display RAM in the uncomplemented form. Thus, if either the line 514c or line 514e is a logical 1, the output of the NOR gate 516 will be a logical 0 which is inverted by the inverter 518 to a logical 1 on line 492a. However, if both the lines 514c and e are logical 0, the output of the NOR gate 516 is a logical 1 and the output of the inverter 518 is a logical 0. Thus, the logical OR function is performed on the PDB0 bits from the display RAM and from the CPU transmitted through the flopper. To perform an exclusive-OR function, bits 4 and 5 of the function generator register are set to 1 and 0, respectively. The input line 494 then is a logical 1 which pulls the lines 514c and 514e to a logical 0. Also, the line 484b is a logical 1 which pulls the line 514d in addition to a logical 0. The line 377a which carries the PDB0 bit from the CPU (transmitted through the flopper 324a) is coupled to the line 514b by a pull-down transistor 516c. The line 508 which carries the complemented PDB0 bit from the display RAM is coupled to the line 514b by a pull-down transistor 516d. Thus, if the PDB0 bit from the CPU is a logical 0 and the complemented PDB0 bit from the display RAM is a logical 0 (i.e., the PDB0 bit from the display RAM is a logical 1) the logic state of the line 514b will be a logical 1 resulting in the output of the NOR gate 516 being a logical 0 and the output line 492a of the OR/exclusive-OR unit 480a being a logical 1. Otherwise, the logic state of the 514b line is a logical 0 and the logic state of the output line 492a depends upon the logic state of the line 514a. The line 502 which carries the complemented PDB0 bit from the CPU is coupled to the line 514a by a pull-down transistor 516e. The line 506 which carries the PDB0 bit from the display RAM is coupled to the line 514a by a pull-down transistor 516f. Thus, if the complemented PDB0 bit from the CPU is a logical 0 (i.e., the PDB0 bit from the CPU is a logical 1) and the PDB0 bit from the display RAM is a logical 0, the logic state of the line 514a will be a logical 1 causing the output of the NOR gate 516 to be a logical 0 and the output of the OR/exclusive-OR unit 480a at the output line 492a to be a logical 1. If both the PDB0 bit from the display RAM and from the CPU are both 0 or alternatively are both 1, the logic state of both lines 514a and b will be a logical 0 causing the output of the NOR gate 516 to be a logical 1 and the output line 492a of the OR/exclusive-Or unit 480a to be a logical 0. Thus, the exclusive-OR function may be performed on th PDB0 bits from the display RAM and the CPU. In a similar manner, a logical OR or exclusive-OR function can be performed on the PDB1-PDB7 bits from the CPU and the display RAM by the units 480b-h shown in FIG. 13. The output line 492 of each OR/exclusive-OR unit 480a-h is connected to the tri-state buffer indicated generally at 488 which is in turn connected to the memory data bus 490. The tri-state buffer 488 has 8 units 488a-h. A typical tri-state buffer unit 488a is shown in greater detail in FIG. 26. The unit 488a has an input/output line 522 connected to the MD0 bit of the memory data bus 490. The tri-state buffer unit 488a also has an output line 524, and an input line 526 connected to the DATEN control signal. When the DATEN control signal is low, the logic state of the output line 522 is the same as the data bit carried on the input line 492a from the OR/exclusive-OR unit 480a. In this manner, the pixel data outputted from the OR/exclusive-OR unit may be transmitted to the display RAM at an address supplied through the address chip. The CPU may read an intercept register 528 (FIG. 11C) having address 8H to determine if an intercept occurred during a write to the display RAM in which the OR or exclusive-OR function is utilized. An "intercept" is defined as the writing of a non-zero pixel data value at a location in the display RAM that previously contained a non-zero pixel data value. The intercept register 528 has an input connected to the 4-bit output line 482b of the flopper 324b and an input connected to the 4 bit output line 482a of the flopper 324a by which the pixel data bits from the CPU may be inputted. The intercept register 528 also has an 8-bit input line 530 connected to the OR/exclusive-OR circuit 480 by an 8-bit line 530. The output of the intercept register 528 is connected by an 8-bit output line 532 to the input of a 2-to-1 multiplexer 534. The intercept register 528, shown in greater detail in FIG. 13, comprises 8 units 528a-h. A 1 in a particular intercept register unit means that an intercept has occurred. Since a pixel is represented by 2 bits of data, a byte of pixel data represents 4 pixels and thus has 4 pixel positions. Intercept register units 528a-d indicate whether an intercept has occured in any of the 4 pixel positions in the last write to the display RAM in which the OR or exclusive-OR functions were utilized. The unit 528a indicates whether an intercept has occurred in the first pixel position with the unit 528b indicating whether an intercept has occurred in a secon | ||||||