Spelled word input directory information retrieval system with input word error corrective searching4164025Abstract An arrangement for retrieving information from a directory responsive to a sequence of spoken character signals in which a set of probable characters for each character signal is stored in a position ordered array. A candidate word is formed from the most probable characters of the array and the directory is repeatedly searched for words therein which match a candidate word. After each unsuccessful search, the candidate word is modified by selectively substituting array characters for mismatched position characters on the basis of the closest mismatched word found in the preceding search. If there are no more array characters for substitution after an unsuccessful search, a new candidate word is formed by placing an ignore character in the first mismatched position of the best candidate word of all preceding searches. The position of the ignore mismatch character is shifted left each time no further array characters are available for substitution. Responsive to detection of a matching word, a spoken message is generated from the information associated therewith. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
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INTENDED NAME B E C K G A
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Probable D B C J .phi.
A
Character B V Z .phi.
.phi.
.phi.
Sets P E .phi. .phi.
.phi.
.phi.
.phi. .phi. .phi. .phi.
.phi.
.phi.
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Each character set in Table 1 is arranged in most probable to least probable order. The most probable character in the zero, or leftmost position, is D. The intermediate probable character in this position is B, and the least probable character in this position is P. There is no recognized character in the fifth position, and only one recognized character appears in each of the fourth and sixth positions. An unrecognized character is represented by .phi. and is ignored in the character matching operations of the circuit of FIG. 1. It is readily apparent from Table 1 that, (a) no combination of characters corresponds to the intended spelled name of the input character string, (b) the most probable candidate name is DBCJ.phi.A which contains four misrecognized or unrecognized characters, and (c) the directory comprises an alphabetically ordered list of subscriber names, each of which is equally likely. After the most probable candidate word is generated in array 110, for the most probable characters of the positions of Table 1, the signal INIT is applied to sequence control logic 180 via line 108 which is operative to terminate the acoustic recognition mode and to initiate the first directory search mode. In the first directory search mode, the most probable candidate word is applied from array 110 to directory range selector 120 which is operative to determine the lower and upper bounds of a sequence of directory words corresponding to selected characters of the candidate word supplied thereto. The selected sequence includes all directory words which could possibly match the candidate word. An extension of the directory range does not add possible matching directory words and only increases the time required for the search. Responsive to the lower bound coded signal from directory range selector 120, directory access logic 130 addresses the directory words of the determined sequence, which directory words are stored in store 140. Each addressed directory word from store 140 is supplied to comparison logic 150 and is therein compared in left to right character order with the candidate word from array 110. When a directory word matches the candidate word except for the ignore mismatch positions, the directory word address is applied from directory access logic 130 to matched name logic and store 160 via line 152 and is stored therein. If a directory word does not match the candidate word, the first occurring mismatched character position is detected and a coded signal corresponding to the mismatched position is sent from comparison logic 150 to candidate modifier logic 170 via line 153. In candidate modifier logic 170, the rightmost first occurring mismatch position (MI) of all mismatched directory words of the sequence is detected and stored. The MI position represents the closest mismatched word detected in the sequence, i.e., the word with the greatest sequence of matched characters from left to right. Modifier logic 170 is also operative to determine and store the rightmost first occurring mismatched position of all preceding directory searches as the coded signal MMI. The word in which the MMI position is found is the best mismatched word of the current and preceding directory searches and the candidate word corresponding to this best mismatched word is stored in array 110. At the end of the directory word sequence determined by the upper bound signal NU from directory range selector 120 is directory store logic 140, the directory search mode is terminated by sequence control logic 180. In the event at least one matching directory word is detected during the directory search mode, sequence control logic 180 causes the directory retrieval mode to be started. During the directory retrieval mode, the matching directory word addresses from matched name logic and store 160 are supplied to directory store 140 via directory access logic 130 and the information associated with each matching directory word is retrieved from store 140. A spoken message corresponding to the retrieved information is then generated and supplied to message interface 101. If no matching directory word is detected in the directory search mode, the candidate word change mode is initiated by sequence control logic 180 in which the rightmost first occurring mismatched position (MI) of the sequence is supplied from candidate modifier logic 170 to candidate selector 115 responsive to the (MI) mismatched position signal on line 172. Candidate selector 115 is operative to modify the candidate word at the output of array 110. The modified candidate word is produced by replacing the character in the mismatched position MI with the next most probable character from the corresponding position of the array. It is unnecessary to modify candidate word positions to the right of the MI position since such modifications cannot result in detection of matching directory words or provide a better mismatched word. If all recognized characters in the mismatched position (MI) of the array have been exhausted in preceding directory searches, the most probable character in the mismatched position is returned to the candidate word and the next most probable character in the nearest left position of the array with an available character is substituted in the candidate word. After the modification of the candidate word, the candidate word change mode is terminated by sequence control logic 180 and a new directory search mode is started on the basis of the modified candidate word. The directory search and candidate word change modes are repeated until either (1) matching directory words are found, or (2) there are no more available characters in the first position of candidate array 110 for substitution. In the latter event, the mismatched position MMI of the best mismatched word in the preceding directory searches is supplied to candidate selector 115. At this time, it is concluded that none of the probable characters in at least one position of the array could match the corresponding character of any directory word. It is therefore necessary to ignore mismatches in one candidate word position in succeeding directory searches in order to detect a directory word which corresponds to the input character signal string. The MMI position is the best position to ignore in subsequent directory searches since ignoring positions to the right of the MMI position could not result in detection of matching directory words. The candidate word corresponding to the best mismatched word of all preceding directory searches is obtained from array 110 responsive to the operation of candidate selector 115 and an ignore mismatch character .phi. is placed in the mismatched position MMI of the best candidate word. The directory search and candidate change modes are resumed using the ignore character in the MMI position. Upon exhaustion of all available characters in the zero (leftmost) position of the array for candidate word modification, it is apparent that the MMI position is not the position in which none of the probable characters could match the corresponding directory word position. A position to the left of the MMI position, however, could be in error. The inserted ignore mismatch character is therefore replaced by the most probable character in the MMI position of the array and an ignore character is placed in the adjacent left position of the candidate word. The ignore mismatch character is shifted left one position each time all available characters in the zero position are exhausted. If the ignore mismatch character is used in the zero position of the candidate word during a subsequent directory search, and all available characters in candidate array 110 have been used to modify a candidate word, the directory search and candidate word change mode sequence is halted by sequence control logic 180. A message is then generated in directory store logic 140 to inform the inquirer via message interface 101 that there is no subscriber listed in the directory corresponding to the input character string. Table 2 illustrates the operation of the circuit of FIG. 1 responsive to the spoken spelled character input BECK, GA shown in Table 1.
TABLE 2
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2 3 4 5 6 7
First Modi-
Mis- Best Best fied
Direc-
Candi-
Closest matched
Mis- First Candi-
tory
date Mismatched
Position
matched
Mismatched
date
Search
Word Word (MI) Word Position
Word
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1 DBCJ.phi.A
DAVISRH 1 DAVISRH 1 DVCJ.phi.A
2 DVCJ.phi.A
DVORAKDL 2 DVORAKDL
2 DVZJ.phi.A
3 DVZJ.phi.A
DVORAKDL 2 DVORAKDL
2 DECJ.phi.A
4 DECJ.phi.A
DECNA 3 DECNA 3 DEZJ.phi.A
5 DEZJ.phi.A
DESMETRE 2 DECNA 3 BBCJ.phi.A
6 BBCJ.phi.A
BARTLETTJE
1 DECNA 3 BVCJ.phi.A
7 BVCJ.phi.A
BURKHARDEG
1 DECNA 3 BECJ.phi.A
8 PECJ.phi.A
BECCONEJP
3 DECNA 3 BEZJ.phi.A
9 PEZJ.phi.A
BEZAKST 3 DECNA 3 PBCJ.phi.A
10 PBCJ.phi.A
PARKERK.phi.
1 DECNA 3 PVCJ.phi.A
11 PVCJ.phi.A
PULLEYBM 1 DECNA 3 PECJ.phi.A
12 PECJ.phi.A
PECCAID 3 DECNA 3 PEZJ.phi.A
13 PEZJ.phi.A
PEZDIRTZ 3 DECNA 3 DEC.phi..phi.A
14 DEC.phi..phi.A
DECNA 3 DEZ.phi..phi.A
15 DEZ.phi..phi.A
DESMETRE 2 BBC.phi..phi.A
16 BBC.phi..phi.A
BARTLETTJE
1 BVC.phi..phi.A
17 BVC.phi..phi.A
BURKHARDEG
1 BEC.phi..phi.A
18 BFC.phi..phi.A
BECKGA match
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In Table 2 are listed the search mode candidate word, the closest mismatched word of the search, the rightmost first occurring mismatched position (MI) of the search, the best mismatched word of the current and preceding searches, the rightmost first occurring mismatched position (MMI) of the current and preceding searches, and the modified candidate word generated in the candidate word change mode following the search. During this first directory search, the most probable candidate word DBCJ.phi.A from Table 1 is used. D is in the zero position, B is in the first position and C, J, .phi., A are in the second to fifth positions. The closest mismatched word found is DAVISRH. The first occurring mismatched position MI is the first position corresponding to the mismatch of character B of the candidate word and character A of the directory word. Since only one search has been completed, DAVISRH is the best mismatched word and MMI is the first position. Becuase the first position is mismatched, the next most probable character in the first position, i.e., V, replaces the B in the most probable candidate word. In this way, the modified candidate word DVCJ.phi.A is formed for the second directory search as shown in column 2. In the third directory search, the candidate word is DVZJ.phi.A and the closest mismatched word is DVORAKDL. The second position is the MI mismatched position. Since Z is the last available character of the second position of the array, the most probable second position character C replaces Z in that position, and the next available character of the first position of the array, i.e., E, is substituted for the V in the first position of the candidate word. The modified candidate word becomes DECJ.phi.A as shown in column 7 of directory search No. 3. At the end of the ninth directory search, the last available characters have been used in the first, second and third positions of candidate word BEZJ.phi.A. The first occurring mismatched position MI of the closest mismatched directory word BEZAKST of the ninth directory search is the third position. J, which is the only probable character in the third position, remains in the modified candidate word but the second position character is changed. Since the Z in second position of the candidate word is the last probable character, it is replaced by the most probable character of the second position in the array, i.e., C. The last available character (E) in the first position of the candidate word is then replaced by the most probable character of that position, i.e., B; and the zero position character B of the candidate word is replaced by the next available character in the zero position of the array, i.e., P. The modified candidate word for the next directory search is then PBCJ.phi.A. In the candidate change mode following the thirteenth directory search, the third position of the candidate word (J) is mismatched and there are no available characters for substitution in the zero, first, second and third positions of array 110 as shown in Table 1. Since the last available character in the zero position has already been used, the candidate word corresponding to the stored best mismatched word of all preceding directory searches is retrieved from array 110. This candidate word, DECJ.phi.A from directory search No. 4, is now modified by placing an ignore mismatch character .phi. in the mismatched third position. The candidate word for the fourteenth search is then DEC.phi..phi.A. The candidate word in the eighteenth directory search (BEC.phi..phi.A) matches the directory word BECKGA except for the ignore mismatch characters in the third and fourth positions since the .phi. positions of the candidate word are ignored in character comparison operations. Responsive to the detection of at least one matching directory word in a directory search mode, control logic 180 initiates the directory retrieval mode after the eighteenth directory search. In this directory retrieval mode, the information in directory store 140 associated with the directory word BECKGA is retrieved; a spoken message is generated from the retrieved information in store 140; and the synthesized message from directory store 140 is transmitted to the inquirer via message interface 101. DETAILED DESCRIPTION Referring to the general block diagram of FIG. 1, acoustic recognizer 105 includes a stored set of previously obtained feature signals for each alphabetic character. The string of input character signals from message source 101 represents the spoken spelled name of a subscriber whose name is asserted to be in directory store 140. Each input character signal of the spoken spelled name is transformed into a predetermined set of feature signals representing the input character signal. The feature signals for the input character are compared to the stored previously obtained feature signals for each alphabetic character. Responsive to the feature signal comparison, a set of probable character codes NC are generated. A zero (.phi.) code represents an unrecognized character which is ignored in character comparisons; the one to twenty-six codes represent the characters A to Z, respectively; and a 27 code represents a stop signal corresponding to the end of input characters. For each probable character, a signal PC representative of the degree of similarity between the probable character feature signal and the input character feature signal is also generated. With respect to the example illustrated in Tables 1 and 2, the probable characters for the zero or leftmost position input character signal are D, B and P in most to least probable order. The PC, or post number signal corresponding to the D is zero since D is the most probable character. The PC signal corresponding to the B is one, and the PC signal corresponding to the third most probable character P is two. The NC and PC coded signals for the zero character position are sequentially applied to candidate array 110. A shift signal SC is supplied with each pair of NC and PC signals. In similar manner NC, PC and SC signals are generated for each succeeding input character signal. One arrangement for acoustic recognizer 105 is described in the article, "Minimum Predictive Residual Principle Applied to Speech Recognition," by F. Itakura appearing in the IEEE Transactions on Acoustics Speech and Signal Processing, Vol. 23, pp. 67-72, February 1975. In the Itakura arrangement, reference linear prediction derived signals are stored for prescribed words or characters spoken by a designated individual. When an unknown character is later uttered by the designated individual, the linear prediction derived signal obtained therefrom is compared to the reference character derived signal by means of a distant metric. The closest corresponding (least distance metric) reference character is identified as the unknown input character. As used in the circuit of FIG. 1, the acoustic recognizer of Itakura provides a set of probable characters NC ordered in accordance with distance metrics for each input character signal, a set of correspondence signals PC for each probable character, and a set of signals SC upon the occurrence of the probable characters. In the circuit of FIG. 1, the NC and PC signals for the set of probable characters of each character position are sequentially applied to candidate array 110 shown in detail in FIG. 2. Referring to FIG. 2, recirculating shift register 205-0 is used to store the zero, or leftmost, character position probable character set and associated shift register 206-0 is operative to store the order or post numbers corresponding to the probable characters in the zero position set. Similarly, shift register 205-1 stores the first position probable character set while shift register 206-1 stores the associated probable character post numbers. In like manner, shift register 205-7 stores the seventh or rightmost position probable character set and shift register 206-7 stores the post numbers associated with the probable characters in shift register 205-7. The probable character sets for the third to sixth positions are stored in similar shift register arrangements not shown in FIG. 2. Latch 213 comprises a group of eight latching stores which selectively store the post numbers from the outputs of shift registers 206-0 to 206-7 whereby the candidate word corresponding to the best matched word is identified. At the beginning of the acoustic recognition mode for the input character string corresponding to the spoken spelled character string BECK, GA, the leftmost position probable character set D, B, P is generated in acoustic recognizer 105. This probable character set, NC(0) is then sequentially applied to zero position shift register 205-0 via line 201-0 of cable 106 and multiplexer 203-0. As illustrated in waveform 1101 of FIG. 11, a series of eight SC shift pulses are generated in acoustic recognizer 105 for each character set so that eight characters are inserted into shift register 205-0. Waveform 1103 illustrates the sequence of probable character codes applied to shift register 205-0 and waveform 1105 illustrates the sequence of post number codes which are applied into register 206-0 to indicate the order or degree of similarity of the probable characters in register 205-0. After the recognized characters are inserted, .phi. (ignore mismatch) characters are inserted. At time t.sub.1 in FIG. 11, the D character signal is applied to the input of shift register 205-0 and the 0 post signal is applied to the input of register 206-0. Responsive to the SC shift signal at t.sub.1 (waveform 1101) applied to line 109, the D character signal is inserted into the last or seventh position of register 205-0, and the 0 signal is inserted into the corresponding position of register 206-0. At time t.sub.2, the B character signal is inserted into the last position of register 205-0 while the D character signal is shifted into the sixth position of this register. Concurrently, the one post number signal of waveform 1105 is inserted into the seventh position of register 206-0 while the 0 post number signal is shifted into the sixth position thereof. Responsive to the third SC shift pulse occurring at time t.sub.3, the P character signal of waveform 1103 and the 2 signal of waveform 1105 are inserted into the seventh positions of shift registers 205-0 and 206-0, respectively, while the previously inserted D and B character signals are shifted to the fifth and sixth positions, respectively, in register 205-0. Concurrently, the 0 and 1 post number signals are shifted to the fifth and sixth positions of register 206-0, respectively. Subsequent to the insertion of the P character signal, a sequence of five .phi. coded signals are placed in register 205-0 while the sequence of 3 to 7 post signals are placed in the corresponding positions of register 206-0. Upon termination of the insertion of the leftmost probable character set in zero position register 205-0, the D, B and P signals are in the zero, first and second positions in shift register 205-0, and the post numbers are in sequential order in shift register 206-0. After generation of the next to leftmost probable character set in acoustic recognizer 105, the probable character signals, B, V, E are applied to shift register 205-1 via line 201-0 of cable 106 and multiplexer 203-1 while the corresponding post numbers are applied to register 206-1 via line 202-1 of cable 107 and multiplexer 203-1. At t.sub.9, the most probable character signal B is applied to the input of register 205-1 and is shifted into the seventh position thereof by the then occurring SC shift signal on line 109. The zero post number signal is shifted into the seventh position of register 206-1 at this time. At time t.sub.10, the V signal is shifted into the seventh position of register 205-1 while the 1 post signal is shifted into the seventh position of register 206-1. Subsequent to the insertion of the E character signal at time t.sub.11, five .phi. characters are shifted into register 205-1 while the 3 to 7 post signals are shifted into register 206-1. After time t.sub.16, registers 205-1 and 206-1 are filled. The zero or output position of register 205-1 contains the most probable character B. The next or first position of this register contains the next most probable character V, and the second position contains the least most probable character E. Register 206-1 identifies the order of the probable characters in register 205-1. The probable character sets corresponding to the E, C, K and G character signals are then inserted into similar shift registers not shown in FIG. 2 responsive to the generation of these character sets in recognizer 105. Upon the generation of the rightmost character set in recognizer 105 for the rightmost character signal which character set consists of all .phi. characters, shift register 205-7 is filled with .phi. character codes in all positions and the post number signals are placed in register 206-7 as illustrated in waveforms 1101 and 1111, and 1113 between times t.sub.17 through t.sub.25. After registers 205-7 and 206-7 have been filled, the shift registers of array 110 contain the position ordered sets of probable characters for use in the generation of candidate words. FIG. 12 shows the contents of array 110 at the end of the acoustic recognition mode. Character position zero contains the sequence D, B, P followed by five zero characters. Character position 1 contains the sequence B, V, E followed by five zero characters. Position 2 contains the sequence C, Z followed by six .phi. characters. Position 3 contains the sole recognized character J followed by seven .phi. characters. Position 4 corresponding to an unrecognized character contains eight .phi. characters. Positive five corresponding to the single recognized character A contains the A character signal in the first position and zero characters in the following seven positions. Since the input sequence is a six character sequence, a special code "27" is generated by the acoustic recognizer in the sixth position to indicate the termination of the input character sequence. Position 7 contains all .phi. characters, since there is no character signal in the input character signal string for this position. A control signal INIT shown in waveform 1115 of FIG. 11 is generated in acoustic recognizer 105 after the eighth character set is inserted into register 205-7. The INIT signal is applied to sequence control logic 180 via line 108 at time t.sub.25 so that the acoustic recognition mode may be terminated. Control logic 180 is shown in detail in FIGS. 10A and 10B. Referring to FIG. 10B, the control logic therein comprises a set of 18 D-type flip-flops well known in the art. Each of the flip-flops in flip-flop set 1000 is reset by the INIT signal from recognizer 105. Flip-flop 1001A, for example, is reset by signal INIT so that its zero output is high and its one output is low. Similarly, the zero outputs of the other flip-flops of set 1000 are placed in their high states while the one outputs of said other flip-flops are placed in their low states. The zero outputs of all the D-type flip-flops of set 1000 are applied to NAND gate 1001 in FIG. 10A which in turn provides a low level signal to inserter 1002. The output of inverter 1002 becomes high thereby enabling the ST0 and D1 signals therefrom. The ST signals from flip-flop set 1000 in FIG. 10B are selectively applied to the other circuit blocks of FIG. 1 via line 181. These ST state signals are utilized to control the operation of the circuit of FIG. 1 in conjunction with the CL1 and CL2 clock signals from clock 190. Clock 190 comprises an arrangement of oscillators and timing circuits well known in the art which are operative to produce clock signals CL1 and CL2 illustrated in waveforms 1301 and 1303 of FIG. 13. The CL1 clock pulses shown in waveform 1301 are generated at a first predetermined repetition rate as shown in FIG. 3. The first CL1 clock pulse of waveform 1301 occurs between times t.sub.0 and t.sub.1. The second CL1 clock pulse occurs between times t.sub.10 and t.sub.11. In the interval between t.sub.1 and t.sub.10, clock 190 generates the regularly spaced sequence of seven CL2 clock pulses shown in waveform 1303. The CL2 clock pulses define the character positions of array 110 for each state time interval between two successive CL1 clock pulses. Assume for purposes of illustration that the INIT signal shown in waveform 1305 of FIG. 13 becomes high prior to time t.sub.N. At time t.sub.N in FIG. 13, each flip-flop of the flip-flop set 1000 in FIG. 10B is reset whereby the ST0 and the D1 signal from the output from inverter 1002 of FIG. 10A become high as illustrated in waveform 1307. The ST0 signal initiates the first directory search mode. The ST0 signal is utilized to initially reset storage devices in comparison logic 150, matched name logic and store 160, and candidate modified logic 170 which are shown in detail in FIGS. 7, 8 and 9, respectively. Referring to FIG. 8, the low ST0 signal supplied to one input of NAND gate 815 provides a high output therefrom. Upon the appearance of the high CL1 clock signal at time t.sub.10 of the state 0 time interval, NAND gate 817 is enabled and provides a low output to the clear input of match counter 821 whereby the match counter is reset to its zero state. As is well known in the art, a NAND gate provides a high output when at least one input thereto is low and provides a low output only when all its inputs are high. In FIG. 9, the high ST0 and CL1 signals enable gate 907 at t.sub.10 whereby counting latch 910 is reset to its zero state. Similarly, the high ST0 state and CL1 signals applied to NAND gate 952 at time t.sub.10 are operative to reset W counter latch 960 to its minus state. The low ST0 signal applied to gate 933 during the state 0 time interval provides a high input to NAND gate 935 whereby MI counting latch 940 is cleared to minus 1 at t.sub.10 by the CL1 clock pulse input to NAND gate 935. At time t.sub.11 the high D1 signal from inverter 1002 in FIG. 10A coincident with the negative transition of clock pulse CL1 in the state 0 time interval causes flip-flop 1001A in FIG. 10B to be set to its one state wherein the ST1 output is high and the ST1 output is low. The ST1 signal is shown in waveform 1311 of FIG. 13. Responsive to the ST1 signal doing high at time t.sub.11, the ST0 signal goes low, whereby the latch resetting operation of the state zero time interval is terminated. The low ST1 signal is applied via line 211 to the clear input of latch 213 in array 110 shown in detail in FIG. 2. The IP0 through IP7 output codes of latch 213 are thereby reset low preparatory to the later storage of the candidate word post numbers corresponding to the best candidate word in latch 213. In the ST1 time interval, the most probable candidate word zero, first and second position characters are available at the outputs of shift registers 205-0, 205-1 and 205-2, respectively as coded signals N0, N1 and N2. These characters (D, B, C) are inspected to determine whether they are all .phi.s. In the event these characters are .phi.s, a directory word sequence for comparison with the candidate word cannot be selected. The inspection is accomplished in comparison logic 150 shown in FIG. 7. Referring to FIG. 7, JP counter 780 which counts character positions in array 110 was previously cleared to its zero state by the low ST0 signal on gate 763 and the high CL1 pulse on gate 766 at the end of the state 0 time interval. The JP=0 output from counter 780 (waveform 1313) is applied to the control input of multiplexer 705 via multiplexer 701 in the absence of an ST15 control signal. The zero through seven position outputs of candidate array 110 from shift registers 205-0 through 205-7 are applied in parallel to the N(0) through N(7) inputs of multiplexer 705, respectively. Responsive to the JP=0 signal, the zero position character (D) from shift register 205-0 is selected and supplied via multiplexer 705 to one input of comparator 709. A .phi. code is supplied to the other input of comparator 709 from zero code generator 707, and the D character from array 110 is compared to the zero code from generator 707. Since they are not equal, the ZN output of comparator 709 is low. Consequently, no input pulse is applied to the CLK input of NST counter 718 via gate 715 during the first CL2 clock pulse of the state 1 time interval. During the state 1 interval, signal ST1 is high (waveform 1311) and the CL2 clock pulses applied to gate 745 in FIG. 7 pass through gates 745 and 748 to increment JP counter 780. Responsive to the first CL2 clock pulse (waveform 1303 at time t.sub.12), JP counter 780 is placed in its 1 state. The JP=1 signal beginning at time t.sub.12 causes the B character output of shift register 205-1 to be applied to the input of comparator 709. No high ZN signal is obtained from comparator 709 as a result of comparing the B character signal from shift register 205-1 with the zero signal from generator 707. The next CL2 clock pulse applied to gate 745 at t.sub.13 places JP counter 780 in its second state (waveform 1313); and the JP=2 pulse causes multiplexer 705 to connect the C character output of shift register 205-2 to comparator 709. No high ZN signal is obtained from comparator 709 as a result of comparing the second position character C of array 110 to the zero code from generator 707. During the state 1 time interval, a three signal from code generator 790 is applied to comparator 732 responsive to the high ST1 control signal applied to the control input of selector 794. When counter 780 reaches its third state, the output of comparator 732 inhibits gate 715 for the remainder of the state 1 time interval. Counter 718 is thereby prevented from counting any .phi. character in the third to seventh character positions of array 110. Since NST counter 718 does not change state responsive to the operation of counter 709 in the state 1 time interval, a high NST signal and a low NST signal are produced. If the zero, first and second position characters from array 110 were all .phi., NST counter would be in its third state so that a high signal NST would be enabled. The high NST signal from NST counter 718 (waveform 1314) is applied to one input of gate 1005 (FIG. 10A) in sequence control logic 180 via line 151. The coincidence of the high ST1 signal and the high NST signal causes gate 1009 to produce a high D2 signal. This D2 signal is supplied to the input of D-type flip-flop 1002A in FIG. 10B. On the occurrence of the negative transition of the state one interval CL1 pulse (time t.sub.21 in waveform 1301) flip-flop 1002A is set to its 1 state and flip-flop 1001A is reset to its 0 state. In this manner, the ST1 signal is waveform 1311 goes low at time t.sub.21, while the ST2 signal in waveform 1315 goes high. During the state 2 time interval between times t.sub.21 and t.sub.23, the zero position character (D) from array 110 is inspected to determine if it is a .phi. character. In the event this position character is .phi., an indirect directory range selection is made as described later. Range counter and decoder 436 in directory range selector 120 of FIG. 4 is reset by the state 2 time interval CL1 clock pulse on gate 434 at time t.sub.23. MI counting latch 940 in candidate modifier logic 170 of FIG. 9 is reset to its minus 1 state by the state 2 interval CL1 clock pulse on gate 935 at time t.sub.23 ; and match counter 821 in match name logic and store 160 of FIG. 8 is reset to its zero state by the state 2 interval CL1 clock pulse on gate 817 at time t.sub.23. The output of JP counter 780 is JP=0 in the ST2 time interval as shown in waveform 1313 since the counter was cleared responsive to the low ST1 signal input to gate 763 and the high CL1 clock pulse input to gate 766 at time t.sub.20 of the state 1 time interval. The JP=0 signal from the output of counter 780 is supplied to the control input of multiplexer 705 via multiplexer 701 in the state 2 time interval. Responsive to the JP=0 signal, multiplexer 705 connects the zero position character from shift register 205-0 (D) to the input of comparator 709 wherein it is compared to the zero code from generator 707. This is done to insure that an acceptable sequence of directory words is selected for the directory search by a direct access method. Responsive to the D character from multiplexer 705, comparator 709 produces a high ZN pulse. The high ZN signal is applied to gate 1011 (FIG. 10A) of sequence control logic 180 via line 151. Gate 1011 is enabled by the high ZN and ST2 signals whereby a high D3 signal is supplied from the output of inverter 1020 to flip-flop 1004A in FIG. 10B. The negative transition of the state 2 interval clock pulse CL1 at time t.sub.23 then causes flip-flop 1004A to be set and also resets flip-flop 1002A. In this manner, the high ST2 signal in waveform 1315 is terminated and the high ST3 signal in waveform 1317 is initiated at time t.sub.23. During the state 3 time interval between times t.sub.23 and t.sub.28, directory range selector 120 shown in detail in FIG. 4 is operative to determine the lower bound (NL) and the upper bound (NU) of a sequence of directory words responsive to the zero, first and second position characters of the most probable candidate word at the outputs of array 110. At time t.sub.23, JP counter 780 in FIG. 7 is in its zero state. The JP=0 output of counter 780 selects the zero position of array 110 from the output of shift register 205-0 and supplies the zero position character (D) to selectors 405 and 415 in FIG. 4 via multiplexer 705 in FIG. 7. The output of selector 405 is connected to the inputs of latches 407, 409 and 411 while the output of selector 415 is connected to the inputs of latches 418, 420 and 422. Range counter and decoder circuit 436 supplies clock signals to selectively enable these latches. At time t.sub.23, range counter 436 is in its zero state (waveform 1318) whereby signal CLa' is obtained therefrom. Latches 411 and 422 are enabled by the CLa' signal. The zero position (D) character from shift register 205-0 is inserted into latch 411 via selector 405 and is also inserted into latch 422 via selector 415. occurrence of the first CL2 clock pulse at time t.sub.24, signal RC is generated by gate 432 responsive to the low ST3 signal applied to gate 430 and the high CL2 pulse applied to gate 432. Range counter 436 is incremented to its first state by signal RC and clock pulse CLb' is generated. Latches 409 and 420 are enabled by the CLb' pulse. Signal RC is also supplied to the clock input of JP counter 780 via inverter 758. The JP=1 pulse from counter 780 causes the output of shift register 205-1 to be connected to the inputs of selectors 405 and 415 via multiplexer 705. The coded B character signal in this character position is thereby inserted into latches 409 and 420. The next CL2 clock pulse occurring at time t.sub.25 increments both range counter 436 and JP counter 780 to their second states as shown in waveforms 1313 and 1318, respectively. Consequently, the second position character C from shift register 205-2 is supplied to selectors 405 and 415 while the CLc' clock pulse is applied to latches 407 and 418. The C character signal from shift register 205-2 is thereby inserted into latches 407 and 418. In the event a zero character output is obtained from shift registers 205-1 or 205-2, selector 405 is responsive to the high ZN signal from comparator 709 to insert a "26" coded signal corresponding to a Z character into latch 207 and selector 415 is operative to insert a "1" signal corresponding to an A character into latch 418. At time t.sub.26, the upper bound signal NU corresponding to the characters DBZ is available from latches 411 and 409 and generator 406. Similarly, at time t.sub.26, the lower bound signal NL corresponding to the characters DBC is available at the outputs of latches 418, 420 and 422. Preparatory to the selection of the first directory word of the sequence defined by the lower bound and upper bound signals, key counter 507 (waveform 1325) in directory access logic 130, shown in FIG. 5, is cleared to its zero state responsive to the low ST3 signal applied to gate 508 and the high CL1 clock pulse occurring at t.sub.27 which is applied to gate 510. Directory access logic 130 in FIG. 5 is operative to select the addresses of the directory word sequence defined by the NL lower bound and NU upper bound signals from directory range selector 120. Where the zero position character of the candidate word is not .phi., the direct accessing arrangement utilizing K read-only-memory (ROM) 516 and D read-only-memory (ROM) 520 is employed. K read-only-memory 516 contains a list of selected directory words. Each location in memory 516 consists of the zero, first and second characters of the selected key directory words. The first location in K ROM 516 corresponds to the first directory word in directory store 140. The second location in K ROM 516 corresponds to the 128th directory word in the directory store. Similarly, the other locations in K ROM 516 correspond to spaced directory word entries in the directory store. K ROM 516 is used to select the first directory word of the sequence so that the first directory word is within a predetermined range, e.g., 128 words of the lower bound directory word defined by signal NL. D ROM 520 contains a list of directory word addresses for the directory store which addresses correspond to the key ROM 516 locations. Thus, once a key directory word is selected, the output of D ROM 520 may be utilized as the address of the first word of the directory sequence which is within 128 words of the lower limit signal NL. At time t.sub.28, the D4 signal from the ST3 output of control flip-flop 1004A in FIG. 10B sets control flip-flop 1006A whereby the ST4 signal shown in waveform 1319 is initiated. Control flip-flop 1004A is reset at this time responsive to the high ST4 signal in the state 4 time interval, multiplexer 512 in FIG. 5 connects the K(I) signal obtained from ROM 516 to one input of comparator 514. The lower bound signal NL from directory range selector 120 is applied to the other input of comparator 514. At this time, the zero, first and second characters of the first directory word location from K ROM 516 are compared to the corresponding characters of the lower bound NL signal from latches 418, 420 and 422. The high CL1 clock pulse applied to gate 505 between times t.sub.29 and t.sub.30 increments key counter 507 responsive to the NL signal applied to comparator 514 being greater than the K(I) signal applied thereto. Thus, at time t.sub.29, key counter 507 is placed in its first state as shown in waveform 1325. The second location K(I) signal is obtained from ROM 516 and this second location K(I) signal is compared to signal NL in comparator 514. Upon the occurrence of the next CL1 signal at time t.sub.31, key counter 507 is incremented to its second state and a new K(I) signal is supplied to comparator 514 from K ROM 516. Key counter 507 is successively incremented until it reaches its n.sup.th state at time t.sub.33 in waveform 1325. At this time, the K(I) signal accessed from key ROM 516 is less than the NL signal from directory range selector 120 so that corresponding directory address from D ROM 520 is less than the directory address corresponding to signal NL. Responsive to the NL signal to comparator 514 being less than or equal to the K(I) code from K ROM 516, signal NLGK is obtained from comparator 514 (t.sub.33 in waveform 1327). At this time, the address of the first word of the directory sequence as addressed by key counter 507 is available as signal D from directory address ROM 520. The D address signal is supplied to the input of directory pointer-counter 565 via multiplexer 580. The first directory address of the sequence is loaded into directory counter pointer 565 at time t.sub.35 responsive to the low ST4 signal on gate 556 and the high CL1 signal applied to the clock input of counter 565 via gates 558 and 563. The DR directory address from directory pointer 565 on line 190 (waveform 1329) is applied to address input 621 of directory 620. The DR address accesses the first character of the first directory word of the selected sequence. Directory address counter 615 is cleared to its zero state at time t.sub.35 by the high ST4 and CL1 signals applied to gate 609. Responsive to the low output of gate 609, gate 614 provides a high signal to the clear input of counter 615. As indicated in waveform 1331, the output of directory address counter 615 is zero between times t.sub.35 and t.sub.37. Responsive to the DR signal and the output of counter 615, the first character of the selected directory word is applied to multiplexer 629 at time t.sub.35 when the directory address counter 615 is cleared by the the state 4 CL1 clock pulse. Assume for purposes of illustration that the directory word from directory 620 is DAVISRH(27). The characters of this word appear in left to right sequence at the output of directory 620 responsive to the incrementing of counter 615 as indicated in waveform 1335. The D5 signal is generated in the state 4 interval responsive to the high NLGK and ST4 signals applied to gate 1021 in sequence control logic 180 shown in FIG. 10A. At time t.sub.36, control flip-flop 1008A in FIG. 10B is set, producing the ST5 signal of waveform 1333 and control flip-flop 1006A is reset by the negative transition of the CL1 pulse terminating the ST4 signal in waveform 1319. In this way, the state 4 time interval is terminated and the state 5 time interval during which the selected directory word of the sequence is placed in shift register 640 is initiated. At time t.sub.37, directory address counter 615 is incremented to its first state responsive to the high ST5 and CL2 signals applied to gate 605. Multiplexer 629 connects the directory output to the input of register 640 during the ST5 time interval responsive to the high ST5 signal applied to the control input of multiplexer 629 via gates 623 and 627. At time t.sub.37, the D character from directory 120 is inserted into the seventh position of shift register 640. At t.sub.38, counter 615 is incremented by the next CL2 pulse and the A character of the directory word is supplied to the seventh position of shift register 640 and is entered into this position under control of the shift pulse from gate 639 generated by the high ST5 and CL2 inputs to gate 633. Directory address counter 615 is successively incremented by the CL2 pulses during the state 5 time interval as shown in waveform 1331 to produce the sequence of characters indicated in waveform 1335. At time t.sub.40, the last character (27) from directory 620 is placed in the seventh position of shift register 640 by the leading edge of the CL1 pulse applied to inverter 624. The first three characters of the directory word, i.e., DAV, are also placed into latches 654, 656 and 658, respectively, during the state 5 time interval under control of LK counter 650 and decoder 652. Counter 650 is cleared to its zero state during the CL1 clock pulse terminating the state 4 time interval through gates 648 and 649. The zero output of LK counter 650 causes the CLA signal to be generated by decoder 652. Between times t.sub.35 and t.sub.37, the CLA pulse enables latch 654 so that the D character signal from the output of directory 620 is inserted therein by time t.sub.37. Responsive to the first CL2 pulse at time t.sub.37, LK counter 650 is incremented to its first state by gates 644 and inverter 646. The output of decoder 652 is changed so that the CLB signal enables latch 656 and the A character from directory 620 is stored in latch 656 by time t.sub.38. The CL2 clock pulse at time t.sub.39 increments counter 650 to its second state whereby latch 658 is enabled by signal CLC from decoder 652 and the V character from directory 620 is entered into latch 658. Gate 644 and decoder 652 are inhibited by the output on line 651 from counter 650 after it is in its second state. The sequential states of counter 650 are shown in waveform 1337. The outputs of latches 654, 656 and 658 form the LK signal, e.g. DAV, which is representative of the directory word in shift register 640. Comparator 660 compares the LK signal to the upper bound signal NU and thereby determines when the directory search sequence is completed. Until the directory sequence range is exceeded, signal LKGNU is obtained from comparator 660 in state 5 time intervals. The LKGNU signal is transmitted to gate 1029 (FIG. 10A) in sequence control logic 180 via line 142. Responsive to the high ST5 and LKGNU signals, gates 1029 and 1036 are enabled so that the D6 output from gate 1036 sets control flip-flop 1010A in FIG. 10B at time t.sub.41. The negative transition of the CL1 clock pulse at time t.sub.41 also resets control flip-flop 1008A. In this way, the ST5 signal (waveform 1333) is terminated and the ST6 signal (waveform 1339) is initiated at time t.sub.41. During the state 6 time interval, the candidate word DBCJ.phi.A(27).phi. at the N0 through N7 outputs of array 110 are compared to the directory word DAVISRH(27) in shift register 640. Preparatory to the comparison, JP counter 780 in FIG. 7 is cleared to its zero state at time t.sub.40 by the low ST5 signal applied to gate 763 and the high CL1 clock pulse applied to gate 766. The JP=0 signal from counter 780 causes the zero character position output from shift register 205-0 to be applied to comparators 709, 713 and 728 as shown in waveform 1341. The zero character position of the directory word at the output of shift register 640 is applied to comparators 713 and 730. Comparator 709 determines whether the applied position character from array 110 is a .phi. character. If it is a .phi. character, the character mismatch is ignored and a match is assumed. In this event the ZN output of comparator 709 is high and the ZN output is low. Comparator 713 determines whether the position character from array 110 matches the position character from shift register 640. If there is a match, signal NEL is high and signal NEL is low. Comparator 728 provides a high NE27 signal and a low NE27 signal if the character applied from shift register 640 is a coded "27" representative of the end of characters in the candidate word. Similarly, comparator 730 provides a high LE27 signal if the position character from array 110 is a "27" code representative of the end of characters in the directory word in shift register 640. If a "27" code is detected in comparator 728 after all preceding characters match or are ignored, the comparison operation of the state 6 time interval is successful and the address of the matching directory word is stored in matching name store range 160. Directory 620 also provides a coded NLS signal representative of the number of characters in the selected directory word. The NLS signal is compared to the JP signal from counter 780 in comparator 732 which produces a high JPENLS signal and a low JPENLS signal during the last character of the directory word. As indicated in waveforms 1341 and 1343, the zero position outputs of array 110 and shift register 640 is D. Consequently, a high NEL and a low NEL signal is obtained from comparator 713 as shown in waveform 1345 between times t.sub.40 and t.sub.42. Comparator 709 provides a high ZN output, comparator 728 provides a high LE27 output and comparator 730 provides a high NE27 output. Since the zero position characters of the candidate array and the selected directory word match, register 640 is shifted right one position upon the occurrence of the next CL1 pulse at time t.sub.42. Gate 635 provides a high output responsive to a low NEL signal from comparator 713. Gate 637 is enabled at time t.sub.42 and causes shift register 640 to be shifted one position. In the absence of an output from gate 627, the D character is shifted from the zero position of register 640 into the seventh position thereof and the first position A character appears at the output of register 640 as shown in waveform 1343 between times t.sub.42 and t.sub.44. The low NEL signal is also applied to gate 740 to enable gates 741 and 748 at time t.sub.42 whereby the JP counter 780 is incremented to its one state. Responsive to the JP=1 signal, the B character output from shift register 205-1 appears at the output of multiplexer 705 as indicated in waveform 1341. Since the A character coded signal from shift register 640 is not equal to the B character coded signal from array 110, comparator 713 provides a high NEL signal and a low NEL signal. Similarly, the ZN signal from comparator 709, the LE27 signal from comparator 728 and the NE27 signal from comparator 730 are high while ZN, LE27 and NE27 signals are low. Upon detection of a mismatch between the first position character of the candidate word and the first position character of the selected directory word, the mismatched position value is compared to the position value stored in MI counting latch 940 in FIG. 9 and the greater of the two is inserted therein. Referring to FIG. 9, the JP=1 signal from counter 780 in FIG. 7 is supplied to one input of comparator 970 via multiplexer 967. In the absence of a high ST7 signal or a high ST13 signal, multiplexer 967 connects the JP signal to comparator 970. The output of MI counting latch 940 which was previously reset to -1 is supplied to the other input of comparator 970. Since the JP=1 signal is greater than the MI=-1 signal from latch 940, the K output of comparator 970 becomes high and the load input to MI counting latch 940 is made high through enabled gate 912 and inverter 921. At the beginning of the next CL1 clock pulse at time t.sub.44, gates 923 and 925 are enabled whereby the JP=1 signal is loaded into counting latch 940 as indicated in waveform 1347. The high ZN, NEL, NE27, and LE27 signals are applied to gate 1043 (FIG. 10A) in sequence control logic 180 so that the D7 signal becomes high during the state 6 time interval. At time t.sub.45 control flip-flop 1011A in FIG. 10B is set and control flip-flop 1010A is reset so that the state 6 time interval is terminated and the state 7 time interval is initiated as shown in waveform 1349. In the state 7 time interval, the mismatched position MI is compared to the best mismatched position MMI previously stored in the current and preceding directory searches and the greater position value of MI and MMI is stored. In this manner, the best mismatched position store is updated. This is accomplished in candidate modifier logic 170 of FIG. 9 responsive to the ST7 control signal. Referring to FIG. 9, the state of multiplexer 967 is changed responsive to the high ST7 control signal at time t.sub.45 so that the output of MMI counting latch 910 is supplied to one input of comparator 970. The MMI output is compared with the MI output from MI counting latch 940 during the state 7 interval. A high signal K is obtained from comparator 970 since the MMI latch was previously reset to its -1 state as indicated in waveform 1351, and the MI latch is now set to its one state as indicated in waveform 1347. The high K signal from comparator 970 enables gate 903 at time t.sub.46 whereby the MI=1 signal is loaded into MMI counting latch 910 as indicated in waveform 1351. During the state 7 time interval, gates 1023 and 1025 are enabled by the coincidence of the ST7 and FL signals. The FL signal is produced in the preceding state 5 interval by a high ST5 signal applied to FL flip-flop 1035A in FIG. 10B. The high FL signal indicates that the directory store is accessed on the basis of the zero, first and second position characters. The high D5 output of gate 1025 is applied to the input of control flip-flop 1008A in FIG. 10B which is set at time t.sub.47. Control flip-flop 1011A is reset at this time and the state 5 time interval is reinitiated. The D5 signal from gate 1025 is also applied to gate 550 in FIG. 5. During the CL1 clock pulse between times t.sub.46 and t.sub.47, gates 550, 554, 561 and 563 are enabled whereby directory pointer counter 565 is incremented. In this manner, the next directory word of the sequence is selected from directory 620 during the preceding state 5 interval. In each succeeding state 5 interval of the directory search mode, the first character of the selected directory word in directory 620 is addressed by the DR signal from directory pointer counter 565 and the zero output of directory address counter 615. Multiplexer 629 connects the output of directory 620 to the input of shift register 640 under control of gates 623 and 627. Responsive to the CL2 clock pulses applied to gate 625 and the clock pulses applied to gate 626, the successive characters of the selected directory word are shifted into register 640. The zero, first and second position characters are latched into latches 654, 656 and 658, respectively, as previously described and the LK signal from these latches is compared to the upper bound signal NU in comparator 660. In the state 6 time intervals of the directory search mode, the characters of the selected directory word in shift register 640 are compared to the characters of the candidate word from array 110 in left to right order as described with respect to the first directory search. Upon detection of a mismatched character position MI, the detected mismatched position is compared to the mismatched position previously stored in MI counting latch 940. The greater position value is retained in MI counting latch 940. Thus, at the end of the directory search, MI counting latch 940 stores the greatest mismatched position value i.e., the rightmost first occurring mismatched position for the directory search sequence. This rightmost first occurring mismatched position corresponds to the closest mismatched word of the directory word sequence, that is, the directory word having the greatest number of successive matched characters. In the event the successive characters of the candidate word from array 110 match the successive characters of the directory word, address signal DR from directory pointer-counter 565 is inserted into matched name store 825 in FIG. 8. Comparator 732 compares the output of JP counter 780 to the NLS output of directory 620 since the NLS signal is applied to comparator 732 via selector 794 in state 6. The NLS signal represents the position of the last character of the selected directory word from store 620. During the comparison of the character of the candidate word with the last (NLS) character of the directory word from shift register 640, the JPENLS output of comparator 732 is a high signal. Since the compared last characters match and the previous characters matched, the NEL output of comparator 713 is high and the NEL output of comparator 713 is low. Gate 803 in the matched name logic and store of FIG. 8 is enabled by the low NEL signal from comparator 713. The high output of gate 803, the high JPENLS signal, and the high ST6 signal enable gate 810 during the next CL1 clock pulse Responsive to the high output of gate 810, gate 812 is enabled and match counter 821 is incremented since there is a high ST12 signal applied to the up/down input of counter 821. The write input to matched name store 825 is also enabled via inverter 819 so that the directory address DR of the matching directory word is inserted into the first position of store 825 as addressed by the output of match counter 821. Upon detection of a match in the last character position, the low NEL signal from comparator 713 is applied to gate 1015 in the sequence control logic of FIG. 10A. Responsive to the low NEL signal and the high JPENLS signal, gates 1015, 1016, 1017, 1019 and 1025 are enabled to provide a high D5 signal which terminates the state 6 time interval by resetting control flip-flop 1010A in FIG. 10B and initiates the state 5 time interval by setting control flip-flop 1008A at the negative transition of the next state 6 CL1 pulse. The next directory word from directory 620 may thus be accessed for comparison with the candidate word from array 110. Each selected directory word of the sequence is compared to the candidate word from array 110 as previously described. When the numerical values of the coded zero, first and second characters of the selected directory word placed into latches 654, 656 and 658, respectively, exceed the upper bound signal NU in a state 5 time interval comparator 660 produces a high LKGNU signal as shown in waveform 1353 at t.sub.48. In the example of Table 1, the upper bound signal NU from directory range selector 120 of FIG. 4 is DBZ. When the selected directory word generates an LK signal corresponding, for example, to DEC, the directory search mode is completed. If matching directory words were found during the preceding directory search, match counter 821 is in a nonzero state and zero code detector 828 provides a high ZM output. During the last state 5 time interval of the directory search, a high LKGNU signal appears at the output of comparator 660. The LKGNU signal from comparator 660 in FIG. 6 and the ZM signal from zero code detector 828 in FIG. 8 enable gate 1060 in the sequence control logic of FIG. 10A whereby a high D12 signal appears at the output of gate 1063. Responsive to the termination of the last state 5 interval CL1 clock pulse, control flip-flop 1019A in FIG. 10B is set and control flip-flop 1008A is reset. The directory retrieval mode in which the matching directory addresses are used to retrieve associated information from directory 620 is thereby initiated. Responsive to a low ST12 signal on the up-down input to match counter 821 during the state 12 time interval, the counter is set to decrement its state on the occurrence of a clock input signal. The clock signal is provided by gates 807 and 812 responsive to high ZM and CL1 signals during the state 12 interval. The last entered directory word address in match name store 825 is addressed by counter 821 and read out therefrom as address signal DR1, which address signal is supplied to address input 621 of directory 620 via directory pointer counter 565. At the end of the preceding state 5 interval, a low signal ST5 enabled gate 612; and, responsive to the state 5 interval CL1 signal applied to gate 613, directory address counter 615 was cleared to its zero state. Responsive to the DR address signal from directory pointer counter 565 and the output of directory address counter 615 which is successively incremented by the CL2 clock pulses applied via gate 607, the information associated with the matched directory word is retrieved from directory 620 and applied to speech synthesizer 680 via line 610. Speech synthesizer 680, as is well known in the art, is operative to produce a spoken output message signal which includes the information associated with the matched directory name. Such information, including the subscriber telephone number or subscriber address, is thereby transmitted to the inquirer via message interface 101. If there is more than one matching directory word match counter 821 is in a nonzero state and is decremented by the ST12 signal on gate 807 whose output is applied to the clock input of match counter 821 by CL1 clock pulses via gate 812. Responsive to the decremented address from counter 821, the next directory word address is read from matched name store 825 so that the information associated with this directory word is retrieved from directory 620. When match counter 821 is decremented to its zero state, zero code detector 828 produces a high ZM signal which is supplied to gate 1075 in the sequence control logic of FIG. 10A. Responsive to the coincidence of the high ST12 and ZM signals, gates 1075 and 1079 are enabled whereby control flip-flop 1023A is set and the state 14 time interval is initiated. The state 14 interval is repeatedly reinitiated by the low ST14 signal applied to gate 1079. The circuit of FIG. 1 remains in state 14 until the next request for subscriber information is initiated. Assume for purposes of illustration that there is no matching directory word detected in the first directory search. In this event, the candidate word is modified by substituting other probable characters from array 110. Since the closest mismatched word is mismatched in the first position, changes in positions to the right of the first position will not result in matching directory words. Therefore, in the first candidate word change mode, a probable character substitution is made in the first mismatched position if there are probable characters available in the first position. The candidate word change mode is entered by the initiation of the state 13 time interval. During the last state 5 interval of the first directory search, in which the LKGNU signal shown in waveform 1407 of FIG. 14 is generated in comparator 660, the ZM signal from zero code detector 828 (waveform 1409) in FIG. 8 is high. Responsive to the high ST5 (waveform 1403) LKGNU, and ZM signals, gate 1066 in sequence control logic 180 shown in FIG. 10A is enabled and a high D13 signal is obtained from the output of gate 1071. This D13 signal sets flip-flop 1021A in FIG. 10B producing a high ST13 signal upon the termination of the state 5 CL1 clock pulse (time t.sub.1 on waveform 1401 of FIG. 14). At this time, control flip-flop 1008A is also reset. In the initiated state 13 time interval, the mismatched position MI is 1 as shown for the first directory search in Table 2. This is so because the closest mismatched word found during the directory search is DAVISRH for the directory search candidate word DBCJ.phi.A. DAVISRH is also the best mismatched word whereby MMI counting latch 910 in FIG. 9 contains a 1. W counting latch 960 was previously reset to its -1 state. Responsive to the high ST13 signal on its control input, multiplexer 967 connects the output of W counting latch 960 to one input of comparator 970. The MI signal from latch 940 is supplied to the other input of comparator 970. Since the output of the W latch is -1 while the output of the MI latch is 1, a high MIEW signal (waveform 1413) is obtained by time t.sub.2 from the output of inverter 971 connected to comparator 970. Responsive to the 1 output from MI counting latch 940, -1 code detector 962 provides a high MIEN signal (waveform 1415). The high MIEN and MIEW signals enable gate 323 in the state 13 time interval whereby the MI=1 signal from latch 940 is supplied to the control inputs of decoder 319 via multiplexer 331. Responsive to the MI=1 signal, decoder 319 is operative to connect its input to line SJ1. During the CL1 clock pulse in state 13, gate 317 is enabled whereby a single shift pulse (waveform 1417) is applied to shift registers 205-1 and 206-1 via line SJ1 between times t.sub.2 and t.sub.3. In this manner, shift registers 205-1 and 206-1 are shifted one place to the right. The B character formerly at the output of register 205-1 is inserted into the seventh position of this register and the V character formerly in the first position of shift register 205-1 is shifted to the zero position and appears at the output of register 205-1. The post number corresponding to the B character, i.e., 1, now appears in the zero position of shift register 206-1 and at its output. In accordance with the invention, the character in the mismatched position of array 110 is replaced by the next most probable character therein in the absence of the detection of matching directory words in the preceding directory search. All other positions of the candidate word array remain unchanged. The MIEN and MIEW signals from candidate modifier logic 170 of FIG. 9 are also applied to gate 1083 in the sequence control logic of FIG. 10A via line 171. Responsive to the high MIEN and MIEW signals during the state 13 time interval, a high D15 signal appears at the output of inverter 1085. At the termination of the state 13 CL1 clock pulse (time t.sub.3 in FIG. 14), control flip-flop 1025A in FIG. 10B is set. Signal ST15 becomes high as shown in waveform 1419, and control flip-flop 1021A is reset. In this manner, the state 15 time interval is initiated during which the new available character at the output of shift register 205-1 of FIG. 1 is compared to .phi. from zero code generator 707 in comparator 709. The MI=1 signal from MI counting latch 940 of FIG. 9 is supplied to the control input of multiplexer 705 responsive to the high ST15 control signal from control flip-flop 1025A in FIG. 10B. The output of shift register 205-1 is thereby connected to one input of comparator 709. The output of multiplexer 705 is shown in waveform 1421. Since the output of shift register 205-1 is V at this time, comparator 709 produces a high ZN signal (waveform 1425) and low ZN signal. Flip-flop 787 is set by a high ZN signal applied to its level input and provides ZN1 and ZN1 signals. The high ZN1 signal from flip-flop 787 is applied to gate 1008 in sequence control logic 180 of FIG. 10A during this state 15 time interval since no high ZN signal was produced. Consequently, a high D2 signal (waveform 1425) is obtained from gate 1009. At the termination of the CL1 clock pulse of the state 15 time interval (t.sub.5 in FIG. 14), control flip-flop 1002A in FIG. 10B is set and control flip-flop 1025A is reset. At this time, the modified candidate word at the output of array 110 is DVCJ.phi.A as shown in column 7 of Table 2. The second directory search mode is entered by the initiation of the state 2 time interval. In the state 2 time interval of the second and the succeeding directory searches, MI counting latch 940 is reset to its minus 1 state so that the rightmost first occurring mismatched position of the new directory search may be determined and entered therein. Match counter 821 in FIG. 8 is also cleared to its zero state preparatory to the storage of detected matching directory word addresses in matched name store 825. MMI counting latch 910, however, is not reset since this latch stores the rightmost first occurring mismatch position of the best mismatched word of all preceding directory searches. In the second directory search, a new sequence of directory words is selected for the modified candidate word DVCJ.phi.A at the output of array 110 and each directory word of the sequence is compared to the modified candidate word as described with respect to the first directory search. In accordance with Table 2, no matching directory word is detected during the second directory search. Also, in accordance with Table 2, the closest mismatched word found during the second directory search is DVORAKDL. The rightmost first occurring mismatched position stored in MI counting latch 940 at the end of the second directory search is MI=2. The best mismatch word changes from DAVISRH to DVORAKDL and a best mismatch position MMI=2 is found for the latter word. The new best first mismatched position is stored in MMI counting latch 910. Upon reaching the upper bound NU of the second directory range in a state 5 time interval, a high LKGNU signal is produced by comparator 660 (waveform 1407 between times t.sub.5 and t.sub.6). The high ZM signal from zero code detector 828 and the high LKGNU signal from comparator 660 enable gate 1066 of FIG. 10A in this state 5 time interval so that a high D13 signal is produced by gate 1071. Upon the occurrence of the state 5 CL1 clock pulse at T.sub.6 control flip-flop 1021A in FIG. 10B is set to initiate the state 13 time interval of the second candidate change mode. Control flip-flop 1008A is reset so that the second directory search mode is terminated at this time. During the CL1 clock pulse of the state 13 of the second candidate word change mode, between times t.sub.7 and t.sub.8 in FIG. 14, shifted register 205-2 is shifted right one position by the shift pulse shown in waveform 1417. The C character at the output of shift register 205-2 is thereby replaced by the next available character, i.e., Z, since the mismatched position is the second position as previously described. The character Z at the output of multiplexer 705 (waveform 1421) is found not to be a .phi. character in the succeeding state 15 time interval of the second candidate word change mode between times t.sub.8 and t.sub.10. The modified candidate word formed in the second candidate word change mode is DVZJ.phi.A as shown in column 7 of Table 2. The third directory search mode is then initiated using the modified candidate word DVZJ.phi.A of column 2 of Table 2. As shown in Table 2, the closest mismatched word of the third directory search in which no matching directory words are detected is DVORAKDL. The MI mismatch position is 2 and the best mismatch position of all previous searches is 2. During the state 7 time interval just after the state 6 interval comparison of the candidate word DVZJ.phi.A with the directory word DVORAKDL, gate 208 in FIG. 2 is enabled by signal K since the MMI output of latch 910 applied to comparator 970 via multiplexer 967 is greater than the MI=1 output of MI counting latch 940. Responsive to the low output of gate 208, the post numbers at the outputs of registers 206-0 through 206-7 are inserted into latch 213. In this manner, the candidate word corresponding to the best mismatched word of the current and preceding directory searches may be accessed at a later time. The third directory search mode is terminated at the end of the state 5 time interval in which a high LKGNU signal is obtained from comparator 660. This state 5 time interval ends at time t.sub.12 in FIG. 14. In the first state 13 time interval of the third candidate word change mode (between times t.sub.12 and t.sub.14 in FIG. 14) the MI=2 signal is supplied to the control input of decoder 319 via multiplexer 331 as previously described. Since a high MIEN signal (waveform 1415) is obtained from detector 962 and a high MIEW signal (waveform 1413) is obtained from comparator 970, gate 317 supplies a shift pulse (waveform 1417 at time t.sub.13) to registers 205-2 and 206-2 via decoder 319 and line SJ2. The contents of shift registers 205-2 and 206-2 are thereby shifted right one position. The Z character at the output of shift register 205-2 is replaced by the first .phi. character at time t.sub.13 as indicated in waveform 1421 and the state 15 time interval is initiated at t.sub.14 as previously described. In the state 15 time interval between times t.sub.14 and t.sub.23, the MI=2 signal from MI counting latch 940 causes multiplexer 705 to connect the output of shift register 205-2 to one input of comparator 709. Since the .phi. character appears at the output of shift register 205-2 at this time, high ZN and low ZN signals are obtained from comparator 709. Flip-flop 787 is set by a high ZN signal from comparator 709 and a high ZN1 signal appears at its one output. The high ZN1 signal is applied to gate 321 which causes multiplexer 331 to pass the MI=2 signal from its input to the control inputs of encoder 307 and decoder 319. Encoder 307 is operative at this time to connect the output of shift register 206-2 to the input of gate 309. As long as the output of encoder 307 is a nonzero post number, gate 309 produces a high signal (waveform 1427 between times t.sub.14 and t.sub.18) which, in combination with the high ZN signal on gate 311 causes the successive CL2 clock pulses occurring during the state 15 time interval to be applied to the input of decoder 319. Decoder 319 connects its input to line SJ2 so that the six successive CL2 clock pulses between times t.sub.15 and t.sub.18 are applied from gate 311 to the shift control inputs of registers 205-2 and 206-2 in FIG. 2. The resulting shift pulses are shown in waveform 1417 and the characters at the output of shift register 205-2 are shown in waveform 1421. At time t.sub.13, the Z character at the output of shift register 205-2 is replaced by a .phi. character. The six .phi. characters are shifted between times t.sub.15 and t.sub.16. The C character is shifted to the output of register 205-2 at time t.sub.17 when the zero post number appears at the output of register 206-2. No more shift pulses are applied to registers 205-1 and 206-1 because gate 309 is inhibited by the zero post number from the output of shift register 206-2. At time t.sub.17, the most probable character of shift register 205-2, i.e., C, is in the zero position of shift register 205-2. In this way, the most probable character of the mismatched position of the candidate word is returned to the candidate word after all available characters in that position have been used for substitution in directory searches. The high ZN1 signal from flip-flop 787 is applied to gate 915 in FIG. 9 during the state 15 time interval. Gates 915 and 928 are enabled and, responsive to the CL1 clock pulse between times t.sub.22 and t.sub.23 during the state 15 time interval, a clock pulse is applied to MI counting latch 940 via gates 931 and 925. MI counting latch 940 is thereby decremented from its second state to its first state. The high ZN1 signal from flip-flop 787 is also applied to gate 1069A of the sequence control logic shown in FIG. 10A. Gate 1069A is enabled during the state 15 time interval whereby a high D13 signal is produced by gate 1071. The state 15 time interval is terminated upon the negative transition of the state 15 time interval CL1 pulse at time t.sub.23 and the state 13 time interval is reinitiated by the setting of control flip-flop 1021A in FIG. 10B responsive to the high D13 signal. During the reinitiated state 13 time interval between times t.sub.23 and t.sub.25 in which signal ST13 is high (waveform 1411), gate 323 is enabled by the high MIEN and MIEW signals from latch 940 and comparator 970. Responsive to the low output of gate 323 the MI=1 signal is supplied to the control input of decoder 319 via multiplexer 331. Gate 317 produces an output pulse during the CL1 clock pulse of this state 13 time interval between times t.sub.24 and t.sub.25, and the pulse from gate 317 (waveform 1417) is applied to shift registers 205-1 and 206-1 via line SJ1. The contents of shift registers 205-1 and 206-1 are shifted right one position. The V character formerly at the output of shift register 205-1 is inserted into the seventh position of this register and the E character from the first position of shift register 205-1 is inserted into the zero position thereof and appears at the register output. The post number corresponding to the E character, i.e., 2, appears at the output of shift register 206-1. The state 15 time interval is reinitiated at time t.sub.25 and the E character from shift register 205-1 is supplied via multiplexer 705 (waveform 1421 between times t.sub.25 and t.sub.27) to one input of comparator 709. Since the E character does not match the .phi. code from code generator 707, comparator 709 produces a high ZN signal between times t.sub.25 and t.sub.27. Flip-flop 787 is reset by the low ZN signal from comparator 709 and the ZN1 signal from flip-flop 787 enables gate 1008 in sequence control logic 180 of FIG. 10A so that a high D2 signal (waveform 1425) is generated by gate 1009. The state 15 CL1 clock pulse terminates the candidate word change mode by resetting control flip-flop 1025A in FIG. 10B at time t.sub.27. The fourth directory search mode is entered at this time by the setting of control flip-flop 1002A responsive to the high D2 signal and the state 15 CL1 clock pulse. The modified candidate word formed during the third candidate word change mode is DECJ.phi.A as shown in column 7 of Table 2. In the fourth directory search mode, a new sequence of directory words is selected responsive to the zero, first and second characters (DEC) of the modified candidate word. Each selected directory word of this sequence is compared to the candidate word DECJ.phi.A(27).phi. from array 110 as shown in FIG. 12; and the | ||||||