Subclass 506	Subclass 507	Subclass 508
Form filling

System for automatically processing and printing the contents and the format of a text

4028680

Abstract

An automatic text processing system, wherein a text is printed by a typewriter and simultaneously recorded line by line in corresponding blocks of a magnetic tape. The system automatically prints the address of the block in which each line is stored, whereby an operator can cause the system to print selected lines of the text by posting the corresponding addresses on the typewriter. The lines or paragraphs of a text can be cancelled or added and their succession can be changed, by posting the addresses of the lines which are to be cancelled, added or shifted in the text. The fair copy is then automatically printed with the lines justified according to a format selected by the operator. According to another embodiment the system can be used to automatically search the information recorded on the magnetic tape.

Claims

What is claimed is:

1. A system for automatically processing and printing the contents and the format of a text of lines of characters, the system comprising:

input means for developing character codes corresponding to desired characters to be entered into the system on a line-by-line basis;

printing means receptive of character codes for printing characters in character lines each line having a maximum predetermined length;

storage means receptive of character codes for storing each of the codes associated with entered character lines into one of a plurality of storage blocks and including means for reading out each storage block to apply the character codes therein to the printing means for the printing of same, each block having a cpacity for storing the code of one character line of said maximum predetermined length; and

actuatable control means associated with said input means for controlling the operation of said storage means and said printing means to effect the reading of character codes from the storage blocks and the printing of same by the printing means, said control code of a given storage block with the second service character code of said given storage block and character codes recordable in each block and for developing a first service character code corresponding thereto, means operable with said input means for controlling said storage means to store the first service character code in each of said blocks, means responsive to each character code entered by said input means in each character line for developing a second service character code for each block corresponding to the number of character codes entered in the associated line, first comparison means for comparing the first service character code with said second service character code and print control means responsive to said first comparison means for effecting the printing of said given storage block by said printing means when the first service character code thereof is equal to the second service character code thereof.

2. A system according to claim 1, wherein said means for developing said second service character code comprises counting means for counting the numbers of characters entered in each of said lines of characters and wherein said control means further comprises manually actuatable means for generating an end-of-line signal and transfer means responsive to said end-of-line signal for effective storage of said second service character into the block storing the line of characters entered before the actuation of said manually actuatable means.

3. A system according to claim 2, wherein said first comparison means has means for generating a second command signal when said first and second service character codes associated with a line are different and wherein said control means further comprises second comparison means enabled by said second command signal for comparing each character code of the line with the space character code and for generating a third command signal in correspondence with the successful comparison and means responsive to said third command signal for inserting a space character code adjacent to the space character code of the line which has caused the successful comparison, and means responsive to said third command signal for the incrementing of one unit second service character code associated with the line.

4. A text processing system comprising:

manual input means having means for entering textual information including character and space codes and means for entering a text justification command;

storage means for storing and reading the entered textual information on a line-by-line basis;

printing means for printing said entered textual information read from said storage means in different character lines, each character having associated therewith a width of at least one given unit width, said space codes including a unitary space code having associated therewith a width of one given unit width;

manually operable means for defining a predetermined line length corresponding to a total number of said given unit widths; and

a control unit comprising

means responsive to said text justification command for controlling said storage means to sequentially read the stored lines of text,

means for calculating the length of each read line as the total number of said given unit widths associated with each read line,

means for comparing each calculated length with said predetermined length,

means actuated by said comparing means, when a calculated length is less than said predetermined length for inserting in the corresponding line a number of unitary space codes adjacent to space codes of the corresponding line sufficient to equalize the two compared lengths, and

means responsive to said comparing means when a match occurs for controlling the printing of the corresponding line, whereby each printed line of the text has said predetermined length and the text is printed in a justified form.

5. A text processing system according to claim 4, wherein all of said characters have a width comprised of an equal number of given unit widths.

6. A text processing system comprising:

manual input means having means for entering textual information including character and space codes and means for entering a line centering command for a selected line of text entered into the system;

storage means for storing and reading the entered textual information on a line-by-line basis;

printing means for printing said entered textual information read from said storage means in different character lines, each character having associated therewith a width of at least one given unit width, said spaces codes including a unitary space code having associated therewith a width of one given unit width;

manually operable means for defining a predetermined line length corresponding to a total number of said given unit widths; and

a control unit comprising

means responsive to said line centering command for calculating the length of said selected line as the total number of said given unit widths associated with the character and space codes of the selected line,

means for comparing said calculated length with said predetermined length,

means actuated by said comparing means when said calculated length is less than said predetermined length for inserting a number of pairs of unitary space codes in said selected line sufficient to equalize the two compared lengths, wherein one unitary space code of each pair is inserted at the beginning of said selected line and the other unitary space code of each pair is inserted at the end of the selected line, and

means responsive to said comparing means when a match occurs for controlling the printing of said selected line, whereby said selected line is printed centered with respect to said predetermined line length.

7. A text processing system as in claim 6, wherein all said characters have a width comprised of an equal number of given unit widths.

8. A system for automatically processing and printing the contents and the format of a text of lines of characters, the system comprising:

input means for developing character codes corresponding to desired characters to be entered into the system on a line-by-line basis and comprising means for generating a centering command,

printing means receptive of character codes for printing characters in character lines each line having a maximum length;

storage means receptive of character codes for storing each of the codes associated with entered character lines into one of a plurality of storage blocks and including means for reading out each storage block to apply the character codes therein to the printing means for the printing of same, each block having a capacity for storing the code of one character line of said maximum predetermined length; and

control means associated with said input means for controlling the operation of said storage means and said printing means, said control means comprising means responsive to said centering command for a given line for effecting the reading of the associated storage block by said reading means and developing at least one space character code dependent in number upon the number of character codes in the associated storage block and means for effecting insertion of the space character code at the beginning of said given line of character codes to shift all the character codes of said given line to the right

and including means for effecting the printing of the shifted line by the printing means to obtain a centered line of print.

9. A text processing system comprising:

input means for entering character signals and a pair of underlining control signals into the system;

storage means receptive of the signals from said input means for storing the signals and including means for reading out in a predetermined sequence, the signals stored therein;

serial printing means including a printing unit, means for moving said printing unit with respect to a printing medium to define a printing line, means receptive of the character signals read from said storage means for controlling said printing unit to print character symbols corresponding to said character signals and actuatable means receptive of the underlining control signals read from said storage means for said printing unit to print underlining symbols;

control means for effecting the reading out of character codes from said storage means to effect a first scan by the printing unit;

first means operative during a first scan of the printing unit along a printing line and receptive of signals read by said reading means for feeding the read character signals to the printing controlling means to effect the printing of a line of character symbols;

second means operative during said first scan and responsive to the read underlining control signals for controlling said moving means to effect at the end of the first scan a second scan of the same printing line; and

third means operative during said second scan and receptive of the read underlining control signals from said storage means for actuating said actuatable means included in said printing means upon receiving one of said underlining control signals and for deactuating said actuatable means upon receiving the other of said underlining control signals.

10. A text processing system comprising:

input means for entering lines of textual information into the system including a succession of character signals and for entering a pair of underlining control signals;

storage means receptive of the signals from said input means for storing lines of textual information and for storing one of said underlining control signals in correspondence with the beginning of the portion of a line of text to be underlined and the other underlining control signal at the end of the portion to be underlined and including means for sequentially scanning the stored character and underlining control signals of a line and means for reading out character and underlining control signals;

serial printing means including a printing unit, means for moving said printing unit with respect to a printing medium to define a printing line, means receptive of the character signals read from said storage means for controlling said printing unit to print character symbols corresponding to said character signals and actuatable means receptive of the underlining control signals read from said storage means for controlling said printing unit to print underlining symbols;

control means for effecting the reading out of character codes from said storage means to effect a first scan by the printing unit;

first means operative during a first scan by said printing unit of a line for controlling said scanning and reading means to scan and read a line of text to be printed;

second means operative during the first scan of the printing unit along a printing line and receptive of signals read by said reading means for feeding the read character signals to the printing controlling means to effect the printing of a line of character symbols;

third means operative during said first scan and responsive to the read underlining control signals for controlling said moving means at the end of the first scan to effect a second scan of the same printing line;

fourth means operative during said second scan for controlling said scanning means to effect another scan of the signals of the line to be printed and for actuating said reading means; and

fifth means operative during said second scan and receptive of the read underlining control signals from said reading means for actuating said actuatable means included in said printing means upon receiving one of said underlining control signals and for deactuating said actuating means upon receiving the other of said underlining control signals, whereby the portion of the printed line defined by character signals included between the two underlining control signals is underlined.

11. A text processing system comprising:

input means for entering a line of textual information into the system including character signals and a pair of underlining control signals;

storage means receptive of the signals from said input means for storing the line of textual information signals and including means for sequentially scanning the stored signals of a line and means for reading the signals out;

serial printing means including a printing unit, means for moving said printing unit with respect to a printing medium to define a printing line, means receptive of the character signals read from said storage means controlling said printing unit to print character symbols corresponding to said character signals and actuatable means receptive of the underlining control signals read from said storage means controlling said printing unit to print underlining symbols;

control means for effecting the reading out of character codes from said storage means to effect a first scan by the printing unit;

first means operative during a first scan by the printing unit of the line for controlling said scanning and reading means to scan and read the line of text;

second means operative during a first scan by the printing unit of the line for controlling said scanning and reading means to scan and read the line of text;

second means operative during the first scan of the printing unit along a printing line and receptive of signals read by said reading means for feeding the read character signals to the printing controlling means to effect the printing of a line of character symbols;

third means operative during said first scan and responsive to the read underlining control signals for controlling said moving means at the end of the first scan to effect a second scan of the same printing line;

fourth means operative during said record scan for controlling said scanning means to effect another scan of the signals of said line and for actuating said reading means; and

fifth means operative during said second scan and receptive of the read underlining control signals from said reading means for actuating said actuatable means included in said printing means upon receiving one of said underlining control signals and for deactuating said actuating means upon receiving the other of said underlining control signals.

12. A text processing system comprising:

input means for entering a line of text information into the system including a succession of character signals and a line underlining control signal;

storage means fed by said input means for storing said signals and

including means for reading them out in a predetermined sequence;

serial printing means including a printing unit, means for moving said unit with respect to a printing medium to define a printing line, means receptive of character signals read from said storage means for actuating said printing unit to print character symbols corresponding to said character signals, and actuatable means for controlling said printing unit to print underlining symbols;

control means for effecting the reading out of character codes from said storage means to effect a first scan by the printing unit;

first means operative during a first scan of the printing unit along a line and fed by said reading means for supplying the read character signals to the printing controlling means whereby a line of character symbols is printed;

second means operative during said first scan and responsive to said read line underlining control signal for controlling said moving means to effect a second scan of the same line after the end of said first scan; and

third means operative during said second scan for actuating said controlling means included in said printing means to underline said same line.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a text processing system having the feature of automatically printing a prerecorded text according to format control information predefined by the operator.

More particularly, the invention refers to a text processing system having the features of automatically printing lines of text justified with respect to a predetermined length selected by the operator, of automatically centering titles with respect to this selected length and of automatically underlining selected portions of the text.

These features allow the operator to record a draft text without controlling the justification of the text, to enter titles, and to underline portions of the text without backspacing during the recording of the same as is known from prior art machines.

In particular for the underlining feature typewriting machines that are automatically operated by a punch tape on which a text is recorded are known in the art and are disclosed in patents such as U.S. Pat. Ser. No. 2,093,581. In this type of machine, on the same punch tape there are recorded at the beginning and at the end of the next portions to be underlined, two respective underline control codes.

When the machine reads the first control code at the beginning of the portion to be underlined, it stops the escapement of the carriage after the printing of each character and commands the printing of the underlining symbol. After the printing of the underlining symbol, it advances the carriage one character step. When the machine reads the second underlining control code at the end of the portion to be underlined, it resumes the usual control of the carriage escapement.

Clearly this machine has the disadvantage of requiring a special device for controlling the escapement of the carriage during the underlining operation.

The main disadvantage of this machine is however its very slow printing speed due to the particular method of underlining used. In fact, this method requires that at the portion to be underlined, the carriage is stopped for a time sufficient to print a character and an underline symbol in the same position through two consecutive steps. This method cannot be used in the text processing system using a high speed output printer.

A typewriting system with a word underscore control in which the operator records on the text on a magnetic card is known in the art and is described in U.S. Pat. Ser. No. 3,630,336. In this system when it is desired to underline a word, the operator firstly enters the word to be underlined and then records an underlining symbol.

During the automatic printing operation, the symbol is recognized after the printing of the word and causes the printing unit to backspace to the beginning of the word. After this, the printing unit underlines each character of the word and then it resumes the normal printing mode until the next underlining symbol is recognized. Clearly this system has the disadvantage of permitting the automatic underlining of only single words at a time and never groups of words, such as phrases, in one operation.

In fact, to underline a phrase the operator must insert the underlining symbol at the end of each word of it. Moreover, this system does not permit the underlining of spaces between two words to be underlined.

SUMMARY OF THE INVENTION

An object of the present invention is therefore to provide a text processing system having the capability for automatically underlining portions of prerecorded text at high speeds.

Another object of the present invention is to provide a text processing system for automatically underlining portions of a line irrespective of the word spaces contained in the portion of the line.

Still another object of the present invention is to provide a text processing system having serial printing means and which automatically underlines portions of a line in which the entire line comprising the portion to be underlined is printed during one scan of the printing means and the portion to be underlined is then underlined during a second scan of the same line by the printing means.

Yet another object of the invention is to provide a text processing system having the feature of automatically printing lines of prerecorded text justified with respect to a predefined line length selected by the operator.

A further object of the invention is to provide a text processing system having the feature of automatically centering titles with respect to a predetermined line length.

BRIEF DESCRIPTION OF THE DRAWINGS

These characteristics and other characteristics of the invention will become clearer from the following description of a preferred embodiment given by way of example, but without restriction, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a printing system according to the invention;

FIG. 2 is a block diagram of the central unit of the system of FIG. 1;

FIG. 3 is a block diagram of a timing circuit of the central unit of FIG. 2;

FIG. 4 is a diagram of the timing signals generated by the circuit of FIG. 3;

FIG. 5 shows a circuit for generating the working states of the central unit of FIG. 2;

FIGS. 6-12 show the command circuits corresponding to an equal number of working states of the unit of FIG. 2;

FIG. 13 shows an input circuit of the central unit of FIG. 2;

FIG. 14 is a block diagram of a control unit for the input and output devices of the system of FIG. 1;

FIG. 15 shows a length of magnetic tape of the system of FIG. 1;

FIG. 16 shows a detail of the tape of FIG. 15;

FIG. 17 is a block diagram of the control unit of the device for recording and reading the magnetic tape of the system of FIG. 1;

FIG. 18 is a flowchart of the operation of the control unit of FIG. 17;

FIGS. 19 and 20 are flowcharts of the loading of instructions in the system of FIG. 1;

FIG. 21 is a flowchart relating to the recording of a text;

FIG. 22 is a flowchart relating to the modifications of format of a text;

FIG. 23 is a flowchart relating to the correction of a line of the text;

FIG. 24 is a flowchart relating to the printing of a text;

FIG. 25 is a flowchart relating to the justification of a line of a text;

FIG. 26 is a flowchart relating to the recording of the format of a file;

FIG. 27 is a flowchart relating to the recording of a file;

FIG. 28 is a flowchart relating to the amendment of the file;

FIG. 29 is a flowchart relating to the search for a document;

FIG. 30 is a block diagram of a second embodiment of a system according to the invention; and

FIG. 31 is a flow chart of the functions of FIG. 30.

    ______________________________________
    INDEX TO THE DESCRIPTION
    ______________________________________
    INTRODUCTION                PAGE 9
    CENTRAL UNIT                "  10
    EXECUTION OF INSTRUCTIONS   "  26
      1st Group of Instructions "  27
      2nd Group of Instructions "  36
      3rd Group of Instructions "  39
      4th Group of Instructions "  45
    INTERRUPT                   "  49
    TYPEWRITER CONTROL UNIT     "  54
    COMMAND KEYBOARD CONTROL UNIT
                                "  58
    MAGNETIC TAPE STORE CONTROL UNIT
                                "  59
    INTRODUCTION OF THE INSTRUCTIONS INTO THE
                                "  67
    CENTRAL UNIT
    RECORDING A TEXT            "  73
    AMENDING A TEXT             "  85
    CORRECTION OF WORDS         "  90
    PRINTING OF A CORRECTED TEXT
                                "  93
    1st EXAMPLE OF OPERATION    "  101
    RECORDING THE FORMAT OF A FILE
                                "  105
    RECORDING A FILE            "  109
    AMENDING A FILE             "  113
    SEARCHING FOR DOCUMENTS     "  115
    2nd EXAMPLE OF OPERATION    "  121
    SECOND EMBODIMENT           "  128
    ______________________________________

DESCRIPTION OF A PREFERRED EMBODIMENT - INTRODUCTION

The automatic printing system according to the invention comprises a central unit 5 (FIG. 1) having a processing unit 39 and a core store 42. The unit 5 is connected to a group of peripheral units including a typewriter 6, a magnetic tape store 7 and a command keyboard 8. The typewriter 6 is connected to the central unit 5 through a control unit 9, which controls the transmission of the commands and data between the typewriter 6 and the central unit 5.

The typewriter 6 is of known type and comprises an input/output device 12 adapted to encode and decode the characters coming from the central unit 5 and to transmit the relevant commands to the typewriter 6, which may be of any known type.

The typewriter 6 is the input/output device of the central unit 5. In fact, by means of the typewriter 6 it is possible both to enter texts and transmit them to the store 42 of the central unit 5, and to select the processing operations to be carried out by means of the automatic printing system, and to print the processed texts in their final form, as will be seen hereinafter.

The magnetic tape store 7 is also connected to the central unit 5 through a control unit 10. The store 7 contains all the instructions for controlling the printing system, which from time to time are selected and transferred to the store 42 of the central unit 5, and moreover contains the magnetic recording of the texts which are entered by means of the typewriter 6. These texts can be retrieved from time to time by the operator and placed in the central unit 5 for the purpose of being printed by the typewriter 6.

The command keyboard 8 is connected to the central unit 5 through another control unit 11 and comprises a plurality of keys each associated with a particular group of instructions of the system. By means of these keys it is therefore possible to select the corresponding group of instructions without making use of the typewriter 6.

Firstly, the text to be processed is entered on the typewriter 6, which at the same time prints of the text itself and transmits the latter, through the input/output device 12 and the control unit 9, to the store 42 of the central unit 5. From here the text is transferred through the control unit 10 to the tape store 7 to be recorded. The operator can now amend or modify this text both by adding or removing lines or paragraphs, and by modifying the length of the lines and by correcting typing errors. To effect these operations, the operator selects through the typewriter or of the command keyboard 8 that group of instructions which corresponds to the change he intends to make.

Each group of instructions is identified by a label, consisting for example of four letters, so that it can be easily picked out. In consequence of this operation, the selected group of instructions is transferred from the tape store 7 to the store 42 of the central unit 5 to become operative. The central unit 5, carrying out the selected instructions, therefore processes the text and then transfers it to the tape store 7. The text is thus recorded in the desired form to be then printed by the typewriter.

The operations described hereinbefore are carried out by means of the execution of a set of instructions which are recorded in the tape store 7.

CENTRAL UNIT

The central unit 5 includes a timing circuit or timer 20 (FIG. 2) for generating the timing signals necessary for the flow of the data within the central unit 5 itself. The timer 20 an oscillator 21 (FIG. 3) which supplies a signal C of frequency 6 MH.sub.z (FIG. 4). This signal acts on a shift register 22 (FIG. 3) formed by six flip-flops F1 - F6, which performs its entire cycle in twelve periods each with a duration of 2 .mu.s. The output signals of the six flip-flops F1 - F6 are shown in FIG. 4 and are indicated by the references T1 - T6, respectively. To obtain the signals required for timing, the outputs of the six flip-flops F1 - F6 are coupled to one another through the medium of gate circuits the outputs of which constitute the timing signals of the central unit 5.

For example, for the purpose of obtaining a signal TS, the flip-flop F1 is coupled with the flip-flop F3. More precisely, through an inverter 23 (FIG. 3) the direct output of the flip-flop F3 is applied to one input of an AND gate circuit 24, while on the other hand the output of the flip-flop F1 is applied to the other input of the circuit 24. The output TS of the circuit 24 will therefore be at level "1" when the outputs of the flip-flops F1 and F3 have the values 1 and 0, respectively. It will be at level "0" in the other cases. It is therefore clear that by suitably coupling the outputs of the other flip-flops F1 - F6 all the other timing signals shown in FIG. 4 can be obtained.

The central unit 5 moreover comprises a register 30 (FIG. 2) with a capacity of three bits and composed of three flip-flops. The register 30 is provided with three inputs 30a, 30b and 30c which are respectively connected to the typewriter 6 (FIG. 1), to the external store 7 and to the operative keyboard 8. The register 30 (FIG. 2) is moreover provided with three outputs 31a, 31b and 31c which constitute an equal number of inputs for a logic circuit 31 adapted to force into a register 32 with a capacity of eight bits the code of an eight-bit character indicating the peripheral unit which has activated the corresponding input 30a, 30b or 30c of the register 30.

More precisely, during the execution of an instruction by the central unit 5, a peripheral unit 6, 7 or 8 can interrupt this execution to transmit data or instructions to the central unit 5. To this end, the peripheral unit 6, 7 or 8 then activates the corresponding input 30a, 30b or 30c of the register 30, and therefore the input 31a, 31b or 31c of the logic circuit 31, which supplies the corresponding eight-bit character.

Moreover, in the event of two peripheral units activating the respective inputs 31a, 31b and 31c at the same time, the logic circuit 31 is adapted to select from the two peripheral units the one which has precedence over the other and supplies as output a configuration of eight bits corresponding to this unit in accordance with a given priority order. To this end, the logic circuit 31 is constituted substantially by a combinatory network with three inputs and eight outputs. The voltage values of the eight outputs selectively constitute the configuration of eight bits corresponding to each of the inputs 30a, 30b and 30c.

The three inputs 31a, 31b and 31c are moreover connected to the logic circuit 31 in such manner that each of them can condition the corresponding combination of eight bits only if the input of higher order of priority is at zero level, in a manner known per se. For example, the input 31b can activate as output from the logic circuit 31 the combination of eight bits associated therewith only if the input 31a is at level "O". This obviously entails the input 31a having precedence over the input 31b. The same also applies to the input 31c compared with the input 31b.

As has been said, the outputs of the logic circuit 31 constitute as many inputs for the register 32. The outputs of the register 32 are connected through a channel 33 to a reset logic circuit 34. This last-mentioned circuit has three outputs 34a, 34b, 34c each associated with a combination of eight bits transmitted to the circuit through the channel 33 from the register 32, so that the reset logic circuit 34 activates the output corresponding to the combination of eight bits present on the channel 33.

Each of the outputs 34a, 34b and 34c is connected to a corresponding reset circuit for the three flip-flops forming the register 30, so that when one of these outputs is activated the corresponding flip-flop of the register 30 is zeroized. In this way, if two signals are present at the same time as input to the register 30, for example at the inputs 30a and 30b, the logic circuit 31 forces into the register 32 an eight-bit character corresponding to the peripheral unit of a higher order of priority, that is to the typewriter 6, which is associated with the input 31a. Consequently, this character is transmitted through the channel 33 to the logic circuit 34, which activates only the output 34a corresponding to the typewriter 6. The flip-flop of the register 30 corresponding to the peripheral unit of higher order of priority is therefore zeroized, that is the flip-flop connected to the input 30a. In this way, after the operations connected with the peripheral of higher order have been effected, the flip-flop of the register 30 corresponding to the peripheral of less high order of priority remains activated, that is the flip-flop connected to the input 30b. There is therefore forced into the register 32 the eight-bit character corresponding thereto, after which the operations previously described are repeated, so that the peripheral units are taken into consideration by the central unit 5 always in accordance with the predetermined order of priority.

The outputs of the register 32 are moreover connected through a channel 40 to another register 41 completely identical to the register 32 and forming an input register of the core store 42. The character stored in the register 41 is transferred through a channel 43 to a counting network 44, the operation of which is known and which is adapted to increment by one unit the character introduced into it through the channel 43. The outputs of the counting metwork 44 are connected in turn to the inputs of the register 32. In this way, the contents of the register 41 are incremented by one unit whenever a configuration of eight bits is forced into it through the channel 40. As will be better explained hereinafter, this enables the cells of the store 42 in which the data or the instructions of the programme in process of development are contained to be accessed sequentially.

The bits contained in the input register 41 are also transferred to an address decoding network 45 of the store 42. On the basis of the configuration of the eight bits present in the register 41, the decoding network 45 is adapted to select one of the cores of the store 42. The core store 42 has a capacity of 1024 eight-bit characters and is divided into four zones, called pages, each with a capacity of 256 characters. Each page is identified by a code number, these being 0, 1, 2 and 3, respectively. For identifying a cell of the store 42, ten bits are therefore necessary, that is two for identifying the page and eight for identifying a cell in the compass of the identified page.

The store 42 comprises eight like core matrices disposed in eight planes. Each core matrice is formed of thirty-two rows and thirty-two columns for a total of 1024 cores, so that each matrix has a capacity of 1024 bits. As is known, each core of the store 42 is traversed by four conductors: a write or inhibit conductor, a read or sense conductor and two addressing conductors. More particularly, each inhibit or sense conductor passes serially through all the cores in each plane and there are therefore eight sense and eight inhibit conductors. The two addressing conductors, on the other hand, are disposed at right angles and intersect in a corresponding core. Each addressing conductor passes serially through all the cores disposed in the same row and the same column of the eight matrices. More precisely, the addressing conductors associated with the first row and the first column of a core matrix pass serially through all the cores of the eight planes disposed in the first row and in the first column of each matrix. There are therefore in all thirty-two pairs of addressing conductors.

The decoding network 45 may be a combinatory network of any known kind and is therefore not described in detail. More particularly, the decoding network 45 has eight input conductors, to which the signals present in the register 41 are applied, and thirty-two outputs which are connected in order to the thirty-two pairs of addressing conductors. Each core is selected when the two addressing conductors which intersect in it are activated at the same time. Each pair of addressing conductors is energized in correspondence with a particular configuration of the signals present on the eight input conductors of the decoding network 45, thus selecting a corresponding group of eight cores which are brought to the O state. In order to introduce the information coming from one of the peripheral units 6, 7, 8 into a core of the store 42 which is selected in this way, these peripherals are connected through a channel 46 formed by eight conductors to the input of a store input logic circuit 47 hereinafter described. The output of this logic circuit 47 is formed by eight conductors forming a transmission channel 48. These conductors are connected to the corresponding inhibit conductors of each of the eight matrices of the store 42.

Over the inhibit conductors corresponding to those cores in which it is desired to write a O there is sent a current such as not to cause the switching or change of state of the selected core, whereas on the conductors corresponding to those cores in which it is desired to write a 1 the change of state is effected in known manner.

Similarly, in order to read the information recorded in the cores, the logic circuit 47 sends to the pair of addressing conductors a current opposite to that sent during the writing, so that there will be a change-over only in the cores in which a O was recorded. There will therefore be an induced voltage only in the sense conductors passing through a core in which a O was recorded. The eight sense conductors are connected through the medium of an output channel 49 of the store 42 to an output register 50. The information read in the store 42 and recorded in the output register 50 may have different significances. In fact, it may relate to data which are to be transmitted to the peripheral units 6, 7, 8 or to store addresses which are to be used thereafter, or to data which are to be temporarily stored to be then compared with other data read in the store 42 or transferred to other addresses in the store 42, or to codes of the instructions which are to be executed by the central unit 5 during the carrying out of a set of instructions.

To this end, the register 50 is connected through a channel 51 to the peripheral units to transmit to them the data read in the store 42. The register 50 is moreover connected through a channel 55 to the register 41 to force into the same the store address which is to be used next. The register 50 is moreover connected through a channel 56 to an eight-bit register 57 to force into the same the data which are to be temporarily stored. Finally, the register 50 is connected through a channel 58 to another eight-bit register 59 for forcing into the same the codes of the instructions. The data which are to be temporarily stored in the register 57 may come, apart from the register 50, also from the register 32. To this end, the output of the register 32 is connected through a channel 66 to the input of the register 57.

The register 59 is connected through an output channel 60 to a decoding network 62 which has thirteen outputs 62.sub.1 to 62.sub.13, each one associated to an instruction used by the central unit 5. The decoding network 62 is a combinatory network of the type described in regard to the circuit 31.

As will be better explained hereinafter, each instruction is identified by an eight-bit code. The first four bits of the code distinguish an instruction from the remaining twelve, the second four bits constitute the so-called "address modifier", the significance of which will be seen hereinafter.

The network 62 activates from among the thirteen output conductors the one corresponding to the instruction expressed by the four-bit code present on the channel 60. The outputs 62.sub.1 to 62.sub.13 of the decoding network 62 command a command logic unit 63 which supplies, in the manner to be described, a series of commands indicated hereinafter by the symbols COM01 . . . COM27, which control the transfer of the data within the central unit 5. More particularly, these commands actuate the gate circuits indicated in FIG. 2 by a circle, therefore permitting the transfer of the information along the transmission channel in which these circuits are inserted, from one register to the other or from the store 42 (FIG. 2) to one of the registers 50, 57, 59 connected to it, thus executing the respective instructions.

In FIG. 2, near each gate circuit there is indicated its particular actuating command. For example, the command COMO1 actuates a gate circuit 64 which allows the transfer of the contents of the register 32 through the channel 40 to the register 41.

The register 59 is divided into two parts each formed of four flip-flops. To the first four flip-flops there are sent the first four bits of the code of the instructions which define the type of instruction. The outputs of these flip-flops are grouped together in the channel 60. To the second four flip-flops of the register 59 there are sent the bits constituting the modifier. The outputs of these flip-flops are grouped together in another channel 61.

The bits of the modifier have a different significance according to the type of instruction. More precisely, the bits of the modifier can identify one of the peripheral units 6, 7, 8, to which is directed a message, or a command expressed by the instruction, or the store page to which a given address belongs. Moreover, the bits of the modifier can indicate that an address or a datum is to be incremented by one unit.

In the first case, the bits of the modifier are present on a channel 64' and are used by a decoding network 65 of the same type as the network 62, which selects the peripheral unit on the basis of the contents of the modifier activating one of its three outputs 65.sub.1, 65.sub.2, 65.sub.3. In this way, through the channel 51, the decoding network connects the register 50 with the selected peripheral unit for the transfer of the data between the central unit 5 and the selected peripheral unit.

When the bits of the modifier indicate a store page, the gate circuit 121 is activated by the command logic unit 63, as a result of which the first two bits of the modifier are sent through a channel 70 to a register 71 with a capacity of two bits, which thus stores the address of the page of the store 42. The contents of the register 71 and those of the register 41 form a complete store address which, as already seen, is formed by ten bits which define the 1024 cells of the store 42. The contents of the registers 71 and 41 may be varied or statiticized independently of one another, since the bits forced separately into the two registers 59 and 32 are sent to them through the respective channels 70 and 40. This possibility, for example, enables the data to be addressed by keeping the contents of the register 71 constant. The number of the page can also be directly introduced into the decoding logic network 45 through a channel 72, as will be seen hereinafter. The command logic unit 63 is also adapted to be conditioned by the bits of the modifier which are staticized in the register 59 and transmitted to it by means of a channel 75. A conductor 76 moreover connects the logic circuit 31 to the command logic unit 63. In this way, every time a peripheral unit 6, 7, 8 causes an interruption, activating one of the flip-flops of the register 30, the logic circuit 31 transmits a signal on the conductor 76. This signal is then used by the command logic unit 63 for generating the commands appertaining to the interruption itself.

The operative condition in which the central unit 5 is during the carrying out of an instruction is given the name of "machine state." Each machine state has a duration of 2 .mu.s and is defined by the time signal TS, the course of which is shown in FIG. 4. In each machine state defined in this way, a series of commands is generated by the command logic unit 63 (FIG. 2) as a function of the signals present at its inputs, which, as has been said, are significative of the individual instructions. More precisely, the instructions are executed by the central unit 5 by means of the succession of a plurality of machine states. In each state there are defined univocally the operations to be carried out by the central unit 5. To this end, the command logic unit 63 comprises two blocks 63A and 63B. The block 63A, shown in detail in FIG. 5, determines the sequence of machine states through which the selected instruction is to be carried out on the basis of the input signals transmitted by the function decoding network 62. The block 63B, shown in FIGS. 6 to 12 for each machine state, generates a sequence of operative commands COMO1 - COM27 relating to the selected instruction.

More particularly, the block 63A has as inputs the conductors 62.sub.1 - 62.sub.13 (FIG. 2) coming from the decoding network 62, each of the conductors 62.sub.1 - 62.sub.13 being associated with one of the thirteen instructions. Moreover, the block 63A has as input the conductors 75 and 76 coming respectively from the second series of four flip-flops of the register 59 and from the register 31, and a conductor 100 coming from the store input logic circuit 47. Each machine state is defined by the energization of a corresponding output MA-MG of a series of flip-flops FA-FG included in the block 63A. Since each machine state has a duration of 2 .mu.s, each of the flip-flops FA-FG must remain activated for an interval of time equal to 2 .mu.s. To achieve this, there is introduced into the block 63A the timing signal TS, which activates the inputs of the flip-flops FA-FG through the AND circuits DA-DG The outputs MA-MG of the flip-flops FA-FG condition the block 63B, so that in each state there are generated the commands associated with the individual instructions. More particularly, each circuit shown in FIGS. 6 to 12, of which the block 63B is composed, is activated by a corresponding signal MA-MG and is conditioned furthermore by the same input signals to the block 63A.

Since the need arises for timing a number of the commands COM01-COM27 in the compass of a machine state, timing signals TR, TI and TM (FIG. 4) generated by the timing circuit 20 (FIG. 3) are also located as input to the circuits of the block 63B.

The commands COM01-COM27 generated by the block 63B of the logic unit 63 moreover act on the input logic circuit 47 (FIG. 2) of the store 42. This logic circuit 47 also has as inputs two channels 80 and 81, each with a capacity of eight bits. The channel 80 comes from the register 50, while the channel 81 comes from the register 57. The logic circuit 47 moreover has as input a channel 82 with a capacity of two bits and coming from the register 71. The channels 80, 81 and 82 transfer the contents of the registers 50, 57 and 71 to the input logic circuit 47, so that they may be processed therein in accordance with the corresponding commands COM01-COM27 generated by the command logic unit 63. The results of these processing operations, represented by a combination of eight bits, are sent throught the output channel 48 to the cell of the store 42 identified by the address contained in the addressing register 41.

More precisely, the logic circuit 47 simply transfers the data present at its inputs on the output channel 48 when one of the commands COM03 COM14 and COM17 acts on it. In fact, the command COMO3 acts on a gate circuit 85 (FIG. 13), as a result of which the bits present on the channel 80 coming from the register 50 are transferred on the channel 48. The commands COM14 and COM17, acting on two gate circuits 86 and 87, respectively, cause the transfer of the bits present on the channels 81 and 46, respectively, to the output channel 48. In this way, the characters present in the register 57 (FIG. 2) and the characters coming from one of the peripheral units 6, 7, 8 are introduced into the store 42 without being processed.

On the other hand, when the command COMO6 acts on the logic circuit 47, the character present on the input channel 80 is incremented by one unit from a counting network 88 (FIG. 13) and is then transferred through a gate circuit 89 to the output channel 48. When the command COM19 is generated, the eight bits present on the input channel 81 are introduced into an interchange network 90, which interchanges the first four bits with the second four in a manner known per se. The new character obtained in this way is transferred through a gate circuit 91 on the output channel 48.

The logic circuit 47 (FIG. 2) can moreover compare the contents of the register 50 with the contents of the register 57. More precisely, if the command COM20 is present, a comparison circuit 98 known per se is actuated and compares the contents of the two registers 50 and 57 coming from them through the channels 80 and 81. The comparison effected by the comparison circuit 98 is significative of the likeness or dissimilarity of the characters present in the two registers 50 and 57. The result of this comparison is represented by a bit E generated by the comparison circuit 98 and sent over a conductor 95. This bit is equal to 1 if the characters present in the two registers 50 and 57 are alike and equal to O if they are different. The bit E is forced through the conductor 95 into a register 96 (FIG. 2) having a capacity of one bit. The contents of the register 96 can be forced into another register 97 identical to the register 96 when the command COM26 is generated. Conversely, the command COM13 produces the reverse transfer. Through the conductor 100, the bit E can moreover condition the operation of the command logic unit 63 during the carrying out of particular instructions.

Moreover, if the command COM21 is present, an AND circuit 92 (FIG. 13) effects the logical AND between the eight bits respectively present on the input channels 80 and 81. The result of this operation is an eight-bit character which is transferred through a gate circuit 93 on the output channel 48. If, on the other hand, the command COM22 is present, a circuit 94 effects the logical exclusive-OR between the bits respectively present on the input channels 80 and 81. As is known, the result of this logical operation is equal to 1 if the two bits are different and is equal to 0 if the bits are alike. This result is then transferred through a gate circuit 99 on the output channel 48.

As has been said, all the groups of instructions which condition the operation of the central unit 5 are recorded, in a configuration described hereinafter, in the magnetic tape store 7 (FIG. 1). So that these groups of instructions may be executed by the central unit 5, they must be transferred one at a time from this store 7 to the core store 42 (FIG. 2). After this, the instructions making up the selected group are executed in sequence by the central unit 5. For transferring the groups of instructions from the tape store 7 to the core store 42, a particular group of instructions called the "group of initial instructions" is used. This group of instructions is composed of 64 characters and is also recorded in the external store 7, in two positions predetermined by the magnetic tape.

The control unit 10 of the store 7 is adapted to recognize, in a manner which will be described hereinafter, the two store addresses in which the group of initial instructions is recorded. When these addresses are recognized, it initiates the transfer of the "group of initial instructions" in the following manner. Normally, the central unit 5 is in an inoperative condition, so that all its registers are zeroized. when the timer 20 (FIG. 2) generates the signal TS, through the AND circuit DA (FIG. 5) the output MA of the flip-flop FA is brought to level 1, so that the central unit 5 is put into the state A.

Then, an AND circuit 12 (FIG. 6) of the block 63B activated at the time TS, generating the command COMO1 which opens the gate circuit 64 (FIG. 2), causes the transfer of the contents of the register 32 to the register 41 and therefore to the decoding network 45. Moreover, the output MA directly generates the command COM18 (FIG. 6) which, opening a gate circuit 113 (FIG. 2), transfers the contents of the register 71 to the circuit 45. The address 00000000 of the store 42-since all the registers of the central unit 5 are zeroized-is then forced into the decoding network 45. The contents of the corresponding cell are now transferred to the output register 50.

The control unit 10 of the tape store 7 has meanwhile already selected the character to be transmitted to the central unit 5 and has put this character into the input channel 46 in a manner which will be described hereinafter.

An AND circuit 114 (FIG. 6) of the block 63B generates in turn a command COM17, which opens the gate 87 (FIG. 13) of the circuit 47 and causes the transfer of the first character present on the channel 46 from the tape store 7 to the cell of the core store 42 the address of which is indicated by the decoding network 45.

At the instant TR (FIG. 4) following the time interval TS, and AND circuit 115 (FIG. 6) of the block 63B generates the command COM04, which opens a gate circuit 116 (FIG. 2) and transfers to the register 32 the contents of the register 41 incremented by one unit from the counting network 44. In this way, into the register 32 there is forced the configuration 00000001, therefore incrementing the address of the store 42.

The central unit 5 then controls the operation of the control unit 10 of the store 7 so that it selects and puts into the channel 46 the following character to be introduced into the store 42. The same operations as are described hereinbefore are then repeated, so that the succeeding information is recorded in the cell 00000001 of the store 42. In this way, the sixty-four characters of the group of initial instructions are recorded in the first sixty-four cells of the store 42. Since each machine state has a duration of 2 .mu.s, the entire transfer of the group of initial instructions has a duration of 128 .mu.s.

When the contents of the register 32 reach the binary value 64, the flip-flop of weight 64 of the register 32 assumes the value 1, therefore generating a signal R64 which activates an AND circuit 120 (FIG. 6) of the block 63B. The AND circuit 120 now generates a signal RBT which resets a flip-flop 35 (FIG. 2), so that the output BT of the latter assumes the value 0. At the same time, the register 32 is zeroized by a signal R4 generated by an AND circuit 121 (FIG. 6) of the block 63B, since the output signal BT of the flip-flop 35 is zero. At this instant, therefore, all the registers of the central unit 5 (FIG. 2) are zeroized and that the group of initial instructions is recorded in the core store 42. This group contains the instructions adapted to load the following instructions into the store 42.

All the following instructions begin with the state A. For these instructions, however, the flip-flop 35 is reset, that is its output BT has the value 0. When the commands COM01 and COM18 (FIG. 6) are now generated again, the address of the cell of the store 42 recorded in the registers 32 and 71 is transferred to the decoding network 45 (FIG. 2). The contents of this cell are therefore read and are then transferred to the output register 50. Therefore, when BT= 0, the reading of the store 42 takes place.

Since, as is known, the reading of the core store 42 is destructive, it is necessary to re-write the information read in the selected store cell. To this end, an AND circuit 123 of the block 63B (FIG. 6) activated by the signal BT generates the command COMO3, which closes the gate circuit 85 (FIG. 13) of the logic circuit 47 and now transfers the contents of the register 50 (FIG. 2) to the same cell of the store 42 in which they were stored at the instant TR. The command COM04, in turn, transfers to the register 32 the contents of the register 41 incremented by one unit.

An AND circuit 122 of the block 63B (FIG. 6) being controlled by the signal BT through an inverter, now generates the command COMO5 at the instant TR (FIG. 4) following the instant TS. This command, opening a gate 124 (FIG. 2), transfers to the register 59 the contents of the register 50 which represents the first character of the instruction, so that during the state A the first character of the instruction is read.

An AND circuit 124 of the block 63A which is also controlled by the signal BT through an inverter (FIG. 5) now activates the flip-flop FB at the instant TS, through the AND circuit DB, so that the output MB of this flip-flop is brought to the level 1. At the same time, the flip-flop FA is reset, as a result of which the central unit 5 passes from the state A to the state B.

During the state B there are generated the commands COM01, COM18 and COM03 common to all the instructions, which commands, as has been seen, cause the transfer to the output register 50 of the contents of the cell of the store 42 identified by the contents of the register 32 and the subsequent writing of these contents in the same cell of the store 42. These operations during the state B produce the reading of the second character of the instruction, since the address staticized in the register 32 has been incremented by one unit during the state A.

During the state B there are moreover generated by the block 63B commands relating to the individual instructions, on the basis of the contents of the register 59, which still contains the code of the instruction. The first four bits of this code are transferred through the channel 60 to the decoding network 62, which activates the output corresponding to the instruction expressed by the four bits that are input. As will be seen hereinafter, this output remains activated throughout the interval necessary for the execution of the instruction itself and therefore conditions the generation of the commands by the logic unit 63 during the various machine states which are generated by the block 63A.

EXECUTION OF INSTRUCTIONS

There will now be described the execution of the individual instructions by the central unit 5. There are thirteen instructions provided for the execution of any programme and they may be formed by two or three characters, each character comprising eight bits. The first character of each instruction is used to characterize the instruction itself and it has the format:

b0 b1 b2 b3 b4 b5 b6 b7

The first four bits b0 - b3 represent the code of the instruction, while the second four b4 - b7 represent the modifier. The instructions are substantially of two types in relation to the number of characters of which they are formed.

The instructions of the first type are composed of three characters, the first of which defines the instruction, while the second and third characters respectively define the addresses of the cells of the core store 42 on the contents of which the instruction itself is to operate. The contents of these cells will be called the operand. More particularly, the operand of which the address is defined by the second character of the instruction will be called the 1st operand, and the operand the address of which is defined by the third character of the instruction will be called the 2nd operand.

The instructions of the second type are composed of two characters, the first of which defines the instruction, while the second character defines the address of the cell of the operand in the store 42. The instructions of the second type are called external instructions, since, as will be explained hereinafter, they permit the transfer of commands or information from the central unit 5 to one of the peripheral units 6, 7, 8 connected thereto or vice versa.

The thirteen instructions are divided in relation to the machine states necessary for their execution into four groups, which will now be described in detail.

1st Group of Instructions

To the 1st Group of Instructions there belong the instructions which are executed by the central unit 5 by means of the sequence of the five states A, B, C, D, E. The time necessary for their execution is therefore 10 .mu.s.

These instructions are: Transfer (TRA), Interchange (SCA), Comparison (CFR), Logical product (AND), Exclusive-OR (EX OR), Free Transfer (TRL) and are described individually in detail hereinafter with reference to Tables I and II on pages 47 and 48.

1. Transfer (TRA)

The transfer instruction identified by the code 1000 effects the transfer of the 1st operand from the address defined by the second character of the instruction to the address defined by the third character. As has been said, the address of the cells of the store 42 is such that every store cell is identified by the number of the page and the number of the cell in that page. However, the instructions are organized in such manner that all the addresses of the operands relating to the instructions of a single program are located in the same page of the store, called precisely the "current page." Moreover, during the execution of a programme, as will be seen hereinafter, reference may be made to operands or to instructions the address of which belongs to page 0. An operand or an instruction may therefore belong either to the "current page" or to "page 0."

The code relating to the store page to which the operands of the instructions belong is supplied with the bits b4 and b6 of the modifier in the following manner. If the bit b4= 1, the store cell defined by the second character of the instruction (address of the 1st operand) belongs to the current page, if the bit b4= 0 it belongs to the page 0. If the bit b6= 1, the store cell defined by the third character (address of the second operand) belongs to the current page, if b6= 0 it belongs to the page 0.

During the execution of a programme, moreover, it may become necessary, after the execution of an instruction, for the store address of the two operands to be incremented or not by one unit. This eventuality is expressed by the value assumed by the bits b5 and b7. If the bit b5= 1, the address of the 1st operand is incremented by one unit after the execution of the instruction, if b5= 0 it remains unchanged. The same occurs in the case of the address of the 2nd operand if b7= 1 or b7=0, respectively.

As has been said, the code of the instruction TRA is read during the state A and is sent through the register 59 (FIG. 2) to the decoding network 62. During the state B, this network effects the decoding of the code of the instruction while the commands COM01, COM18 and COM03 are generated, which cause the reading of the second character of the instruction, that is the address of the 1st operand. In correspondence with the code of this instruction, the decoding network 62 activates the output 62.sub.1 (FIGS. 2 and 7) and, therefore, the output of an OR circuit 130 (FIG. 7) of the block 63B.

If the bit b5 of the modifier of the instruction has the value 1, the second character of the instruction, which is staticized in the register 50 (FIG. 2), must be re-written in the store 42 incremented by one unit. In this case, the inputs of an AND circuit 131 (FIG. 7) of the block 63B are all at the level 1, so that the circuit 131 generates the command COM06. This command opens the gate 89 (FIG. 13) of the circuit 47, the character contained in the register 50 is carried through the input channel 80 to the circuit 98, which increments it by one unit; it is then transferred through the output channel 48 to the store 42.

If, on the other hand, the bit b5 of the modifier is zero, the output of the AND circuit 131 (FIG. 7) is at zero level, whereby the command COM06 is not generated. During the state B, an AND circuit 300 of the block 63B being now activated, the command COM04 is now generated at the instant TR and opens the gate circuit 116 (FIG. 2), causing, as has been seen, the transfer to the register 32 of the address staticized in the register 41 and incremented by one unit by the counting network 44. At the same instant TR (FIG. 4) there is activated the output of another AND circuit 132 (FIG. 7) of the block 63B, whereby the command COM15 is generated. This command causes the activation of a gate circuit 146 (FIG. 2), which causes the transfer of the contents of the register 50 to the register 57.

During the state B, there has therefore been carried out the reading of the second character of the instruction which represents the address of the first operand and this has then been transferred to the register 57. If the bit b5 is equal to 1, this address has moreover been re-written in store incremented by one unit.

The passage of the central unit 5 to the state C now takes place. To this end, during the state B, the outputs 62.sub.7, 62.sub.10, 62.sub.11 and 62.sub.13 (FIG. 5) of the decoding circuit 62 are all at the level 0, since only the output 62.sub.1 corresponding to the instruction TRA is activated. Through the inverter circuits 134, these outputs activate the corresponding inputs of an AND circuit 133 of the block 63A. Moreover, since also the output 62.sub.6 of the circuit 62 is at zero level, through an inverter 135 the input 136 of an OR circuit 137 of the block 63A is activated. In this way, an AND circuit 133 of the block 63A is actuated and in turn actuates the input 138 of another AND circuit 139 of the block 63A. Since the other input of this AND circuit 139 is connected to the output MB of the flip-flop FB, the AND circuit DC is activated at the instant TS, as a result of which the flip-flop FC places the output MC at the level 1. At the same time, the AND circuit DC resets the flip-flop FB, as a result of which the central unit 5 therefore passes from the state B to the state C.

The state C is used for the reading of the 1st operand. In fact, an AND circuit 140 (FIG. 8) of the block 63B generates the command COM10 at the instant TS. This command, opening a gate circuit 141 (FIG. 2) of the channel 55, causes the transfer of the address of the first operand from the register 50 to the addressing register 41.

If the address of the 1st operand belongs to the current page, since the bit b4 of the modifier of the instruction TRA has the value 1, the input 142 of an AND circuit 143 (FIG. 8) is activated. The input 144 of the circuit 143 is moreover activated through an inverter, since the output 62.sub.6 of the decoding circuit 62 is at the level 0. The AND circuit 143 therefore generates the command COM18 which, as has been seen, controls the transfer of the contents of the page register 71 (FIG. 2) to the address decoding circuit 45.

If, on the other hand, the bit b4 is at the level 0, the command COM18 is not generated and no bit is forced into the address decoding circuit 45, so that the store page selected is the page 0.

At the same time there takes place the reading of the contents of the store cell selected by the address of the 1st operand and the transfer of the contents to the output register 50. At the instant TR (FIG. 4) an AND circuit 145 (FIG. 8) is moreover enabled, so that the command COM15 is generated. This command, opening a gate circuit 146 (FIG. 2), causes the transfer of the first operand from the register 50 to the register 57. Finally, the command COM03 is generated by another AND circuit 146 (FIG. 8) and commands the writing in the cell of the store 42 of the same information that has been read. Thus, in the state C, there is carried out the reading of the 1st operand, which is re-written in the cell in which it was located and transferred to the register 57.

The passage of the central unit 5 to the state D is then effected. In fact, since the output 62.sub.1 of the decoding circuit 62 has the value 1, an OR circuit 147 (FIG. 5) of the block 63A is now activated and, consequently, the input 148 of an AND circuit 149. Since the other input 150 of the AND circuit 149 is activated by the flip-flop FC, the flip-flop FD is activated at the instant TS through the AND circuit DD; at the same time, the AND circuit DD resets the flip-flop FB, as a result of which the central unit 5 passes from the state C to the state D.

The state D is used for reading the address of the cell to which the first operand is to be transferred. In fact, at the time TS (FIG. 4), an AND circuit 155 (FIG. 9) of the block 63B generates the command COM01 which, opening the gate circuit 64 (FIG. 2), transfers the contents of the register 32 to the register 41. The contents of the register 32 have been incremented by one unit during the state C, so that into the addressing register 41 there is forced the address of the store cell following that in which the contents were read during the state C. If the bit b6 of the modifier is 1, the current page is selected by an AND circuit 156 (FIG. 9) through the command COM18. In fact, in this case, the outputs 62.sub.12 and 62.sub.13 of the decoding circuit 62 are at zero level and through two inverters energize, together with the bit b6, the AND circuit 156. Through the medium of the circuit 113 (FIG. 2), the command COM18 now transfers the contents of the page register 71 to the addressing circuit 45. Since the contents of the register 71 have not been changed during the preceding states, they define the current page.

If the bit b6 is 0, the command COM18 is not generated by the AND circuit 156 (FIG. 9), so that no bit is forced into the addressing circuit 45, causing the selection of the page 0.

At the same time there takes place the reading of the store cell selected by the third character of the instruction, that is by the address of the cell to which the first operand is to be transferred. These contents are then transferred to the output register 50. The command COM03 (FIG. 9) is moreover generated directly by the flip-flop FD and causes the address read to be re-written in the cell selected.

If the bit b7 of the modifier is 1, it activates an input of an AND circuit 157 (FIG. 9). Since the output 62.sub.12 is at the level 0, the other input is also activated, as a result of which the AND circuit 157 activates in turn an OR circuit 158 and therefore an AND circuit 159. The lastmentioned circuit then generates the command COM06 which, as has been seen hereinbefore, conditions the store input circuit 47 (FIG. 2) in such manner as to re-write in the selected store cell the address read therein incremented by one unit. During the state D, an AND circuit 160 generates at the instant TR the command COM04 which, as has been seen before, causes the contents of the register 32 (FIG. 2) to be incremented by one unit.

Finally at the instant TS (FIG. 2) there is activated the AND circuit DE (FIG. 5), which in turn activates directly the flip-flop FE, as a result of which the output ME is brought to the level 1. The AND circuit DE moreover resets the flip-flop FD, as a result of which the central unit passes from the state D to the state E.

The state E is used to transfer the 1st operand, which has been staticized during the state C in the register 57 (FIG. 2), to the cell of the store 42 the address of which has been read during the state D. In fact, at the instant TS, the command COM10 is generated by an AND circuit 161 (FIG. 10) of the block 63B and, acting on the gate circuit 141 (FIG. 2), causes the transfer to the register 41 of the address read during the state D and forced into the register 50.

If the bit b6 is 1, an AND circuit 162 (FIG. 10) generates the command COM18 which, causes the transfer of the contents of the page register 71 (FIG. 2) to the addressing circuit 45. Since the output 62.sub.1 of the circuit 62 corresponding to the transfer instruction is at level 1, an OR circuit 163 (FIG. 10) is activated and, therefore, an AND circuit 164. In this way there is generated the command COM14 which, by means of the store input circuit 47 (FIG. 13), causes the transfer of the 1st operand contained in the register 57 to the store cell selected by the decoding network 45. Therefore, during the state E, the 1st operand is transferred from the cell corresponding to the address identified by the second character of the instruction read during the state B to the cell corresponding to the address identified by the third character read during the state D.

At the instant TS (FIG. 4) following the operations described, if any of the peripheral units 6, 7, 8 do not interrupt, the flip-flop FE (FIG. 5) activates the input 166 of an AND circuit 167. The other input 168 is activated through an inverter 169 by a signal INT indicating the interrupt, since it has the value 0. The output 204 of the AND circuit 167 activates in turn, through the AND circuit DA, the flip-flop FA, as a result of which the central unit passes from the state E to the state A and the execution of the following instructions can be initiated.

2. Interchange (SCA)

The interchange instruction (SCA) is identified by the code 1010 and effects the transfer of the 1st operand read in the cell defined by the second character to the cell defined by the third character, interchanging the first four bits with the second four bits of the 1st operand. The modifier of this instruction has the same significance as the modifier of the instruction TRA.

The instruction SCA is recognized by the decoding circuit 62, which then generates as output a signal 62.sub.2. The instruction is executed in a manner entirely identical to that in which the instruction TRA discussed above is executed. The only difference consists in the fact that during the state E an AND circuit 175 (FIG. 10) activated by the output 62.sub.2 generates the command COM19. This command, acting on the store input circuit 47, in the manner hereinbefore described, causes the transfer of the contents of the register 57 (FIG. 2) to the selected store cell, interchanging the two groups of bits.

3. Comparison (CFR)

The comparison instruction (CFR) is identified by the code 1001 and effects the comparison bit by bit between the 1st operand and the 2nd operand, the result of which is expressed by the bit E forced into the register 96 (FIG. 2) of the central unit 5. The modifier of this instruction has the same significance as the modifier of the preceding instructions.

The instruction CFR is recognized by the circuit 62, which then generates a signal at the output 62.sub.3. The instruction CFR is executed in a similar manner to the instruction TRA. The sole difference consists in the fact that during the state E the commands COMO3 and COM20 are generated. In fact, the command COM03 is now generated by an AND circuit 176 (FIG. 10) and causes the writing of the contents of the register 50, that is the writing of the 2nd operand, in the selected store cell. The command COM20 is generated at the instant TI (FIG. 4) by an AND circuit 177 (FIG. 10) and, as has been seen, conditions the store input circuit 47 (FIG. 2) so that a comparison is made between the contents of the registers 50 and 57 and the bit E= 1 is forced into the register 96 if the two contents are the same.

4. Logical product (AND)

The instruction AND is identified by the code 1111 and effects the logical AND bit by bit between the 1st operand and the 2nd operand. The modifier of this instruction has the same significance as the modifier of the preceding instructions.

The instruction AND is recognized by the circuit 62, which then generates as output a signal 62.sub.4. This instruction is executed in an entirely similar manner to the instruction CFR. The sole difference consists in the fact that during the state E the output 62.sub.4 activates an AND circuit 178 (FIG. 10) which generates in turn the command COM21. This, as has been said, acts on the store input circuit 47 so that the logical AND is effected between the contents of the registers 50 and 57. The result of this comparison, represented by an eight-bit character, is in turn transferred to the store cell in which the 2nd operand was located. This is made possible by the fact that during the state E the address of the 2nd operand is present in the register 41.

5. Exclusive-OR (ORE)

The instruction ORE is identified by the code 1110 and effects the exclusive-OR bit by bit between the 1st operand and the 2nd operand. The result of this operation is stored in the cell of the 2nd operand in the store 42. As regards this instruction also, the modifier has the same significance as the modifier of the preceding instructions.

The instruction ORE is recognized by the circuit 62, which then generates as output a signal 62.sub.5 and operates like the instruction AND. The sole difference consists in the fact that during the state E the output 62.sub.5 activates an AND circuit 179 (FIG. 10), which in turn generates the command COM22. As has been seen, this command acts on the store input circuit 47 so that the exclusive-OR operation is carried out.

6. Free transfer (TRL)

The free transfer instruction (TRL) is defined by the code 1011 and effects the transfer of the 1st operand from the cell defined by the second character to the cell defined by the third character, in any page of the store 42, in contrast to the instruction TRA. The page in which the transfer takes place is identified by the bits b6 and b7 of the modifier. If b6= b7= 0, the address defined by the third character belongs to page 0, if b6= 0 and b7= 1 it belongs to page 1, if b6= 1 and b7= 0 it belongs to page 2, if b6= b7= 1 it belongs to page 3. The bits b4 and b5 of the modifier have the same significance as the bits b4 and b5 of the modifier of the instruction TRA.

The instruction TRL is recognized by the circuit 62, which then generates as output a signal 62.sub.12, and is executed in the same way as the instruction TRA, except that, in the state D, the output 62.sub.12 activates an OR circuit 180 (FIG. 9) which in turn generates the command COM27. This command, acting on a gate circuit 185 (FIG. 2), transfers to the decoding network 45 the bits b6 and b7 of the modifier, that is the address of the store page to which the 1st operand is to be transferred.

2nd Group of Instructions

To this group there belong the instructions concerning a constant which represents the 1st operand and is expressed by the second character of the instruction. These instructions are: transfer of constant (TRC), free transfer of constant (TLC) and comparison of constant (CDC). The said instructions are executed by the central unit 5 by means of the sequence of the states A, B, D, E. The time required for their execution is therefore 8 .mu.s. These instructions are respectively associated with the outputs 62.sub.10, 62.sub.13 and 62.sub.11 of the decoding circuit 62.

They are executed substantially in the same way as the instructions (TRA), (TRL) and (CFR) except for the fact that the state C is not carried out. In fact, the operations carried out in the states A and B are entirely identical to the operations executed by the corresponding instructions of the 1st Group. More precisely, during the state A the code of the instruction is read and during the state B the second character, which now represents the constant, is read. Since the constant is now read during the state B, it is not necessary to carry out the state C, which hand is used by the corresponding instructions of the 1st Group to read the 1st operand in the store 42.

Since one of the outputs 62.sub.10, 62.sub.13, 62.sub.11 is now always at level 1, the OR circuit 186 (FIG. 5) is activated. This circuit activates the input 187 of an AND circuit 188, while the other input 189 is activated by the flip-flop FB, as a result of which the AND circuit 188 activates the flip-flop FD through the AND circuit DD at the time TS (FIG. 4). The AND circuit DD moreover resets the flip-flop FB, acting on the corresponding reset circuit, so that there is a change directly from the state B to the state D.

1. transfer of constant (TRC)

The transfer-of-constant instruction (TRC) is identified by the code 1100 and effects the transfer of the constant expressed by the second character of the instruction to the cell identified by the third character of the instruction. The constant may also be incremented or not by one unit after the execution of the instruction under the control of the bit b5 of the modifier. If b5= 0, the constant remains unchanged, if the bit b5= 1 the constant is incremented by one unit. The store address defined by the third character may also be incremented or not by one unit under the control of the bit b7 of the modifier If b7= 0, the address remains unchanged, if b7= 1 the address is incremented by one unit.

It is to be noted that the bit b4 of the modifier is always zero and is not used. Therefore, to define the store page to which the address expressed by the third character belongs, the bit b6 of the modifier is used. If b6= 0, the address belongs to page 0, if b6= 1 the address belongs to the current page.

The instruction TRC is recognized by the circuit 62, which then generates as output a signal 62.sub.10. As has been said, this signal directly causes the passage of the central unit 5 to the state D. During this state, the same operations as have been described for the instruction TRA are performed, that is the reading of the third character of the instruction. During the state E there then takes place the transfer of the constant to the address defined by the third character, as for the instruction TRA.

2. free transfer of constant (TLC)

The instruction for free transfer of constant (TLC) is defined by the code 0100 and effects the transfer of the constant defined by the second character to the address defined by the third character. The modifier of this instruction has the same significance as the modifier of the instruction TRL. During the states A and B there are executed the same operations as have been described for the instruction TRC, that is the reading of the code of the instruction and of the constant.

The instruction is recognized by the circuit 62, which then generates as output a signal 62.sub.13. As has been said, this signal directly causes the passage of the central unit 5 from the state B to the state D. During this state there is effected the reading of the third character of the instruction, as in the case of the instruction TRL. During the state E there then is carried out the transfer of the constant to the address defined by the third character as for the instruction TRA.

3. comparison of constant (CDC)

The instruction for comparison of a constant (CDC) is identified by the code 1101 and effects the comparison bit by bit between the constant expressed by the 1st operand and the 2nd operand. The result of this comparison is expressed by the bit E= 1 if the two operands are alike and by the bit E= 0 is they are different. This bit is placed in the register 96 of the central unit 5 (FIG. 2).

The modifier of the instruction CDC has the same significance as the modifier of the instruction TRC. The instruction CDC is recognized by the circuit 62, which then generates as output a signal 62.sub.11, as a result of which the passage of the central unit 5 from the state B to the state D takes place. During this state, the reading of the second operand is effected as in the case of the instruction CFR. Finally, during the state E comparison takes place between the constant and the 2nd operand.

3rd Group of Instructions

To this group there belong the instructions which are executed by the central unit 5 (FIG. 2) by means of the sequence of the states A, B and C. The time required for their execution is therefore 6 .mu.s. These instructions are: the character-from-peripheral instruction (CDP), the character-to-peripheral instruction (CAP) and the jump instruction (SAL).

These instructions have a single address and are therefore formed by two characters. The first character contains the code which characterizes the type of instruction within the limits of the group and the relevant modifier. The second character contains the store address of the operand.

1. Character from peripheral (CDP)

The character-from-peripheral instruction (CDP) is defined by the code 0110 and effects the transfer of the operand from the peripheral unit defined by the bits b6 and b7 of the modifier to the store address defined by the second character. The bit b4 of the modifier defines the store page to which the address defined by the second character belongs. If b4= 0, the address belongs to page 0, if b4= 1 it belongs to the current page. If, moreover, the bit b5= 0, the address remains unchanged after the execution of the instruction, if the bit b5= 1 the address is incremented by one unit.

During the state A, the instruction CDP is recognized by the circuit 62, which then generates as output a signal 62.sub.8. During the state B, the second character of the instruction is read, as for the instructions of 2nd 1st and 1nd Groups. The second character of the instruction identifies the cell of the store 42 in which is to be recorded the character transmitted by the peripheral unit 6, 7 or 8 defined by the bits b6 and b7 of the modifier.

From the state B the central unit then passes to the state C, since the AND circuit 139 of the block 63A (FIG. 5) is activated by the OR circuit 133, the outputs 62.sub.6, 62.sub.7, 62.sub.10, 62.sub.11 and 62.sub.13 of the circuit 63 being zero. During the state C, the output 62.sub.8 activates an AND circuit 197 (FIG. 8) which in turn generates the command COM17, which causes in the store input circuit 47 the transfer of the character present on the channel 46 (FIG. 2) to the cell of the store 42 the address of which has been read during the state B.

After these operations, the central unit 5 returns to the state A. In fact, since the output 62.sub.8 is at level 1, an OR circuit 198 (FIG. 5) is always activated. Consequently, there is activated an input 199 of an AND circuit 200, the other input 201 of which is activated through an inverter 169. In this case, the AND circuit 200 activates an AND circuit 202 enabled by the output 203 of the flip-flop FC. The output 204 of the AND circuit 202 activates in turn at the instant TS (FIG. 4) the flip-flop FA, as a result of which the central unit passes from the state C to the state A.

2. character to peripheral (CAP)

The character-to-peripheral instruction (CAP) is identified by the code 0111 and effects the transfer of the operand the address of which is defined by the second character to the peripheral defined by the bits b6 and b7 of the modifier. These bits have the same significance as the corresponding bits of the instruction CDP. During the state A, this instruction is recognized by the circuit 62, which then generates as output a signal 62.sub.9.

The second character of the instruction read in the state B now identifies the address of the character which is to be transmitted to the peripheral unit defined by the bits b6 and b7 of the modifier. As regards this instruction also, the central unit passes from the state B to the state C owing to the fact that the OR circuit 133 of the block 63A (FIG. 2) is activated. During the state C there takes place the reading of the character the address of which has been selected during the state B and simultaneous staticization in the register 50 (FIG. 2). Moreover, the output 62.sub.9 activates the AND circuit 195 (FIG. 8), which in turn generates the command COM08. This command is transmitted to the selected peripheral unit to prepare it to receive the character transmitted from the central unit 5. After these operations, the central unit 5 returns to the state A, as in the case of the instruction CDP.

3. jump (SAL)

The jump instruction (SAL) is identified by the code 0010 and makes it possible to pass from one instruction to another, even if these instructions are not consecutive in the course of the programme being executed. The second character of the instruction SAL indicates the address in store of the next instruction which is to be carried out by the central unit 5.

The same operations as have been described for the preceding instructions are also carried out for the instruction SAL during the states A and B. The bits b6 and b7 of the modifier define, on the other hand, the page to which the cell defined by the second character of the instruction belongs, as for the instructions TRL and TLC. In this store cell there is now contained the first character of the instruction which is to be executed thereafter.

The jump may be conditional or unconditional. For example, in a comparison effected by the instruction CDC, the result is expressed by the bit E forced into the register 96 (FIG. 2) of the central unit 5. The instruction SAL may then be conditioned either by the bit E= 0 or by the bit E= 1, in dependence upon the particular arrangement of the programme in process of execution.

The value of the bit E which conditions the execution of the jump instruction is identified by the bits b4 and b5 of the modifier of the instruction. More precisely, we have the following two cases: b4= b5= 0 for the instruction SAL conditioned by the value E= 0, that is effected if E= 0, b4= 0 and b5= 1 for the jump instruction conditioned by the value E= 1.

The second character, read during the state B and recorded in the register 50, now represents the store address to which the jump is to take place.

The block 63A comprises a logic circuit 105 (FIG. 5) adapted to emit in known manner an output signal CV which represents the following logical function:

CV= b4+ b5.E+ b5.E

Therefore, CV is 1 if b4= b5= E= 0 or b4= 0 and b5= E= 1.

If the jump condition is not verified, that is if in the said two cases we have respectively E= 1 and E= 0, the signal CV= 0. An AND circuit 210 of the block 63A is then activated, since the two inputs 211 and 212 are at level 1, the output 62.sub.6 of the circuit 62 being activated. In consequence, through an OR circuit 213, the AND circuit 210 activates the input 214 of an AND circuit 215, the other input 216 of which is then activated by the inverter 169. In this case, the AND circuit 215 activates the input 217 of an AND circuit 218, the other input 219 of which is connected to the output 220 of the flip-flop FB. Consequently, the output 221 of the AND circuit 218 activates the flip-flop FA at the instant TS through a conductor 204. Therefore, when the jump condition is not verified, the central unit 5 returns from the state B to the state A, as a result of which the jump instruction is not executed.

If, on the other hand, the jump condition is verified, that is, referring to the two preceding cases, if the bit E has the values 0 and 1, respectively, the signal CV is at level 1. This signal therefore activates an OR circuit 137 and, through the AND circuit 133, also the input 138 of the AND circuit 139. The other input of this circuit is activated by the flip-flop FB, inasmuch as the central unit 5 is in the state B. Consequently, the flip-flop FC is activated at the instant TS through the AND circuit DC.

The central unit then passes from the state B to the state C, wherein the command COM10 is generated by the AND circuit 140 (FIG. 8) and commands the transfer of the contents of the register 50 (FIG. 2) to the addressing register 41. In this way, the store address to which the jump is to be made is staticized in the register 41. At the instant TI, an AND circuit 225 (FIG. 8) generates the command COM12 which, opening a gate circuit 221 (FIG. 2), transfers to the page register 71 the bits b6 and b7 indicating the page to which the address belongs.

Another AND circuit 226 moreover generates the command COM11, which is adapted to inhibit the counting network 44 (FIG. 2). In this way, when an AND circuit 227 generates the command COM04 at the instant TR, the same address which is staticized in the register 41 is forced into the register 32, that is the second character of the instruction which indicates the address from which the following instruction will be carried out.

The operations carried out in the state C having been completed, the central unit 5 passes to the state A, as seen in the case of the instructions CDP and CAP. During the state A which follows there will then be forced into the addressing registers 41 and 71 the address defined by the second character of the instruction and by the bits b6 and b7 of the modifier.

The unconditional jump is effected, for example, when any peripheral unit interrupts a programme which is in course of execution. For example, the interrupt may be caused when a peripheral unit has carried out the operation indicated by an instruction CAP sent to it by the central unit 5, or when a peripheral unit introduces a character into the central unit 5 by means of an instruction CDP. Owing to this interrupt, it is necessary for the central unit 5 to store in a store cell a jump instruction which will make it possible to return to the last address taken into consideration by the programme before the interrupt. This jump instruction is therefore not conditioned by the value of the bit E. It is identified by the bits b4 and b5 of the modifier, which assume in this case the values 1 and 0, respectively. The output signal CV of the circuit 105 (FIG. 5) is then always at level 1, whatever the value of the bit E. In this case, the same operations as have been described for the conditional jump instruction with the condition verified are performed by the central unit 5.

Moreover, there is an unconditional jump instruction called the "re-entry", jump instruction the significance, of which will be explained hereinafter. This instruction is identified by the bits b4 and b5 of the modifier, which both assume the value 1. The signal CV is also always at level 1 in this case, as a result of which the same operations as have been described for the conditional jump instruction with the condition verified are performed by the central unit 5.

4th Group of Instructions

To the 4th Group of Instructions there belong the instructions which are executed by the central unit 5 by means of the sequence of the states A and B. To this group there also belongs the conditional jump instruction when the jump condition is not verified, as already described.

To this group there moreover belongs the command-to-peripheral instruction (COP), which is identified by the code 0101 and effects the transfer of the command, the code of which is defined by the second character, to the peripheral defined by the bits b6 and b7 of the modifier in the manner described with reference to the instructions CDP and CAP. It is to be noted that the bits b4 and b5 of the modifier are not used by this instruction and are therefore always at level 0.

During the state A there now is carried out the decoding of the instruction by the circuit 62, which activates the output 62.sub.7. During the state B there takes place the reading of the second character of the instruction which represents the command to be transmitted to the selected peripheral unit, and the transfer thereof to the register 50.

Two AND circuits 230 and 231 (FIG. 7) activated by the output 62.sub.7 now generate the commands COM08 and COM09, respectively. The command COM08 causes the transfer of the contents of the register 50 to the peripheral unit, while the command COM09 is transmitted directly to the peripheral unit to specify that the character coming from the central unit is a command and not a character.

After the execution of these operations, the circuit 213 (FIG. 5) activated at the instant TS by the output 62.sub.7 of the circuit 62 causes the activation of the flip-flop FA in the same way as has been described for the jump instruction with the condition not verified, as a result of which the central unit therefore passes from the state B to the state A.

The above-mentioned instructions are synthetized in the following recapitulatory Tables, there being given in Table I the symbol for each instruction, the corresponding name, the code associated with the instruction, the corresponding output of the circuit 62, the bits b4 and b5 and their significance. In Table II there are given machine states in which each instruction is executed by the central unit 5, the group to which the instruction belongs, the value of the bits b6 and b7 and their significance.

                  TABLE I
    ______________________________________
                     Code    out-
    Symbol
          Instruction
                     b0-b3   put  b4 and b5
                                          Significance
    ______________________________________
    TRA   Transfer   1000    62.sub.1
    SCA   Interchange
                     1010    62.sub.2
                                  b4 = 0  1st operand
                                          is on page 0
    CFR   Comparison 1001    62.sub.3
    AND   AND        1111    62.sub.4
                                  b4 = 1  1st operand
                                          is on current
    ORE   Exclusive-OR
                     1110    62.sub.5     page
    TRC   Transfer of
                     1100     62.sub.10
          constant
    CDC   Comparison 1101     62.sub.11
                                  b5 = 0  1st operand
          of constant                     unchanged
    TRL   Free transfer
                     1011     62.sub.12
    TLC   Free transfer
                     0100     62.sub.13
                                  b5 = 1  1st operand
          of constant                     .+-. 1
    CDP   Character  0110    62.sub.8
          from
          peripheral
    CAP   Character to
                     0111    62.sub.9
          peripheral
    COP   Command to 0101    62.sub.7
                                  b4=b 5=0
                                          not used
          peripheral
                                  b4=0 b5=0
                                          jump condi-
                                          tioned by
                                          E=0
                                  b4=0 b5=1
                                          jump condi-
                                          tioned by
                                          E=1
    SAL   JUMP       0010    62.sub.6
                                  b4=1 b5=1
                                          uncondi-
                                          tional
                                          jump
                                  b4=1 b5=0
                                          re-entry
                                          jump
    ______________________________________


              TABLE II
    ______________________________________
          Machine
    Symbol
          states     Group   b6 and b7
                                      Significance
    ______________________________________
    TRA
    SCA   A,B,C,D,E  I       b6=0     2nd operand is
                                      on page 0
    CFR
    AND                      b6=1     2nd operand is
                                      on current page
    ORE                      b7=0     2nd address
                                      unchanged
    TRC
          A,B,D,E     II     b7=1     2nd address
    COC                               + 1
                             b6=0 b7=0
    TRL   A,B,C,D,E  I       b6=0 b7=1
                                      as for jump
                             b6=1 b7=0
                                      instruction
    TLC   A,B,D,E     II     b6=1 b7=1
    CDP                      b6=0 b7=1
                                      tape store
          A,B,C      III     b6=1 b7=0
                                      typewriter
    CAP                      b6=1 b7=1
                                      console
    COP   A, B        IV
                             b6=0 b7=0
                                      2nd operand is
                                      on page 0
                             b6=0 b7=1
                                      2nd operand is
    SAL   A, B, C    III              on page 1
                             b6=1 b7=0
                                      2nd operand is
                                      on page 2
                             b6=1 b7=1
                                      2nd operand is
                                      on page 3
    ______________________________________

INTERRUPT

During the carrying out of one of the instructions hereinbefore described an interrupt command may reach the central unit 5 (FIG. 2) from any one of the peripheral units connected to it. For the purpose of executing the current instruction, the execution of the programme in process of execution is then interrupted and another series of instructions is carried out. The machine states used for carrying out the interrupt are the states F and G, so that the interrupt is carried out in 4 .mu.s.

When one of the peripheral units 6, 7 and 8 sends an interrupt signal INT, the logic circuit 31 (FIG. 2) activates the conductor 76, which introduces the signal INT into the block 63A (FIG. 5). If, at the instant when the signal INT is sent, an instruction of the 1st or 2nd group, which terminates with the state E, is in process of execution, the central unit 5 continues to execute the instruction until this state has been reached. Then, as has been said, the output ME of the flip-flop FE is activated and the input 232 of an AND circuit 233 is activated, the other output 234 of which circuit is activated by the signal INT. Through the AND circuit DF, the circuit 233 therefore activates the flip-flop FF at the instant TS, so that the central unit passes from the state E to the state F.

If, at the instant when the signal INT is sent, an instruction of the 3rd group, the execution of which terminates with the state C, is in process of execution, the interrupt begins to be carried out only when this state is reached. In fact, the output MC of the flip-flop FC is activated and, consequently, the input 203 of an AND circuit 248 is activated. The other input 235 of this circuit is activated only when an AND circuit 236 is activated. This occurs only when both the conductor 76 and the output of the OR circuit 198 are at level 1. This OR circuit is activated when an instruction terminating with the state C is in process of execution, inasmuch as its inputs are connected to the outputs 62.sub.6, 62.sub.8, 62.sub.9 corresponding to the instructions SAL, CAP and CDP. In this way, it can never happen that the execution of an instruction which does not terminate with the state C can be interrupted in the state C by the signal INT. When the AND circuit 248 is activated through the AND circuit DF, the central unit passes from the state C to the state F.

Similarly, when an instruction of the 4 th group, which terminates with the state B, is in process of execution, the signal INT acts only when this state is reached. In fact, the output 220 of the flip-flop FB activates the input 240 of an AND circuit 241, the other input 242 of which is activated by another AND circuit 243. This last-mentioned circuit is activated only when both the signal INT and the output of the OR circuit 213 are at level 1. This occurs only when the instruction COP or the jump instruction with condition not verified is in process of execution. In this way, the possibility of the execution of an instruction which does not terminate with the state B being interrupted in the state B by the signal INT is prevented. When the AND circuit 241 is activated, the central unit therefore passes from the state B to the state F.

In each case, during the state F there is carried out in known manner the reading of the store cell selected during the preceding state, as if the central unit 5 had returned to the state A. The contents of this cell are transferred to the output register 50 in the manner seen hereinbefore.

An AND circuit 245 (FIG. 11) then generates at the instant TM (FIG. 4) the command COM25 which, acting on a gate circuit 246 (FIG. 2), transfers the contents of the register 32 to the register 57. These contents correspond to the store address of the last instruction in process of execution. At the same time, the command COM25 puts all the flip-flops of the register 41 at level 1, acting on the respective set circuits. In this way, the cell 255 is selected, since the configuration 11111111 of the register 41 corresponds precisely to this cell.

The page to which this cell belongs is page 0, since the contents of the register 71 are not transmitted to the addressing circuit 45, the gate circuit 113 being closed. In fact, during the state F, the command COM18 which opens the gate circuit 113 is not generated, as a result of which the configuration 00 is present in the register 71.

The output MF of the flip-flop FF then generates directly the command COM23 (FIG. 11) which, acting on the store input circuit 47 (FIG. 2), forces into the output channel 48 the character 001011, followed by the bits contained in the register 71. To this end, the logic circuit 47 comprises a circuit 101 (FIG. 13) formed, for example, by six flip-flops which are conditioned by the command COM23 in such manner that the bit configuration 001011 is obtained at their outputs. To this configuration the circuit 101 moreover adds the two bits coming from the register 71 through the input channel 82. The configuration of eight bits is then transferred on the output channel 48. The output channel 48 constitutes the input of the store 42 (FIG. 2), so that the configuration of eight bits is written into the cell of the store 42 selected by the address contained in the register 41. This address, as has been seen, corresponds to the cell 255 of page 0. As has been said, the character 001011 defines the "re-entry jump" instruction, the bits in the register 71, on the other hand, define the current page. At the instant TR (FIG. 4), an AND circuit 247 (FIG. 11) generates the command COM04, which causes the forcing into the register 32 of the contents of the register 41 incremented by one unit, that is the character 00000000 corresponding to cell 0 of page 0.

It is therefore clear that during the state F there is written into the cell 255 of page O the re-entry jump instruction and there is forced into the addressing register 32 the address 00000000.

At the instant TS (FIG. 4) following these operations, the central unit passes to the state G, since the AND circuit DG (FIG. 5) is activated. During the state G, another AND circuit 250 (FIG. 12) generates at the instant TS the command COM01 which commands the transfer to the register 41 of the contents of the register 32, that is the address corresponding to cell 0 to page 0.

At the instant TN (FIG. 4) following the instant TS, an AND circuit 251 (FIG. 12) moreover generates a signal R0 which resets the flip-flops of the register 71 (FIG. 2) in known manner, selecting in this way the page 0. The output MG of the flip-flop FG moreover generates directly the command COM14 (FIG. 12) which, acting on the circuit 47 in the manner already seen, transfers the address in store of the last instruction in process of execution, this address being contained in the register 57 (FIG. 2), to cell 0 of page 0 of the store 42.

By means of the operations which have just been described there has therefore been compiled in the cell 255 of page 0 an instruction for a re-entry jump to the page to which belongs the address of the instruction in process of execution at the moment when the interrupt occurred. This address has moreover been stored in cell O of page 0.

After these operations, another AND circuit 252 (FIG. 12) generates at the instant TR following the instant TM (FIG. 4) the command COM26. This command, acting on a gate circuit 253 (FIG. 2), transfers the contents of the logic circuit 31 to the register 32, that is forces into the register 32 the address corresponding to the peripheral 6, 7 or 8 which has caused the interrupt. Through the channel 33 the contents of the register 32 are at the same time forced into the reset logic circuit 34. Moreover, the command COM26, acting on a gate circuit 255, transfers the possible comparison bit E from the register 96 to the register 97, where it is stored for the entire duration of the interrupt. In fact, the register 96 could be used during the interrupt itself if, for example, the interrupt contains, the instruction CFR or CDC.

If the signal INT is generated in the course of an instruction by more than one of the peripherals 6, 7, 8, at the instant TI following the instant TR (FIG. 4), an AND circuit 256 (FIG. 12) generates the command COM24 and opens a gate circuit 257 (FIG. 2). This therefore causes the resetting of the flip-flop of the register 30 corresponding to the peripheral unit of higher order of priority which has caused the interrupt. In this way, after the execution of the programme corresponding to the interrupt introduced by this peripheral, there can once more be introduced another possible interrupt corresponding to a peripheral unit of less high order of priority.

After these operations, the central unit 5 returns to the state A at the instant TS following the instant TI, inasmuch as at this instant the AND circuit DA (FIG. 5) activated by the output MG of the flip-flop FG is enabled. There is begun, therefore, the execution of the first instruction of the series of instructions relating to the interrupt, the address of which has been staticized in the register 32. Consequently, during the state A in which the central unit 5 is at the end of the interrupt, there is generated inter alia the command COM01, which permits the transfer of the address corresponding to the first instruction which is to be executed, from the register 32 to the register 41. This instruction, together with the others of the series relating to the interrupt, is then carried out under the same conditions which have been seen hereinbefore in accordance with the type of the instruction itself.

For the purpose of resuming the execution of the interrupted instructions by the central unit 5, the last instruction of the series relating to the interrupt is always an instruction for an unconditional jump to the address of cell 255 of page 0. In this cell, as has been said, there has been stored the first character of an instruction for a re-entry jump to the address defined by the second character of the instruction stored in cell O of page O following cell 255.

The re-entry jump instruction is then carried out by the central unit 5 in the manner seen hereinbefore and in fact causes the central unit 5 to return to the same conditions in which it was at the time of the interrupt. More precisely, at the end of the re-entry jump instruction there is recorded in the register 41 the address defined by the second character of the instruction itself, that is the same address of which the central unit 5 was at the instant of the interrupt. Morevoer, during the state B of the re-entry jump instruction, since the bits b4 and b5 of the modifier both assume the value 1, the command COM13 is generated by the AND circuit 258 (FIG. 7). This command, acting on a gate circuit 259 (FIG. 2), transfers the bit E from the register 97 to the register 96. In the register 96 there is therefore staticized the bit E which was therein at the moment of the interrupt. The re-entry jump instruction having been completed, return to the state A is effected, which gives rise to the continuation of the interrupted programme.

TYPEWRITER CONTROL UNIT

The controller 9 (FIGS. 1 and 14) of the typewriter 6 is adapted to control the exchange of data and commands between the typewriter 6 and the central unit 5. The input and output device 12 of the typewriter 6 comprises an input device 12' for receiving from the controller 9 the codes of the printing characters and the codes of the function characters. These codes are formed by eight bits, six of which are used to define the character, one of which is a shift bit for defining upper case and lower case, while one bit can be used, for example, as a parity bit. The six bits of the character act in known manner on a series of six electromagnets for selecting the character or the function to be effected.

The device 12 moreover comprises an output device 12" adapted to transmit to the control unit 9 the codes of the 7 characters and of the functions entered in known manner on the keyboard 270 and the keyboard 271, respectively. The transmission of the codes takes place through the switching of six switches of any known type which are not shown in FIG. 14.

The function conductor 65.sub.1 connecting the controller 9 to the central unit 5 is activated by the decoding network 65 only when this network selects, in the manner seen hereinbefore, the typewriter 6. The data are moreover exchanged with the central unit 5 through the output channel 46 connected to the store input circuit 47 of the central unit 5 and through the input channel 51 connected to the output register 50 of the central unit 5.

The input channel 51 transfers the data present in the register 50 to an eight-bit register 273 of the controller 9. The operation of the controller 9 is controlled by the central unit 5 through the external instructions COP and CAP for the reception of a command or a writing character from the central unit 5 and through the instruction CDP for the transmission of a character to the central unit 5. More precisely, the controller 9 can be put into a transmitting or receiving state by the central unit 5 by means of the instruction COP. In fact, as has been seen, the instruction COP generates two commands COM08 and COM09 which are sent through a conductor 269 to a decoding circuit 274 of the controller 9. This circuit 274 effects in known manner the decoding of the command received. If this command is the command COM08, the circuit 274 activates the output COM08', if it is the command COM09 it activates the output COM09'. These outputs put the controller 9 in the transmitting condition and the receiving condition, respectively.

If the central unit 5 proposes to receive a character from the control unit 9 by means of the instruction CDP, it sends to the control unit 9 an instruction COP which generates the command COM08. This command, together with the signal present on the conductor 65.sub.2 which selects the controller 9, activates an AND circuit 275 which acts in such manner on the reset circuit of a flip-flop 276 that it then indicates that the controller 9 is in the transmitting condition.

If the operator actuates a character key on the keyboard 270, the output device 12" activates in known manner, through a conductor 277, an AND circuit 278 enabled in turn by the flip-flop 276. The output signal of the AND circuit 278, acting on the reset circuit of a flip-flop 279, opens a gate circuit 280, so that the character entered on the keyboard 270 is transferred to the output channel 46. The conductor 277 is connected to the input 30a of the register 30 (FIG. 2), and causes in the register 30, in the manner described before, an interrupt in the operation of the central unit 5. The central unit 5 then jumps to the store address identified by the conductor 30a, corresponding to the typewriter 6 and decoded by the circuit 31. In this address there is contained the first character of an instruction CDP, whereby the central unit 5 is arranged to receive the character present on the channel 46.

If the operator actuates a function key of the keyboard 271 (FIG. 14), the keyboard emits a signal on the conductor 285, which causes in the same way as the conductor 277 the transmission of an interrupt signal to the central unit 5. This is therefore prepared to receive the function character which is present on the channel 46. The conductor 285 moreover activates an AND circuit 282 which, acting in turn on the set circuit of the flip-flop 279, opens the gate circuit 283 which places a channel 284 in communication with the output channel 46.

The keyboard 271 moreover emits on a conductor 286 a signal corresponding to the function key actuated. This signal acts on a decoding circuit 287, which supplies the code corresponding to the key actuated. This code is formed of eight bits, of which the bits b4, b5 and b6 are always zero to distinguish a function character from a printable character. This code is sent over the channel 284 and through the gate circuit 283 to the output channel 46.

If it is desired to transmit a command character to the control unit 9, the central unit 5 sends thereto on the channel 57 an instruction CAP which generates the command COM09. This command is decoded by the decoding circuit 274, which then activates the output COM09'. Through an AND circuit 290 this output acts on the set circuit of the flip-flop 276, which puts the control unit 9 into the receiving condition. This condition is identified by an output signal R of an AND circuit 291 enabled at the instant TN by the flip-flop 276. The enabling of the AND circuit 291 at the instant TN is effected since at this instant during the instruction CAP the central unit 5, as has been seen hereinbefore, has already read in the store 42 the character to be sent to the peripheral and has staticized it in the register 50 (FIG. 2) connected to the input channel 57 of the control unit 9.

In the execution of the instruction CAP, the character present on the channel 57 is then transferred by the central unit 5 to the register 273. If this character is a service character, identified as has been said by the zero bits b4, b5 and b6, a decoding circuit 299 for these bits which is connected to the register 273 emits a signal Y, while if this character is a printing character the decoding circuit 274 emits instead a signal W in a manner known per se.

In the first case, a gate circuit 295 is enabled, whereby the character present in the register 273 is sent through a channel 296 to the decoding circuit 287. This circuit supplies at an output 297 a signal which is sent through a gate circuit 298 enabled by the signal Y to the input circuit 12' of the typewriter 6. It is to be noted that the gate circuits 295 and 298 are opened only when the receiving condition obtains (R= 1) and the character is a function character (Y= 1 and W= 0).

If the character present in the register 273 is printable, the signal W enables a gate circuit 300, so that this character is transferred to the input circuit 12' of the typewriter 6. It is to be noted that the gate circuit 300 is opened only when the control unit 9 is in the receiving condition (R= 1) and the character is printable (W= 1 and Y= 0).

What has been said for a single character also applies as regards succeeding characters both being received and being transmitted.

Every time the input circuit 12' has received a character, it emits a signal on a conductor 301, which introduces an interrupt into the central unit 5 through the input 30a, so that the central unit 5 is prepared for sending another character.

On the basis of the contents of the store cell which are identified by the interrupt, the central unit 5 can now send a command or a character through a following instruction. If, for example, the control unit 9 is in the transmitting condition, the central unit 5 can send either an instruction CDP, whereby the transmission continues, or an instruction COP for reception, whereby the control unit 9 is put into the receiving condition. Of course, the character is sent from the central unit 5 by means of a following instruction CAP. It is to to be noted that the connecting of the input device 12' and the output device 12" to the register 6 have not been described in details, because it is known in the field of the machines with I/O devices to derive from the character and command signals supplied to the I/O devices, the functions associated to them. For example, if a character is to be printed, the input device 12' is able to selectively position the code bars of the typewriter 6 in order to carry out the printing of the character. In the same manner the other functions can be carried out.

COMMAND KEYBOARD CONTROL UNIT

The command keyboard 8 is used for sending a number of commands to the central unit 5 through the corresponding control unit 11. More precisely, this keyboard comprises a general switch, not shown in the drawings, for the electrical supply of all the units of the printing system. It moreover comprises a start button known per se which enables the operation of the units to be started in such manner as to cause the loading of the group of initial instructions into the store 42 of the central unit 5 in the manner hereinbefore described. These instructions moreover allow the loading into the store 42 of a particular group of instructions called the "loading" instructions which are adapted to load into the store 42 any other operative group of instructions, in the manner which will be explained hereinafter. The keyboard 8 moreover comprises an indicator lamp which is lit by means of a command coming from the central unit 5. To this end, since the exchange of commands between the central unit 5 and the keyboard 8 takes place through the medium of an instruction COP, this acts on the keyboard 8 in the manner described for the control unit 9 of the typewriter 6. More precisely, by means of the decoding circuit 65 (FIG. 2) the instruction COP selects the keyboard 8, which accepts only a particular command expressed by the second character of the instruction COP and formed by eight bits all at level one. This command acts in known manner on the keyboard 8 to produce the lighting of the indicator lamp.

The keyboard 8 in turn is adapted to send only one interrupt signal to the central unit 5 by means of the actuation of the interrupt key connected to the input 30c of the circuit 30 (FIG. 2). The interrupt key then conditions the central unit 5 in the manner seen hereinbefore to carry out a series of instructions associated with the interrupt originating from the keyboard.

MAGNETIC TAPE STORE CONTROL UNIT

The control unit 10 of the tape store 7 controls the reading and writing of addresses, programmes and data in the store 7.

The store 7 is constituted by a magnetic tape 310 (FIG. 15) closed on itself and contained in a cartridge. The cartridge is interchangeable, so that the system may comprise any number of cartridges whatsoever. The tape 310 comprises a series of parallel tracks P1, P2 . . . PN on which the data are recorded serially in blocks B1 . . . B256, each of which corresponds to a line of print. Each block is separated from an adjacent block by a zone, called the erasure zone, in which no recording takes place.

Each store block has a fixed length and comprises 80 characters each of eight bits. The characters of each block are numbered in progression (FIG. 16) from fixed 0 to 79. The characters from 6 to 78 are used for recording the data relating to a corresponding line of print, while the characters from 0 to 5 are used as function characters. More precisely, the first function character contains a constant which is used by the central unit 5 to select from among the tracks P1 . . . PN the one which contains the block in which the following characters are to be recorded. The address of this block in the limits of the track selected is defined by the second character, while the cartridge itself is identified by the third character. The fourth character indicates the number of characters that each line can contain; this number can be selected by the operator to extend or reduce, in the manner which will be seen hereinafter, the length of a line of print. The fifth character indicates the number of characters actually contained in the line of print. The sixth character indicates the code of the function to be carried out on the line, for example centring, underlining, etc. The 79th character, finally, is a longitudinal parity character relating to the remaining seventy-nine characters.

In addition to the data tracks P1 . . . PN, the tape 310 also contains a track P0 which contains the addresses I1 . . . I256 of the data blocks. Each address block I1 . . . I256 i