Running character display4970502Abstract A dot matrix type liquid crystal display panel is used with a central processor unit for displaying a message longer than the capacity of the display panel. The beginning portion of the message of a length equal to the capacity of the display panel is first displayed at one time and held on the display panel for a limited length of time facilitating the viewers' recognition of the meaning of the message. When the repeated display of the message is desired, the display state where the end of the message is in alignment with the last digit position of the display panel is held for a given length of time. The first and final holdings of the message results in enhancing legibility of the display contents on the panel. Claims What is claimed is: Description BACKGROUND OF THE INVENTION
TABLE 1
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A B D
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1 I.sub.O SKIP .circle.42
2 I.sub.O AD .circle.23 , .circle.26
3 I.sub.O ADC .circle.23 , .circle.26 , .circle.25 ,
.circle.1
4 I.sub.O ADCSK .circle.23 , .circle.26 , .circle.25 ,
.circle.50 , .circle.1
5 I.sub.O
I.sub.A
ADI .circle.24 , .circle.26 , .circle.50
6 I.sub.O
I.sub.A
DC .circle.24 , .circle.26 , .circle.50
7 I.sub.O SC .circle.21
8 I.sub.O RC .circle.22
9 I.sub.O
I.sub.A
SM .circle.2
10 I.sub.O
I.sub.A
RM .circle.3
11 I.sub.O COMA .circle.27
12 I.sub.O
I.sub.A
LDI .circle.13
13 I.sub.O
I.sub.A
L .circle.28 , .circle.8
14 I.sub.O
I.sub.A
LI .circle.28 , .circle.8 , .circle.15 ,
.circle.10 , .circle.43
15 I.sub.O
I.sub.A
XD .circle.28 , .circle.8 , .circle.14 ,
.circle.15 , .circle.10 , .circle.44
16 I.sub.O
I.sub.A
X .circle.28 , .circle.4 , .circle.8
17 I.sub.O
I.sub.A
XI .circle.28 , .circle.4 , .circle.8 ,
.circle.15 , .circle.10 , .circle.43
18 I.sub.O
I.sub.A
XD .circle.28 , .circle.4 , .circle.8 ,
.circle.14 , .circle.16 , .circle.10 ,
.circle.44
19 I.sub.O
I.sub.A
LBLI .circle.11
20 I.sub.O
I.sub.A
I.sub.B
LB .circle.8 , .circle.12
21 I.sub.O
I.sub.A
ABLI .circle. 16 , .circle.10 , .circle.43
22 I.sub.O
I.sub.A
ABMI .circle.6 , .circle.7
23 I.sub.O
I.sub.A
T .circle.20
24 I.sub.O SKC .circle.45
25 I.sub.O
I.sub.A
SKM .circle.46
26 I.sub.O
I.sub.A
SKBI .circle.48
27 I.sub.O
I.sub.A
SKAI .circle.47
28 I.sub.O SKAM .circle.49
29 I.sub.O SKN.sub.1
.circle.36
30 I.sub.O SKN.sub.2
.circle.37
31 I.sub.O SKF.sub.1
.circle.38
32 I.sub.O SKF.sub.2
.circle.39
33 I.sub.O SKAK .circle.40
34 I.sub.O SKTAB .circle.41
35 I.sub.O SKFA .circle.51
36 I.sub.O SKFB .circle.54
37 I.sub.O WIS .circle.32
38 I.sub.O WIR .circle.33
39 I.sub.O NPS .circle.34
40 I.sub.O NPR .circle.35
41 I.sub.O ATF .circle.31
42 I.sub.O LXA .circle.29
43 I.sub.O XAX .circle.29 , .circle.30
44 I.sub.O SFA .circle.52
45 I.sub.O RFA .circle.53
46 I.sub.O SFB .circle.55
47 I.sub.O RFB .circle.56
48 I.sub.O SFC .circle.17
49 I.sub.O RFC .circle.18
50 I.sub.O SFD .circle.62
51 I.sub.O RFD .circle.63
52 I.sub.O SFE .circle.65
53 I.sub.O RFE .circle.66
54 I.sub.O SKA .circle.68
55 I.sub.O SKB .circle.19
56 I.sub.O KTA .circle.57
57 I.sub.O STPO .circle.58
58 I.sub.O EXPO .circle.58 , .circle.59
59 I.sub.O
I.sub.A
TML .circle.62 , .circle.20
60 I.sub.O RIT .circle.61
61 I.sub.O
I.sub.A
I.sub.B
LNI .circle.69
62 I.sub.O READ .circle.70 , .circle.72
63 I.sub.O STOR .circle.71 , .circle.73
64 I.sub.O
I.sub.A
EX .circle.28 , .circle.4 , .circle.75 ,
.circle.16
65 I.sub.O DECB .circle.74
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Instruction Description Listed in Table 1 SKIP: Only the program counter PL is incremented without executing a next program step instruction, thus skipping a program step. AD: A binary addition is effected on the contents of the accumulator ACC and the contents of the RAM, the addition results being loaded back into the accumulator ACC. ADC: A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry F/F C, the results being loaded back to the accumulator ACC. ADCSK: A binary addition is effected on the contents of the accumulator ACC, the memory RAM and the carry flip flop C, the results being loaded into the accumulator ACC. If the fourth bit carry C.sub.4 occurs in the results, then a next program step is skipped. ADI: A binary addition is achieved upon the contents of the accumulator ACC and the operand I.sub.A and the results are loaded into the accumulator ACC. If the fourth bit carry C.sub.4 is developed in the addition results, then a next program step is skipped. DC: The operand I.sub.A is fixed as "1010" (a decimal number "10") and a binary addition is effected on the contents of the accumulator ACC and the operand I.sub.A in the same way as in the ADI instruction. The decimal number 10 is added to the contents of the accumulator ACC, the results of the addition being loaded into ACC. SC: The carry F/F C is set ("1" enters into C). RC: The carry F/F C is reset ("0" enters into C). SM: The contents of the operand I.sub.A are decoded to give access to a desired bit position of the memory specified by the operand ("1" enters). RM: The contents of the operand I.sub.A are interpreted to reset a desired bit position of the memory specified by the operand ("0" enters). COMA: The respective bits of the accumulator ACC are inverted and the resulting complement to "15" is introduced into ACC. LDI: The operand I.sub.A enters into the accumulator ACC. L: The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the file address counter BM. LI: The contents of the memory RAM are sent to the accumulator ACC and the operand I.sub.A to the memory file address counter BM. At this time the memory digit address counter BL is incremented. If the contents of BL agree with the preselected value n.sub.1, then a next program step is skipped. LD: The contents of the memory RAM are exchanged with the contents of ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is decremented. In the event that the contents of BL agree with the preselected value n.sub.2, then a next program step is skipped. X: The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is loaded into the memory file address counter BM. XI: The contents of the memory RAM are exchanged with the contents of the accumulator ACC and the operand I.sub.A is sent to the memory file address counter BM. The memory digit address counter BL is incremented. In the event that BL is equal to the preselected value n.sub.1, a next program step is skipped. XD: The contents of the memory RAM replaces the contents of the accumulator ACC, the operand I.sub.A being sent to the memory file address counter BM. The memory digit address counter BL at this time is incremented. If the contents of BL are equal to n.sub.2, then a next program step is skipped. LBLI: The operand I.sub.A is loaded into the memory digit address counter BL. LB: The operand I.sub.A is loaded into the memory file address counter BM and the operand B to the memory digit address counter BL. ABLI: The operand I.sub.A is added to the contents of the memory digit address counter BL in a binary addition fashion, the results being loaded back to BL. If the contents of BL are equal to n.sub.1, then no next program step is carried out. ABMI: The operand I.sub.A is added to the contents of the memory file address counter BM in a binary fashion, the results being into BM. T: The operand I.sub.A is loaded into the program step counter PL. SKC: If the carry flip flop C is "1", then no next program step is taken. SKM: The contents of the operand I.sub.A are decoded and a next program step is skipped as long as a specific bit position of the memory specified by the operand I.sub.A assumes "1". SKBI: The contents of the memory digit address counter BL are compared with the operand I.sub.A and a next succeeding program step is skipped when there is agreement. SKAI: The contents of the accumulator ACC are compared with theoperand I.sub.A and if both are equal to each other a next program step is skipped. SKAM: The contents of the accumulator ACC are compared with the contents of the RAM and if both are equal a next program step is skipped. SKN.sub.1 : When the input KN.sub.1 is "0", a next program step is skipped. SKN.sub.2 : When the input KN.sub.2 is "0", a next program step is skipped. SKF.sub.1 : When the input KF.sub.1 is "0", a next program step is skipped. SKF.sub.2 : When the input KF.sub.2 is "0", a next program step is skipped. SKAK: When the input AK is "1", a next program step is skipped. SKTAB: When the input TAB is "1", a next program step is skipped. SKFA: When the flag F/F F/A assumes "1" a next program step is skipped. SKFB: When the flag F/F F.sub.B assumes "1", a next program step is skipped. SKFD: When the flag F/F F.sub.D assumes "1", a next program step is skipped. SKFE: When the flag F/F F.sub.E assumes "1", a next program step is skipped. WIS: The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position) receiving "1". WIR: The contents of the output buffer register W are one bit right shifted, the first bit position (the most significant bit position being loaded with "0"). NPS: The output control F/F N.sub.p for the buffer register W is set ("1" enters). NPR: The buffer register output control flip flop N.sub.p is reset ("0" enters therein). ATF: The contents of the accumulator ACC are transferred into the output buffer register F. LXA: The contents of the accumulator ACC are unloaded into the temporary register X. XAX: The contents of the accumulator ACC are exchanged with the contents of the temporary register X. SFA: The flage F/F FA is set (an input of "1"). RFA: The flag F/F FA is reset (an input of "0"). SFB: The flag flip flop F.sub.B is set (an input of "1"). RFB: The flag flip flop F.sub.B is reset (an input of "0"). SFC: An input testing flag F/F F.sub.C is set (an input of "1"). RFC: The input testing flag F/F F.sub.C is reset (an input of "0"). SFD: The input testing flag F/F F.sub.D is set (an input of "1"). RFD: The input testing flag F/F F.sub.D is reset (an input of "0"). SFE: The input testing flag F/F F.sub.E is set (an input of "1"). RFE: The input testing flag F/F F.sub.E is reset (an input of "0"). SKA: When an input .alpha. is "1", a next program step is skipped. SKB: When an input .beta. is "1", a next program step is skipped. KTA: The inputs k.sub.1 -k.sub.4 are introduced into the accumulator ACC. STPO: The contents of the accumulator ACC are sent to the stack register SA and the contents of the temporary register X to the stack register SX. EXPO: The contents of the accumulator ACC are exchanged with the stack register SA and the contents of the temporary register X with the stack register SX. TML: The contents of the program counter P.sub.L incremented by one are transferred into the program stack register SP and the operand I.sub.A into the program counter P.sub.L. RIT: The contents of the program stack register SP are transmitted into the program counter P.sub.L. LN.sub.1 : The operands I.sub.A and I.sub.B enter the display and key input controlling flag F/Fs N.sub.1 and N.sub.2, respectively. READ: Data externally applied to D.sub.I/O are introduced into the accumulator ACC. STOR: The contents of the accumulator ACC are unloaded into D.sub.I/O. EX: The contents of the memory RAM are exchanged with that of the accumulator ACC and an exclusive-OR'ed output of the operand I.sub.A and the contents of the memory file address counter B.sub.M is supplied to B.sub.M. DECB: The memory digit address counter B.sub.L is decremented by "1". When the contents of B.sub.L are equal to the preset value n.sub.2, a next instruction is skipped. Table 2 sets forth the relationship between the operation codes contained within the ROM of the CPU structure and the operand.
TABLE 2
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I.sub.O
.THorizBrace.
AD .fwdarw.
0 0 0 1 0 1 1 0 0 0
I.sub.O
.THorizBrace.
COMA .fwdarw.
0 0 0 1 0 1 1 1 1 1
I.sub.O I.sub.A
.THorizBrace.
.THorizBrace.
SKBI .fwdarw.
0 0 0 1 1 0
0 0 1 0
I.sub.O
I.sub.A I.sub.B
.THorizBrace.
.THorizBrace.
.THorizBrace.
LB .fwdarw. 0 1 0 0 1 0 1 0
1 1
.dwnarw.
to G.sub.7
.dwnarw.
to DC.sub.5
______________________________________
wherein I.sub.O : the operation codes and
I.sub.A, I.sub.B : the operands
Taking an example wherein the output of the read only memory ROM is 10 bit long, the instruction decoder DC.sub.5 decides whether the instruction AD or COMA (see Table 1) assumes "0001011000" or "0001011111" and develops the control instructions .circle.23 , .circle.26 , or .circle.27 . SKBI is identified by the fact that the upper six bits assume "000110", the lower 4 bits "0010" being treated as the operand I.sub.A and the remaining ninth and tenth bits "11" as the operand I.sub.B. The operand forms part of instruction words and specifies data and addresses for next succeeding instructions and can be called an address area of an instruction. Major processing operations (a processing list) of the CPU structure will now be described in sufficient detail. PROCESSING LIST (I) A same numeral N is loaded into a specific region of the memory RAM (NNN.fwdarw.X) (II) A predetermined number of different numerals are loaded into a specific region of the memory (N.sub.1, N.sub.2, N.sub.3, . . . .fwdarw.X) (III)The contents of a specific region of the memory are transferred into a different region of the memory (X.fwdarw.Y) (IV)The contents of a specific region of the memory are exchanged with that of a different region (X.fwdarw.Y) (V) A given numeral N is added or subtracted in a binary fashion from the contents of a specific region of the memory (X.+-.N) (VI) The contents of a specific region of the memory are added in a decimal fashion to the contents of a different region (X.+-.Y) (VII)The contents of a specific region of the memory are one digit shifted (X right, X left) (VIII) A one bit conditional F/F associated with a specific region of the memory is set or reset (F set, F reset) (IX) The state of the one bit conditional F/F associated with a specific region of the memory is sensed and a next succeeding program address is changed according to the results of the state detection. (X) It is decided whether the digit contents of a specific region of the memory reach a preselected numeral and a next succeeding program step is altered according to the results of such decision. (XI) It is decided whether the plural digit contents of a specific region of the memory are equal to a preselected numeral and a program step is altered according to the results of the decision. (XII) It is decided whether the digit contents of a specific region of the memory are smaller than a given value and a program step to be next executed is changed according to the decision. (XIII) It is decided whether the contents of a specific region of the memory are greater than a given value and the results of such decision alter a program step to be next executed. (XIV) The contents of a specific region of the memory are displayed. (XV) What kind of a key switch is actuated is decided. (XVI) The external memory is shifted digit by digit within the same memory file address. The above processing events in (I)-(XVI) above are executed according to the instruction codes step by step in the following manner.
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(I) PROCEDURE OF LOADING A SAME VALUE A INTO
A SPECIFIC REGION OF THE MEMORY (NNN .fwdarw. X)
(Type 1)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.A
n.sub.E
P.sub.2
LBI .dwnarw.
N
P.sub.3
XD .dwnarw.
n.sub.A
P.sub.4
T .dwnarw.
P.sub.2
.dwnarw.
P: Step
(Type 2)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
LDI .dwnarw.
N
P.sub.3
XD .dwnarw.
.dwnarw.
(Type 3)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.C
n.sub.C
P.sub.2
LDI .dwnarw.
N
P.sub.3
XD .dwnarw.
m.sub.C
P.sub.4
SKBI .dwnarw.
n.sub.A
P.sub.5
T .dwnarw.
P.sub.2
.dwnarw.
(II) PROCEDURE OF LOADING A PREDETERMINED
NUMBER OF DIFFERENT VALUES INTO A SPECIFIC
REGION OF THE MEMORY
(N.sub.1, N.sub.2, N.sub.3, . . . .fwdarw. X)
(Type 1)
.dwnarw.
P.sub.1
LB m.sub.A
n.sub.E
P.sub.2
LDI .dwnarw.
N.sub.1
P.sub.3
XI .dwnarw.
m.sub.A
P.sub.4
LDI .dwnarw.
N.sub.2
P.sub.5
XI .dwnarw.
m.sub.A
P.sub.6
LDI .dwnarw.
N.sub.3
P.sub.7
XI .dwnarw.
m.sub.A
P.sub.8
LDI .dwnarw.
N.sub.4
P.sub.9
XI .dwnarw.
m.sub.A
(Type 2)
.dwnarw.
P.sub.1
LDI .dwnarw.
N
P.sub.2
LXA .THorizBrace.
.dwnarw.
(III) PROCEDURE OF TRANSFERRING THE CONTENTS
OF A SPECIFIC REGION OF THE MEMORY TO A
DIFFERENT REGION OF THE MEMORY (X .fwdarw. Y)
(Type 1)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.A
n.sub.E
P.sub.2
L .dwnarw.
m.sub. B
P.sub.3
XI .dwnarw.
m.sub.A
T .dwnarw.
P.sub.2
(Type 2)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
L .dwnarw.
m.sub.C
P.sub.3
LBLI .dwnarw.
n.sub.O
P.sub.4
X .dwnarw.
.dwnarw.
(Type 3)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
L .dwnarw.
P.sub.3
LXA .dwnarw.
.dwnarw.
(Type 4)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
L .dwnarw.
m.sub.8
P.sub.3
XAX .dwnarw.
P.sub.4
X .dwnarw.
.dwnarw.
(IV) PROCEDURE OF EXCHANGING CONTENTS
BETWEEN A SPECIFIC REGION OF THE MEMORY AND
A DIFFERENCE REGION (X .fwdarw. Y)
(Type 1)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.A
n.sub.E
P.sub.2
L .dwnarw.
m.sub.B
P.sub.3
X .dwnarw.
m.sub.A
P.sub.4
XI .dwnarw.
m.sub.A
P.sub.5
T .dwnarw.
P.sub.2
.dwnarw.
(Type 2)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
L .dwnarw.
m.sub.C
P.sub.3
LBLI .dwnarw.
n.sub.O
P.sub.4
X .dwnarw.
m.sub.B
P.sub.5
LBLI .dwnarw.
n.sub.C
P.sub.6
X .dwnarw.
.dwnarw.
(Type 3)
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
L .dwnarw.
m.sub.C
P.sub.3
X .dwnarw.
m.sub.B
P.sub.4
X .dwnarw.
.dwnarw.
(V) PROCEDURE OF EFFECTING A BINARY ADDITION
OR SUBTRACTION OF A GIVEN VALUE N ONTO A
SPECIFIC REGION OF THE MEMORY
(Type 1) M.sub.1 + N .fwdarw. M
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
L .dwnarw.
m.sub.B
P.sub.3
ADI .dwnarw.
N
P.sub.4
X .dwnarw.
.dwnarw.
(Type 2) X + N .fwdarw. X
.dwnarw.
P.sub.1
XAX
P.sub.2
ADI .dwnarw.
N
P.sub.3
XAX
.dwnarw.
(Type 3) M.sub.1 + N .fwdarw. M.sub.2
.dwnarw.
P.sub.1
LB .dwnarw.
m.sub.B
n.sub.C
P.sub.2
L .dwnarw.
m.sub.C
P.sub.3
ADI .dwnarw.
The foregoing is the description of the respective major processing events in the CPU architecture. By reference to FIG. 5 an example of the display operation implementing the present invention will now be decribed in detail. For example, if the displaying of a character "I" is desired, each display panel digit being of a 7.times.5 dot matrix is divided into an upper half and a lower half and encoded information is defined as "11F1144744" in the descending order. This is accomplished by sending selected ones of the segment signals S1-S126 and selected ones of the opposite electrode signals H1-H7 to dot positions necessary for the displaying of the character "I". As indicated in FIG. 5(b), each digit 0, 1, 2, . . . 9, A, B, . . . F of the encoded information consists of their unique combination of 4 bits. The enabling waveform signals and disabling waveform signals are provided when the respective bits have "1" and "0", respectively. The display data storage section DRM as shown in FIG. 6 is for temporarily storing those display encoded data. The respective segments (1)-(21) store independently the encoded information characteristic of characters to be displayed. In the illustrated example, the segment (1) stores the encoded information "11F1144744" associated with the character "I". The display data storage section DRM has a 21 digit capacity. Of those digits the 12 digit long data contained within the segments (1)-(12) in FIG. 6 may appear on the display panel DSP at a time. Additionally, 21 digit long data may be stored in the external memory unit MU in the same manner as in FIG. 6. It is therefore possible to display a total of 42 digits on the display panel DSP with accompanying shift operation through a combination of the display data storage section DRM and the external memory unit MU. FIG. 7 is a typical display state of the display panel DSP. In order to display of a full message consisting of multi characters longer than the maximum possible display of 12 digits, "MAY I ASK YOU TO POST THIS LETTER ?", the maximum possible digits are first displayed at a time as depicted in FIG. 7(1) and held for a given length of time as depicted in FIGS. 7(1) to 7(2). Thereafter, the characters are shifted digit by digit as depicted in FIGS. 7(3)-7(7). To repeat the displaying of this sentence, the state of FIG. 7(7) is held for a limited period of time as shown in FIG. 7(8). The final characters of the sentence are held in this manner so that it becomes easier to appreciate the end of the message. As indicated in FIG. 7(9) the overall message then disappears from the display panel for a time and the displaying of the sentence resumes. FIG. 8 is a flow chart for achieving the display operation in FIG. 7. The steps n.sub.1 -n.sub.4 are executed to place the leading portion of the sentence to be displayed in alignment with the left extremity of the display in the shifting direction. The steps n.sub.7 and n.sub.8 or n.sub.10 or n.sub.8 are to perform display operation. The effect of the steps n.sub.9, n.sub.11, n.sub.12 and n.sub.13 is to place the end of the sentence in alignment with the right extremity of the display in FIG. 7 in the shifting direction. Likewise the steps n.sub.14 and n.sub.15 the steps n.sub.7 and n.sub.8 have the same effect of holding the display contents for the limited period of time. During the step n.sub.1 the contents of the display data storage section DRM in the display control circuitry DSC and those of the external memory unit MU are shifted by one digit or 6 dots. The step n.sub.2 decides whether the segment (1) in the display data storage section DRM in FIG. 6 corresponding to the leading digit position is vacant. The steps n.sub.3 and n.sub.4 do the same job. Each sentence has a total number of characters and spaces no greater than 40. Each space is no more than one character long. If the vacant space lasts for more than one character, the display operation proceeds with the steps n.sub.5 and n.sub.6. Provided that the step n.sub.6 senses a character after one vacant space, the step n.sub.7 would be in effect whereby a given value Na is fed into the register X. The step n.sub.8 holds this stage of operation for the length of time corresponding to the given value Na. In this manner, the display states as depicted in FIGS. 7(1) and 7(2) are ensured. The effect of the steps n.sub.11 and n.sub.13 is to determine the contents of segment (13) of the display data storage section DRM corresponding to the second last digit position along the shifting direction. A chain of the steps n.sub.9, n.sub.11, n.sub.12 and n.sub.13 senses if the vacant space persists for at least two digit positions. If not, the step n.sub.10 is executed to supply the given value Nb to the register X. The present display state is held only for the limited period corresponding to the given value Nb and then shifted. This results in the display operation starting from FIG. 7(2) and ending at FIG. 7(7). When the space lasts for two digit positions or more, the steps n.sub.14 and n.sub.15 hold the display state as shown in FIGS. 7(7) and (8) for the length of time as determined by the value Na. The display data then disappear from the panel for a while before execution of the steps n.sub.1 through n.sub.7. This is depicted in FIG. 7(9). The above mentioned procedure completes a cycle of the display operation according to the present invention. FIG. 9 details the steps n.sub.8 and n.sub.15 of FIG. 8 wherein the display operation is triggered by supplying the display/disable signal DIS to the display control circuitry DSC during the step m.sub.1. At the next succeeding step m.sub.2 the register X already loaded with the given value is decremented. The steps m.sub.2 and m.sub.3 are carried out repeatedly until X=0 at the step m.sub.3. When X=0, the display/disable control signal DIS disables the display panel at the step m.sub.4. The steps m.sub.2 and m.sub.3 correspond to the processing events (V) and (X). FIG. 10 details the steps n.sub.11 and n.sub.13 of FIG. 8 for deciding if the addresses BMBL: 8A and 9A of the display data storage section DRM are zero. It will be noted that BMBL: 8A means that the memory file address BM is "8" and the memory digit address BL is "A". BMBL:8A and BMBL:9A contain data corresponding to the intermediate longitudinal 8 dots of a chatacter to be displayed at the last digit position along the shifting position. All of the characters consisting of the 5.times.7 dot matrix except for special symbols may be displayed by actuating at least a dot in the intermediate longitudinal 7 dots. It can be regarded as vacant unless at least one of the intermediate longitudinal 7 dots of the 5.times.7 dot matrix are actuated. FIG. 11 shows the steps nhd 2, n.sub.4 and n.sub.6 of FIG. 8 in more detail. Those steps are to decide if the contents of the display data storage section DRM at the addresses BLBM: 02 and 12 are zero. These addresses correspond to the foremost digit position in the shifting direction. Those steps are carried out in the same manner as shown in FIG. 10. It is appreciated that the steps n.sub.1, n.sub.3, n.sub.5 and n.sub.12 of FIG. 8 are effected based upon the processing events (22) and (3) of type 4 and the steps n.sub.7, n.sub.10 and n.sub.14 based upon the processing event (2). While the characters are shifted digit by digit in the above illustrated embodiment, they may be shifted dot by dot along the shifting direction as an alternative. In the case where a train of characters is displayed only once, the steps n.sub.14 and n.sub.15 of FIG. 8 may be eliminated. Whereas the present invention has been described with respect to a specific embodiment, it will be understood that various changes and modifications will be suggested to one skilled in the art, and it is intended to encompass such changes and modifications as fall within the scope of the appended claims.
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