System and method for slot based ARL table learning and concurrent table search using range address insertion blocking6965945Abstract A network device including at least one network port, a clock, address resolution (ARL) tables, and address resolution logic. The at least one network port is configured to send and receive a data packet. The clock is for generating a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and configured to perform a search and an update to data into the ARL tables based on the data packet, to calculate a current range of the search, to determine an intended result of the update, and to block the update when the intended result will move data out of the current range of the search, the search and the update being performed concurrently during alternating slots of the timing signal. Claims 1. A network device comprising: Description BACKGROUND OF THE INVENTION
The opcode field of the P-channel message defines the type of message currently being sent. While the opcode is currently shown as having a width of 2 bits, the opcode field can be widened as desired to account for new types of messages as may be defined in the future. Graphically, however, the P-channel message type defined above is shown in FIG. 4. An early termination message is used to indicate to CBM 71 that the current packet is to be terminated. During operation, as discussed in more detail below, the status bit(S) field in the message is set to indicate the desire to purge the current packet from memory. Also, in response to the status bit, all applicable egress ports would purge the current packet prior to transmission. The Src Dest Port field of the P-channel message, as stated above, define the destination and source port addresses, respectively. Each field is 6 bits wide and therefore allows for the addressing of sixty-four ports. The CRC field of the message is two bits wide and defines CRC actions. Bit 0 of the field provides an indication whether the associated egress port should append a CRC to the current packet. An egress port would append a CRC to the current packet when bit 0 of the CRC field is set to a logical one. Bit 1 of the CRC field provides an indication whether the associated egress port should regenerate a CRC for the current packet. An egress port would regenerate a CRC when bit 1 of the CRC field is set to a logical one. The CRC field is only valid for the last cell transmitted as defined by the E bit field of P-channel message set to a logical one. As with the CRC field, the status bit field (st), the Len field, and the Cell Count field of the message are only valid in this example for the last cell of a packet being transmitted as defined by the E bit field of the message. Last, the time stamp field of the message in this example has a resolution of 1 μs and is valid only for the first cell of the packet defined by the S bit field of the message. A cell is defined as the first cell of a received packet when the S bit field of the message is set to a logical one value. The C channel 81 and the P channel 82 are synchronously tied together such that data on C channel 81 is transmitted over the CPS channel 80 while a corresponding P channel message is simultaneously transmitted. S-Channel or Sideband Channel The S channel 83 can be a 32-bit wide channel which provides a separate communication path within the SOC 10. The S channel 83 is used for management by CPU 52, SOC 10 internal flow control, and SOC 10 intermodule messaging. The S channel 83 is a sideband channel of the CPS channel 80, and is electrically and physically isolated from the C channel 81 and the P channel 82. It is important to note that since the S channel is separate and distinct from the C channel 81 and the P channel 82, operation of the S channel 83 can continue without performance degradation related to the C channel 81 and P channel 82 operation. Conversely, since the C channel is not used for the transmission of system messages, but rather only data, there is no overhead associated with the C channel 81 and, thus, the C channel 81 is able to free-run as needed to handle incoming and outgoing packet information. The S channel 83 of CPS channel 80 provides a system wide communication path for transmitting system messages, for example, providing the CPU 52 with access to the control structure of the SOC 10. System messages include port status information, including port link status, receive port full, and port statistics, ARL table 22 synchronization, CPU 52 access to GBP 60 and CBP 50 memory buffers and SOC 10 control registers, and memory full notification corresponding to GBP 60 and/or CBP 50. FIG. 5 illustrates an exemplary message format for an S channel message on S channel 83. The message is formed of four 32-bit words; the bits of the fields of the words are defined as follows:
With the configuration of CPS channel 80 as explained above, the decoupling of the S channel from the C channel and the P channel is such that the bandwidth on the C channel can be preserved for cell transfer, and that overloading of the C channel does not affect communications on the sideband channel. SOC Operation The configuration of the SOC 10 can support fast Ethernet ports, gigabit ports, and extendible interconnect links as discussed above. The SOC configuration can also be "stacked" or "linked", thereby enabling significant port expansion capability. Once data packets have been received by SOC 10, sliced into cells, and placed on CPS channel 80, stacked SOC modules can interface with the CPS channel and monitor the channel, and extract appropriate information as necessary. As will be discussed below, a significant amount of concurrent lookups and filtering occurs as the packet comes in to ingress submodule 14 of an EPIC 20 or GPIC 30, with respect to layer two and layer three lookups, and fast filtering, according to the present invention. Table management may also be achieved through the use of the CPU 52. CPU 52, via the CMIC 40, can provide the SOC 10 with software functions which result in the designation of the identification of a user at a given port 24. As discussed above, it is undesirable for the CPU 52 to access the packet information in its entirety since this would lead to performance degradation. Rather, the SOC 10 is programmed by the CPU 52 with identification information concerning the user. The SOC 10 can maintain real-time data flow since the table data communication between the CPU 52 and the SOC 10 occurs exclusively on the S channel 83. While the SOC 10 can provide the CPU 52 with direct packet information via the C channel 81, such a system setup is undesirable for the reasons set forth above. As stated above, as an ingress function an address resolution lookup is performed by examining the ARL table 21a. If the packet is addressed to one of the layer three (L3) switches of the SOC 10, then the ingress sub-module 14a performs the L3 and default table lookup. Once the destination port has been determined, the EPIC 20a sets a ready flag in the dispatch unit 18a which then arbitrates for C channel 81. The C channel 81 arbitration scheme, as discussed previously, may be a Demand Priority Round-Robin. Each I/O module, EPIC 20, GPIC 30, and CMIC 40, along with the PMMU 70, can initiate a request for C channel access. If no requests exist at any one given time, a default module established with a high priority gets complete access to the C channel 81. If any one single I/O module or the PMMU 70 requests C channel 81 access, that single module gains access to the C channel 81 on-demand. If EPIC modules 20a, 20b, 20c, and GPIC modules 30a and 30b, and CMIC 40 simultaneously request C channel access, then access may be granted in round-robin fashion. For a given arbitration time period each of the I/O modules would be provided access to the C channel 81. For example, each GPIC module 30a and 30b would be granted access, followed by the EPIC modules, and finally the CMIC 40. After every arbitration time period the next I/O module with a valid request would be given access to the C channel 81. This pattern would continue as long as each of the I/O modules provide an active C channel 81 access request. If all the I/O modules, including the PMMU 70, request C channel 81 access, the PMMU 70 is granted access as shown in FIG. 4B since the PMMU provides a critical data path for all modules on the switch. Upon gaining access to the channel 81, the dispatch unit 18a proceeds in passing the received packet 112, one cell at a time, to C channel 81. Referring again to FIG. 3, the individual C, P, and S channels of the CPS channel 80 are shown. Once the dispatch unit 18a has been given permission to access the CPS channel 80, during the first time period Cn0, the dispatch unit 18a places the first 16 bytes of the first cell 112a of the received packet 112 on the C channel 81. Concurrently, the dispatch unit 18a places the first P channel message corresponding to the currently transmitted cell. As stated above, the first P channel message defines, among other things, the message type. Therefore, this example is such that the first P channel message would define the current cell as being a unicast type message to be directed to the destination egress port 21c. During the second clock cycle Cn1, the second 16 bytes (16:31) of the currently transmitted data cell 112a are placed on the C channel 81. Likewise, during the second clock cycle Cn1, the Bc/Mc Port Bitmap is placed on the P channel 82. As indicated by the hatching of the S channel 83 data during the time periods Cn0 to Cn3 in FIG. 3, the operation of the S channel 83 is decoupled from the operation of the C channel 81 and the P channel 82. For example, the CPU 52, via the CMIC 40, can pass system level messages to non-active modules while an active module passes cells on the C channel 81. As previously stated, this is an important aspect of the SOC 10 since the S channel operation allows parallel task processing, permitting the transmission of cell data on the C channel 81 in real-time. Once the first cell 112a of the incoming packet 112 is placed on the CPS channel 80 the PMMU 70 determines whether the cell is to be transmitted to an egress port 21 local to the SOC 10. If the PMMU 70 determines that the current cell 112a on the C channel 81 is destined for an egress port of the SOC 10, the PMMU 70 takes control of the cell data flow. FIG. 6 illustrates, in more detail, the functional egress aspects of PMMU 70. PMMU 70 includes CBM 71, and interfaces between the GBP, CBP and a plurality of egress managers (EgM) 76 of egress submodule 18, with one egress manager 76 being provided for each egress port. CBM 71 is connected to each egress manager 76, in a parallel configuration, via R channel data bus 77. R channel data bus 77 is a 32-bit wide bus used by CBM 71 and egress managers 76 in the transmission of memory pointers and system messages. Each egress manager 76 is also connected to CPS channel 80, for the transfer of data cells 112a and 112b. CBM 71, in summary, performs the functions of on-chip FAP (free address pool) management, transfer of cells to CBP 50, packet assembly and notification to the respective egress managers, rerouting of packets to GBP 60 via a global buffer manager, as well as handling packet flow from the GBP 60 to CBP 50. Memory clean up, memory budget management, channel interface, and cell pointer assignment are also functions of CBM 71. With respect to the free address pool, CBM 71 manages the free address pool and assigns free cell pointers to incoming cells. The free address pool is also written back by CBM 71, such that the released cell pointers from various egress managers 76 are appropriately cleared. Assuming that there is enough space available in CBP 50, and enough free address pointers available, CBM 71 maintains at least two cell pointers per egress manager 76 which is being managed. The first cell of a packet arrives at an egress manager 76, and CBM 71 writes this cell to the CBM memory allocation at the address pointed to by the first pointer. In the next cell header field, the second pointer is written. The format of the cell as stored in CBP 50 is shown in FIG. 7; each line is 18 bytes wide. Line 0 contains appropriate information with respect to first cell and last cell information, broadcast/multicast, number of egress ports for broadcast or multicast, cell length regarding the number of valid bytes in the cell, the next cell pointer, total cell count in the packet, and time stamp. The remaining lines contain cell data as 64 byte cells. The free address pool within PMMU 70 stores all free pointers for CBP 50. Each pointer in the free address pool points to a 64-byte cell in CBP 50; the actual cell stored in the CBP is a total of 72 bytes, with 64 bytes being byte data, and 8 bytes of control information. Functions such as HOL blocking high and low watermarks, out queue budget registers, CPID assignment, and other functions are handled in CBM 71 within the PMMU 70. When PMMU 70 determines, e.g., by a table look-up (i.e., a search described further below), that cell 112a is destined for an appropriate egress port on SOC 10, PMMU 70 controls the cell flow from CPS channel 80 to CBP 50. As the data packet 112 is received at PMMU 70 from CPS 80, CBM 71 determines whether or not sufficient memory is available in CBP 50 for the data packet 112. A free address pool (not shown) can provide storage for at least two cell pointers per egress manager 76, per class of service. If sufficient memory is available in CBP 50 for storage and identification of the incoming data packet, CBM 71 places the data cell information on CPS channel 80. The data cell information is provided by CBM 71 to CBP 50 at the assigned address. As new cells are received by PMMU 70, CBM 71 assigns cell pointers. The initial pointer for the first cell 112a points to the egress manager 76 which corresponds to the egress port to which the data packet 112 will be sent after it is placed in memory. In the example of FIG. 6, packets come in to port 24a of EPIC 20a, and are destined for port 24c of EPIC 20c. For each additional cell 112b, CBM 71 assigns a corresponding pointer. This corresponding cell pointer is stored as a two byte or 16 bit value NC—header, in an appropriate place on a control message, with the initial pointer to the corresponding egress manager 76, and successive cell pointers as part of each cell header, a linked list of memory pointers is formed which defines packet 112 when the packet is transmitted via the appropriate egress port, in this case 24c. Once the packet is fully written into CBP 50, a corresponding CBP Packet Identifier (CPID) is provided to the appropriate egress manager 76; this CPID points to the memory location of initial cell 112a. The CPID for the data packet is then used when the data packet 112 is sent to the destination egress port 24c. In actuality, the CBM 71 maintains two buffers containing a CBP cell pointer, with admission to the CBP being based upon a number of factors. Since CBM 71 controls data flow within SOC 10, the data flow associated with any ingress port can likewise be controlled. When packet 112 has been received and stored in CBP 50, a CPID is provided to the associated egress manager 76. The total number of data cells associated with the data packet is stored in a budget register (not shown). As more data packets 112 are received and designated to be sent to the same egress manager 76, the value of the budget register corresponding to the associated egress manager 76 is incremented by the number of data cells 112a, 112b of the new data cells received. The budget register therefore dynamically represents the total number of cells designated to be sent by any specific egress port on an EPIC 20. CBM 71 controls the inflow of additional data packets by comparing the budget register to a high watermark register value or a low watermark register value, for the same egress. FIG. 8 illustrates some of the concurrent filtering and look-up details of a packet coming into the ingress side of an EPIC 20 according to the present invention. FIG. 8 addresses the application of filtering, address resolution, and rules application segments of SOC 10. These functions are performed simultaneously with respect to the CBP admission. Packet 112 is received at input port 24 of EPIC 20. It is then directed to input FIFO 142. As soon as the first sixteen bytes of the packet arrive in the input FIFO 142, the address resolution logic performs a lookup in the ARL/L3 tables 21. The address resolution logic may include an ARL engine 143 which receives an address resolution request in order to initiate a lookup in ARL/L3 tables 21. A description of the fields that may be contained in an ARL table of ARL/L3 tables 21 is as follows:
It should also be noted that VLAN tables 23 may include a number of table formats; all of the tables and table formats will not be discussed herein. However, as an example, the port based VLAN table fields are described as follows:
The ARL engine 143 reads the packet; if the packet has a VLAN tag according to IEEE Standard 802.1q, then ARL engine 143 performs a look-up based upon tagged VLAN table 231, which is part of VLAN table 23. If the packet does not contain this tag, then the ARL engine performs VLAN lookup based upon the port based VLAN table 232. Once the VLAN is identified for the incoming packet, ARL engine 143 performs an ARL table search based upon the source MAC address and the destination MAC address. This search may be a binary search. If the results of the destination search is an L3 interface MAC address, then an L3 search is performed of an L3 table within ARL/L3 tables 21. If the L3 search is successful, then the packet is modified according to packet routing rules and the ARL tables are updated according to the description above. To better understand lookups, learning, and switching, it may be advisable to once again discuss the handling of packet 112 with respect to FIG. 6. If data packet 112 is sent from a source station A into port 24a of EPIC 20a, and destined for a destination station B on port 24c of EPIC 20c, ingress submodule 14a slices data packet 112 into cells 112a and 112b. The ingress submodule then reads the packet to determine the source MAC address and the destination MAC address. As discussed previously, ingress submodule 14a, in particular ARL engine 143, performs the lookup of appropriate tables within ARL/L3 tables 21a, and VLAN table 23a, to see if the destination MAC address exists in ARL/L3 tables 21a; if the address is not found, but if the VLAN IDs are the same for the source and destination, then ingress submodule 14a will set the packet to be sent to all ports. The packet will then propagate to the appropriate destination address. A "source search" and a "destination search" may be binary searches and may occur in parallel. Concurrently, the source MAC address of the incoming packet can be "learned", and therefore added to an ARL table within ARL/L3 table 21a. After the packet is received by the destination, an acknowledgement is sent by destination station B to source station A. Since the source MAC address of the incoming packet is learned by the appropriate table of B, the acknowledgement is appropriately sent to the port on which A is located. When the acknowledgement is received at port 24a, therefore, the ARL table learns the source MAC address of B from the acknowledgement packet. It should be noted that as long as the VLAN IDs (for tagged packets) of source MAC addresses and destination MAC addresses are the same, layer two switching as discussed above is performed. L2 switching and lookup is therefore based on the first 16 bytes of an incoming packet. For untagged packets, the port number field in the packet is indexed to the port-based VLAN table within VLAN table 23a, and the VLAN ID can then be determined. If the VLAN IDs are different, however, L3 switching is necessary wherein the packets are sent to a different VLAN. L3 switching, however, is based on the IP header field of the packet. The IP header includes source IP address, destination IP address, and TTL (time-to-live). In order to more clearly understand layer three switching, data packet 112 is sent from source station A onto port 24a of EPIC 20a, and is directed to destination station B; assume, however, that station B is disposed on a different VLAN, as evidenced by the source MAC address and the destination MAC address having differing VLAN IDs. The lookup for B would be unsuccessful since B is located on a different VLAN, and merely sending the packet to all ports on the VLAN would result in B never receiving the packet. Layer three switching, therefore, enables the bridging of VLAN boundaries, but requires reading of more packet information than just the MAC addresses of L2 switching. In addition to reading the source and destination MAC addresses, therefore, ingress 14a also reads the IP address of the source and destination. As noted previously, packet types are defined by IEEE and other standards, and are known in the art. By reading the IP address of the destination, SOC 10 is able to target the packet to an appropriate router interface which is consistent with the destination IP address. Packet 112 may therefore be sent on to CPS channel 80 through dispatch unit 18a, destined for an appropriate router interface (not shown, and not part of SOC 10), upon which destination B is located. Control frames, identified as such by their destination address, are sent to CPU 52 via CMIC 40. The destination MAC address, therefore, is the router MAC address for B. The router MAC address may be learned through hardware or with the assistance of CPU 52, which uses an ARP (address resolution protocol) request to request the destination MAC address for the router for B, based upon the IP address of B. Through the use of the IP address, therefore, SOC 10 can learn the destination MAC address. Through the acknowledgement and learning process, however, if the CPU 52 is used for learning, only the first packet is subject to "slow" handling because of the involvement of CPU 52. After the appropriate MAC addresses are learned, linespeed switching can occur through the use of concurrent table lookups since the necessary information will be learned by the tables. Implementing the tables in silicon as two-dimensional arrays enables such rapid concurrent lookups. Once the MAC address for B has been learned, therefore, when packets come in with the IP address for B, ingress 14a changes the IP address to the destination MAC address, in order to enable linespeed switching. Also, the source address of the incoming packet is changed to the router MAC address for A rather than the IP address for A, so that the acknowledgement from B to A can be handled in a fast manner without needing to utilize a CPU on the destination end in order to identify the source MAC address to be the destination for the acknowledgement. Additionally, a TTL (time-to-live) field in the packet is appropriately manipulated in accordance with the IETF (Internet Engineering Task Force) standard. A unique aspect of SOC 10 is that all of the switching, packet processing, and table lookups are performed in hardware, rather than requiring CPU 52 or another CPU to spend time processing instructions. It should be noted that the layer three tables for EPIC 20 can have varying sizes. Referring again to the discussion of FIG. 8, as soon as the first sixty four bytes of the packet arrive in input FIFO 142, a filtering request is sent to FFP 141. FFP 141 is an extensive filtering mechanism which enables SOC 10 to set inclusive and exclusive filters on any field of a packet from layer 2 to layer 7 of the OSI seven layer model. Filters are used for packet classification based upon a protocol fields in the packets. Various actions may be performed based upon the packet classification, including packet discard, sending of the packet to the CPU, sending of the packet to other ports, sending the packet on certain COS priority queues, changing the type of service (TOS) precedence. An exclusive filter is primarily used for implementing security features, and allows a packet to proceed only if there is a filter match. If there is no match, the packet is discarded. It should be noted that SOC 10 has a unique capability to handle both tagged and untagged packets coming in. Tagged packets are tagged in accordance with IEEE standards, and include a specific IEEE 802.1p priority field for the packet. Untagged packets, however, do not include an 802.1p priority field therein. SOC 10 can assign an appropriate COS value for the packet, which can be considered to be equivalent to a weighted priority, based either upon the destination address or the source address of the packet, as matched in one of the table lookups. As noted in the ARL table format discussed herein, an SCP (Source COS Priority) bit is contained as one of the fields of the table. When this SCP bit is set, then SOC 10 can assign weighted priority based upon a source COS value in the ARL table. If the SCP is not set, then SOC 10 will assign a COS for the packet based upon the destination COS field in the ARL table. These COS of values are three bit fields in the ARL table, as noted previously in the ARL table field descriptions. FFP 141 is essentially a state machine driven programmable rules engine. The filters used by the FFP may be, for example, 64 (sixty-four) bytes wide, and are applied on an incoming packet; any offset can be used, however, a preferred embodiment uses an offset of zero, and therefore operates on the first 64 bytes, or 512 bits, of a packet. The actions taken by the filter may include tag insertion, priority mapping, TOS tag insertion, sending of the packet to the CPU, dropping of the packet, forwarding of the packet to an egress port, and sending the packet to a mirrored port. The filters utilized by FFP 141 are defined by rules table 22. Rules table 22 may be programmable by CPU 52, through CMIC 40. The rules table can be, for example, 256 entries deep, and may be partitioned for inclusive and exclusive filters, with, again as an example, 128 entries for inclusive filters and 128 entries for exclusive filters. It should also be noted that the block diagram of SOC 10 in FIG. 2 illustrates each GPIC 30 having its own ARL/L3 tables 31, rules table 32, and VLAN tables 33, and also each EPIC 20 also having its own ARL/L3 tables 21, rules table 22, and VLAN tables 23. In a preferred embodiment of the invention, however, two separate modules can share a common ARL/L3 table and a common VLAN table. Each module, however, may have its own rules table 22. For example, therefore, GPIC 30a may share ARL/L3 table 21a and VLAN table 23a with EPIC 20a. Similarly, GPIC 30b may share ARL table 21b and VLAN table 23b with EPIC 20b. This sharing of tables reduces the number of gates which are required to implement the invention, and makes for simplified lookup and synchronization as will be discussed below. In support of high-speed switching, the present invention includes improved systems and methods for performing searching and learning concurrently. Table searching typically has priority over learning. However, to optimize switching performance, it is desired to guarantee some bandwidth to learning. Thus, according to the present invention, table access may be delegated in a slotted fashion. For example, referring to FIG. 9, a timing signal (e.g., a clock signal, square wave, etc.) may be slotted into three slots. Each slot may be dedicated to searching or learning. For example, access to Rules table 22 may be limited based on slots of the timing signal. SA0 and SB0 represent the first steps of two binary searches SA and SB. L0 represents a learning step, such as an update or insert, as described above. Each three slots represents a single cycle. As shown, each complete cycle is a learning and searching cycle. Thus, a portion (slot) of every cycle is dedicated to performing searching functions and a portion of every cycle is dedicated to learning functions. However, allowing learning to occur while searches are being performed causes some problems that need to be addressed (i.e., problems caused by shared table access). In order to better understand the relationship between learning and searching, a brief discussion of binary searching according to the present invention is provided next. Referring to FIG. 10, shown is an exemplary table 1100 to be searched, which could be any of the on-chip tables already described above. Assuming that table 1000 is sorted in an order and indexed or keyed, a binary search is extremely efficient. Binary search steps are illustrated by curved arrows. First, a search begins in the center of a memory bank (unless it's indexed). As an example, the table has 128 rows or memory units (word lines, etc.). Therefore, the search begins at row 64. The search engine or facility controlling the search, such as the FFP 141, PMMU 70 or CBM 71, compares the value stored in row 64 against the search criteria. If the value is greater than or less than the search criteria, then the search jumps up or down, respectively, a number of rows equal to 2(m-n), where m is logarithm of the number of rows in the table, and n is the number of the current search step. For example, in a 128 row table, step 1 begins at row 64=2(m-n)=27-1=26. At step 2, the next jump is plus or minus 25=32, therefore, the search jumps down to 32 or up to 96 depending on the result of the comparison. The search continues jumping until a match is found, that is, until the value not higher or low than the search criteria. As an example, if the match is in a row 21, the process steps from 64 to 32 at step 1, because 21 is less than 64. Next, at step 2, the search jumps from 32 to 16. Since 21 is greater than 16, the search then jumps from 16 to 20, then from 20 to 22, and finally from 22 to back to 21, at step 6. Note the search takes a total of six steps. Considering that the memory bank contains 128 rows, which could require a full scan of 128 steps to find a match, a binary search is much more efficient. As described above, the ARL/L3 table includes a hit-bit for aging purposes. As matches are made during table look-ups, the appropriate hit-bits in the ARL tables are updated for aging purposes (hit-bit updates may be performed as part of the search function and during search slots). Therefore, several potential problems may occurs when performing learning functions and searching functions concurrently against the same tables. For example, as will be described below, learning updates can move data records, thereby disrupting the search process including hit-bit updates. As a result, hit-bit updates may be incorrect or fail, or learning may cause blind spots in searches. Special handling is required to overcome these problems. The first problem that can occur while trying to perform searching and learning concurrently are caused by inserting a record into the ARL table while concurrently trying to update a record in the ARL table. For example, when a match is made in a search, such as a table lookup for an incoming packet, the hit-bit of the matching record is updated for aging purposes. However, if during the same cycle a new address is learned, and therefore a new record is inserted into the ARL table, which could in turn move the record being updated, the hit-bit update may occur against the wrong row or data record. In order to prevent this from occurring, learning functions can be blocked for the cycle after a match is made for a search, so that the hit-bit update may occur at the exact same record the match occurred. As an example, referring to FIG. 11, during the first cycle of a search, there may be a hit on search SA0 or SB0. Therefore, during the second cycle a hit-bit update to the ARL table will be performed. During the second cycle there is no learning activity because learning is blocked in order to prevent an insertion into the ARL table from affecting the hit-bit update. After the update in the third cycle, learning may be resumed. It should be noted that learning can be blocked until the hit-bit update is finished, or if other updates are performed on a match, until all updates related to the search are finished. ARL logic or other switch logic may be used to "snoop" (monitor) learning and hit-bit updates in order to block or prioritize the functions according to the present invention. Internal switch logic is preferred over the use CPU 52, because the use of the CPU 52 to perform functions related to network performance will considerably decrease the over all performance. Furthermore, the ARL logic may be configured to control reads and writes to the various tables in order to perform blocking and prioritizing functions in accordance with the present invention. A second problem caused by concurrently performing learning and searching is caused by bubble sorting a table after an insert have upon a search in progress. A brief description of a bubble sort is described with reference to FIG. 12. As described above, searching may be performed via binary searches, which require that the tables being searched to be in a sorted order prior to the search (or to pre-sort the table prior to the search). Therefore, new records being inserted into a table must be inserted into the correct, sorted location. All the records must be shifted up or down to accommadate the new record and maintain the sorted table. This is commonly accomplished via a bubble sort or "bubbling." For example, during the learning process, a new record is inserted in the table 1000, such as when a new address has been found attached to SOC 10, then a bubble sort is performed in order to cascade update every row in order to keep the table 1000 sorted. If a new address is to be inserted to row 20 of table 1000, row 20 is read out and inserted into row 19. Additionally, row 19 is read out and inserted into row 18, and so on. From a practical standpoint, in order to successfully perform the bubble sort, the sort will begin at the top of the table and bubble down to the new insert. Accordingly, row 2 is read out and written into row 1, and row 3 is read out and written into row 2, and so forth up to row 20. After row 20 is read out and written into row 19, then the new record is inserted into row 20. One having ordinary skill in the art will readily understand a bubble sort and will recognize that many forms of the bubble sort may be used with the present invention. As the records are moved up the table, this is often referred to as "bubbling" or "bubbling up". The following is an example of how bubbling affects searching and learning according to the present invention. Referring back to FIG. 10, during a binary search, the search jumps a number of rows up or down the table depending on the current step. One having ordinary skill in the art will understand that a bubble sort will "bubble" records up or down after an insert into the table, from or to the point of the insertion. Therefore, if a bubble sort is occurring concurrently with a search against the same table, blind spots can be caused. For example, assume that during step 1 the determination is made that a record to be found is lower than row 64, and the search jumps from 64 to 32. Next, at step 2, it is determined that the record to be found is higher than row 32 and therefore the search jumps to row 16. However, if the record to be found was at row 17 during the cycle wherein the search determined where to jump next for step 3, but then is bubbled to row 16, then the search will never be able to find the record. This is because a binary search is unable to mathematically return to a row that is already checked. In the example just given, the search would attempt to jump from row 16 to row 24, then again downward to row 28, then downward to row 30, and then finish at row 31 never actually returning to row 32. Therefore, concurrently bubble sorting a table while a binary search is being performed can cause blind spots and cause a search to fail. In order to prevent the search from failing, precautions can be taken. One way to prevent the bubbling from interfering with a binary search, is to "snoop," bubble updates (data reads and writes to the table), i.e., to monitor the updates. ARL logic within SOC 10 can be configured to snoop search hits and updates to the ARL table. During a bubble sort, learning (part of ARL logic) performs a data read and a data write on alternating cycles until the table is properly sorted after an insert. When a data is written into a location that the search request is trying to hit, the write is blocked. To block the write, the write can be simply changed into a read. Therefore, the write can be performed in the next cycle. To more efficiently coordinate concurrent reading and writing of data caused by concurrent learning and searching, a technique of range address insertion blocking can be adapted. By this technique, the range of current searches is determined, such as by the ARL logic, and then, only write inserts into the table are blocked which will move a record out of the range of the current searches. For example, the ARL logic is configured to calculate the range of a current search based on the current search location, the current step, and the size of the table. For a binary search, the number of steps is equal to log2(MAX-MIN), and the amount to jump=2(5-current step). Thus, for a table of 512 rows, the first step begins at row 256, and a search can take up to 9 steps. The range can therefore be determined by calculating adding and subtracting (amount of last jump-1) to the current location. At step one, the range would be 256-255 to 256+255, or 1-511. Since any records within the range can be found, even if they move during the next step, only inserts which will move data out of range are snooped and blocked. For example, referring to FIG. 13, a series of search steps are shown. Below each search step is shown a row number and a search key. If in this exemplary search, the search key being sought is 1900 at row 383, then it will take 9 steps to make a match. At step two, the current range of the search is determined to be 320-448 and at step 3, the range is determined to be 257-383. Therefore, if after step 2, the entry for 1900 is bubbled up to 384, at step 3 it is now out of range. The ARL logic may configured to block the bubble write for a cycle, until there is a match. In this example, the write is blocked, but after step 3, there is still no match. At step 4, the current location of the search is row 352, and the range is determined to be 321-383. Therefore, the bubble write is blocked again, since it is still attempting to move data out of range of the search. The bubble write is successively blocked, therefore, until a match is made at step 9. Then, once a match is made, the write is allowed to occur. Referring to FIG. 14, a flow chart is shown of a method for performing searching and learning concurrently within a network device, according to the present invention. Processing begins at step S14-1 and proceeds next to step S14 in a network device. In a network device, such as the switch SOC 10 described above with reference to FIGS. 1-8, a data packet is received at a network port. As described above, the data packet is handled, sliced, processed, etc. At step S14-3, a number of searches may be initiated against ARL tables in order to determine a location. As data packets are received and switched to network devices, switch SOC 10 is configured to perform learning as well. As already described above, searching and learning can be concurrently performed by dedicating slots of a timing signal to each function. For example, every third square wave of a timing signal may be dedicated to learning while two out of every three waves may be dedicated to parallel searching. In this case, a complete cycle would comprise three slots, two of which are dedicated to searching and one of which is dedicated to learning. At step S14-4, the first step of the search is performed. At step S14-5, the current range of the search is determined. As described above, for binary searches, the current range may be calculated based on the current step, the number of rows in a table and the current location of the search. Next, at step S14-6, updates and inserts are snooped. As described above, the ARL logic or other logic within the switch can be configured to snoop updates against the table including hit-bit updates and bubble sort writes. Updates can be blocked which will move data out of the range of any current searches. As already described above, the update (write) will be blocked so that the data will be found and therefore, to prevent error in the search. The write may be changed to a read in the current cycle. Next, at step S14-7, it is determined whether the current search returned a match. If there is a match, then processing ends at step S14-9. If there is no match, then the next step of the search is performed at step S14-8, and steps S14-5 through S14-7 are repeated. Accordingly, for each search the current range of the search is determined and any updates that will move data out of range are blocked until the search makes a match. Also, note that the current range may be calculated for each step of the search, and therefore, an update that will move data out of range may be blocked for a single cycle up and until a match is made, depending on whether the range changes. For example, if a bubble update intends to move data from row 383 to 384, the update will be blocked as long as one of the borders of the search range remains to be 383. As soon as the related border (383) of the range changes, the update will be allowed. Thus, provided is a more efficient and effective method of providing concurrent search and learning in a high speed network device. One having ordinary skill in the art will readily understand that the preceding systems and methods may be applicable to other network devices and processes. Accordingly, the present invention is not meant to be limited to the embodiments described above or network switches. Although the invention has been described based upon these preferred embodiments, it would be apparent to those of skilled in the art that certain modifications, variations, and alternative constructions would be apparent, while remaining within the spirit and scope of the invention. In order to determine the metes and bounds of the invention, therefore, reference should be made to the appended claims.
|
Same subclass Same class Consider this |
||||||||||