Three-dimensional power modeling table having dual output capacitance indices

Abstract

A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs. A library developer can specify a 3-D power table having three indices, input transition time, output1 capacitance (e.g., for Q), and output2 capacitance (e.g., for Q'). The power value output is then an accurate measure of the total power consumed by the dual output cell during the output transition.

Claims

What is claimed is:

1. A computer-readable medium having stored therein computer-readable program codes that when executed cause a computer system to perform a computer implemented method of representing physical power consumption of a physical circuit within an integrated circuit, said method comprising the steps of:

a) storing into a computer memory a plurality of first reference index values within a first reference index of a three dimensional lookup table, said plurality of first reference index values representing output load capacitances for a first output of a library cell representing said physical circuit;

b) storing into said computer memory a plurality of second reference index values within a second reference index of said lookup table, said plurality of second reference index values representing output load capacitances for a second output of said library cell;

c) storing into said computer memory a plurality of third reference index values in a third reference index of said lookup table, said plurality of third reference index values representing input transition times of an input signal received at an input of said library cell, wherein each distinct combination of a first reference index value, a second reference index value, and a third reference index value forms a distinct coordinate position within said lookup table; and

d) storing into said computer memory a first plurality of reference power values computed based on a first power model of said physical circuit, wherein each distinct coordinate position of said lookup table receives a power reference value and wherein power reference values represent amounts of power physically dissipated by said physical circuit based on a transition of said first output under said first power model.

2. A computer-readable medium as recited in claim 1 wherein said method further comprises the step of e) storing into said computer memory a second plurality of reference power values corresponding to a second power model, wherein each distinct coordinate position of said lookup table receives a power reference value and wherein power reference values represent amounts of power physically dissipated by said physical circuit based on a transition of said first output under said second power model.

3. A computer-readable medium as recited in claim 1 wherein said first output and said second output transition contemporaneously.

4. A computer-readable medium as recited in claim 3 wherein said method further comprises the steps of:

determining three input values pertinent to a power consumption event of said library cell, said three input values comprising: an output load capacitance value for said first output; an output load capacitance value for said second output, and an input signal transition time for said input; and

generating an output power value for said power consumption event of said library cell based on said three input values by using said three dimensional lookup table and linear interpolation.

5. A computer-readable medium as recited in claim 1 wherein said first reference index contains N first reference index values, said second reference index contains N second reference index values, said third reference index contains N third reference index values, and said power consumption lookup table comprises N3 reference power values.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of electronic design automation (EDA). More specifically, the present invention relates to the field of power modeling for logic cells used in EDA applications.

2. Prior Art

In the field of EDA, in one level of abstraction in the design process, integrated circuit (IC) designs are represented by cells (e.g., logic cells) and interconnections between the cells. Often the IC design has associated with it a number of constraints that the EDA system needs to satisfy during logic synthesis and/or optimization. These constraints include timing constraints, area constraints, and power consumption constraints. There are well known EDA processes that determine if a synthesized IC design meets the given constraints and that perform certain steps if the constraints are not met. If a design does not meet one or more constraints after optimization, it is often redesigned by a designer in order to fall within the prescribed constraints. Therefore, it is important for an EDA system to accurately determine the amount of power consumed by the individual cells of the IC design so that the EDA system can accurately report whether or not the IC design, as an aggregation of individual cells, meets the prescribed power constraints.

Circuits or logic elements are represented in EDA by logic cells whose electrical, timing, logic, and power characteristics and behavior are represented in an entry in a library as a library cell. The libraries are stored in a computer readable format within a computer readable memory for use by appropriate EDA processes. The libraries are typically technology dependent, e.g., CMOS, FPGA, etc., and vary by technology manufacturer (e.g., LSI, Xilinx, etc.). The developer of the library of logic cells needs to characterize each individual logic cell and report, in the library, the above logic cell characteristics, including the power consumed by the logic cell. The more accurate are the individual logic cell characterizations found in the logic cell library, the more accurate is the EDA aggregate report regarding all the cells of a given integrated circuit design.

Currently, prior art library developers can only specify one internal power lookup table at each output pin or input pin of a library cell and one leakage power value per library cell. The internal power table associated with an output pin is then referenced when the output pin switches (transitions), regardless of the state of any signals at the time of transition or regardless of which input pin path caused the output transition. An example is shown with reference to FIG. 1A. A logic cell 10 is shown having four gates 11, 13, 15, 17, and 19 and seven inputs, A-G, and one output, O, taken from gate 19. The prior art library representation for cell 10 includes a power consumption model that indicates a certain amount of estimated power consumption for a transition at the output pin 19a, regardless of what signal state or input pin caused the transition. The power consumed by the cell within this prior art power consumption model for a particular output transition is basically an average of all power consumed by the cell as a result of each possible input state that could cause output O to transition.

This prior art modeling technique leads to inaccuracies during power estimation because the actual power consumed by logic cell 10 varies depending on which input caused the output transition or the state (condition) of any signals existing at the time of the transition. For instance, if input G (FIG. 1A) caused the output transition, only gate 19 is used to cause output O to transition. However, if inputs A and B caused the output transition, gates 11, 13 and 19 are used, thereby creating a longer path from the inputs (A/B) to the output (O) and thereby consuming more power over the former case. Although the prior art library model gives an average power consumption estimation by averaging the output transition power consumption over each input transition, for any particular use of logic cell 10 (e.g., for any particular application of logic signals to the inputs A-G) the prior art model can and does often give inaccurate power consumption results. What is needed is a power modeling system and method that advantageously allows power modeling of a library cell to include information regarding the logic cell's power consumption given an input transition over a particular input pin of the logic cell. One aspect of the present invention provides such advantageous functionality.

Furthermore, the prior art power consumption model gives a library cell's power consumption for an output transition regardless of the state of the input signals that caused the transition. In many instances, a logic cell consumes different amounts of power depending on the condition of the input signals that caused the transition. For instance, FIG. 1B illustrates a random access memory cell 21 (RAM) having an address bus input (ADDR), a data bus input/output (DATA), a read signal, a write signal, and an enable signal (EN). Depending on whether the RAM cell 21 is in read or write mode (as indicated by the state of input signals), the internal and leakage power used by the RAM cell 21 can be quite different. Also, depending on whether or not RAM cell 21 is enabled also impacts the power consumption of RAM cell 21. The prior art power model assigns one "averaged" power consumption amount for RAM cell 21 regardless of the state of the input signals. Therefore, the prior art model either reports too much power consumption or too little power consumption for an application of the RAM cell 21 that performs mostly reads or that performs mostly writes (or vice-versa). What is needed is a power modeling system and method that advantageously allows a library cell to include information regarding the logic cell's particular power consumption given a particular condition (e.g., signal state) that exists contemporaneously with a transition causing the power consumption. One aspect of the present invention provides such advantageous functionality.

Another aspect of EDA power estimation is common power. Common power is the power consumed in the common logic among multiple outputs. It is also the power consumed in the logic which may transition without the output changing. FIG. 1C illustrates a logic cell 50 for a case of common logic shared between two outputs Y and Z. In this case, input A can cause both outputs Y and Z to change. However, the library developer needs to ensure that the power of gate 51 is not counted twice in the power model. This is difficult to perform in prior art library power modeling because the power consumed for a transition of output Y and Z is reported irrespective of the input lines or the conditions of the input signals that caused the transition. What is also needed is a system to provide accurate power modeling for the common logic case shown in FIG. 1C.

Internal power is any power dissipated within the boundary of a cell. This includes short circuit power, as well as the power dissipated due to the charging and discharging of any other existing capacitances internal to the cell. This definition does not distinguish between a cell's short circuit power and other power dissipated internally due to the charging and discharging of internal capacitances during switching. Short circuit power is the power consumed by the cell during a signal transition when both the P and N type transistors can be ON simultaneously. During this short time, current flows from Vdd to ground causing short circuit power dissipation. A cell's internal power is the sum of the internal power of all of the cell's inputs and outputs as modeled in the library.

Internal power of a cell is determined by prior art libraries based on: (1) a single value representing the output load capacitance of an output pin of the cell; and (2) a value representing the input transition time of a signal of an input pin of the cell. Generally, the longer the transition time, the more power is consumed and the more the load capacitance, the more power is consumed. The exact function of power consumption based on input transition time and output load capacitance is determined based on linear interpolation within a model of reference index and reference power points. FIG. 2A illustrates a sample two dimensional power lookup table 30 of the prior art. The prior art table 30 is two dimensional because two input reference indices are used, one along the y dimension which represents output load capacitance (pf) of the cell, and one along the x-dimension which represents weighted average input transition time (ns). The power value output is then modeled along the vertical (z-axis). The library cell's power model includes a group of reference power points 32a-32d that corresponds to reference index points along the x-dimension and y-dimension. The reference index and power points are included in the power model for the representative library cell. A particular power consumption value at point 32 representing a particular input transition time and a particular output load capacitance (e.g., x'=0.34, y'=110.1) is determined by linear interpolation with respect to the reference index and power points. The above library models are formulated on an output pin-by-output pin basis for each cell.

FIG. 2B illustrates an example cell 40 (e.g., a flip-flop) having a first output 42 (e.g., O) and a second output 44 (e.g., O') whereby the first output 42 and the second output 44 switch contemporaneously. Using the power model 30 of FIG. 2A, each output of cell 40 has its own power consumption model since only one output load capacitance value is allowed in the model 30. However, it is often difficult for library developers to apportion the output power between the output 42 and output 44 for cell 40. This is the case for one reason because power consumption is measured by input current to cell 40, and since both outputs switch contemporaneously, only one current is measured for both outputs. Further, since many library developers do not want to analyze the specific internal circuitry 41 causing the second output 44 to switch, it is difficult to apportion the power consumption of cell 40 between the first output 42 and the second output 44 on a gate level. What results in prior art power modeling for cell 40 is often a doubling of the power consumption for cell 40 whereby the same power consumption value is placed on both output 42 and output 44 in the library. This causes an over estimation of the power consumed by cell 40 during power estimation processes. Alternatively, in the prior art model, only one power consumption value is placed on output 42 and nothing on output 44 (or vice-versa), causing an under estimation of the power consumed by cell 40. What is needed is a method and system for providing increased accuracy in power estimation for a cell having two outputs which switch contemporaneously. The present invention provides these advantages.

Accordingly, the present invention provides a system and method that advantageously allows power modeling of a library cell to include information regarding the logic cell's power consumption given an input transition over a particular input of the logic cell. Further, the present invention provides power modeling of a library cell which includes information regarding the logic cell's power consumption given a particular condition (e.g., signal state) that exists contemporaneously with a pin transition causing the power consumption. The present invention also provides the above system including an accurate power modeling for the common logic case described above. The present invention yet provides a system, as above, offering increased accuracy in power estimation for a cell having two outputs which switch contemporaneously. By allowing a gate-level power estimation process to be more accurate, the present invention advantageously avoids the need to perform a lengthy and design-size limited transistor-level cost estimation process. These and other advantages not specifically discussed above will become clear within discussions of the present invention herein.

SUMMARY OF THE INVENTION

A system and method are described for modeling power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells using a three dimensional power modeling table. The three dimensional power modeling table (3-D power table) utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time). Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs. A library developer can specify a 3-D power table having three indices, input transition time, output1 capacitance (e.g., for Q), and output2 capacitance (e.g., for Q'). The power value output is then an accurate measure of the total power consumed by the dual output cell during the output transition. Because there are many complementary outputs in many IC designs, the present invention adds accuracy in the overall power estimation process.

Specifically, an embodiment of the present invention includes a computer readable memory having stored therein a power consumption lookup table used for estimating power consumed by a physical circuit of an integrated circuit device, the power consumption lookup table comprising: a first reference index comprising a plurality of first reference index values representing output load capacitances for a first output of a library cell, the library cell representing the physical circuit; a second reference index comprising a plurality of second reference index values representing output load capacitances for a second output of the library cell; a third reference index comprising a plurality of third reference index values representing input transition times of an input signal received at an input of the library cell, wherein each distinct combination of a first reference index value, a second reference index value, and a third reference index value forms a distinct coordinate position within the power consumption lookup table; and a plurality of reference power values wherein each distinct coordinate position contains one reference power value associated therewith and wherein the plurality of reference power values represent amounts of power physically dissipated by the physical circuit based on a transition of the first output. Embodiments of the present invention include the above and wherein the first output and the second output transition contemporaneously.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates an exemplary cell wherein power consumption varies depending on which input transition path caused the output transition.

FIG. 1B illustrates an exemplary cell wherein power consumption varies depending on the state of the input signals at the time of the power measurement.

FIG. 1C illustrates an exemplary cell exhibiting the need for common logic power modeling.

FIG. 2A illustrates a prior art two dimensional library model for power consumption of a logic cell.

FIG. 2B illustrates an exemplary logic cell having a first and a second output that transition contemporaneously.

FIG. 3 is a logical block diagram of a computer system utilized in accordance with the present invention power modeling embodiments.

FIG. 4 illustrates a generic state dependent power modeling structure in accordance with one embodiment of the present invention.

FIG. 5 illustrates an exemplary library cell having different power consumption functions depending on the state of its input signals.

FIG. 6A illustrates a first exemplary synchronous RAM cell having different power consumption functions depending on the state of its input signals.

FIG. 6B illustrates a second exemplary asynchronous RAM cell having different power consumption functions depending on the state of its input signals.

FIG. 7 illustrates an exemplary library cell having different power consumption functions depending on which input pin path transitioned to cause the power event.

FIG. 8 illustrates a generic path dependent power modeling structure in accordance with one embodiment of the present invention.

FIG. 9A is a schematic diagram of an exemplary library cell having two output signals that switch contemporaneously and are opposite.

FIG. 9B is a schematic diagram of an exemplary library cell having output signals that may transition independently of each other.

FIG. 10 illustrates an exemplary library cell having two outputs that switch contemporaneously.

FIG. 11 illustrates a three dimensional power lookup table (3-D power LUT) having dual output load capacitance indices used in accordance with the present invention.

FIG. 12A is a generic data structure for an internal power group using a 3-D LUT of the present invention.

FIG. 12B is a generic data structure for an internal power group using both a 3-D LUT and state dependent modeling in accordance with the present invention.

FIG. 12C is a generic data structure for an internal power group using both a 3-D LUT and path dependent modeling in accordance with the present invention.

FIG. 12D is a generic data structure for an internal power group using a 3-D LUT and both state and path dependent modeling in accordance with the present invention.

FIG. 13 is an exemplary flip flop library cell.

FIG. 14 is an overall flow chart of steps and data used within an exemplary embodiment of the power analysis processes of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the present invention, a three dimensional power modeling table having dual output capacitance indices, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present invention.

I. NOTATION AND NOMENCLATURE

Some portions of the detailed descriptions which follow are presented in terms of steps, procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. A procedure, logic block, process, step, etc., is here, and generally, conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the action and processes of a computer system (e.g., 112 of FIG. 3), or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

COMPUTER SYSTEM ENVIRONMENT

Refer to FIG. 3 which illustrates an exemplary computer system 112. Within the following discussions of the present invention, certain processes, steps, structures, models, tables, and libraries are discussed that are realized, in one implementation, as a series of instructions (e.g., software program) and/or data that reside within computer readable memory units of system 112 and executed and/or read by processors of system 112. When executed, the instructions cause the computer system 112 to perform specific actions and exhibit specific behavior which are described in detail to follow where appropriate. Further, the models, libraries, and data structures discussed herein are stored in computer readable memory units of system 112 and represent physical characteristics and behaviors (e.g., power consumption) of physical integrated circuits (e.g., gates, connections between gates, etc.).

In general, computer system 112 of FIG. 3 used in accordance with the present invention comprises an address/data bus 100 for communicating information, one or more central processors 101 coupled with the bus 100 for processing information and instructions, a computer readable volatile memory unit 102 (e.g., random access memory, static RAM, dynamic, RAM, etc.) coupled with the bus 100 for storing information and instructions for the central processor(s) 101, a computer readable non-volatile memory unit (e.g., read only memory, programmable ROM, flash memory, EPROM, EEPROM, etc.) coupled with the bus 100 for storing static information and instructions for the processor(s) 101. System 112 also includes a mass storage computer readable data storage device 104 (hard drive or floppy) such as a magnetic or optical disk and disk drive coupled with the bus 100 for storing information and instructions. Optionally, system 112 can include a display device 105 coupled to the bus 100 for displaying information to the computer user, an optional alphanumeric input device 106 including alphanumeric and function keys coupled to the bus 100 for communicating information and command selections to the central processor(s) 101, an optional cursor control device 107 coupled to the bus for communicating user input information and command selections to the central processor(s) 101, and an optional signal generating device 108 coupled to the bus 100 for communicating command selections to the processor(s) 101.

II. STATE DEPENDENT POWER MODELING

The present invention provides a library cell model (state dependent model) for the power consumption of a particular pin of a library cell wherein the power model depends on the condition or state of specific signals, e.g., the state of specific input, output, internal and/or bidirectional signals that are present contemporaneously with a transition over a pin causing the power consumption. The state dependent model of the present invention is particularly advantageous for library cells whose actual power consumption varies depending on the state of certain signals (e.g., input, output, internal, bidirectional) pertinent to the library cell. One example given above is the random access memory cell (or RAM) which consumes different amounts of power depending on whether it is in the read state or in the write state, as indicated by the state of certain signals (e.g., input signals) of the library cell. Further, the RAM cell consumes different power amounts whether or not it is enabled. Each of these conditions can be represented by functions of the state of certain signals (e.g., input signals, in this case) including the read signal, the write signal, and the enable signal, etc. The present invention provides a power model stored within computer readable memory that allows a library developer to indicate particular power consumption amounts for a library cell, for a transition over a designated pin, depending on the state of certain signals of the library cell that exist contemporaneously with the transition over the designated pin.

Within the present invention, the library cell and its power model (e.g., whether state dependent, power dependent, or three dimensional power table) represent the physical power consumption of a particular, physical, integrated circuit element.

With respect to state dependent modeling, a state that exists "contemporaneously" with the transition of a designated pin is defined herein. A signal transition over an input pin can cause a transition of a designated pin of a state dependent power model. In addition, the state of any other pins (e.g., input, output, internal, bidirectional) of the library cell are important in defining the power consumption of the library cell at the time of the dedicated pin's transition. The state of "any other" signal pins can also include the static and/or transitional state of the above referenced input pin. The state of these "any other" pins is evaluated contemporaneously with a signal transition over the designated pin within the state dependent power model of the present invention. The term contemporaneously with a signal transition on the designated pin means: (1) at or near the time of this transition of the designated pin; and/or (2) at or near the time of a signal transition over the above referenced input pin that causes the designated pin to transition. Typically these two events occur closely in time, but need not within the scope of the present invention.

FIG. 4 illustrates a generic data structure 250 utilized in accordance with the present invention state dependent model to represent power consumption within a logic cell. Data structure 250 resides within computer readable memory units of system 112 (FIG. 3) and is accessed by processor 101 during power estimation (see FIG. 14). The particular logic cell modeled by structure 250 is identified by a cell name designation (data field) 252. A cell library includes many logic cell power models 250, one for each distinct cell supported by the technology specific library. For each pin of the logic cell whose transition causes a power consumption event, the present invention state dependent data structure 250 allows a library cell developer to specify: (1) certain conditions, e.g., signal states; and (2) the specific power consumed by the logic cell during those conditions with respect to a transition over a designated pin. For instance, FIG. 4 illustrates power consumption information for one pin of the designated cell; this designated pin is identified by the pin designation field 254. It is appreciated that one pin is shown for clarity only and that structure 250 can contain analogous definitions for multiple designated pins of the designated cell. This aspect is shown in an example discussed further below.

For each pin designation 254, the structure 250 contains an identification of whether the designated pin is an input pin, output pin, internal pin, or bidirectional pin. This information is contained in the input/output/internal/bidirectional designation 256. It is appreciated that in many logic cells, the transition of an input pin causes a power event within the logic cell irrespective of whether or not an output signal transitions. For example, the clock pulse on a flip-flop cell causes a power event within the flip-flop cell although the output (Q) may not change. Further, in many combinational logic circuits, an input transition can cause many intermediate circuits to alter state while the final output of the cell does not transition in response to the input transition.

For each pin designation 254, the structure 250 of FIG. 4 contains one or more internal power headers 258 indicating that power modeling information is to follow (within an internal power group 265) regarding the designated pin of the designated cell. Within each internal power group 265 associated with an internal power header 258, the present invention contains an identification designation 260 of a power look-up table used in determining the power consumption for the designated pin/cell. Also within each internal power group 265 associated with an internal power header 258, the present invention contains a list of power reference values 262 for use in conjunction with the designated power look-up table 260 for determining the power consumption for the designated pin/cell.

Also included within each internal power group 265 of FIG. 4 is a "when" clause 264 indicating the state of specific signals of the logic cell for which the particular internal power group 265 applies. The when clause 264 typically contains a function of selected signals to represent the identified or designated static state. Although shown as at the end of an internal power group 265, the when clause 264 can be positioned at any place within the internal power group 265 within the scope of the present invention. The particular internal group 265 is used to evaluate the power consumption of the library cell provided the state of the selected signals 264 exists contemporaneously with a transition over the designated pin 254.

During power analysis, if the state of the identified signals at 264 is present contemporaneously with a transition at the pin identified by designation 254, then the power information designated within 260 and 262 is used to determine the power consumed by the logic cell designated by 252 based on a given input signal transition time and/or one or more output capacitance values associated with the power event.

As shown in FIG. 4, a particular pin can have more than one internal power group. Structure 250 contains a second internal power group 266 for the designated pin/cell which contains a different "when" clause for the designated pin. It is appreciated that the functions of each "when" clause for a designated pin are mutually exclusive within the preferred embodiment the present invention. At the completion of a pin designation, the present invention data structure 250 includes a default power consumption group (270, 272, 273) for the designated pin. This default internal power group contains the default power consumption values when none of the when conditions are true for the designated pin 254. Designation 270 indicates an internal power header while designation 272 indicates a power look-up table for the default condition. Designation 273 indicates the default power values used for the designated power look-up table 272. It is appreciated that the absence of a "when" clause within an internal power group of structure 250 indicates the default cause for the designated pin. State dependent power model structures based on designated input pins do not need default internal power groups. State dependent power model structures based on designated output pins generally require a default internal power group unless their associated internal power groups exhaustively define each possible input state.

It is appreciated that within the state dependent power model of the present invention, when statements are allowed to be Boolean expressions of the library cell signals (e.g., input, output, internal, bidirectional). This allows library developers to specify state dependent power which is related to both input and output pins for a given library cell. Therefore, under the present invention there is no restriction that there can only be one internal power table per output or input pin (as in the prior art). In accordance with the present invention, there can be multiple internal power tables defined per designated output or input pin. Each power table of the multiple power tables is represented by one internal power group of the state dependent model data structure 250 (FIG. 4). This is advantageous because a designated pin/cell can have multiple different power consumption functions based on different input states.

Although a number of different programming and data structure languages can be used to implement the specifics of the generic outline of FIG. 4, one exemplary structure of the state dependent power modeling of the present invention is described below. The exemplary power model is representative of an exemplary cell 210 shown in FIG. 5. The cell 210 contains two logic gates 212 and 216, three inputs A, B and C, and one output Z. The look-up tables (LUTs), input_by_trans and output_by_cap, are one dimensional LUTs because they contain only one input index, however, two or three dimensional LUTs are equally well suited for application with the state dependent structure shown below. These LUTs contain reference index values and their structures are shown following the exemplary power model structure.

Exemplary State Dependent Power Model Structure

    cell(mycell) {
         pin(A) {
            direction : input;
            internal_power( ) {
                power(input_by_trans) {
                   values("1.5, 2.5, 4.7");
                }
                when : "B";
            }
            . . .
         }
         pin(B) {
            direction : input;
            internal_power( ) {
                power(input_by_trans) {
                   values("1.5, 2.5, 4.7");
                }
                when : "A";
            }
            . . .
         }
         pin(C) {
            direction : input;
            . . .
         }
         pin(Z) {                           **default**
            direction : output;
            internal_power(output_by_cap) {
                power(output_by_cap) {
                   values("2.0, 5.0, 9.0");
                }
            }
            . . .
         }
    }
                Output_by_Cap and Input_by_Trans LUTs
         library(internal_power_example) {
            power_lut_template(output_by_cap) {
                variable_1 : total_output_net_capacitance;
                index_1("0.0, 5.0, 20.0");
            }
            power_lut_template(input_by_trans) {
                variable_1 : input_transition_time;
                index_1("0.0, 1.0, 2.0");
            }
    }

    Synchronous RAM-State Dependent Power Model
    Example One
    library(internal_power_example) {
         power_lut_template(input_by_trans) {
            variable_1 : input_transition_time;
            index_1("0.0, 1.0, 2.0");
         }
         type (bus16) {
            base_type : array;
            data_type : bit;
            bit_width : 16;
            bit_from : 0;
            bit_to : 15;
         }
         type (bus8) {
            base_type : array;
            data_type : bit;
            bit_width : 8;
            bit_from : 0;
            bit_to: 7;
         }
         . . .
         cell(RAM1) {
            bus(DATA_OUT){
                bus_type: bus16;
                direction : output;
                . . .
            }
            bus(DATA_IN) {
                bus_type: bus16;
                direction : input;
                . . .
            }
            bus(ADDR) {
                bus_type: bus8;
                direction : input;
            }
            pin(R_W) {
                direction : input;
                . . .
            }
            pin(RAM_EN) {
                direction : input;
                . . .
            }
            pin(CLK) {
                direction : input;
                internal_power( ) {
                   when: "R_W * RAM_EN'";
                   power(input_by_trans) {
                       values("1.5, 2.5, 4.7");
                   }
                }
                internal_power( ) {
                   when: R_W' & RAM_EN'"
                   power(input_by_trans) {
                       values("1.8, 2.8, 5.1");
                   }
                }
                internal_power( ) {
                   when : "RAM_EN"
                   power(input_by_trans) {
                       values("0.5, 0.8, 1.6");
                   }
                }
            }
         }
    }

    Asynchronous RAM - State Dependent Power Model
    Example Two
                library(internal_power_example) {
                   power_lut_template(input_by_trans) {
                       variable_1 : input_transition_time;
                       index_1("0.0, 1.0, 2.0");
                   }
                   type (bus16) {
                       base_type : array;
                       data_type : bit;
                       bit_width : 16;
                       bit_from : 0;
                       bit_to : 15;
                   }
                   type (bus8) {
                       base_type : array;
                       data_type : bit;
                       bit_width : 8;
                       bit_from : 0;
                       bit_to : 7;
                   }
                   . . .
                   cell(RAM1) {
                       bus(DATA_OUT) {
                          bus_type : bus16;
                          direction : output;
                          . . .
                       }
                       bus(DATA_IN) {
                          bus_type : bus16;
                          direction : input;
                          . . .
                       }
                       bus(ADDR) {
                          bus_type : bus8;
                          direction : input;
                       }
                       pin(R) {
                          direction : input;
                          internal_power() {
                              when : "RAM_EN"";
                              power(input_by_trans) {
                                 values("1.51, 2.5, 4.7");
                              }
                          }
                            internal_power() {
                              when : "RAM_EN";
                              power(input_by_trans) {
                                 values("0.5, 0.8, 1.6");
                              }
                          }
                          . . .
                       }
                       pin(W) {
                          direction : input:
                          internal_power() {
                              when : "RAM_EN"";
                              power(input_by_trans) {
                                 values("1.8, 2.8, 5.1");
                              }
                          }
                            internal_power() {
                              when : "RAM_EN";
                              power(input_by_trans) {
                                 values("0.5, 0.8, 1.6");
                              }
                          }
                          . . .
                       }
                       pin(RAM_EN) {
                          direction : Input;
                          . . .
                       }
                   }
                }

                       leakage_power() {
                          when : <logical condition>;
                          value: <value>;
                       }

                       cell(mycell) {
                          . . .
                          leakage_power() {
                              when : "IA";
                              value : 2.0;
                          }
                          cell_leakage_power : 3.0;
                       }

    Exemplary Path Dependent Power Model Structure
    cell(mycell) {
         pin(A) {
            direction : input;
            . . .
         }
         pin(B) {
            direction : input:
            . . .
         }
         pin(C) {
            direction : input;
            . . .
         }
         pin(D) {
            direction : input:
            . . .
         }
         pin(E) {
            direction : input:
            . . .
         }
         pin(Z) {
            direction : output;
            internal_power( ) {
                power(output_by_cap_and_trans) {
                   values("2.2, 3.7, 4.3", "1.7, 2.1, 3.5", "1.0, 1.5, 2.8");
                }
                related_pin : "D E";
            }
            internal_power( ) {
                power(output_by_cap_and_trans) {
                   values("2.0, 3.5, 4.1", "1.5, 1.9, 3.3", "0.8, 1.3, 2.6");
                }
                related_pin : "C";
            }
            internal_power( ) {
                power(output_by_cap_and_trans) {
                   values("1.8, 3.3, 3.9", "1.3, 1.7, 3.1", "0.6, 1.1, 2.4");
                }
                related_pin: "B";
            }
            internal_power( ) {
                power(output_by_cap_and_trans) {
                   values("1.6, 3.1, 3.7", "1.1, 1.5, 2.9", "0.4, 0.9, 2.2");
                }
                related_pin : "A";
            }
         }
    }
                   Output_by_Cap_and_Trans LUT
    library(internal_power_example) {
         power_lut_template(output_by_cap_and_trans) {
            variable_1 : total_output_net_capacitance;
            variable_2 : input_transition_time;
            index_1("0.0, 5.0, 20.0");
            index_2("0.0, 1.0, 2.0");
         }
    }

    Example of 3-D Power Table
    library(internal_power_example) {
         power_lut_template(output_by_cap1_cap2_and_trans) {
            variable_1 : total_output_net_capacitance; *** inputs ***
            variable_2 : total_other_output_net_capacitance;
            variable_3 : input_transition_time;
            index_1("0.0, 5.0, 20.0"); *** index
            index_2("0.0, 5.0, 20.0"); reference
            index_3("0.0, 1.0, 2.0"); values ***
         }
         power_lut_template(output_by_cap_and_trans) {
            variable_1 : total output_net_capacitance;
            variable_2 : input_transition_time;
            index_1("0.0, 5.0, 20.0");
            index_2("0.0, 1.0, 2.0");
         }
         power_lut_template(input_by_trans) {
            variable_1 : input_transition_time;
            index_1("0.0, 1.0, 2.0");
         }
         . . .
         cell(FLOP1) {
            pin(CP) {
                direction : input;
                internal_power(input_y_trans) {
                   power(input_by_trans) {
                       values("1.5, 2.5, 4.7");
                   }
                }
                . . .
            }
            pin(D) {
                direction : input;
                . . .
            }
            pin(S) {
                direction : input;
                . . .
            }
            pin(R) {
                direction : input;
                . . .
            }
            pin(Q) {
                direction : output;
                internal_power( ) {
                   power(output_by_cap1_cap2_and_trans) {
                   values("2.2, 3.7, 4.3", "1.7, 2.1, 3.5", "1.0, 1.5,
     2.8",.backslash.
                       "2.1, 3.6, 4.2", "1.6, 2.0, 3.4", "0.9, 1.5,
     2.7",.backslash.
                       "2.0, 3.5, 4.1", "1.5, 1.9, 3.3", "0.8, 1.4, 2.6");
                   }
                   when : "S' or R'";
                   equal_or_opposite_output : "QN"
                   related_pin : "CP";
                }
                internal_power( ) }
                   power(output_by_cap_and_trans) {
                   values("1.8, 3.4, 4.0", "1.5, 1.9, 3.3", "0.8, 1.3, 2.5");
                   }
                   related_pin : "S R";
                }
            . . .
            pin(QN) {
                direction : output;
                internal_power( ) {
                   power(output_by_cap_and_trans) {
                   values("0.5, 0.9, 1.3", "0.3, 0.7, 1.1", "0.2, 0.5, 0.9");
                   }
                   related_pin : "S R";
                }
                . . .
            }
            . . .
    }

    internal_power( )
         rise_power(output_by_cap_and_trans) {
            values("2.2, 3.7, 4.3", "1.7, 2.1, 3.5", "1.0, 1.5, 2.8");
         }
         fall_power(output_by_cap_and_trans) {
            values("2.0, 3.5, 4.1", "1.5, 2.3, 3.3", "1.2, 1.3, 2.6");
         }
         related_pin : "A";
    }

• Inventors
  Mauskar, Ashutosh S.; Olson, Janet; Sproch, James; Lin, Yueqin; Nedelchev, Ivailo;
• Assignee
  Synopsys, Inc. (Mountain View, CA)
• Published
  Feb-27-2001
• Current US Classes:
  702/60
  703/18
  707/101
  716/1
• Application #
  309485
• International Classes
  G06F 017/50
• Field of Search
  703/14 703/15 703/16 703/18 707/101 707/102 716/1 702/60
• Examiner
  Teska; Kevin J.
• Agent
  Wagner, Murabito & Hao LLP
• US Patent References:
  5553008
  5655109
  5682320
  5692160
  5696694
  5726918
  5835380
  5838579
  5903476