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Manipulating data structure (e.g., compression, compaction, compilation) |
Apparatus for managing relationships between objects5845287
Abstract
For any pair of two distinct objects (i, j) and for each relationship that may exist between said two objects, the management apparatus includes a memory element RMP(i,j) for storing either the existence or the non-existence of said relationship. This memory element includes an input corresponding to a first object (i) and an input corresponding to a second object (j), which inputs are connected to two individual buses (CC(j), LC(i)) corresponding respectively to said two objects. These two inputs must receive two respective control signals simultaneously in order to write information in said element indicating either the existence or the non-existence of a relationship between these two objects. In a preferred embodiment, the input corresponding to the first object must receive a read signal for the memory element to restore said information on an output corresponding to the second object; and the input corresponding to the second input must receive a read signal for the memory element to restore said information on an output corresponding to the first object. These memory elements are organized in a triangular array (TN') if the relationship is symmetrical. The apparatus is applicable to asynchronous transfer mode telecommunications switching systems.
Claims
What is claimed is:
1. An apparatus for managing relationships between individually identifiable objects in a finite address field, wherein for each pair of two distinct objects including a first object X and a respective second object Y, a particular relationship may operably exist to associate said first object X and said second object Y, the apparatus comprising:
an array of relationship memory elements for storing relationship information indicating the existence or the non-existence of said relationship between respective pairs of first objects X and second objects Y,
said array having at least two dimensions and formed by a plurality of buses capable of conveying object selection signals and operation control signals, and wherein a relationship memory element is situated at a cross-point between two individual buses, that are orthogonal to each other among said plurality of buses making up said array, each individual bus corresponding to a respective object and operable to convey at least one selection signal for selecting said respective object;
each said relationship memory element includes a logic circuit operable to receive at least one selection signal and operable to receive at least one operation control signal to write or read relationship information in said relationship memory element; and
a logic means coupled to bus access points to supply the buses with said object selection signals, and to receive from the buses relationship information read from the relationship memory elements.
2. The apparatus according to claim 1 for managing relationships that are not necessarily symmetrical between two distinct objects in a set of objects comprising N objects, wherein the plurality of buses comprise:
N column control buses, corresponding respectively to the N objects, and respectively controlling N columns of relationship memory elements;
N row control buses, corresponding to the N rows of relationship memory elements; each row control bus forming a cross-point with each column control bus; and
wherein the array of relationship memory elements comprises N(N-1) relationship memory elements to operably store each relationship relating a respective first object and a respective second object out of N distinct objects; said relationship memory elements located at cross-points between the column control buses and the row control buses, with the exception of cross-points situated on a diagonal of the array.
3. The apparatus according to claim 1 for managing symmetrical relationships in a set of objects comprising N objects, wherein the plurality of buses comprise:
N individual buses corresponding respectively to the N objects, each individual bus having a first branch and a second branch sharing a common end; each individual bus forming a cross-point with each of the other buses of said N individual buses;
wherein the array of relationship memory elements includes ##EQU3## relationship memory elements (RMP(I,K)), to operably store each symmetrical relationship that may associate a respective first object and a respective second object in said set of N objects;
wherein the relationship memory elements storing the relationship information between the objects of rank i=1 to K-1 and the object of rank K, for K lying in the range 1 to N, are situated at cross-points between the first branch of the individual bus corresponding to said object of rank K, and the second branches of respective individual buses corresponding to the objects of ranks i=1 to K-1; and
wherein the relationship memory elements storing relationship information between the object of rank K and the objects of ranks j=K+1 to N are situated at cross-points between the second branch of the individual bus corresponding to said object of rank K, and the first branches of respective individual buses corresponding to the objects of ranks j=K+1 to N.
4. The apparatus according to claim 1, wherein the logic circuit of a relationship memory element situated at the cross-point of an individual bus corresponding to a first object X and an individual bus corresponding to a second object Y comprises read authorizing means for authorizing the reading of relationship information stored at said relationship memory element, if said read authorizing means receives at least one selection signal conveyed by the individual bus corresponding to the first object, and for authorizing the reading of said information if it receives at least one selection signal conveyed by the individual bus corresponding to the second object; the information read being restored at least on the individual bus corresponding to the second object Y when the selection signal is received on the individual bus corresponding to the first object, and the information read is restored at least on the individual bus corresponding to the first object X when the selection signal is received on the individual bus corresponding to the second object.
5. The apparatus according to claim 1, wherein said apparatus is operable to enable an operation of writing relationship information in the relationship memory element to store information indicating the existence or the non-existence of a relationship between a first object and a second object, by explicitly selecting said first and second objects, the logic circuit of said relationship memory element further includes write authorizing means for authorizing the writing of relationship information concerning a relationship between said first object X and said second object Y if said write authorizing means simultaneously receives at least one selection signal conveyed by the individual bus corresponding to the first object X, and at least one selection signal conveyed by the individual bus corresponding to the second object Y.
6. The apparatus according to claim 1, wherein each individual bus, corresponding to a respective object is operable to convey at least first and second selection signals to select the object by assigning the object to at least one group of first and second groups of objects concerned by a writing operation;
wherein the logic circuit of each relationship memory element includes write authorizing means for authorizing a writing operation in the relationship memory element if, simultaneously:
at least the first selection signal relating to the first group is present on the individual bus corresponding to the first object X; and
at least the second selection signal relating to the second group is present on the individual bus corresponding to the second object Y.
7. The apparatus according to claim 6, wherein the logic means coupled to the bus access points includes:
supplying means for supplying a first combination of values of the selection signals to each individual bus corresponding to an object which is to be assigned exclusively to the first group (A) for a given writing operation;
second supplying means for supplying a second combination of values of the selection signals to each individual bus corresponding to an object which is to be assigned exclusively to the second group (B) for said given writing operation; and
third supplying means for supplying a third combination of values of the selection signals to each individual bus corresponding to an object which is to be assigned both to the first group and to the second group for said given writing operation;
wherein to write information indicating the existence or the non-existence of a relationship associating each first object in a first subset of predetermined objects with each second object in a second subset of predetermined objects, without performing the same writing operation for relationships between the objects belonging exclusively to the first subset, or performing the same writing operation for relationships between the objects belonging exclusively to the second subset, the logic means supplies:
the first combination of values to the individual buses corresponding to the objects belonging exclusively to the first subset or to the second subset, one of the two subsets being chosen arbitrarily so as to assign these objects exclusively to the first group (A);
the second combination of values to the individual buses corresponding to the objects belonging exclusively to the second subset so as to assign these objects exclusively to the second group (B); and
the third combination of values to the individual buses corresponding to any objects belonging simultaneously to both the first and second subsets so as to assign these objects exclusively to the second group (B).
8. The apparatus according to claim 1, wherein the logic circuit of each relationship memory element includes operation authorization means for authorizing an operation if the logic circuit receives at least one of:
object selection signal and operation control signal supplied by one of the two individual buses at a cross-point where the relationship memory element is situated, for an operation based on selecting a single object, the other object being arbitrary and
two object selection signals and operation control signals simultaneously supplied respectively by the two individual buses at the cross-point where said relationship memory element is situated for an operation based on selecting two objects.
9. The apparatus according to claim 8, wherein each individual bus corresponding to an object is operable to convey:
at least one signal for selecting an object and controlling writing of information indicating the existence of a relationship between said object and another object;
at least one signal for selecting an object and for controlling writing of information indicating the non-existence of a relationship between said object and another object;
at least one signal for selecting an object and controlling reading of information indicating the existence or the non-existence of a relationship between said object and another object; and
at least one read output signal conveyed an access point of the bus.
10. The apparatus according to claim 1, further comprising an operation control bus (OC) common to all of the relationship memory elements and operable to convey at least one non-specific operation control signal
wherein the logic control circuit of each relationship memory element further includes means for authorizing an operation if the logic control circuit receives simultaneously at least one operation control signal operation control bus, and at least one selection signal conveyed by at least one individual bus.
11. The apparatus according to claim 8, wherein each individual bus corresponding to an object is operable to convey:
at least one read output signal for conveying read information to an access point of said bus; and
said apparatus further comprises an operation control bus common to all of the relationship memory elements is operable to convey at least:
a common signal for controlling an operation of writing information indicating the existence of a relationship between said object and another object;
a common signal for controlling an operation of writing information indicating the non-existence of a relationship between said object and another object; and
a common signal for controlling an operation of reading information indicating the existence or the non-existence of a relationship between said object and another object.
12. The apparatus according to claim 1, wherein said apparatus is operable to perform a first complex operation said first complex operation comprising writing common information indicating the existence or the non-existence of relationships between a given object and all of the other objects simultaneously
wherein said buses are capable of conveying a combination of signals to all of the relationship memory elements that are capable of storing relationship information concerning relationships between the given object and all of the other objects, said combination of signals being specific to the given object and specific to the first complex operation, so as to select the given object and so as to cause the first complex operation to be performed;
wherein the logic means coupled to the access points of the buses include means for transmitting the combination of signals over the buses;
and wherein the logic circuit of each relationship memory element (RMP1 (X, Y); RMP2 (X, Y)) includes a first authorizing means (OC1; OC'1) for authorizing writing of relationship information in the relationship memory element, if the logic circuit receives said combination of signals.
13. The apparatus according to claim 1, wherein said apparatus is operable to perform a plurality of different operations simultaneously, the operations respectively belonging to subsets of disjoint possible operations, wherein
each individual bus is operable to convey a plurality of distinct selection signals supplied by the logic means coupled to the access points of the buses; and
the logic circuit of each relationship memory element includes means for authorizing performance of all of the operations belonging to a subset when the circuit receives at least one of:
a selection signal conveyed by one of the two individual buses that form a crosspoint where a respective relationship memory element is situated, said selection signal being allocated specifically to the subset of operations, in the case of a subset of operations based on selecting a single object; and
a combination of two different selection signals respectively conveyed by the two individual buses that form across point where a respective relationship element is situated, the combination of two selection signals being allocated specifically to the subset of operations, in the case of a subset of operations based on simultaneously selecting two objects.
14. The apparatus according to claim 13, wherein said apparatus is operable to perform a first write operation and a different second write operation simultaneously, for relationships between two selected objects, each of the write operations belonging to a distinct subset of possible operations,
wherein each individual bus (B0(P), B0(P); B0(N), B0 (N); B0 (Q), B0 is operable to convey at least two distinct types of selection signals; and
the logic circuit of each relationship memory element includes means for authorizing:
the first write operation when the logic circuit receives a first combination (IST1 (P).IST1 (Q)=1) made up of two selection signals respectively supplied by the two individual buses that form a crosspoint where a respective relationship memory element is situated; and
the second write operation when the logic circuit receives a second combination made up of two selection signals respectively supplied by the two individual buses that form a crosspoints where a respective relationship memory element is situated.
15. The apparatus according to claim 12, wherein for said first complex operation, each individual bus corresponding to a given object is operable to convey said combination of signals specific to the given object and specific to the first complex operation; and
wherein the logic means coupled to the access points of the individual buses include means for supplying said combination of signals to the individual bus corresponding to each given object;
wherein the logic circuit of each relationship memory element further includes means authorizing writing of information indicating the non-existence of a relationship in the relationship memory element if said combination of signals is conveyed by one of the two individual buses that form a crosspoint where the respective relationship memory element is situated.
16. The apparatus according to claim 12, wherein said combination of signals specific to a given object and specific to the fist complex operation is made up firstly of a selection signal corresponding to the given object and secondly of a releasing control signal conveyed by an operation control bus that is common to all of the relationship memory elements;
wherein the logic means coupled to the access points of the buses include means for simultaneously applying the releasing control signal to the operation control bus, and the selection signal (SSA.sub.X =1; RD.sub.P =1) to the individual bus corresponding to each given object;
wherein the logic circuit of each relationship memory element further includes a second authorizing means for authorizing writing of information, indicating the non-existence of a relationship in the relationship memory element if the releasing control signal is applied to the operation control bus, and if, simultaneously, the selection signal is applied to one of the two individual buses (B02 (X), B02 (Y); B03 (X), B0'3 (Y)) that form a crosspoint where the respective relationship memory element is situated.
17. The apparatus according to claim 13, wherein said apparatus is operable to perform a second complex operation said second complex operation comprising two simultaneous read operations for reading all of the relationship information indicating the existence or the non-existence of relationships established between at least one object and any other object for a first read operation (La), and between at least one other object and any other object for a second read operation, the identified objects being split up into two distinct groups referred to as output groups relating respectively to the first and second read operations;
wherein the individual bus corresponding to each object is operable to transmit a first read selection signal a second read selection signal, the first and second read selection signals being distinct and specific to the second complex operation; and wherein the individual bus is operable to transmit a first read output signal, and for transmitting a second read output signal, the first and second read output signals being specific to the second complex operation;
logic means including means for supplying the first read selection signal, and means for supplying the second read selection signal to the individual buses; the first read selection signal and the second read selection signal being supplied respectively to the individual buses corresponding respectively to each object from which a first read operation is to be performed, and to each object from which a second read operation is to be performed; and the logic means include means for receiving the first and second read output signals that may be conveyed by each individual bus; and
wherein the logic circuit of each relationship memory element relating to the first object and to the second object further includes means for authorizing four read operations, that may or may not be simultaneous, for reading the relationship memory element such that:
a first read operation from the first object is performed if the first read selection signal is conveyed by the individual bus corresponding to the first object;
a second read operation from the first object is performed if the second read selection signal is conveyed by the individual bus corresponding to the first object;
a first read operation from the second object is performed if the first read selection signal (RSA.sub.Y ; SSA.sub.Y) is conveyed by the individual bus corresponding to the second object; and
a second read operation from the second object is performed if the second read selection signal (RSB.sub.Y ; SSB.sub.Y) is conveyed by the individual bus corresponding to the second object.
18. The apparatus according to claim 17, wherein each of the first and second read selection signals also constitutes a read operation control signal;
and wherein the means for performing the four possible read operations depends on the first and second read selection signals and read operation control signals that are received by the logic circuit.
19. The apparatus according to claim 17, further comprising an operation control bus that is common to all of the elements and is operable to convey a non-specific read control signal {(RD) that is common to the first and second read operations (La, Lb);
wherein the logic means include means for further supplying the non-specific read control signal to the operation control bus; and
wherein the means for performing the four read operations operates only if the logic circuit further receives the non-specific read control signal.
20. The apparatus according to claim 4 wherein said apparatus is operable to perform a third complex operation, said third complex operation comprising reading by propagation from a reference object so as to identify all of the objects having direct or indirect relationships with the reference object, said apparatus further comprising:
a bus that is common to all access points of the selection buses, and that is operable to convey an operation control signal specific to the third complex operation; and
wherein the logic means coupled to the access points of the individual buses includes, for each individual bus (B01 (K), B)'1 (K); B02 (K), B0 corresponding to an object logic means supplying at least one selection signal to the bus if a read output signal is present on the bus, and if the operation control signal specific to the third complex operation is present on the bus that is common to all of the access points.
21. The apparatus according to claim 20, wherein a selection signal supplied by the logic means coupled to the access points of the selection buses also constitutes a read operation control signal for the relationship memory elements.
22. The apparatus according to claim 20 further comprising an operation control bus that is common to all of the relationship memory elements (RMP1"(X,Y); RMP2 (X,Y))" and that is operable to convey at least one non-specific operation control signal;
wherein the read authorizing means authorizes a reading operation only if the logic circuit receives the non-specific read control signal; and
wherein the logic means coupled to the access points of the individual buses further supply the non-specific read control signal to the operation control bus that is common to all of the elements, simultaneously with selection signal.
23. The apparatus according to claim 20 wherein said apparatus is operable to perform a fourth complex operation, said fourth complex operation comprising: identifying and releasing, by propagation, direct or indirect relationships between a given object and any other object, wherein the logic means supplies:
a selection signal to the bus corresponding to the given object; and
an operation control signal specific to the third complex operation, to the bus that is common to all of the access points of the buses to identify all of the objects that have direct or indirect relationships with the given object;
wherein the logic means further receives read output signals identifying by propagation each object that has a relationship with the given object;
supplies a selection signal to the individual bus of each object identified by propagation; and
supplies at least to the elements storing information indicating the existence of relationships between the given object and the objects identified by propagation, a combination of selection and releasing control signals so as to write in each of the relationship memory elements information indicating the non-existence of a relationship.
24. The apparatus according to claim 23, wherein the logic means includes:
means for supplying a selection signal to the individual bus of each object identified by propagation during both a first time interval and a second interval; the selection signal also constituting a read control signal; and
means for supplying a selection signal to the individual bus of each object identified by propagation during the second time interval only; the combination of the selection signal and the control signal during the second time interval causing information to be written indicating the non-existence of a relationship.
25. The apparatus according to claim 23, further comprising an operation control bus that is common to all of the elements and is operable to convey a non-specific control signal that is specific to the first complex operation; and
wherein the logic means further includes:
means for supplying a selection signal to the individual bus of each object identifying by propagation during both a first time interval and a second time interval;
means for supplying a read control signal to the operation control bus during both the first time interval and the second time interval; and
means for supplying a non-specific signal to the operation control bus (OC) during the second time interval only, so as to write information indicating the non-existence of a relationship.
26. The apparatus according to claim 14, wherein said apparatus is operable to perform a fifth complex operation said fifth complex relationship comprising releasing a relationship between a first object and any second object and setting up a new first relationship (P-N) between the first object and a third object and a new second relationship between the third object and the second object,
wherein the logic means coupled to the access points of the buses include means for simultaneously supplying:
a selection signal of a first type to the individual buses of the first object and of the second object; and
a selection signal of a second type (RT2, ST2, SS2) to the individual bus of the third object;
and wherein the logic circuit of each relationship memory element includes means for performing the following:
a first write operation comprising writing information indicating the non-existence of a relationship, when the logic circuit receives a first combination of two signals (RT1.sub.P.RT1.sub.Q =1; SS1.sub.P.SS1.sub.Q =1) made up of two signals of the first type over the two individual buses that form a cross-point where a respective relationship memory element is situated; and
a second write operation comprising writing information indicating the existence of a relationship, when the logic circuit receives a second combination of selection signals made up of a signal of the first type and of a signal of the second type over respective ones of the two selection buses that form a crosspoint where the relationship memory element is situated.
27. The apparatus according to claim 12, wherein said apparatus is operable to perform a sixth complex operation said sixth complex operation comprising releasing relationships existing between a given object, referred to as an "object to be removed" and at the most two other objects referred to as "adjacent objects" in a linear chain of relationships between objects, and setting up a relationship directly between the two adjacent objects
wherein said sixth complex comprises a first operation for reading the relationship memory elements storing information indicating the existence of any relationships between the object to be removed and any other object; and a second operation for writing information, indicating the existence of a relationship, in a relationship memory element, relating to two adjacent objects identified by the first operation wherein said first and second operations are performed consecutively during a first time interval and
wherein the logic means coupled to the access points of the buses includes a first operation means for supplying, during the first operation, a first selection and operation control signal (RS.sub.E =1; RD.sub.E =1), applied to the individual bus of the object to e removed to cause reading to be performed in the elements storing the relationships between the object to be removed and all of the other objects; and
said management apparatus further includes a second operation logic means for propagating a second selection and operation control signal relating to the second operation, said second operation logic means being coupled to the individual buses to supply said second selection and operation control signal to the individual bus of an object if the bus is conveying a read output signal so as to write information indicating the existence of a relationship between two adjacent objects identified by the first operation;
and wherein said means to perform the first complex operation is used in a second time interval to release the relationships existing between the object to be removed and the adjacent objects.
28. The apparatus according to claim 27, further comprising a propagation control bus that is common to all of the relationship memory elements, and that transmits a "propagation control" signal (EC=1) specific to the sixth complex during the first time interval ;
logic means for writing information indicating the existence of a relationship between the adjacent objects, produces a write control signal over each individual bus corresponding to an adjacent object to which the relationship memory element is connected, if:
the common propagation control signal specific to the sixth operation is present on the propagation control bus;
and, simultaneously, a read control signal (RS.sub.E =1) is present on the individual bus corresponding to the object to be removed (E); and
and the relationship information read in the relationship memory element indicates the existence of a relationship;
said apparatus further includes means for writing information indicating the existence of a relationship when the logic circuit simultaneously receives two write control signals for causing information to be written indicating the existence of a relationship, the signals being received over respective ones of the two individual buses to which the respective relationship memory element is connected; and.
29. The apparatus according to claim 27, further comprising a propagation control bus that is common to all of the access points and that is capable of transmitting a common propagation control signal specific to the sixth complex operation;
wherein the logic means coupled to the access points of the control buses includes:
means for transmitting during the first time interval the common propagation control signal specific to the sixth complex operation;
wherein for each individual bus corresponding to an object, means for supplying a selection and write control signal for causing information to be written indicating the existence of a relationship, if the propagation control signal specific to the sixth complex operation is active, and if, simultaneously, a read output signal indicating the existence of a relationship between the object to be removed and at least one adjacent object is active on the individual bus; and
means for ceasing transmission during the second time interval, the propagation control signal specific to the sixth complex operation and for transmitting the releasing signal specific to the first complex operation and causing information to be written indicating the non-existence of a relationship, the releasing signal being transmitted over the bus corresponding to the object to be removed, so as to release all of the relationships between the object to be removed and any other objects;
and wherein the logic circuit of each relationship memory element further includes:
means for writing information indicating the existence of a relationship when the logic circuit simultaneously receives two individual selection and write control signals for causing information to be written indicating the existence of a relationship, the signals being received over respective ones of the two individual buses that form a cross-point to which the respective relationship memory element is connected; and
means for writing information indicating the non-existence of a relationship when the logic circuit receives the releasing control signal specific to the first complex operation, for releasing a relationship with the object to be removed.
30. the apparatus according to claim 27, further comprising an identification and propagation bus that is common to all of the relationship memory elements, and that is operable to transmit an identification and propagation control signal specific to the sixth complex operation, and a releasing control signal;
wherein the logic circuit of each relationship memory element includes:
logic means for supplying a "write control propagation" signal for writing information indicating the existence of a relationship, over one of the two individual buses that form a crosspoint where the respective relationship memory element is situated, if a read output signal indicating the existence of a relationship is supplied to the bus by the relationship memory element, and if, simultaneously, the identification and propagation control signal specific to the sixth complex operation is applied; and
means for writing information indicating the non-existence of a relationship, in the relationship memory element, if the releasing control signal is applied to the identification and propagation bus, and if, simultaneously, a selection and read control signal (RD.sub.E =1) is applied to one of the individual buses that intersect each other at the relationship memory element;
and wherein the logic means coupled to access points of the control buses include means for:
activating the following simultaneously during the first time interval:
the identification and propagation control signal specific to the sixth complex operation, over the identification and propagation bus;
the selection and read control signal over the individual bus corresponding to an object to be removed; and
the write control signal over the identification and propagation bus, so as to write information indicating the existence of a relationship between two objects adjacent to the object to be removed; and said logic means coupled to the access points further comprises:
means for activating the following simultaneously during the second time interval:
the selection and read control signal over the individual bus corresponding to the object to be removed; and
the releasing control signal over the identification and propagation bus, so as to write information indicating the non-existence of any relationship between the object to be removed and all of the other objects.
31. The apparatus according to claim 4, wherein when the logic circuit of the relationship memory element performs a read operation, said logic circuit restores relationship information simultaneously over the individual bus corresponding to the first object, and over the individual bus corresponding to the second object, if said logic circuit receives a selection signal via at least one of the two individual buses, as well as a read control signal.
32. The apparatus according to claim 1, wherein said apparatus is operable to restore at least one read output signal at an access point corresponding to an object, said read output signal indicating the existence or the non-existence of at least one relationship with the object X, wherein each memory element includes:
an output relating to the first object X and that is connected to as least one conductor of the bus corresponding to the first object; X all the outputs relating to the first object X being connected together and constituting a wired-OR transmitting at least one read output signal to the access point relating to the first object; and
an output (01(Y); 02(Y)) relating to the second object Y and that is connected to at least one conductor of the bus (B0'1(Y); B0'2(Y)) corresponding to the second object; all of the outputs relating to the second object being connected together and constituting a wired-OR transmitting at least one read output signal to the access point relating to the second object.
33. The apparatus according to claim 1, wherein to limit a reading operation to relationships concerning the objects belonging to a known subset, the logic means further include filter logic means that are coupled to the relationship memory element outputs relating to the objects, and that do not take account of the signals supplied by said outputs, during a read operation.
34. The apparatus according to claim 1, wherein each relationship memory element stores a single bit indicating the existence or non-existence of relationship between said first object X and said second object Y.
35. The apparatus according to claim 34, wherein the relationship information stored in each relationship memory element corresponds to a temporal relationship between said first object X and said second object Y.
36. The apparatus according to claim 34, wherein the relationship information stored in each relationship memory element corresponds to a priority relationship between said first object X and said second object Y .
Description
The invention relates to an apparatus for managing relationships between objects that are individually identifiable in a finite address field, and more particularly to an apparatus for real time applications. Each relationship associates two objects belonging to the same set of objects, or belonging to two respective sets containing objects of the same type or of different types. The term "relationship" should be understood broadly since the particular relationship may vary as a function of the application under consideration. Also, a given object may be associated with one or more other objects by one or more relationships of different kinds.
A particularly important application lies in the field of telecommunications, and more particularly in the field of managing relationships between cells transferred in asynchronous mode. An asynchronous transfer mode (ATM) switching system includes one or more buffer memories for temporary storage of cells to be switched. The buffer memory is generally used as a queue, e.g. of the first-in first-out (FIFO) type. In this first example of an application, it is necessary to manage order relationships between the various locations of the buffer memory to indicate the queue order of cells which are stored in respective ones of said locations.
In this application, the relationship is of the type "next cell in the queue" and it associates one cell which is situated at a certain location in the buffer memory with another cell that is "next" and that is situated in some other location in the buffer memory. In general, for a buffer memory that is shared by a plurality of queues, that other location is not an adjacent location, since locations are released in an order which is random and they are reused as they are released.
Conventionally, the order of respective cells in a queue is managed by managing cell identifiers, such as the addresses of the memory locations containing the cells. For example, to store the queue order of cells stored in a buffer memory, their addresses are written in successive addresses of a so-called "address memory", which is write addressed by a write pointer incremented by unity after each write operation, and read addressed by a read pointer that is incremented by unity after each read operation. The order in which the addresses are written in consecutive rows of this memory determines the order in which the cells will be read back from the buffer memory.
Another conventional method for managing the order of cells in a queue consists in making up a list of addresses that are chained in a random access memory referred to as a "link memory". Locations in the link memory correspond to respective locations in the buffer memory. Each location in the link memory contains an address which is the next address to be used, both for reading the next cell in the buffer memory and for reading the next address to be used in the link memory. Such a method of managing order between cells is described, for example, in European patent application No. 0 441 787 (Henrion 18).
In those two conventional examples of managing the order between cells in a queue, the explicit identifiers used are cell addresses, while the relationships between cells remain implicit.
There exists another type of relationship which does not define a special order or a special classification of objects, but rather that they belong to the same subset or group of objects, with all of the objects of the subset under consideration having exactly the same characteristics with respect to this relationship. In the field of telecommunications, an example of such a relationship is to be found between cells that are to be restored by a buffer memory during the same time interval for the purpose of resequencing cells in an order corresponding to their order of arrival. When a cell arrives in the switching system under consideration, the system associates therewith a time label indicating the time interval during which the cell is to be restored on one of the outlets of the switching system. All of the cells which are associated with the same time label are then associated with said time label by a special relationship of the "belonging to a subset" type, without there being any order relationship between the various cells belonging to the set. Such a method of resequencing cells is described, for example, in European patent application No. 0 438 415 (Henrion 17).
To manage such groupings in a set of non-ordered objects, it is conventional to use:
a queue memory in which the cells remain long enough for late cells to catch up with others having the same time label; and
a stack to which all of the cells having said label are transferred in no particular order other than that of the time labels of each subset of cells.
Known methods of managing relationships between objects in sets of objects that are ordered or not ordered, are conventionally implemented by means of conventional random access memories or by means of contents-addressable memories. Implementing those known methods always reduces to storing object identifiers, not identifiers of relationships between objects. It is thus the manner in which object identifiers are stored, e.g. as a function of their order in a queue, which determines implicitly the order relationships between the objects. As a result, conventional apparatuses for managing objects by means of implicit relationships suffer from the following limitations:
The time required for executing management operations becomes prohibitive if it is necessary to manage a plurality of relationships during the same operation; for example to find and rearrange relationships when an object is to be added or removed from a given set.
Implementing apparatus for managing a plurality of relationships is extremely complex because the management of implicit relationships is distributed in a plurality of distinct memories containing object identifiers for the purpose of saving time by enabling operations to be performed in parallel. Complexity increases rapidly with the number of memories and with the number of parallel paths needed to interconnect the various accesses to the memories: conductors for selecting a memory element; conductors for controlling writing; and conductors for controlling reading.
The object of the invention is to propose apparatus for managing relationships between objects, which apparatus satisfies real time constraints better, and therefore makes it possible to consider management operations that are more complex than those performed at present (parallel execution and/or combined execution of a plurality of unit operations), implying one or more types of relationship within the same set of objects or within a structure comprising a plurality of sets of objects.
For example, in the field of asynchronous transfer mode switching systems, it may be advantageous to manage a plurality of relationships in an ordered set of cells, the relationships respectively indicating: the next cell, the preceding cell, the first cell of an ordered list, and the last cell of an ordered list. In a non-ordered subset of cells, it may be advantageous to manage relationships between a cell and each of the other cells, or between each cell and a cell considered as a reference for the subset under consideration. Managing such "belonging-to" relationships makes it possible to group cells together in different priority levels concerning cell loss and/or delay to apply to each cell; in cell resequencing groups; in outlet queues; etc.
The invention provides apparatus for managing relationships between individually identifiable objects in a finite address field,
characterized in that for each pair of two distinct objects, referred to as a first object and a second object, and for each relationship that may associate these two objects, the apparatus includes a "relationship" memory element for storing "relationship" information indicating the existence or the non-existence of said relationship;
in that said relationship memory elements are structured in an array having at least two dimensions by means of a plurality of buses capable of conveying object selection signals and operation control signals, each element being situated at a cross-point between two "individual" buses, each individual bus corresponding to a respective object and being suitable for conveying at least one "selection" signal for selecting said object;
in that each element includes a logic circuit capable of receiving at least one selection signal and capable of receiving at least one operation control signal to write or read relationship information in said element; and
in that the apparatus includes logic means coupled to bus access points to supply them with operation control signals, to supply them with object- selection signals, and to receive from them information read in the relationship memory elements.
in that the apparatus includes logic means coupled to bus access points to supply them with at least operation control signals and object selection signals; and to receive information read in the relationship memory elements.
The apparatus characterized in this way thus manages relationships between two objects directly, i.e. explicitly, instead of managing them indirectly, since each memory element serves to store or to restore the existence or the non-existence of a relationship between two objects by direct addressing, by activating individual buses corresponding to the objects.
The apparatus characterized in this way provides much faster processing speed than prior art apparatuses since it makes it possible to access relationship information directly by a bus array. This distributed array structure provides very fast access to each memory element corresponding to a relationship between two objects. Also, read activation of an individual bus corresponding to a given object gives access in a single operation to all of the memory elements storing the relationships established between said object and the other objects of the set. A single read operation thus makes it possible to know all of these relationships simultaneously. The time required is thus very short. Similarly a single write operation makes it possible to store the existence or the non-existence of a plurality of relationships simultaneously.
A preferred embodiment of the apparatus of the invention for managing relationships that are not necessarily symmetrical between two distinct objects in a set of objects comprising N objects, is characterized in that the individual buses comprise:
N column control buses, corresponding respectively to the N objects, and respectively controlling N columns of elements;
N row control buses, corresponding to the N objects, and respectively controlling N rows of elements; each row control bus having a cross-point with each column control bus; and
in that the relationship management apparatus comprises N(N-1) memory elements for each relationship capable of relating two out of N distinct objects; said elements being situated at cross-points between the column control buses and the row control buses, with the exception of cross-points situated on a diagonal of the array.
Another preferred embodiment of the apparatus of the invention for managing symmetrical relationships in a set of N objects is characterized in that it comprises N individual buses corresponding respectively to the N objects, each individual bus having a first branch and a second branch sharing a common end; and each individual bus having a cross-point with each of the other buses of said N buses;
in that the relationship management apparatus includes ##EQU1## relationship memory elements, for each symmetrical relationship that may associate two distinct objects in said set of N objects;
in that the memory elements storing the relationship information between the objects of rank i=1 to K-1 and the object of rank K, for K lying in the range 1 to N, are situated at cross-points between the first branch of the individual bus corresponding to said object of rank K, and the second branches of the respective individual buses corresponding to the objects of ranks i=1 to K-1; and
in that the memory elements storing relationship information between the object of rank K and the objects of ranks j=K+1 to N are situated at cross-points between the second branch of the individual bus corresponding to said object of rank K, and the first branches of the respective individual buses corresponding to the objects of ranks j=K+1 to N.
This embodiment presents the advantage of being particularly simple since it makes it possible with N access points to manage symmetrical relationships between N objects, while using only 1/2(N.sup.2 -N) memory elements. It is usable for most relationships since they are generally symmetrical. For example, if a cell A is placed in front of a cell B, then it is clear that the cell B is placed behind the cell A when use is made of the cells being sequenced in a known order. There is then no need to store both of these redundant relationships.
In certain particular applications, this structure also makes it possible to gain access simultaneously to relationships between first and second subsets of the set of memory elements without simultaneously accessing the relationships between the objects within the same subset. Access is then both fast and selective.
The invention will be better understood and other characteristics will appear from the following description of embodiments and from the accompanying drawings:
FIGS. 1 to 4 are diagrams summarizing four embodiments of the apparatus of the invention;
FIG. 5 is a diagram summarizing a first embodiment of a relationship memory element for the apparatus of the invention;
FIG. 6 shows an "orthogonal" bus and an access point corresponding to a given object, for controlling the embodiment shown in FIG. 5;
FIG. 7 is a diagram summarizing a variant of the first embodiment shown in FIG. 5;
FIG. 8 shows how management apparatus including memory elements such as the element shown in FIG. 5 operates, during a reading operation for reading relationships between objects of two subsets A and B (when reading is performed from A);
FIG. 9 is a diagram summarizing an embodiment of apparatus of the invention including memory elements such as the element shown in FIG. 5, and showing how it operates when an operation is performed on relationships relating the objects of a subset S of a set of objects;
FIG. 10 shows the problem that arises when a writing operation concerns two subsets of objects (S1 and S2);
FIG. 11 is a diagram summarizing a second embodiment of a relationship memory element for the apparatus of the invention;
FIG. 12 shows an "orthogonal" bus and an access point corresponding to a given object, for controlling the embodiment shown in FIG. 10;
FIG. 13 shows how management apparatus including memory elements such as the element shown in FIG. 10 operates, during reading of all of the relationships existing between a single object and all of the other objects in the set under consideration;
FIGS. 14 and 15 show two operating variants of the same apparatus during two variants of the same write operation performed on relationships relating the objects of a subset S1 and the objects of a subset S2 (where S1 and S2 are disjoint), with the exception of all of the relationships between the objects of the same subset;
FIGS. 16 and 17 are diagrams summarizing a variant embodiment of the apparatus of the invention that includes memory elements such as the element shown in FIG. 5, and showing how it operates while a write operation is being performed on relationships relating the objects of a subset S1 and the objects of a subset S2, where S1 and S2 are disjoint;
FIG. 18 shows another use of management apparatus including memory elements such as-the element shown in FIG. 11, during a write operation for writing relationships between objects of two arbitrary and non-disjoint subsets S1 and S2;
FIG. 19 is a diagram summarizing a variant of the second embodiment shown in FIG. 11;
FIGS. 20 to 22 show the use of the apparatus of the invention in managing relationships between a plurality of static subsets of objects respectively grouping together objects belonging to different categories;
FIGS. 23 to 26 show four elementary structures of relationships making it possible to manage the objects of a dynamic subset;
FIG. 27 shows the read operation for reading the relationships existing between a given object and the objects belonging to three distinct subsets;
FIGS. 28 and 29 show a write operation concerning relationships between objects belonging to two groups;
FIGS. 30 and 31 show a first complex operation consisting in releasing any relationship existing between an object and any other object;
FIG. 32 is a diagram summarizing a variant of the first embodiment of a relationship memory element, which variant makes it possible to perform the first complex operation;
FIG. 33 is a diagram summarizing a variant of the second embodiment, which variant makes it possible to perform the first complex operation;
FIGS. 34 and 35 show a second complex operation consisting in two simultaneous read operations for reading all of the relationships existing between two given objects and other objects, with the output being separated into respective groups for the objects identified by the two read operations;
FIG. 36 is a diagram summarizing a variant of the first embodiment, which variant makes it possible to perform the second complex operation;
FIG. 37 is a diagram summarizing a variant of the second embodiment, which variant makes it possible to perform the second complex operation;
FIG. 38 shows a third complex operation consisting in reading by propagation;
FIG. 39 is a diagram summarizing a variant embodiment of the access point shown in FIG. 6, which variant includes additional logic means for performing the third complex operation;
FIG. 40 is a diagram summarizing a variant embodiment of the access point shown in FIG. 12, which variant includes additional logic means for performing the third complex operation;
FIG. 41 shows a fourth complex operation consisting in releasing the relationships by propagation;
FIG. 42 is a diagram summarizing a variant embodiment of the access point shown in FIG. 6, which variant makes it possible to perform the fourth complex operation;
FIG. 43 is a timing diagram showing how this variant operates;
FIG. 44 is a diagram summarizing a variant embodiment of the access point shown in FIG. 12, which variant includes additional means making it possible to perform the fourth complex operation;
FIG. 45 is a timing diagram showing how the fourth complex operation is performed;
FIG. 46 shows a fifth complex operation consisting in releasing a relationship between two objects and in inserting a new object between the two objects by establishing two new relationships;
FIG. 47 shows how the fifth complex operation is implemented;
FIGS. 48 and 49 are diagrams summarizing two variants of the first embodiment, which variants include additional logic means for making it possible to perform the fifth complex operation;
FIGS. 50 and 51 are diagrams summarizing two variants of the second embodiment, which variants include additional logic means for making it possible to perform the fifth complex operation;
FIG. 52 shows a sixth complex operation consisting in removing a known object E from a linear chain of objects related by relationships without knowing its adjacent objects, and in automatically establishing a direct relationship between the two possible adjacent objects that flanked the removed object;
FIG. 53 is a diagram summarizing a variant of the first embodiment, which variant includes additional logic means compared with the variant shown in FIG. 30, so as to make it possible to perform the sixth complex operation;
FIG. 54 is a timing diagram showing how this variant operates;
FIG. 55 is a diagram summarizing a variant embodiment of the access point shown in FIG. 12, which variant includes additional logic means making it possible to perform the sixth complex operation;
FIG. 56 is a diagram summarizing a third embodiment of a relationship memory element for the apparatus of the invention, this variant including additional logic means making it possible to perform the first complex operation and the sixth complex operation, i.e. releasing all of the relationships existing between a given object and any other object, then automatically establishing relationships between the objects which were previously related indirectly via the given object;
FIG. 57 is a timing diagram showing how the variant operates for performing the sixth complex operation; and
FIGS. 58 and 59 respectively show variants of the first and second embodiment.
FIG. 1 is a diagram summarizing a portion of a non-optimized first embodiment of the apparatus of the invention. This portion comprises a square array SN constituted by a matrix of memory elements RMP, each element storing the existence or the non-existence of a relationship that could associate two objects belonging to the same set E constituted by N objects that are respectively identifiable by N distinct identifiers: Nos. 1, . . . , N. Initially, we consider the case of a uniform set E, i.e. a set made up of objects belonging to a single category. For example, they may all be cells or they may all be time intervals.
The logic circuits that make use of the stored information are not shown. The array SN has N rows and N columns, each row and each column comprising N elements RMP. The elements RMP are placed at the cross-points of row buses LC(1) . . . LC(N) serving the respective rows of the matrix and column buses CC(1) . . . CC(N) serving respective columns of the matrix.
The existence of a relationship, e.g. between the Xth object and the Yth object, taken in that order, is stored by writing a 1-value bit in the element RMP(X,Y) situated at the cross-point between buses CC(X) and LC(Y). The existence or the non-existence of a relationship between these two objects can be determined by reading the contents of this element.
Write and read control of the buses is described below. The term "bus" is used to cover any conventional means for conveying the same signal to or from a set of memory elements. The simplest embodiment comprises one conductor per signal, but other conventional embodiments implementing multiplexing can be used in apparatus of the invention.
Such a structure requires N.sup.2 memory elements RMP for a set E constituted by N objects. It can quickly be seen that some of the elements are not useful. Those situated on the diagonal of the matrix, shown in dashed lines, are not useful since no object has a relationship with itself. Also, the relationships encountered in practice are generally symmetrical relationships: being reciprocal or inverse. For reciprocal relationships, if an object X has a certain relationship with an object Y, then the object Y has the same relationship with the object X. For example, the relationship "identical to" is symmetrical. For inverse relationships, if the object X has a certain relationship with the object Y, then Y has a fully specified inverse relationship with the object X. For example, considering the order of arrival of a sequence of objects in the context of processing said objects sequentially in the order of their arrival: if an object X arrived before an object Y, then it can be deduced implicitly that the object Y arrived after the object X, and it is therefore not necessary to store the existence of the second relationship.
FIG. 2 is a diagram summarizing a portion of a second embodiment of the apparatus of the invention, optimized for a symmetrical relationship. It comprises a triangular array TN of memory elements. As in FIG. 1, the logic circuits that make use of the stored information are not shown. The matrix of memory elements has been simplified by omitting the memory elements situated on the diagonal and those situated on one-half of the matrix, as defined by said diagonal. The buses CC(1) and LC(N) are omitted since neither of them serves any memory elements.
For example, by using the column bus CC(K) and the row bus LC(1) . . . LC(K-1), for given K less than or equal to N, it is possible to write or read information representing the existence or the non-existence of a relationship between an object of rank K and K-1 other objects Nos. 1, . . . , K-1. The corresponding elements RMP are shown in black. Below, the object of rank K is called object K.
By using the column buses CC(K+1), . . . , CC(N) and the row bus LC(K), it is also possible to write or to read in the elements RMP information indicating the existence or the non-existence of relationships between object K and the objects K+1, . . . , N. The corresponding elements RMP are shown with shading. It can thus be seen that the buses CC(K) and LC(K) are used simultaneously for writing or reading information concerning relationships between the object K and all of the other objects in the set of objects 1, . . . , N. It is possible to connect these two buses together at a common point referred to below as the access point for object K, and written AP(K).
FIG. 3 is a diagram summarizing a third embodiment of the apparatus of the invention that is optimized for a symmetrical relationship and in which there is only one access point AP(K) for each object K, with K lying in the range 1 to N. It comprises a triangular array TN' having, for example, the form of a right-angle triangle. The N column buses CC(X) and the N row buses LC(Y) are replaced by N "orthogonal" buses each comprising two mutually orthogonal branches sharing a common end connected to an access point. Each orthogonal bus corresponds to a respective object. For example, access point AP(K) corresponding to the object of rank K in a set of N objects is connected to an orthogonal bus comprising a branch BO(K) and a branch BO'(K) which branches are respectively parallel to the two sides of the array TN' that are at right angles.
To store information representing the existence or the non-existence of a symmetrical relationship between two distinct objects selected from N, this array TN' comprises ##EQU2## memory elements RMP. The memory elements RMP(i,K) that store relationship information between the object of rank K, for K selected in the range 1 to N, and the objects of ranks i=1 to K-1, are situated at the respective cross-points between the branch BO(K) and the branches BO'(i) of the respective orthogonal buses corresponding to objects of ranks i=1 to K-1. The memory elements RMP(j,K) that store relationship information between the object of rank K and the objects of ranks j=K+1 to N are situated at the cross-points between the branch BO'(K) of the orthogonal bus corresponding to the object of rank K, and the branches BO(j) of the respective control buses corresponding to the objects of ranks j=K+1 to N.
All of the access points AP(1), . . . , AP(N) of the triangular array TN' are connected to logic means LM to provide the control buses with read control signals and write control signals to manage the relationships between the objects.
Below, only symmetrical relationships are considered and the memory element storing the existence or the non-existence of a relationship between an object X and an object Y, and the symmetrical relationship, is written RMP(X,Y) or RMP(Y,X).
The examples of array structure described herein have control buses in the form of mutually orthogonal straight segments. However any other form could be used providing each bus corresponding to an object has at least one cross-point with each of the control buses corresponding to the other objects, since each memory element must be situated at a cross-point between two buses.
FIG. 4 is a perspective diagram summarizing a fourth embodiment of the array which is distributed over three space dimensions. This embodiment is optimized for a symmetrical relationship between four objects No. 1, . . . , No. 4. It comprises four orthogonal buses each constituted by a first branch and a second branch, with the exception of one of the buses in which the second branch is not useful. This fourth embodiment comprises three superposed triangular layers:
a layer TN1 in which the first branches BO(1), . . . , BO(4) of the orthogonal buses are situated;
a layer TN2 in which six relationship memory elements are situated such as the element RMP(3,4) which stores the existence or the non-existence of a relationship between object No. 3 and object No. 4; and
a layer TN3 in which the second branches BO'(1), BO'(2), and BO'(3) of the orthogonal buses are situated.
The first branches BO(1), . . . , BO(4) are connected respectively to four access points AP(1), . . . , AP(4). The branches BO(1), BO(2), and BO(3) are respectively connected to the second branches BO'(1), BO'(2), and BO'(3) by buses BV(1), BV(2), and BV(3) which are orthogonal to the planes of the three layers. Each memory element is connected to the first branch of an orthogonal bus and to the second branch of another orthogonal bus by a plurality of links which are orthogonal to the planes of the layers TN1, TN2, and TN3. For example, memory element RMP(3,4) is connected to branch BO'(3) by a plurality of links L3; and it is connected to the branch BO(4) by a plurality of links L4.
In the same set of N objects, two types of relationship may exist simultaneously between objects: relationships which are mutually exclusive, and relationships which are not exclusive:
When all of the relationships are exclusive, i.e. if there can be only one relationship between two objects in the set belonging to two given categories at any instant, the nature of the relationship between two objects can remain implicit since it can be deduced from the category of each of the two objects. A single relationship memory element can then manage the existence of a relationship between two objects whatever the nature of the relationship. For example, when each of the two objects is either a cell or a time position, there exists three kinds of relationship which are exclusive depending on whether the two objects both belong to the same "cell" category, or both belong to the same "time position" category, or belong respectively to the "cell" category and to the "time position" category.
When the relationships are non-exclusive, and therefore capable of existing simultaneously between two given objects, the array of the management apparatus must include a plurality of memory elements per pair of objects in order to be able to store the existence or non-existence of each of the possible relationships. This array comprises either one memory element per relationship, or else a restricted number of memory elements, with the data representing the existence or the non-existence of each relationship being encoded. For example, the existence or non-existence of six relationships called relationships of types 1, 2, 3, . . . , 6 can be encoded and stored by means of three memory elements by storing the following binary words:
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000 No relationship
001 Relationship of type 1
010 Relationship of type 2
011 Relationship of type 3
100 Relationships of types 2 and 3
101 Relationships of types 2 and 4
110 Relationship of type 5
111 Relationships of types 5 and 6
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FIG. 5 is a diagram summarizing an embodiment of a memory element referenced RMP1(X,Y). It may be used in any of the embodiments described above, SN, TN, or TN'.
For example, this element RMP1(X,Y) is situated at the cross-point between a branch BO1(X) of an orthogonal bus connected to an access point AP1(X) corresponding to an object X, and a branch BO'1(Y) of another orthogonal bus connected to an access point AP1(Y) corresponding to an object Y. These two buses cross without being connected together. In the embodiments described below, the buses are of the type comprising one conductor per signal to be conveyed. However the person skilled in the art could replace them by other bus arrangements using conventional techniques, e.g. for enabling the number of conductors to be reduced.
The element RMP1(X,Y) comprises:
a first input I(Y) receiving three signals ST.sub.y, RT.sub.y, and RS.sub.y ; in this example, this input comprises three conductors which are connected respectively to three conductors of the branch BO'1(Y), respectively conveying these three signals in this example;
a second input I(X) receiving three signals ST.sub.x, RT.sub.x, and RS.sub.x ; in this example, this input comprises three conductors which are connected respectively to three conductors of the branch BO1(X), respectively conveying these three signals in this example;
a first output O1(Y) connected to one of the conductors of the branch BO'1(Y) conveying the signal OL.sub.y, said conductor of the branch BO'1(Y) constituting a wired-OR WOR2;
a second output O1(X) connected to a conductor of the branch BO1(X) conveying a signal OL.sub.x, this conductor constituting a wired-OR WOR3;
a bistable 5 having a set input S, a reset input R, and an output referenced 1;
a logic AND gate 1 having two inputs and one output, which output is connected to the S input of the bistable 5;
a logic AND gate 2 having two inputs and one output, which output is connected to the R input of the bistable 5;
a logic AND gate 3 having two inputs and one output, which output constitutes the output O1(X); and
a logic AND gate 4 having two inputs and one output, which output constitutes the output O1(Y).
The two inputs of the gate 1 are connected respectively to the conductor of the branch BO'1(Y) supplying the signal ST.sub.y and to the conductor of the branch BO1(X) supplying the signal ST.sub.x, so as to set the bistable 5 when the signals ST.sub.y and ST.sub.x are applied simultaneously to the respective access points AP1(X) and AP1(Y) corresponding to the objects X and Y. The two inputs of the gate 2 are connected respectively to the conductor of the branch BO'1(Y) which supplies the signal RT.sub.y and to the conductor of the branch BO1(X) which supplies the signal RT.sub.x so as to reset the bistable 5 when the signals RT.sub.y and RT.sub.x are applied simultaneously to the respective access points AP1(X) and AP1(Y) corresponding to the objects X and Y.
The two inputs of the gate 3 are connected respectively to the output 1 of the bistable 5 which supplies a 1 when said bistable is set, and to the conductor of the branch BO'1(Y) which supplies the signal RS.sub.y. The gate 1 conveys to the output O1(X) the bit stored by the bistable 5 whenever the signal RS.sub.y is applied to the access point AP1(Y) corresponding to the object Y for the purpose of receiving the value of said bit on the access point AP1(X) corresponding to the object X, said bit constituting the signal OL.sub.x.
The two inputs of the gate 4 are connected respectively to the output 1 of the bistable 5 and to the conductor of the branch BO1(X) which supplies the signal RS.sub.x. The gate 4 conveys to the output O1(Y) the bit stored by the bistable 5 whenever the signal RS.sub.x is applied to the access point AP1(X) so as to receive the value of said bit on the access point AP1(Y) corresponding to the object Y, with the value of said bit constituting the signal OL.sub.y.
This embodiment RMP1(X,Y) thus serves to store a 1-value bit in the bistable 5 when both signals ST.sub.x and ST.sub.y are active simultaneously; or to store a 0-value bit when both signals RT.sub.x and RT.sub.y are active simultaneously; or to read the bit stored in the bistable 5 from the access AP1(Y) corresponding to the object Y if reading is controlled by the signal RS.sub.x, or to read it from the access point AP1(X) corresponding to the object X if reading is controlled by the signal RS.sub.y. In this first embodiment, each bus corresponding to an object conveys signals that perform two functions simultaneously: selecting the object and controlling an operation.
FIG. 6 shows by way of example the orthogonal bus constituted by the branches BO(K) and BO'1(K), together with the access AP1(K), all corresponding to the object K. This access has four conductors which are connected respectively to the four conductors constituting the branch BO1(K), and to the four conductors constituting the branch BO'1(K). These conductors enable the following management operations to be performed:
writing information, e.g. one bit of value 1, indicating the existence of a relationship between the object K and another object;
writing information, e.g. a bit of value 0, indicating the non-existence of a relationship between the object K and another object; and
reading information, e.g. the value of one bit that indicates the existence or the non-existence of a relationship between the object K and another object.
To perform such operations, the control signals applied to the access point AP(K) are respectively the following:
a set control signal ST.sub.K ;
a reset control signal RT.sub.K ; and
a read control signal RS.sub.K.
A fourth conductor of the access AP1(K) is an output delivering a binary signal OL.sub.K, to the logic circuits LM giving the result of reading in one or more memory elements, with the conductors OL.sub.K, of the branches BO1(K) and BO'1(K) constituting a wired-OR, referenced WOR1 in the figure.
FIG. 7 is a diagram summarizing a variant RMP1"(X,Y) of the first embodiment. In this variant, the number of signals conveyed by the buses corresponding to the respective objects is minimized, however there is an additional bus OC which is common to all of the objects and which is connected to all of the relationship memory elements. The element RMP1"(X,Y) is situated at the cross-point of a branch BO1"(X) of an orthogonal bus connected to an access point AP1"(X) corresponding to an object X, and a branch BO'1"(Y) of another orthogonal bus connected to an access point AP1"(Y) corresponding to an object Y. Each branch has only two conductors, one conveying a selection signal for selecting all of the elements corresponding to a given object, and the other conveying a read output signal for the given object. The common bus OC has one conductor for each of the operations to be controlled:
one conductor conveys a signal RT for controlling the writing of a 0 value indicating the non-existence of a relationship;
one conductor conveying a signal ST for controlling the writing of a 1 value indicating the existence of a relationship; and
one conductor conveying a signal RD for controlling reading of relationship information.
In this variant RMP1" of the first embodiment, there is thus total separation between object selection signals SS.sub.X and SS.sub.Y and common signals for operation control: RT, ST, RD.
In other variant embodiments, partial separation of those two functions could be envisaged.
The memory element RMP1"(X,Y) comprises:
a bistable 5" having a set input S, a reset input R, and an output referenced 1;
a logic AND gate 1" having three inputs and one output, which output is connected to the S input of the bistable 5";
a logic AND gate 2" having three inputs and one output, which output is connected to the R input of the bistable 5";
a logic AND gate 3" having three inputs and one output, which output constitutes an output from the element RMP1"(X,Y) and is connected to a conductor of the branch BO1"(X), said conductor conveying a read output signal OL.sub.X and constituting a wired-OR WOR3"; and
a logic AND gate 4" having three inputs and one output, which output constitutes an output from the element RMP1"(X,Y) which is connected to a conductor of the branch BO'1"(Y) conveying a read output signal OL.sub.Y and constituting a wired-OR WOR2".
A first input of the gate 1" is connected to one of the conductors of the branch BO'1"(Y) to receive an addressing signal SS.sub.Y. A second input of the gate 1" is connected to a conductor of the branch BO1"(X) to receive an addressing signal SS.sub.X. A first input and a second input of the gate 2" are connected respectively in the same manner. Whatever the type of operation that is to be performed, writing a 1 or a 0 in the bistable 5", a particular element RMP1"(X,Y) is selected by providing simultaneously a selection signal SS.sub.X =1 on access point AP1"(X) and a selection signal SS.sub.Y =1 on access point AP1"(Y) corresponding to the object Y. The nature of the operation performed is determined by an operation control signal applied to the common bus OC. The third input of the gate 1" is connected to the common bus conductor OC for receiving the signal ST to write a 1-value in the bistable 5" when the three signals SS.sub.Y, SS.sub.X, and ST are active simultaneously. The third input of the gate 2" is connected to the conductor of the common bus OC providing the signal RT to write a value 0 in the bistable 5" when the three signals SS.sub.Y, SS.sub.X, and RT are active simultaneously.
A first input of each of the gates 3" and 4" is connected to the output 1 of the bistable 5". A second input of the gate 3" is connected to the conductor of the branch BO'1"(Y) that conveys the selection signal SS.sub.Y. The second input of the gate 4" is connected to the conductor of the branch BO1"(X) that conveys the selection signal SS.sub.X. The third input of the gate 3" and the third input of the gate 4" are connected to the conductor of the common bus OC that conveys the signal RD to control reading when the two signals RD and SS.sub.Y are active simultaneously, or when the two signals RD and SS.sub.X are active simultaneously. In the first case, the read output signal is a signal OL.sub.X supplied to a conductor of the branch BO1"(X). In the second case, the read output signal is a signal OL.sub.Y supplied to a conductor of the branch BO'1"(Y).
Naturally, other variant embodiments can be envisaged by the person skilled in the art by considering all of the variants that are intermediate between those shown in FIGS. 5 and 7.
It should be observed that the individual character of the access points corresponding to the various objects, and of the relationship memory points, makes it possible to perform numerous operations in parallel. For example, in the variant embodiment RMP1 shown in FIG. 5, a read operation from an object X, triggered by sending the signal RS.sub.X over the access AP1(X), causes a read operation to take place in all of the memory elements RMP1(X,Y) for Y=1 to N and Y.noteq.X. A logic signal OL.sub.Y of value 1 appears simultaneously on all of the accesses AP1(Y) of objects Y=1, . . . , N and Y.noteq.X having a relationship established with the object X under consideration, i.e. whose memory elements RMP1(X,Y) contain binary information of value 1.
Also, it is possible to perform a multiple read operation, i.e. simultaneously from a plurality of objects, e.g. X.sub.1, X.sub.2, and X.sub.3. In which case, a logic signal OL.sub.Y of value 1 appears simultaneously on all of the accesses AP1(Y) of objects Y=1, . . . , N having a relationship established with at least one of the objects X.sub.1, X.sub.2, X.sub.3. In such a multiple read operation, the set of objects Y identified as having a relationship established with at least one of the objects X.sub.1, X.sub.2, . . . , X.sub.X is thus the union (in the logic meaning of the term) of the X sets of objects Y that would be identified by X individual reads from a single object at a time from X.sub.1, X.sub.2, . . . , X.sub.X. In addition to identifying all of the objects having a relationship established with at least one of the objects X.sub.1, X.sub.2, . . . , X.sub.X, i.e. with X.sub.1, or with X.sub.2, . . . , or with X.sub.X, a multiple read operation performed simultaneously from the set of N objects serves to identify all of the objects which have at least one relationship established with another object, and all of the objects which have no relationship established with any of the other objects, i.e., typically, to identify objects that are "busy" or "used" and objects that are "free" or "not used" respectively.
A write operation triggered by applying the set signal ST.sub.K to n access points corresponding to a subset of n predetermined objects serves to store simultaneously the existence of all of the two-object relationships for all of the pairs of objects that can be taken from said subset of n objects. In analogous manner, it is possible to store the non-existence of all relationships between all possible pairs of objects in a subset of n objects by applying a reset signal RT=1 to the n access points of the objects in said predetermined subset.
Initially we consider only operations performed on predetermined subsets, i.e. subsets that are either static, i.e. of fixed composition, or that are dynamic but of known composition managed from outside the apparatus of the invention. Subsequently we consider more complex operations performed on subsets of objects that are not predetermined, i.e. of composition that is not necessarily known outside the apparatus.
When the N objects are structured in a plurality of subsets of predetermined objects of composition known outside the apparatus, read operations and write operations are possible as described in the following paragraphs.
If a read operation from one or more objects is to be limited to a known subset of n objects, it suffices for the logic circuits LM to include a logic circuit that takes account only of the n signals OL coming from the n access points corresponding to the n objects of the subset.
By way of example, FIG. 8 shows how relationships are identified that are established between the objects X.sub.3 and X.sub.4 constituting a subset S1 of a set E constituted by the objects X.sub.1, X.sub.2, . . . , X.sub.8 ; and the objects X.sub.5, X.sub.6, X.sub.7 constituting another subset S2. The relationship memory elements that are read are represented by circles. They are of the RMP1 type shown in FIG. 5.
Such identification may be performed by reading simultaneously from the objects of one of the subsets (e.g. S1) and selectively taking into account only the signals OL coming from the access points of the objects in the other subset (i.e. S2 in the example chosen).
To limit the reading to the relationships concerning the objects of the subset S1, the logic circuits LM include a logic circuit LA2 only transmitting the signals RS=1 to the access points AP(X3) and AP(X4) corresponding to the objects of the subset S1. To limit the reading to the relationships concerning the objects of the subset S2, the logic circuits LM include a logic circuit LB2 which takes into account only the signals OL coming from the access points AP(X5), AP(X6), AP(X7) corresponding to the subset S2. The shaded circles represent the memory elements that are read but whose information is not taken into account by the circuit LB2. In this example, the signals OL=1 indicate which objects of the set S2 have at least one relationship with the objects of the set S1.
Let us now examine the possibilities of a write operation on subsets known outside the apparatus.
FIG. 9 shows an example for n=5. Let us consider a subset S made up of five objects A1, A2, B1, B2, B3 in a set E of eight objects (N=8) belonging to the same category. For example, the existence of all of the possible relationships between the five objects may be stored by means of a single write operation, by simultaneously applying five signals ST.sub.K =1 to respective ones of the access points AP(A1), AP(A2), AP(B1), AP(B2), AP(B3), by means of a logic circuit L1 that applies a selection of the subset S, and that is part of the logic circuits LM. The buses that are activated are shown in solid lines. The inactivated buses are shown in dashed lines. Each of the memory elements that perform the write operation is shown by a respective circle.
It appears that the existence of all of the relationships A1-A2, A1-B1, A1-B2, A1-B3, A2-B1, A2-B2, A2-B3, B1-B2, B1-B3, B2-B3 can be stored in the single operation. In analogous manner, it is possible to erase the existence of all of these relationships in a single operation.
However, this first embodiment of the memory elements does not make it possible to perform more selective operations, implementing at least two subsets of the set E, e.g: a subset S1 made up of n1=2 objects Al and A2, and a subset S2 made up of n2=3 objects B1, B2, B3. For example, it is not possible:
to store the existence of relationships between the object A1 and each of the n2 objects B1, B2, B3 without storing the existence of relationships B1-B2, B1-B3, B2-B3 within the subset S2;
or to store the existence of relationships between each object of the subset S1 of n1 objects A1, A2 and each object of the subset S2 of n2 objects B1, B2, B3 without storing the existence of a relationship A1-A2 between the objects of the subset S1 and without storing the existence of a relationship B1-B2, B1-B3, B2-B3 between the objects of the subset S2.
Storing the non-existence of relationships, in other words erasing the contents of the memory elements, poses a similar problem.
FIG. 10 illustrates this problem by showing how the apparatus of the invention operates when it is made up of memory elements RMP1 such as the element shown in FIG. 5. By means of signals ST.sub.K =1, a logic circuit LA1 activates the accesses AP(A1) and AP(A2) corresponding to the subset S1 of the set E, and a logic circuit LB1 activates the accesses AP(B1), AP(B2), and AP(B3) corresponding to the subset S2 of the set E. The activated buses are shown in solid lines. The memory elements that are activated are represented by circles. Those which store the existence of a relationship between an object of the subset S1 and an object of the subset S2 are shown unshaded. Those which store the existence of a relationship between two objects of the same subset S1 or S2 are shaded. It is desirable to be able to store or erase information in the unshaded elements without necessarily performing the same operation in the shaded elements.
FIG. 11 is a diagram summarizing a second embodiment RMP2(X,Y) of the memory element used in the apparatus of the invention. The second embodiment offers the advantage of making more selective setting or resetting possible because it makes it possible to modify relationships between two objects belonging to respective subsets S1 and S2 without necessarily modifying the relationships within the subsets. The buses do not have the same functions as in the first embodiment shown in FIGS. 5 and 6. A first bus referenced OC transmits three signals. In this embodiment, the bus comprises three conductors whose path layout is independent of the layout of the memory elements because the path layout is common to all of the memory elements, and the bus supplies "non-specific" signals controlling an operation selected from a plurality of predetermined operations. The three signals conveyed are as follows:
a signal RT controlling resetting of any memory element that is otherwise addressed;
a signal ST which sets again any memory element that is otherwise addressed; and
a signal RD which controls a read operation in any memory element that is otherwise addressed.
The first bus OC is connected to three inputs (not shown) of the apparatus. The three inputs are independent of the individual access points that correspond respectively to the N objects of the management apparatus.
Each element RMP2 is situated at the cross-point between two individual buses respectively corresponding to two objects, it being possible for the two buses to be respectively of the row bus type and of the column bus type, or of the orthogonal bus type, which types are described above with reference to FIGS. 1 and 3. For example, let us consider two buses of the orthogonal bus type. A first orthogonal bus includes in particular a branch BO2(X), and it is connected to an access point AP2(X) corresponding to an object X. A second orthogonal bus includes in particular a branch BO'2(Y) and it is connected to an access point AP2(Y) corresponding to an object Y. The branch BO2(X) conveys three signals. In this example, it comprises three conductors respectively conveying:
a signal SSA.sub.X for write addressing and selecting group A, or for read addressing;
a signal SSB.sub.X for write addressing and selecting group B; and
an output signal OL.sub.X, resulting from reading the memory elements RMP2(X,Y) connected to the orthogonal bus corresponding to the access AP2(X), each memory element RMP2(X,Y) having an output O2(X) that is connected to a common conductor of the branch LC2(X) so as to constitute a wired-OR WOR5.
The branch BO'2(Y) conveys three signals. In this example, it comprises three conductors respectively conveying:
a signal SSA.sub.Y for write addressing and selecting group A, or for read addressing;
a signal SSB.sub.Y for write addressing and selecting group B; and
an output signal OL.sub.Y, resulting from reading the memory elements RMP2(X,Y) connected to the orthogonal bus corresponding to the access point AP2(Y), each of these memory elements having an output O2(Y) that is connected to a common conductor of the branch BO'2(Y) so as to constitute a wired-OR WOR4.
For reading, there is no selection of group A or B, a single addressing signal suffices:
SSA.sub.Y =1 on the bus BO'2(Y) when reading from the object Y, or SSA.sub.X =1 on the bus BO2(X) when reading from the object X.
For writing, an object K may belong to one and/or the other of the two groups A and B depending on the signals SSA.sub.K and SSB.sub.K that are activated on the access AP(K):
if SSA.sub.K =1 and SSB.sub.K =0, the object K belongs to group A only, for writing;
if SSA.sub.K =0 and SSB.sub.K =1, the object K belongs to group B only, for writing;
if SSA.sub.K =0 and SSB.sub.K =0, the object K belongs to neither of the groups A and B (none of the memory elements storing the existence or the non-existence of relationships between the object K and other objects are activated); and
if SSA.sub.K =1 and SSB.sub.K =1, the object K belongs both to group A and to group B.
This embodiment of a memory element RMP2(X,Y), shown in FIG. 11, comprises:
two write selection inputs IA(Y) and IA(X) which are connected respectively to the conductor conveying the signal SSA.sub.Y in the branch BO'2(Y), and to the conductor conveying the signal SSA.sub.X in the branch BO2(X);
two write selection inputs IB(Y) and IB(X) which are connected respectively to the conductor conveying the signal SSB.sub.Y in the branch BO'2(Y), and to the conductor conveying the signal SSB.sub.X in the branch BO2(X);
a non-specific reset input I2 connected to the conductor of the bus OC that conveys the signal RT;
a non-specific set input I1 connected to the conductor of the bus OC that conveys the signal ST;
a non-specific read control input I5 connected to the conductor of the bus OC that conveys the signal RD;
two read selection inputs I3 and I4 which are connected respectively to the conductor conveying the signal SSA.sub.Y in the branch BO'2(Y), and to the conductor conveying the signal SSA.sub.X in the branch BO2(X);
the above-mentioned outputs O2(Y) and O2(X);
two AND gates 11 and 12, each of which has a first input, a second input, and an output; the first inputs of the gates 11 and 12 constituting the inputs IB(Y) and IA(Y); and the second inputs of the gates 11 and 12 constituting the inputs IA(X) and IB(X);
an OR gate 13 having two inputs respectively connected to the two outputs of the gates 11 and 12, and having one output;
two AND gates 14 and 15, each of which has a first input, a second input, and an output, the first inputs being connected in common to the output of the OR gate 13; the second inputs of the gates 14 and 15 respectively constituting the reset input I2 and set input I1 of the element RMP2(X,Y);
a bistable 16 having: a set input referenced S, connected to the output of gate 14, a reset input referenced R, connected to the output of gate 15, and an output; and
two AND gates 17 and 18, each of which has a first input, a second input, a third input, and an output, the first inputs of the gates 17 and 18 being connected together and constituting the read control input I5; the second inputs of the gates 17 and 18 respectively constituting the read selection signals I3 and I4, the third inputs of the gates 17 and 18 being connected in common to the output of the bistable 16, and the outputs of the gates 17 and 18 respectively constituting the outputs O2(Y) and O2(X).
FIG. 12 shows an orthogonal bus and an access point AP2(K) corresponding to an object K taken by way of example. The orthogonal bus comprises two branches: BO2(K) and BO'2(K). The access point AP2(K) comprises:
a conductor connected to a conductor of the branch BO2(K) and to a conductor of the branch BO'2(K) for conveying the signal SSA.sub.K ;
a conductor connected to a conductor of the branch BO2(K) and to a conductor of the branch BO'2(K) for conveying the signal SSB.sub.K ; and
a conductor connected to a conductor of the branch BO2(K) and to a conductor of the branch BO'2(K) for receiving a signal OL.sub.K and constituting a wired-OR WOR6.
At a relationship memory element RMP2(X,Y) relating to the objects X and Y, a write operation is performed in the memory element when the following two conditions are satisfied on the control bus:
ST=1 or RT=1, on the common bus OC, for writing respectively 1 or 0; and
SSA.sub.X =1 and SSB.sub.Y =1, or SSB.sub.X =1 and SSA.sub.Y =1, respectively on control bus BO2(X) and on control bus BO2'(Y).
Under the latter logic condition, SSA.sub.X.SSB.sub.Y + SSB.sub.X.SSA.sub.Y =1, a relationship memory element RMP2(X,Y) is selected for writing each time that the object X belongs to at least one of the groups A or B (SSA.sub.X =1 or SSB.sub.X =1) and that the other object Y belongs to at least the other group, respectively B or A (SSB.sub.Y =1 or SSA.sub.Y =1), independently of whether each of the objects X and Y belong to a single group or to both groups.
For reading, the memory element RMP2(X,Y) is controlled as follows: relationships existing between the object K and any other object L (without distinguishing between groups A and B) are read by making RD=1 on the bus OC, this signal being common to all the memory elements, and by making SSA.sub.K =1 at the access AP(K) corresponding to the object K in question (the signal SSBK has no effect for reading). A signal OL.sub.i =1 then appears at each access point AP(i) corresponding to the objects i having a relationship established with K, i.e. whose memory element RMP2(K, Li) contains a 1 value bit.
Reading is illustrated in FIG. 13 which shows the logic circuits LM that manage the relationships of a set E made up of eight objects: X1, . . . , X8. FIG. 13 illustrates reading the relationship memory elements concerning relationships between the object X6 and all of the other objects in the set E. A logic circuit L2 supplies a signal SSA=1 (the signal SSB being arbitrary for reading) to the access AP(X6). The memory elements read by the signal RD=1 and the signal SSA=1 being applied simultaneously on the common bus are represented by respective circles.
As with the above-described memory elements RMP1, if reading is to be limited to a known subset of the set X1, . . . , X5, X7, X8, it suffices for the logic circuits LM to include a logic circuit which takes into account only those signals OL which come from access points corresponding to the subset. For example, to read the information indicating the existence or the non-existence of a relationship between the object X6 and a single other object, e.g. X3, it suffices to test the value of the signal OL3, 1 or 0, supplied by the access AP(X3), by means of a logic circuit L3 connected to this access.
More generally, the second embodiment RMP2(X,Y) makes it possible to perform the same read operations as the first embodiment RMP1(X,Y): a single read operation or a multiple read operation (simultaneously from a plurality of objects); and identifying relationships established between objects in two subsets (as illustrated by FIG. 8 with RMP1(X,Y)).
In a variant embodiment of the element RMP1(X,Y) or of the element RMP2(X,Y), and while the memory element is performing a read operation, it restores relationship information simultaneously on the individual bus BO1(X) or BO2(X) corresponding to a first object, and on the individual bus BO'(Y) or BO'2(Y) corresponding to a second object, if it receives a selection signal via at least one of the two individual buses, as well as a read control signal. When this variant embodiment is used, the logic means LM must be suited to the variant, i.e., they must capable of distinguishing which one of the read output signals is supplied via the access to which the selection signal is applied, and which one(s) of said output signals is/are supplied via other accesses.
As regards write operations, the second embodiment RMP2(X,Y) makes it possible to perform:
the same write operations as those that can be performed with the first embodiment RMP1(X,Y), i.e. non-selective operations performed on a single predetermined subset of n objects; and
also particular write operations, i.e. performed selectively between the n1 objects of a first subset, and the n2 objects of a second subset, the two subsets being predetermined.
With the second embodiment, to perform a non-selective write operation on a group of n objects, i.e. on all of the relationships between the n objects taken in pairs, it suffices to transmit simultaneously the following signals:
ST=1 or RT=1 (respectively set or reset) on the common control bus OC; and
SSA.sub.K =1 and SSB.sub.K =1 on each access point AP(K) corresponding to an object K belonging to the subset of n objects in question.
By assigning each of the n objects in question both to group A and to group B for the write operation (SSA.sub.K =1 and SSB.sub.K =1), each relationship memory element RMP2(X,Y) relating to two objects X and Y belonging to the subset of n objects in question receives the signals SSA.sub.X =1 and SSB.sub.X =1 via the control bus BO2(X) of the object X, and receives SSA.sub.Y =1 and SSB.sub.Y =1 via the control bus BO2'(Y) of the object Y. Each element RMP2(X,Y) therefore performs the write operation for the relationship X-Y because one of the objects (X,Y) is selected by one of the groups (A,B), and the other object (Y,X) is selected by the other group (B,A), this also being verified redundantly for both permutations of the groups A and B in this case.
The above-described method is valid for a subset of n objects where 2<n<N. However, it can be noted that another method may be used in the special case n=2, i.e. a write operation for a single relationship between two objects X and Y, namely by assigning arbitrarily one of the objects X to one of the groups A or B and the other object Y to the other group B or A, for this operation. In which case, the signals transmitted simultaneously are:
ST=1 or RT=1 (set or reset) on the common bus OC; and
SSA.sub.X =1 and SSB.sub.X =0 on the control bus of the object X, and SSA.sub.Y =0 and SSB.sub.Y =1 on the control bus of the object Y, or else SSA.sub.X =0 and SSB.sub.X =1 on the control bus of the object X, and SSA.sub.Y =1 and SSB.sub.Y =0 on the control bus of the object Y.
The memory element RMP2(X,Y) in question can also perform the write operation for the relationship X-Y using this other method when n=2.
Let us now examine the particular write operations that can be performed with the second embodiment RMP2(X,Y), i.e. performed selectively between the n1 objects of a first predetermined subset and the n2 objects of a second predetermined subset, without necessarily modifying the relationships between the objects in the same predetermined subset (it is assumed that the two subsets are not identical and that n1 and/or n2 is greater than 1).
In a write operation for relationships between objects belonging to two disjoint or non-disjoint subsets, information (1 or 0) indicating the existence or the non-existence of relationships between the n1 objects in the first predetermined subset and the n2 objects in the second predetermined subset is written by arbitrarily assigning, for the operation, the n1 objects in the first subset to one of the groups A or B (using the selection signals SSA and SSB) and the n2 objects of the second subset to other group B or A.
To clarify how such write operations that are selective between two predetermined subsets of objects are performed, a distinction must be made between two cases in which the predetermined subsets of n1 and n2 objects are either disjoint (each object belonging to a single subset only) or else non-disjoint (at least one object belongs to both subsets). In the first case, each object is present in a single group (A or B) only, and the selection signals used for such an object are either SSA=1 and SSB=0 if it belongs to group A, or SSA=0 and SSB=1 if it belongs to group B for the operation. Whereas in the second case, in which the n1 and n2 objects constitute non-disjoint subsets, at least one of the objects in question (from the n1+n2 objects) is common to both of the predetermined subsets, and for each such common object both selection signals are activated simultaneously, SSA=1 and SSB=1, since it belongs to both groups A and B for the operation.
Such a write operation that is selective between two disjoint or non-disjoint predetermined subsets is thus performed by simultaneously transmitting the following signals:
ST=1 or RT=1 (set or reset) on the common bus OC;
SSA.sub.L =1 and SSB.sub.L =0 on the control bus of each object L that is to be assigned to group A only;
SSA.sub.M =0 and SSB.sub.M =1 on the control bus of each object M that is to be assigned to group B only; and
SSA.sub.N =1 and SSB.sub.N =1 on the control bus of each object N that is to be assigned both to group A and to group B (common object).
FIGS. 14 and 15 respectively illustrate these two equivalent methods of writing the existence or the non-existence of relationships between firstly the objects A1, A2 of a subset S1, and secondly the objects B1, B2, B3 of a subset S2, the two subsets S1 and S2 being assumed to be disjoint.
In these figures, the addressing and selection signals are distinguished as follows:
SS.sub.A =1: solid thick lines;
SS.sub.B =1: dashed thick lines;
SS.sub.A =0: solid fine lines; and
SS.sub.B =0: dashed fine lines.
In addition, the memory elements that perform write operations are indicated by circles.
It should be noted that, unlike what occurs with the first embodiment RMP1 (shown in FIG. 8), the second embodiment RMP2 does not cause information to be written indicating the existence or the non-existence of relationships between the objects A1 and A2 in the same subset S, or between the objects B1, B2, B3 in the same subset S2, when the subsets S1 and S2 are disjoint as is assumed in FIGS. 14 and 15. Conversely, when the subsets are not disjoint, the existence of one or more objects common to two subsets causes certain relationships within the same subset to be written (see below with reference to FIG. 18).
For the example shown in FIG. 14, the logic circuits LM include:
a logic circuit LA3 supplying signals SSA=1 and SSB=0 to the accesses AP(A1) and AP(A2) of the objects of the subset S1 assigned to group A; and
a logic circuit LB3 supplying signals SSA=0 and SSB=1 to the accesses AP(B1), AP(B2), AP(B3) of the objects of the subset S2 assigned to group B.
All of the other signals SSA and SSB at the other accesses have a 0 value. The logic circuits LM supply the write signal ST=1 or RT=1 (respectively set or reset) to the common bus which is not shown.
In other examples in which certain objects are to be assigned both to group A and to group B, a logic circuit LAB is provided for supplying the signals SSA=1 and SSB=1 to the access points corresponding to these objects. Since the logic circuit LAB is not used in the example shown in FIGS. 14 and 15, it is shown in dashed lines.
For the example shown in FIG. 15, the logic circuits LM include:
a logic circuit LA4 supplying signals SSA=0 and SSB=1 to the accesses AP(A1) and AP(A2) of the objects of the subset S1 that are assigned to group B; and
a logic circuit LB4 supplying the signals SSA=1 and SSB=0 to the accesses AP(B1), AP(B2), AP(B3) of the objects of the subset S2 that are assigned to group A.
All of the other signals SSA and SSB at the other accesses have a 0 value. The logic circuits LM supply the write signal ST=1 or RT=1 (set or reset respectively) to the common bus which is not shown.
FIG. 16 shows a bus structure in a variant embodiment of the array of memory elements of the apparatus of the invention. This array is still made up of the memory elements RMP1 shown in FIG. 5 but the conductors conveying the signals RT.sub.K and ST.sub.K in the branch BO(K) are no longer connected to the corresponding conductors in the branch BO'(K) as shown on FIG. 6. In this variant, the two branches are independently write controlled.
An access point AP'(K) is shown in FIG. 17. It is provided with six conductors:
a conductor conveying a set signal STA.sub.K to all of the elements connected to branch BO1(K), when the object K belongs to group A;
a conductor conveying a set signal STB.sub.K to all of the elements connected to the branch BO1(K), when the object K belongs to group B;
a conductor conveying a reset signal RTA.sub.K to all of the elements connected to the branch BO1(K), when the object K belongs to group A;
a conductor conveying a reset signal RTB.sub.K to all of the elements connected to the branch BO1(K), when the object K belongs to group B;
a read control conductor conveying a read control signal RS.sub.K to all of the elements connected to the orthogonal bus constituted by the two branches BO1(K) and BO1'(K); and
a read output conductor supplying the logic circuits LM with a signal OL.sub.K resulting, via a wired-OR, from all of the signals supplied by reading the elements connected to the orthogonal bus constituted by the two branches BO'1(K) and BO1(K).
This structure for the array of memory elements RMP1 makes it possible to perform selective addressing similar to that made possible by the above-described bus structure with the elements RMP2, in particular for performing write operations between objects of two disjoint subsets S1 and S2, without causing any unwanted writing of a relationship between two objects belonging to the same subset.
This structure includes twelve buses providing access to the memory elements, instead of nine in the variant shown in FIGS. 11 and 12. But each memory element includes less gates: two AND gates and one OR gate less.
FIG. 16 shows how this variant operates in an example in which the write operation concerns the relationships between the objects A1, A2, A3 constituting a subset S1 and assigned to group A, and the objects B1, B2 constituting a subset S2 and assigned to group B. The logic circuits LM include a logic circuit LA5 which simultaneously supplies a signal STA=1 and a signal STB=0 to the access points AP(A1), AP(A2), AP(A3) corresponding to the objects in group A; and they include a logic circuit LB5 which simultaneously supplies a signal STB=1 and a signal STA=0 to the access points AP(B1) and AP(B2) corresponding to the objects in group B.
The elements RMP1 that are write activated are shown by circles. The conductors conveying the active signals are shown in solid or dashed thick lines. The conductors supplying the signal STA=1 for group A are shown in solid thick lines. The conductors supplying the signal STA=0 for group B are shown in solid fine lines. The conductors supplying the signal STB=1 for group B are shown in dashed thick lines. The conductors supplying the signal STB=0 for group A are shown in dashed fine lines.
However, it should be noted that this variant array as shown in FIG. 16 does not offer the same operating flexibility as the preceding version of the array with the elements RMP2, in terms of the composition of the subsets of objects A and B for a write operation between two subsets.
In the preceding version, with the elements RMP2, each object K may be freely assigned to one of the groups A and B or to both groups, depending on the needs of the operation, independently of the position of the object K relative to the other objects. For example, from a set E of eight objects referenced 1, 2, 3, 4, 5, 6, 7, 8, a write operation may be performed on any two subsets (disjoint or non-disjoint) of the set E, e.g. a subset S1 comprising the objects 1, 3, and 7, and a subset S2 comprising the objects 2, 3, 5, and 8.
Conversely, in the version with the elements RMP1, shown in FIGS. 16 and 17, the physical separation of the two branches BO1(K) and BO1'(K) introduces a constraint into the composition of the subsets S1 and S2 which must be not only disjoint, but also such that their objects are on either side of a physical separation in the row of the access points of the objects in the set E.
For example, FIG. 15 may represent an array for eight objects, where consideration is given to an operation between a subset S2 comprising the objects B1 and B2, and a subset S1 comprising the objects A1, A2, and A3. This operation is possible because the two subsets S1 and S2 are disjoint and are situated on either side of a physical separation between the objects B2 and A1, which separation delimits two distinct regions. This physical separation is shown in dot-dash lines in FIG. 15.
However, this variant does not make it possible to perform an operation on two subsets such as those mentioned above, namely two non-disjoint subsets for which the memory elements cannot be physically separated on either side of such a physical separation.
Such an example is illustrated in FIG. 18 which shows how the array based on the second embodiment RMP2(X,Y) operates for two subsets S1, comprising objects referenced 1, 3, and 7 (n1=3), and S2, comprising objects referenced 2, 3, 5, and 8 (n2=4), from the N=8 objects of the set in question. The subsets S1 and S2 are not disjoint because they have object 3 in common. For example, the subset S1 is assigned to group A and the subset S2 is assigned to group B (assigning subset S1 to group B and subset S2 to group A would give the same result).
The logic circuits LM include logic means (not shown in FIG. 17) supplying the appropriate addressing and selection signals (SSA, SSB) for each object, on the basis of the rules described above for the second embodiment RMP2(X,Y), and depending on whether each object belongs to group A, to group B, or to both groups, namely:
logic means for supplying addressing and selection signals (SSA=1 and SSB=0) for the objects which belong to group A only;
logic means for supplying addressing and selection signals (SSA=0 and SSB=1) for the objects that belong to group B only; and
logic means for supplying addressing and selection signals (SSA=1 and SSB=1) for the objects that belong both to group A and to group B.
The appropriate values of the signals SSA and SSB for each object are given in FIG. 18, and the use of solid or dashed, thick or fine lines is the same as in FIGS. 14 and 15. It can be observed that the access point AP(3) corresponding to the object 3 common to both groups A and B receives signals SSA.sub.3 =1 and SSB.sub.3 =1 simultaneously; in addition, the access points AP(4) and AP(6) of the objects 4 and 6 which are not concerned by this operation receive signals SSA=0 and SSB=0.
In the array of memory elements RMP2(X,Y), the elements that perform a relationship write operation are indicated by a circle in FIG. 18, namely the relationships 1-2, 1-3, 1-5, 1-8, 2-3, 2-7, 3-5, 3-7, 3-8, 5-7, and 7-8. It can be noted that, in this example of non-disjoint subsets, the existence of an object 3 common to the two subsets S1 and S2 causes writing of relationships between objects of the same subset (which are also relationships between objects of the two subsets), namely 1-3, 2-3, 3-5, 3-7, and 3-8.
The apparatus of the invention may include a filter connected to each bus conductor OL.sub.K connecting together all of the memory element outputs relating to a given object K, for applying a filtering mask to the signals supplied in parallel via these bus conductors. The filter may then replace the logic circuits L3, LB3, described above, for the read operations.
FIG. 19 is a diagram summarizing a variant RMP2"(X,Y) of the second embodiment of the memory element used in the apparatus of the invention. This variant includes no common bus for controlling the operations. However, it makes it possible to modify the relationships between two objects belonging to respective ones of two subsets, without necessarily modifying the relationships within the subsets. Each element RMP2" is situated at the cross-point between a branch BO2"(X) of a bus corresponding to an object X and a branch BO'2"(Y) of a bus corresponding to an object Y. Each of the branches comprises six conductors in this embodiment. By way of example, the branch BO'2"(Y) conveys the following signals:
STA.sub.Y and STB.sub.Y for controlling writing of a 1 value, enabling the object Y to be assigned to a group A, to a group B, or to both groups at the same time;
RTA.sub.Y and RTB.sub.Y for controlling writing of a 0 value, enabling the object Y to be assigned to a group A, to a group B, or to both groups at the same time;
RD.sub.Y for controlling reading; and
OL.sub.Y, a common read output signal for all of the elements that might to store a relationship between the object Y and another object.
The element RMP2"(X,Y) comprises:
a bistable 66 that has a set input S, a reset input R, and an output 1;
a an OR gate 63 having two inputs and one output which is connected to the S input of the bistable 66;
an OR gate 67 having two inputs and one output which is connected to the R input of the bistable 66;
an AND gate 62 having two inputs and one output which is connected to a first input of the gate 63;
an AND gate 61 having two inputs and one output which is connected to the second input of the gate 63;
an AND gate 69 having two inputs and one output which is connected to a first input of the gate 67;
an AND gate 68 having two inputs and one output which is connected to the second input of the gate 67;
an AND gate 64 having an input connected to the output 1 of the bistable 66, an input connected to a conductor of the branch BO'2"(Y) conveying the signal RD.sub.Y, and an output which constitutes an output of the element RMP2"(X,Y) and which is connected to a conductor of the branch BO2"(X), conveying a common output signal OL.sub.X and constituting a wired-OR WOR5"; and
an AND gate 65 having an input connected to the output 1 of the bistable 66, an input connected to a conductor of the branch BO2"(X) conveying a signal RD.sub.X, and an output which constitutes an output of the element RMP2"(X,Y) and which is connected to a conductor of the branch BO'2"(Y) conveying a common output signal OL.sub.Y and constituting a wired-OR WOR4".
For reading, there is no group A or B selection, a single addressing signal suffices: RD.sub.Y =1 on the branch BO'2"(Y), when reading from object Y, or RD.sub.X =1 on the branch BO2"(X), when reading from object X.
For writing, an object K may belong to one and/or the other of the two groups A and B, depending on the signals that are applied to the bus. For example, to write a 1 value:
if STA.sub.Y =1 and STB.sub.Y =0, the object Y belongs to group A only for writing;
if STA.sub.Y =0 and STB.sub.Y =1, the object Y belongs to group B only;
if STA.sub.Y =0 and STB.sub.Y =0, the object Y belongs to neither of the groups A and B, and therefore none of the memory elements that store the existence or the non-existence of relationships with the object Y are activated; and
if STA.sub.Y =1 and STB.sub.Y =1, the object Y belongs both to group A and to group B.
Likewise, it is possible for the object to be assigned to group A or B for writing a 0 value, by means of the signals RTA.sub.X and RTA.sub.Y. Naturally, the same operations are possible from the access point AP2"(X) for the object X.
A write operation in which the existence (or the non-existence) of a relationship is written in the element RMP2"(X,Y) relating to the objects X and Y is performed when the selection and operation control signals satisfy the following logic equation: STA.sub.X.STB.sub.Y +STB.sub.X.STA.sub.Y =1 (or RTA.sub.X.RTB.sub.Y +RTB.sub.X.RTA.sub.Y =1).
A person skilled in the art can implement other variants of the second embodiment, as intermediates between the variants RMP2 and RMP2", shown respectively in FIGS. 11 and 19.
Let us now consider the case of managing relationships in a set made up of static subsets of objects belonging to different categories. For example, let us consider managing a set of N objects comprising N1 objects which are cells and N2 objects which are time positions. In this example N=N.sub.1 +N.sub.2. Such an example is not at all uniform because the relationships to be implemented are very different, namely:
managing the relationships between N1 possible cells (such as grouping them together in classes of priority, in sequence, etc.);
managing the relationships between N2 possible time positions (grouping together free time positions, sequence of busy time positions, etc.); and
managing the relationships between N1 possible cells and N2 possible time positions (associating a cell with a time position).
FIG. 20 is a diagram showing the array of apparatus of the invention, making it possible to manage such a non-uniform set EH comprising N objects. The logic circuits LM are not shown in this figure. The array is analogous to the triangular array TN shown in FIG. 3, which array managed a uniform set of N objects belonging to the same category. In the case being considered, the N access points of the array correspond respectively to the N objects of the set EH, e.g. by allocating the access points of rank 1 to N1 to the cells C.sub.1, . . . , C.sub.N1 constituting the subset CL grouping together the cells, and by allocating the access points of rank N+1 to N respectively to the time positions P.sub.1 to P.sub.N2 constituting the subset PT grouping together the time positions. The make-up of the subsets CL and PT is fixed. The relationship management apparatus may be considered to be three simpler apparatuses D1, D2, D3 assembled together.
FIG. 21 shows the three simpler apparatuses:
apparatus D1 has a triangular structure and it manages the relationships between the N1 cells;
apparatus D2 has a rectangular matrix structure and it manages the relationships between the N1 cells and the N2 time positions; and
apparatus D3 has a triangular structure and it manages the relationships between the N2 time positions.
In the particular case when it is not necessary to manage relationships between the time positions, the apparatus may be simplified by omitting apparatus D3.
FIG. 22 is a diagram showing the array as simplified in this way. Apparatus D1 comprises a triangular array analogous to the array TN' described with reference to FIG. 3, while apparatus D2 comprises a rectangular array analogous to the square array SN described above with reference to FIG. 1.
Let us now consider managing relationships between the objects belonging to dynamic subsets. Such management consists in performing operations on certain relationships between objects that are not necessarily all known outside of the apparatus, but that belong to subsets identified indirectly. The apparatus of the invention is organized to manage N objects at the most, but in practice it manages only a number n of objects at a given instant, a number N-n of access points being "not used" or "free" at this instant.
The number of subsets to be managed depends:
either solely on the use that is made of the apparatus of the invention, in which case the number of subsets is fixed;
or else also on the states of the objects managed by the apparatus, in which case the number of subsets varies over time.
For example, the relationships between cells and time intervals referred to as time positions are managed by implementing subsets, each of which groups together cells associated to a given time position. The existence at a given instant of such a subset depends on the existence of at least one cell associated with the time position relating to the subset. Such a subset may therefore disappear at certain moments, if no cell arrives that is associated with one of the possible time positions.
FIGS. 23 to 26 show four examples of relationship elementary structures making it possible to manage the objects in a dynamic subset. In each of the structures, one of the objects F plays a special role and it is referred to as a "reference" object for accessing the subsets being considered. It is the only one of the objects in the subset that is known outside the management apparatus. The other objects are known only by the relationship management apparatus which stores the existence of relationships between all of the objects.
FIG. 23 shows a ring structure which comprises the reference object F and objects T, K, P, and L, related by relationships F-T, T-K, K-P, P-L, and L-F, and forming a ring.
FIG. 24 shows a meshed structure in which the same objects are related by the same relationships as in the preceding structure, but with the following relationships as well: F-K, F-P, T-L, T-P, K-F, and K-L.
FIG. 25 shows a star structure comprising the same objects, but in which the only relationships are:
F-T, F-K, F-P, and F-L.
FIG. 26 shows a linear structure comprising the same objects but in which the relationships are: F-L, L-P, P-K, and K-T.
An additional object W may be added in different ways depending on the structure of the subset to which the object is to be added.
If the subset has a ring structure such as the structure shown in FIG. 23, the new object W is inserted either between objects F and T, or between objects F and L. This insertion involves releasing the relationship F-T, or F-L, and setting up two new relationships W-F and W-T, or W-F and W-L. This operation in which an object is added is therefore an operation |