Method of scheduling interrupts to the linked lists of transfer descriptors scheduled at intervals on a serial bus

Abstract

A computer system including a serial bus host controller and host controller driver. The host controller driver providing data structures for the host controller to operate on. The data structures having a linking mechanism for processing lists of descriptors, and alternate buffer configurations for receiving data from the serial bus devices.

Claims

I claim:

1. A method of scheduling interrupts, the method comprising the steps of:

(a) developing a tree-structured interrupt list comprised of stages numbering x, each stage having a number of individual interrupt lists equal to 2.sup.x-1, two interrupt lists from each higher numbered stage linking to a single interrupt list of a next lower numbered stage to form a linked list, each interrupt list of a lower numbered stage being linked to only two interrupt lists of a higher numbered stage, each stage corresponding to a polling interval;

(b) developing a table having a number of entries corresponding to the number of interrupt lists of the highest stage, each entry containing a pointer to one of the interrupt lists of the highest stage;

(c) indexing into one of the table entries according to a frame number on the occurance of a frame boundary; and

(d) processing the interrupts according to the linked list.

2. The method of claim 1, further comprising the step of:

(e) indicating an error condition if all the interrupts of the linked list are not processed before the frame has ended.

3. The method of claim 1, wherein each individual interrupt list is a list of endpoint descriptors with each endpoint descriptor pointing to a queue of transfer descriptors and wherein step (d) further comprises the steps of:

(f) selecting a list;

(g) obtaining an endpoint descriptor from the selected list;

(h) obtaining a transfer descriptor from the queue of the endpoint descriptor;

(i) processing the interrupt identified in the transfer descriptor;

(j) determining if a next transfer descriptor is available;

(k) repeating steps (h)-(j) if a next transfer descriptor is available;

(l) determining if a next endpoint descriptor is available if a next transfer descriptor is not available; and

(m) repeating steps (g)-(l) if a next endpoint descriptor is available.

4. A data structure in a memory arranged to define a linked list, comprising:

one or more endpoint descriptors, each including:

a transfer descriptor field; and

a next endpoint descriptor field; and

one or more transfer descriptors, each including:

a next transfer descriptor field for linking to a next transfer descriptor if not null,

wherein said endpoint descriptors are linked to a subsequent endpoint descriptor if said next endpoint descriptor field is not null and each said endpoint descriptor is linked to a first transfer descriptor if said transfer descriptor field is not null.

5. The data structure of claim 4, wherein each said transfer descriptor further comprises:

a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.

6. The data structure of claim 5, wherein each said transfer descriptor further comprises:

a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.

7. The data structure of claim 4, wherein each said endpoint descriptor further includes:

a tail pointer field for indicating the presence of an transfer descriptor if said tail pointer field is not equal to said transfer descriptor field.

8. A computer system, comprising:

a processor;

a hard disk subsystem coupled to said processor;

a serial bus host controller coupled to said processor;

a memory coupled to said processor and said serial bus host controller arranged to define a data structure, comprising:

one or more endpoint descriptors, each including:

a transfer descriptor field; and

a next endpoint descriptor field; and

one or more transfer descriptors, each including:

a next transfer descriptor field for linking to a next transfer descriptor if not null,

wherein said endpoint descriptors are linked to a subsequent endpoint descriptor if said next endpoint descriptor field is not null and each said endpoint descriptor is linked to a first transfer descriptor if said transfer descriptor field is not null.

9. The computer system of claim 8, wherein each said transfer descriptor further comprises:

a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.

10. The computer system of claim 9, wherein each said transfer descriptor further comprises:

a current buffer pointer to indicate an address of the next memory location to be accessed during a transfer.

11. The computer system of claim 8, wherein each said endpoint descriptor further includes:

a tail pointer field for indicating the presence of an transfer descriptor if said tail pointer field is not equal to said transfer descriptor field.

Description

SPECIFICATION

This application claims the benefit of U.S. provisional application Ser. No. 60/003,191, filed Sep. 5, 1995, now pending and U.S. provisional application Ser. No. 60/003,190, now pending filed Sep. 5, 1995.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method of managing scheduled transfers, and more specifically to a method of linking lists of scheduled transfers, especially for serial bus transfers.

2. Description of the Related Art

Computer systems are becoming ever more powerful with each passing moment. Many new advanced bus structures such as the PCI or Peripheral Component Interchange bus have been developed to allow greater performance of the computer system. Additionally, new devices and uses are being developed for the computer systems. In the past the computer has been essentially a stand-alone device or networked with other computer systems. However, today the modern personal computer is becoming a much more connected and multimedia oriented system. For example, now high speed video and audio functions are becoming commonplace and the integration with the telephone system has already begun.

However, many of these new features and existing devices such as the keyboard, mouse and serial and parallel ports are well below the ultimate bandwidth or capability of the advanced buses such as the PCI bus. Therefore, it is not efficient to connect each one of the functions and devices to the PCI bus directly, as this would impact bus loading and greatly increase overall costs. Additionally, many of these new functions are essentially serial in nature, with the data transferred in a bit stream rather than over a parallel bus structure. This is provided for many reasons, such as reduced wiring costs, and can be done because of the lower data rates which are required.

Therefore, it has been proposed to develop a serial bus architecture to connect all of these various lower bandwidth devices. The universal serial bus (USB) is organized with a host controller (HC) having a series of ports, which can then be connected either directly to devices or functions or to further hubs which have below them further devices or functions. A hub or the host controller may in addition incorporate functions if desired. In this manner a tree structure can be developed to allow a reasonable number of functions or devices to be attached to the serial bus system.

The host controller connects to a bus in the computer system, for example the PCI bus. It is desirable for the bus to support 32 bit addressing, bus mastering and guaranteed access latency. By having the host controller act as a concentrator, only a single connection to the PCI bus is necessary. The connection is better able to utilize the performance of the PCI bus without requiring numerous connections. The host controller, each hub, and each function or port contain particular control registers and control logic for doing set up and initialization operations.

The USB devices are accessed by a unique USB address. Each USB device additionally supports one or more endpoints with which the computer system may communicate.

Four basic types of data transfers are defined in the USB system. The first type is isochronous transfers, which are characterized as periodic, continuous communication between host and device typically used for time-sensitive data/control, such as telephony information or audio information. The second type is bulk transfers, which is characterized by non-periodic, large bursty communication typically used for transfers that can be delayed until bus band width is available, such as printer operations and conventional serial port operations. The third type is control transfers, which are characterized by bursty, non-periodic, host software initiated requests/response communications typically used for command/status operations. The fourth type of transfer, called interrupt transfers, are characterized as small bursty, non-periodic, low frequency, device-initiated communications typically used to notify the host of device service needs, such as is required for keyboard, mouse, pointing device and pen interfaces.

Information is broadcast over the USB from the host controller in a series of packets, with the host controller acting as the bus master and hubs and devices only responding upon request or polling access of the host controller. The packet types include data packets, token packets for use from host to device, a handshake packet and a special control packet. Data packets are the isochronous, asynchronous block, and asynchronous control types. Token packets allow transfer of data packets. Handshake packets are used to perform a ready handshake after transfer of a data or control packet to acknowledge successful receipt or indicate unsuccessful receipt. Special control packets are used for logical reset and status request transfers. Packets are scheduled into queues for transmission over the serial bus in a time division multiplexed fashion.

Each USB transaction begins when the host controller, on a scheduled basis, send a USB packet describing the type of transfer, the USB device address and the endpoint number. This packet is the token packet. The USB device that is addressed selects itself by decoding the appropriate address fields. In a given transaction, data is transferred either from the host to a device or from a device to the host. The direction of data transfer is specified in the token packet. The source of the transfer then sends a data packet or indicates it has no data to transfer. The destination responds with a handshake packet indicating whether the transfer was successful.

Each device and port on a hub or the host controller includes the capabilities to handle the low level bus transfer protocol between the particular node of the appropriate hub and the device itself. Thus, a relatively simple transfer protocol, with a limited number of packet types is defined. More details on the serial bus architecture are provided in the Universal Serial Bus Specification 0.9, dated Mar. 20, 1995, available from Intel Corp. This specification is hereby incorporated by reference.

The computer system communicates to the USB devices via hardware and software layers and interfaces. The host controller and USB devices are primarily hardware based with the USB devices connecting to the host controller in the manner described above. A host controller driver (HCD) and USB driver are primarily software based and provide the software portion of the architecture. The host controller is responsible for communicating information between the host controller driver and the USB devices. The host controller driver is responsible for communicating information between the USB driver and the host controller. A host controller interface (HCI) is the bridge between software (HCD) and hardware (HC).

The USB does not provide a mechanism for attached devices to arbitrate for use of the bus. As a consequence, arbitration for use of the serial bus is "predictive" with the host controller and host software assigned the responsibility of providing service to devices when it is predicted that a device will need it. Usage of the serial bus varies widely among the different data transfer types (isochronous, interrupt, bulk and control) making the task of managing transfers and memory difficult.

Additionally, interrupts on the USB are controlled by the host controller. Each frame, a list of devices to be polled for interrupts is traversed. The host controller issues a token packet to the device wherein if the device needs servicing it can respond to the token packet, thereby initiating an interrupt. Since devices have different servicing requirements, only certain devices are polled each frame. Other devices may be polled much less frequently. When interrupts have been serviced, the interrupt is removed from the list.

Thus, it is anticipated that the transfer lists and the interrupt list may vary greatly from one frame to another. As a result, the overhead from managing these lists and the related memory space requirements will vary from frame to frame. Therefore, it is desirable to provide simplified data structures to the host controller thereby simplifying the operation of the host controller, minimizing memory access and size requirements and providing a simple method of adding and removing devices from the servicing lists.

SUMMARY OF THE INVENTION

A computer system according to the present invention includes a serial bus for communicating with serial bus devices and accompanying an host controller. Each serial bus device may have more than one endpoint for identifying communications processes. A host controller driver (HCD) provides a software layer for system software to communicate with the host controller.

The host controller driver sets up lists of transactions for the host controller to operation on during serial bus frame intervals. The lists are comprised of endpoint descriptors and transfer descriptors. Endpoint descriptors may be linked to other endpoints descriptors to create a list of endpoint descriptors. Each endpoint may further link to the head of a transfer descriptor list for processing transactions of the endpoint. The structure of the descriptors provides the host controller with a convenient method of linking and unlinking the descriptors as they are processed.

The lists are used for isochronous, interrupt, control and bulk type transfers. The interrupt lists are indexed according to the current frame number. The end of each list is linked to the beginning of the next highest priority list so that during frame processing the host controller may efficiently process the lists.

Data is stored into system memory by the host controller according to a memory data buffer structure of the transfer descriptors. Transfers greater than a single page are handled by either a virtual or physical configuration. In a virtual configuration, a current buffer pointer is incremented after receiving data to indicate the next data location. If the pointer crosses a page boundary, the next page is indicated by a buffer end pointer. Thus, only two pointers are needed to describe a page crossing buffer, and the pages need not be contiguous.

In a physical configuration, page crossings are insignificant. The current buffer pointer is incremented after data is received. When the current buffer pointer is equal to the buffer end pointer, the buffer limit has been reached. Thus, the same buffer descriptors alternatively describe a memory data structure that may cross many page boundaries and be larger than two pages.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:

FIG. 1 is a block diagram illustrating a computer system according to the preferred embodiment;

FIG. 2 is a functional block diagram illustrating the interaction of software and hardware;

FIG. 3 is a process diagram illustrating the endpoint and transfer descriptor lists;

FIGS. 4A, 4B and 4C are format descriptors for an endpoint descriptor, a general transfer descriptor, and an isochronous transfer descriptor respectively; and

FIG. 5 is a process diagram illustrating an interrupt list.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, the computer system C according to the preferred embodiment is generally shown. The computer system C includes a processor 100 such as a Pentium.RTM. or 486 processor by Intel or their equivalents. It is understood that other processors could of course be utilized. The processor 100 is connected to a second level or L2 cache 102 and to a memory and L2 cache controller and PCI bridge 104 and address and data buffer 106. The main memory 108 of the computer system C is connected between the memory and L2 cache controller 104 and the address and data buffer 106. It is understood that the processor 100, cache 102, memory and cache controller 104, address and data buffer 106 and main memory 108 form the processor system and processor to PCI bus bridge according to a PCI system. It is understood of course that alternate processor systems and high speed bus architectures could be utilized if desired. Further, the address buffering could be included in the PCI bridge 104.

The PCI bridge 104 and address and data buffer 106 are connected to a PCI bus 110 which performs the high speed high performance back bone of the computer system C. A PCI to ISA (Industry Standard Architecture) bridge 110 is connected between the PCI bridge 110 and an ISA bus 114. A floppy disk controller 116 is connected to the ISA bus 114, as is the system ROM (read only memory) 118. The ROM 118 contains BIOS (basic input/output services) code for testing and initializing the computer system C and the serial bus. Additionally, there may be a plurality of ISA slots connected to the ISA bus 114 for receiving interchangeable cards.

The majority of the devices are connected to the PCI bus 110. For example, a SCSI or IDE (Intelligent Drive Electronics) controller 122 is connected to the PCI bus 110 and to the associated disk drives and other devices (not shown). A network interface card (NIC) 124 is also connected to the PCI bus 110 to allow high performance network connections. Further, a video graphics system 126 is connected to the PCI bus 110 and to an associated monitor 128. A fax/modem DSP (digital signal processor) 138 can also be connected to the PCI bus 110 for fax and modem data processing. As noted, this is an exemplary computer system architecture and is provided for explanation, variations being readily apparent to one skilled in the art.

Of interest to the present description, a serial bus host controller 130 is also connected to the PCI bus 110. The serial bus host controller 130 of the illustrated embodiment acts as both a host controller and a hub, with various hubs and functions connected to the host bus controller 130. For example, a printer 132 is connected to one port of the serial bus host controller 130, while an expansion hub 134 is connected to a second port. The expansion hub 134 provides further expansion capabilities, such as connecting to a keyboard 140 according to the present invention. The keyboard 140 further acts as a hub itself and a node, in that it is connected to the monitor hub but further contains ports to connect to the mouse 142 and a pen or stylus pointing device interface 144. This further physical connection is appropriate as those are the primary input devices and they are in most cases generally relatively near the keyboard 140 to ease use of operation. The keyboard interface will be described in more detail below. A telephony interface 136 containing the necessary CODEC and DAA components is connected to a third port and also receives a telephone line. The telephone line can be any of the available types such as an analog line, an ISDN line, a PBX connection and so on.

In the illustrated embodiment, the monitor 128 further acts as a hub and as a node. The monitor 128 is thus connected to one port of the serial bus host controller 130. The node or device function of the monitor 128 allows configuration of the monitor 128 independent from the high speed data utilized in the video system 126. The monitor 128 preferably acts as a hub because of the conventional physical arrangement of a modern computer system. Preferably, the system unit which contains the other devices is located under the desk or in a relatively remote location, with only the monitor 128, a keyboard 140, a pointing device such as a mouse 142 or pen 144, a telephone handset 146, and microphone and speakers relatively accessible to the user. As the monitor 128 effectively forms the central core of this unit, it is logically a proper location for a hub. It is noted that, although, preferably the keyboard is coupled to the monitor for physical convenience, for simplicity of explanation herein the keyboard is shown coupled directly to the host controller 130. The telephone handset 146 could be connected to one port of the monitor hub to receive digitized analog information either directly from the telephony interface 136 or as otherwise available, such as from an answering machine or voice mail function. The microphone is part of audio input circuitry 148 which is connected to a second port of the monitor hub, while audio output circuitry 150 contains the speakers used for audio output. In all cases, each one of the particular devices connected over the serial bus system includes control ports and configuration registers which need to be accessed by the processor 100 via the serial bus host controller 130 to allow control and setup of the individual devices. Thus it can be seen that in the computer, the relatively lower data rate functions are connected to the serial bus host controller 130 according to the serial bus system.

The host controller 130 communicates to the computer system C through a software interface, called a host controller driver (HCD) 200, as shown in FIG. 2. The HCD software provides information between the host controller 130 and a serial bus driver 202. The serial bus driver 202 is system software dependent for interfacing an operating system of the computer system C to the serial bus and serial bus devices such as the monitor 128, generically referred to hereafter as serial bus devices 204.

The serial bus devices 204 are accessed by a unique serial bus address. Each serial bus device additionally supports one or more endpoints with which the computer system C may communicate to a serial bus device 204. For example a device might have one endpoint for data transmissions and another endpoint for status and configuration operations.

Four basic types of data transfers are defined in the serial bus system. The first type is isochronous transfers, which are characterized as periodic, continuous communication between host and device typically used for time-sensitive data/control, such as telephony information or audio information. The second type is bulk transfers, which is characterized by non-periodic, large bursty communication typically used for transfers that can be delayed until bus bandwidth is available, such as printer operations and conventional serial port operations. The third type is control transfers, which are characterized by bursty, non-periodic, host software initiated requests/response communications typically used for command/status operations. The fourth type of transfer, called interrupt transfers, are characterized as small bursty, non-periodic, low frequency, device-initiated communications typically used to notify the host of device service needs, such as is required for keyboard, mouse, pointing device and pen interfaces.

Information is broadcast over the serial bus from the host controller 130 in a series of packets, with the host controller 130 acting as the bus master and hubs and devices only responding upon request or polling access of the host controller. The packet types include data packets, token packets for use from host to device, a handshake packet and a special control packet. Data packets are the isochronous, asynchronous block, and asynchronous control types. Token packets allow transfer of data packets. Handshake packets are used to perform a ready handshake after transfer of a data or control packet to acknowledge successful receipt or indicate unsuccessful receipt. Special control packets are used for logical reset and status request transfers. Packets are scheduled into queues for transmission over the serial bus in a time division multiplexed fashion.

Each serial bus transaction begins when the host controller 130, on a scheduled basis, send a serial bus packet describing the type of transfer, the serial bus device address and the endpoint number. This packet is the token packet. The serial bus endpoint that is addressed selects itself by decoding the appropriate address fields. In a given transaction, data is transferred either from the host to a device or from a device to the host. The direction of data transfer is specified in the token packet. The source of the transfer then sends a data packet or indicates it has no data to transfer. The destination responds with a handshake packet indicating whether the transfer was successful.

Referring now to FIG. 3, there are two levels of arbitration for the host controller 130 to select among the endpoints. The first level of arbitration is by data type. The second level of arbitration is circular.

Each endpoint needing service is in a endpoint list 300 of a corresponding data type (i.e., isochronous endpoints are in an isochronous list). Thus, there is an isochronous list, a control list, a bulk list and an interrupt list. The host controller 130 attempts to process all the endpoints in each list every frame. At the beginning of each frame, the interrupt and isochronous lists are assigned the highest priority. The interrupt list is serviced before the isochronous list, but the order could be switched. When all endpoints on both periodic lists have been serviced once, the control and bulk endpoints get the remainder of the frame time with control having priority over bulk data transfers.

Within a list, endpoints are given equal priority and serviced in a round robin fashion, ensuring that all endpoints of a certain type have more or less equal service opportunities. Within the lists, priorities are modified as endpoints are serviced and at periodic intervals, specifically at the start of each frame.

From the perspective of the host controller 130, all four endpoint lists are identical in construction. Each list is comprised of a list of endpoint descriptors 302a and 302b (FIG. 3). Each endpoint descriptor 302a may link to another endpoint descriptor 302b to create one of the endpoint lists 300. An endpoint descriptor (ED) 302 (FIG. 4A) is a data structure which describes information necessary for the host controller 130 to communicate with a device endpoint, as described below. Referring to FIG. 4A, the endpoint descriptor 302 consists of a control field 400, a tail pointer field (TailP) 402, a next transfer descriptor field (NextTD) 404, and a next endpoint descriptor field (NextED) 406, as described in Table 1.

                  TABLE 1
    ______________________________________
    Endpoint Descriptor Fields
    Name     Description
    ______________________________________
    Function This is the USB address of the function containing the
             endpoint that this Endpoint Descriptor controls
    EP       This is the USB address of the endpoint within the
             function
    D        This two bit field indicates the direction of data flow
             (IN or OUT.) If neither IN nor OUT is specified, then
             the direction is determined from the PID field of the
             Transfer Descriptor. the encoding of the bits of this
             field are:
    ______________________________________
           Code            Direction
    ______________________________________
           00b             From TD
           01b             OUT
           10b             IN
           11b             From TD
    ______________________________________
    S        Indicates the speed of the endpoint: full-speed (S = 0)
             or low-speed (S = 1.)
    C        SW set this bit to cause the host controller to cancel
             the next TD on the TD list.
    F        This bit indicates the format of the Transfer
             Descriptors linked to this Endpoint Descriptor. If this
             is a control, bulk or interrupt endpoint then F = 0
             indicating that the general TD format is used. If this
             is an isochronous endpoint, then F = 1 indicating that
             the isochronous TD format is used.
    MaxP     This field indicates the maximum number of bytes that
             can be sent to or received from the endpoint in a single
             packet. This is also the `stride` of the buffer pointer
             for bulk, control and interrupt endpoints.
    TP       If the upper 28 bits of TP and NextTD are the same, then
             the list contains no TD that the host controller can
             process. If TP and NextTD are different, then he list
             contains a TD to be processed.
    NextTD   Points to the next TD to be processed for this endpoint.
             If the LSB of this entry is not 0, then the TD is not
             processes even if TP and NextTD are different.
    NextED   If non zero, then this entry points to the next ED on
             the list.
    ______________________________________

                  TABLE 2
    ______________________________________
    Transfer Descriptor Fields
    Name  R/W     Description
    ______________________________________
    PID   R       This two bit field indicates the PID to be used for
                  the token. This field is only relevant to the host
                  controller if the PID field in the Endpoint
                  Descriptor was set to 00b or 11b indicating that the
                  PID determination is deferred to the Transfer
                  Descriptor. The encoding of the bits within the
                  byte for this field are:
    ______________________________________
                      PXD      Data
            Code      Type     Direction
    ______________________________________
            00b       Setup    to
                               endpoint
            01b       OUT      to
                               endpoint
            10b       IN       from
            11b       Reserved
    ______________________________________
    INTD  R       This field contains the interrupt delay count for
                  this Transfer Descriptor. When a Transfer
                  Descriptor is complete and moved to the done list,
                  INTD is used to determine who long the interrupt
                  associated with the completion of this Transfer
                  Descriptor may be delayed. If INTD is not 111b,
                  then the hose controller may wait the indicated
                  number of frames before generating an interrupt to
                  the host processor (a value of 0 indicates that the
                  interrupt is to be generated at the end of the
                  current frame.) If INTD is 111b, then there is no
                  interrupt associated with completion of this
                  Transfer Descriptor.
    T     R/W     This bit is the data toggle bit. It is used to
                  generate/compare the data PID value (DATA0 or
                  DATA1). It is updated (inverted) after each
                  successful transmission/reception of a data packet.
    EC    R/W     For each transmission error, this value is
                  incremented. If EC is 2 and another error occurs,
                  the error type is recorded in the CC field and
                  placed the done list and when NextTD in the ED is
                  updated, the LSb will be set. When a transmission
                  completes without error, EC is reset to zero so that
                  a Transfer Descriptor will not be cancelled unless
                  there are three consecutive transmission errors.
    CC    R/W     This field contains the completion code when the
                  Transfer Descriptor is moved to the done list.
    CBP   R/W     Contains the physical address of the next memory
                  location that will be accessed for transfer to/from
                  the endpoint. A value of 0 indicates a zero length
                  packet or, if the TD is on the done list, that all
                  bytes of the TD have been transferred.
    NextTD
          R       If non zero, then this value points to the next TD
                  on the list of transfer descriptors linked to the
                  endpoint.
    BE    R       Contains physical address of the last byte in the
                  buffer for this TD.
    ______________________________________

                  TABLE 3
    ______________________________________
    Isochronous Transfer Descriptor Fields
    Name  R/W     Meaning
    ______________________________________
    PID   R       This two bit field indicates the PID to be used for
                  the token. This field is only relevant to the host
                  controller if the PID field in the Endpoint
                  Descriptor was set to 00 indicating that the PID
                  determination is deferred to the Transfer
                  Descriptor. The encoding of the bits within the
                  byte field for this field are:
    ______________________________________
                      PID      Data
            Code      Type     Direction
    ______________________________________
            00b       Setup    to
                               endpoint
            01b       OUT      to
                               endpoint
            10b       IN       from
            11b       Reserved
    ______________________________________
    N     R       Number of packets (frames) of data described by this
                  TD. N = 0 implies 1 packet and N = 7 implies 8.
    Frame R       This field contains the low order five bits of the
                  frame number in which the first packet of the
                  Transfer Descriptor is to be sent.
    INTD  R       This field contains the interrupt delay count for
                  this Transfer Descriptor. When a Transfer
                  Descriptor is complete and moved to the done list,
                  INTD is used to determine how long the interrupt
                  associated with the completion of this Transfer
                  Descriptor may be delayed. If INTD is not 111b,
                  then the host controller may wait the indicated
                  number of frames before generating an interrupt to
                  the host processor (a value of 0 indicates that the
                  interrupt is to be generated at the end of the
                  current frame.) If INTD is 111b, then there is no
                  interrupt associated with completion of this
                  Transfer Descriptor.
    CC    R/W     This field contains the completion code when the
    BPO   R       The 20 bits of this field contain the physical page
    NextTD
          R       If non zero, then this value points to the next TD
                  on the list of transfer descriptors linked to the
                  endpoint.
    BE    R       Contains physical address of the last byte in the
                  buffer for this TD.
    Offset
          R       Difference between two offset values is used to
    N             determine the size of the packet buffer used in a
                  particular frame. Bit 12 of an entry indicates
                  whether the address is in the physical memory page
                  indicated by BPO or BE.
    PSWN  W       Before the indicated packet is transferred by the
                  host controller, the OffsetN/PSN entry is an Offset.
                  After the packet is transferred by the host
                  controller, the entry becomes a Packet Status Word
                  (PSW) which is written by the host controller.
    ______________________________________

• Inventors
  Wooten, David R.;
• Assignee
  Compaq Computer Corporation (Houston, TX)
• Published
  Nov-3-1998
• Current US Classes:
  707/100
  707/101
  707/102
  709/234
  710/100
  710/22
  710/260
  710/5
  711/202
• Application #
  706594
• International Classes
  G06F 017/00
• Field of Search
  395/825 395/200.64 395/280 395/733 395/842 707/102 711/202 345/356
• Examiner
  Black; Thomas G.
• Agent
  Pravel, Hewitt, Kimball & Krieger
• US Patent References:
  4783730
  5165021
  5249265
  5276874
  5301287
  5396632
  5448702
  5513368