System for performing data compression based on a Liu-Zempel algorithm5701468Abstract Data compression using a Liv-Zempel algorithm is enhanced by organizing strings of data in a dictionary using a set of related four related fields. The first field contains an index or codeword for the last character of the string currently being processed. The second field contains an index or codeword for a SON string, a string which includes all of the characters of the current string plus one additional character. The third field contains an index or codeword for a BROTHER string which is identical to the current string except that the last characters in the two strings differ. The fourth field contains an index or codeword for a PARENT to the current string. The PARENT includes all of the characters of the current string except the last character. The memory arrangement comprises a tree structure which can be efficiently accessed by a disclosed processor to perform data compression using minimal processing resources. Claims We claim: Description TECHNICAL FIELD OF THE INVENTION
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Instruction (4 bits)
Destination operand (6 bits)
Source op.
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0001 (move) destination Source
0010 (compare)
the contents of SEL.sub.-- LE bus
Source
and RES selection
0011 (ADD) -- Source
0100 (AND) -- Source
0101 (OR) -- Source
0110 (ILOAD) data (MSB) data (LSB)
0111 (Indirect JUMP)
-- Source
1000 (SHIFTLEFT)
-- --
1001 (SHIFTRIGHT)
-- --
1010 (INC) -- --
1011 (DEC) -- --
1100 (SWAP) -- --
1101 MOVE EXTERNAL
type of move
1111 (Immediate JUMP)
Address (MSB) Address
(LSB)
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The MOVE instruction initiates movement of the contents of a register defined by the SOURCE operand into the register defined by the destination operand. To achieve this, state machine 600 activates both the read control signal defined by the source operand and the write control signal which is defined by the DESTINATION operand. For example, assuming that a move of the contents of register 705 to register REG4 register 724, the following instruction will be used: "0001/01100/000101" since 0001 represents the instruction MOVE; 01100 represents the binary coding of the value "24" (standing for register 724) and 000101 being the binary coding of the value "5" which characterizes the register 705. The COMPARE instruction provides the comparison of the contents of the register which is defined by the SOURCE operand with that of COMPREG register 718. The three LSB bits of the DESTINATION operand defines the contents of the SEL.sub.-- LE bus, that is to say the number of bits which will be used for performing this comparison. Therefore, when decoding the COMPARE instruction, state machine 600 generates those three bits on the SEL.sub.-- LE bus so that comparator 810 performs a comparison of the 8 to 12 least significant bits of COMPREG register 718 and the register which is defined by the SOURCE operand (for instance and as previously, REG3 register 714 has an address which is equal to "001110", the binary coding of the number 14). The result of the comparison is transmitted to processor 600 via its RES1, RES2 and RES3 leads. The final selection of the RES signal among the three RES1, RES2 and RES3 leads is made by state machine 600 in accordance with the contents of the 3 MSB bits contained in the DESTINATION operand. The ADD instruction performs the arithmetic addition of the contents of ADREG register 720 with that of the register which is defined by the SOURCE operand. To achieve this, upon the decoding of an ADD instruction, state machine 600 activates the ADD control signal which is transmitted to ADDER circuit 820, as well as the READ signal of the register defined by the SOURCE operand. The contents of that register is therefore transmitted to the internal bus 650 and therefore, ADDER circuit 820 computes the addition of the latter with the contents of ADREG register 720. The result is stored into REGR register 716. The AND instruction results in an AND operation of the contents of REGL register 727 and that of the register which is defined by the contents of the SOURCE operand. To achieve this, when decoding an AND instruction, state machine 600 activates the AND control signal which is transmitted to BOOL circuit 830, and the READ control signal of the register which address is defined by the SOURCE operand. Therefore, BOOL circuit 830 performs the bit to bit AND operation of the contents of that register with that of REGL register 727. The result is then transferred into REGR register 728. Similarly, the OR instruction results in an OR operation of the contents of REGL register 727 and that of the register which address is defined by the contents of the SOURCE operand. To achieve this, when decoding an OR instruction, state machine 600 activates the OR control signal which is transmitted to BOOL circuit 830, and the READ control signal of the register which has the address defined by the SOURCE operand. Therefore, BOOL circuit 830 performs the bit-to-bit OR operation of the contents of that register with that of REGL register 727. The result is then transferred into REGR register 728. The ILOAD instruction results in the loading of the REG1 register 712 with a data which is defined by the contents of the destination and source operand, the destination operand forming the 6 most significant bits while the source operand forms the 6 least significant bits. To achieve this, when state machine 600 decodes the ILOAD instruction, it activates the WR11 control signal and also transfers on the bus 650 the contents of the 12 least significant bits which are carried by bus 401 and which forms both the destination and source operands. The INDIRECT JUMP instruction results in the transfer into PC register 730 of the contents of the register whose address is defined by the SOURCE operand. To achieve this, when decoding an INDIRECT JUMP instruction, state machine 600 activates the READ control signal of the SOURCE register and the WR13 write control signal which is transmitted to PC register 713. The SHIFT LEFT (SHL) instruction is used for performing the shift function to the left of the contents of the SREG register 730. To achieve this, upon decoding a SHIFT LEFT instruction, state machine 600 activates the SHL control signal which is transmitted to SREG register 730. Conversely, the SHIFT RIGHT (SHR) instruction is used for performing the shift function to the right of the contents of the SREG register 730. To achieve this, upon decoding a SHIFT LEFT instruction, state machine 600 activates the SHR control signal which is transmitted to SREG register 730. The INC instruction is used for performing the incrementation of the CNTR register 729, by the activation of the INC control lead which is connected to CNTR register 729. Similarly, the DEC instruction is used for performing the decrementation of the CNTR register 729, by the activation of the DEC control lead which is connected to the latter register. Therefore, CNTR register 729 is capable of either incrementing or decrementing its contents in accordance with the control signal carried by INC or DEC control lead generated by state machine 600. The SWAP instruction is used of controlling the mutual exchange of the contents of program counter 713 and SWAP register 715. When state machine 600 decodes the existence of the SWAP instruction on the instruction bus 401, it generates the SWAP control signal which is transmitted to both program counter 713 and SWAP register 715. The MOVE EXTERNAL instruction provides a set of 8 individual moves of data between the processor 500 and one among the external devices 100, 200 and 300 in accordance with the contents (referred to a the TYPE of the move) of the DESTINATION operand. A first type of move (READ.sub.-- DATA) allows the transfer of data provided by FLOW.sub.-- CONTROL.sub.-- 1.sub.-- IN circuit 100 into DATA.sub.-- IN register 719. To achieve this, when decoding a MOVE EXTERNAL instruction of this type, state machine 600 activates READ.sub.-- DATA lead 502 which is transmitted to both circuit 100 and the READ.sub.-- DATA input lead of register 719. A second type of move (WRITE.sub.-- DATA) allows the transfer of data provided by DATA.sub.-- IN register 719 to FLOW.sub.-- CONTROL.sub.-- 1.sub.-- IN circuit 100. To achieve this, when decoding a MOVE EXTERNAL instruction of this second type, state machine 600 activates WRITE.sub.-- DATA lead 501 which is transmitted to both circuit 100 and to the WRITE.sub.-- DATA lead of register 719. A third type of move (READ.sub.-- CODEWORD) allows the transfer of data provided by FLOW.sub.-- CONTROL.sub.-- 2.sub.-- OUT circuit 200 into DATA.sub.-- OUT register 726. To achieve this, when decoding a MOVE EXTERNAL instruction of this third type, state machine 600 activates READ.sub.-- CODEWORD lead 506 which is transmitted to both circuit 200 and to the READ.sub.-- CODEWORD input lead of register 726. A fourth type of move (WRITE.sub.-- CODEWORD) allows the transfer of data provided by DATA.sub.-- OUT register 726 to FLOW.sub.-- CONTROL.sub.-- 2.sub.-- OUT circuit 200. To achieve this, when decoding a MOVE EXTERNAL instruction of this fourth type, state machine 600 activates WRITE.sub.-- CODEWORD lead 507 which is transmitted to both circuit 200 and to the WRITE.sub.-- CODEWORD input lead of register 726. A fifth type of move (READ.sub.-- MEM.sub.-- to.sub.-- A) allows the transfer of data from memory 300 from an address defined by the contents of ADDA register 710 to the set of registers 705, 706, 707 and 708. To achieve this, when decoding a MOVE EXTERNAL instruction of this fifth type, state machine 600 activates RDMEMA lead which is connected to an input of OR gate 850 and is also used to access the respective contents of DATAA register 705, S12A register 706, B12A register 707 and P12A register 708. Therefore, the output of OR gate 850 activates READ input lead 511 of memory 300. A sixth type of move (READ.sub.-- MEM.sub.-- to.sub.-- B) allows the transfer of data from memory 300 which address is defined by the contents of ADDB register 709 to the set of registers 701, 702, 703 and 704. To achieve this, when decoding a MOVE EXTERNAL instruction of this sixth type, state machine 600 activates RDMEMB lead which is connected to an input of OR gate 850 and is also used to access the respective contents of DATAB register 701, S12B register 702, B12B register 703 and P12B register 704. Therefore, the output of OR gate 850 activates READ input lead 511 of memory 300. A seventh type of move (WRITE.sub.-- MEM.sub.-- to.sub.-- A) allows the transfer of data to memory 300 at the address being defined by the contents of ADDA register 710 from the set of registers 705, 706, 707 and 708. To achieve this, when decoding a MOVE EXTERNAL instruction of this seventh type, state machine 600 activates WRMEMA lead which is connected to an input of OR gate 840 and is also used to access the respective contents of DATAA register 705, S12A register 706, B12A register 707 and P12A register 708. Therefore, the output of OR gate 840 activates WRITE input lead 510 of memory 300. A eighth type of move (WRITE.sub.-- MEM.sub.-- to.sub.-- B) allows the transfer of data to memory 300 at the address being defined by the contents of ADDB register 709 to the set of registers 701, 702, 703 and 704. To achieve this, when decoding a MOVE EXTERNAL instruction of this eighth type, state machine 600 activates WRMEMB lead which is connected to an input of OR gate 840 and is also used to access the respective contents of DATAB register 701, S12B register 702, B12B register 703 and P12B register 704. Therefore, the output of OR gate 840 activates WRITE input lead 510 of memory 300. The Immediate Jump instruction results in the transfer into PC register 730 of an address which is defined by the contents of the destination and source operands. The destination operand forms the 6 most significant bit of that address while the source operand forms the 6 least significant bits of that address. To achieve this, when decoding an Immediate Jump instruction, state machine 600 activates the WR13 control lead which is connected to PC register 713. Also, state machine 600 transfers the contents of the 12 least significant bits of the bus 401 onto internal bus 650 so as to load the contents within register 713. It should be noticed that the set of instructions which are defined below is not exhaustive and that additional instructions can be introduced in the processor of the invention. Generally speaking, the sequencing is based on the the operation of PCREG register 713. The two states and the raising and falling edge of the master clock signal which is provided throughout the machine on lead 100 are used as follows. In the preferred embodiment of the invention, on the rising edge of the master clock signal, state machine 600 fetches the instruction on bus 401, the address of which is stored within PCREG register 713. This is achieved by activating the OE control signal on lead 403 which is transmitted to storage 400. The instruction is therefore transferred from that memory onto bus 401. On the positive state following the rising edge, state machine 600 performs a decode of the instruction and generates all the logical states which are necessary to control the circuits which are involved in the instruction being decoded. Once the states are fixed, on the falling edge of the master clock signal, state machine produces the necessary pulses which are needed for completing the execution of the instruction, It should be noticed that such a sequencing is well known in the art of RISC (Reduced Instruction Set Computer . . . ) processors. Such processor usually performs the reading, the decoding and the execution of one instruction within one clock period. When the execution of an instruction completes on the negative state of the master clock on lead 001, the PCREG register 713 is either swapped (involving the SWAP register 715), either reset, or incremented by one or two in accordance with the execution of the instruction. The reset of PCREG register 713 is performed when an master reset control signal is received on lead 002. The swapping of PCREG register 713 with register 715 is performed either on the decoding and execution of a SWAP instruction mentioned below, or, at the completion of one instruction, when an interrupt control signal is generated at the INT output lead of MASK register 717. At the end of the execution of each instruction (except for the SWAP instruction), the incrementation of the PCREG register 713 is controlled in accordance with the state of the one of the three RES1, RES2 and RES3 signals which is considered in the particular COMPARE instruction being processed. If the one among the RES1, RES2 or RES3 signal being considered carries a `0` level, state machine 600 activates INC1 control signal which increments PCREG register 713 by one. Conversely, if the signal carries a `1`, state machine 600 activates INC2 control signal which increments PCREG register 713 by two. Also, state machine 600 activates INC1 control signal in order to increment by one PCREG register 713 by default, that is to say when an instruction other than COMPARE is being processed, The structure which was described above is particularly designed for providing the encoding and decoding mechanisms in accordance with the V42bis data compression procedures. Briefly, the encoding mechanism is based on the use of a codeword having a certain length. Each character which is received from the DTE through the interchange circuit forms part of a string of characters which is then represented by a characterizing codeword. This process employs and maintains a dictionary in which strings are stored with their corresponding codeword. The dictionary is dynamically updated in the course of the encoding mechanism. The codewords which are received from the signal converter through the error control functions are then decoded by the decoding mechanism in order to regenerate the original string of characters. To achieve this, a second dictionary is involved for the decoding mechanism is also continuously updated. To perform the data compression and decompression process, a particular tree structure is used in the preferred embodiment of the invention which will be explained in reference with an illustrative example. Let us assume, for instance, that the dictionary comprises the following strings of characters at a given time. The table below illustrates the status of the dictionary.
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Dictionary Entry associated codeword
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BU
BUT
BR
BRI
BRIN
BRIQ
BRIQU
BRIQUE
BRID
BRIDE
BRA
BRAV
BRAVO
BRE
BREVE
BREVET
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This tree structure is illustrated in FIG. 5 of the present application. In the preferred embodiment of the invention, a very specific arrangement of the memory 300 which stores the dictionary has been designed. The organization of the memory, illustrated with reference to table 2, complies with what follows. The first physical locations of the memory are generally used for storing control codewords. The next locations are then allocated to the storage of the ASCII characters. The next locations are then reserved for the storage of the dictionary. Each physical location of the memory is used for characterizing a string which is created within the dictionary (the first locations which are not used for controls codewords or assigned to the storage of the ASCII characters). The physical address of this string defines the codeword which is associated to this string. In accordance with the present invention, the 44 bits data of memory 300 are organized in a set of four distinctive fields. The first field corresponds to the codeword of the last character of the field. Thus, with reference to table 2, the string "BRI" is characterized by a codeword `267`. Therefore, when processor 500 reads memory 300 at the physical address `267`, the memory provides a 44 bit data unit, the 8 most significant bits providing the value `76` which represents the codeword of the character "I". Similarly, the addressing of memory 300 at address `273` (being the codeword of string "BRAVO") returns a 44 bits data which eight MSB are the codeword (`82`) of character "O". The second field of the 44 bit data unit of memory 300 defines the codeword of the string (SON) that comprises the string being considered (defined by the address of the 44 bits data) plus an additional character and which, also, is the first string that chronologically follows the creation of the considered string. With respect to our example again, the string being considered is "BRI". Table 2 reveals that the first string being created within the dictionary that incorporates the string "BRI" plus one additional character is the string "BRIQ". Consequently the codeword of the latter, that is codeword `268` is used for the second field. With respect to the string "BRID", it appears that the first string that appeared after its creation and which incorporates one more character is the string "BRIDE". The codeword of the latter, that is codeword `276` is therefore used for defining the second field. The third field of the 44 bits data of memory 300 defines the codeword of the string (BROTHER) which appears within the dictionary after the creation of the string being considered and which shares the same characters except the last one. Let us consider the string "BRI" again. From table 2, it appears that strings "BRA" and "BRE" do share the same characters than string "BRI" except the last. They both appear as Brothers. However, table 2 reveals that they both appeared before the creation of string "BRI". Consequently, the third field of the 44 bits data characterizing string "BRI" is set to `000`. Considering the additional example "BRIQ". Table 2 shows that the string "BRID" appears as a Brother since it has the same first characters except the one. The latter appears in the dictionary after the creation of the former. As a consequence, the third field of the 44 bits data characterizing the string "BRIQ" is set to the value `269` being equal to the codeword of string `BRID`. The fourth field is used for storing the codeword of the string that is defined by all the characters except the last of the string being considered (PARENT). If the latter comprises n characters, the PARENT string is the string being defined by the n-1 first characters. In our example again, string "BRI" has a parent which is the string "BR". Consequently, the codeword of the latter, that is `259` is used for defining the fourth field of the 44 bits data stored within memory 300. It appears from the above definitions that the second and third fields are closely related to the chronology. The date of creation of the string is therefore considered for defining the second and third field. This time relationship in the generation of the dictionary is illustrated by use of the terms SON, BROTHER and PARENT which will be used for characterizing the strings which are respectively defined by the second, the third and the fourth field. It appears that this relationship is advantageously taken into account in the structure of the processor of the invention, and particularly in the organization and arrangement of the set of registers 705, 706, 707, 708 and registers 701-704. It should be noticed that the SON, BROTHER and PARENTS fields are initialized to "0" at the beginning of the compression process (corresponding to the fact that no BROTHER nor son nor PARENT are existing for a considered string located within the dictionary. The particular arrangement of the memory which was described below shows that some physical locations will always remain available and unused by the dictionary. The invention utilizes this spare memory space in order to store some control data which will be used for processing the instructions by the processor 500. Due to the V. 42 bis algorithm, the (N 5-1) first dictionary entries, N5 referred to in the CCITT Recommendations as a an index number of a first dictionary entry used to store a string, will never use the PARENT and BROTHER field. This results in some available locations within the memory which can be advantageously used for storing temporary data involved in the compression processing. As will appear below, the processor 500 according to the present invention is useful for providing a compression system which complies with the CCITT V42bis recommendations and particularly for embodying the encoding mechanism which is defined in the recommendations and illustrated in the associated figures. In order to demonstrate the particular advantages provided by the processor of the invention, it will be now described the embodiment of a particular procedure which is defined in the CCITT V42bis recommendation. This procedure is referred to as the `process character procedure` which is defined in FIGS. 1-3/V.42bis of the CCITT Recommendations and is reproduced in FIG. 3 of the present application. For the purpose of this description, the following assumptions are made: Let us suppose that a character is received from FLOW.sub.-- CONTROL1.sub.-- IN circuit 100. It is signified to the processor 500 by the activation of CNTL.sub.-- 1.sub.-- IN bus 102. Consequently, an interrupt is generated by register 717 to state machine 600. Let us assume also that, for clarity's sake, processor 500 was executing at this time one waiting-loop, thereby waiting for an interrupt. Upon reception of the interrupt signal, state machine 600 exchanges the contents of SWAP register 715 and that of PCREG register 713. Therefore, the program branches to the address which is stored within the PCREG register 713. In our example, this results in the execution of a PROCESS CHARACTER PROCEDURE routine which will be now described with details and with reference to FIG. 4. It will be also assumed that: The parameters N1-N7, C1-C3 and P0-P2 which are defined in Chapter 10 of the CCITT Recommendations are stored in the PARENT fields of locations at addresses 0-12 of the memory 300 which, in the preferred embodiment of the invention, are available locations not used by the compression mechanism: N1 is stored in the PARENT field of location at address `0` N2 is stored in the PARENT field of location at address `1` N3 is stored in the PARENT field of location at address `2` N7 is stored in the PARENT field of location at address `6` C1 is stored in the PARENT field of location at address `7` C2 is stored in the PARENT field of location at address `8` C3 is stored in the PARENT field of location at address `9` P0 is stored in the PARENT field of location at address `10` P1 is stored in the PARENT field of location at address `11` P2 is stored in the PARENT field of location at address `12` The flag representative of a transparent/compression mode is stored in the BROTHER field of memory location which address is `0`. A ZERO value stands for a transparent mode while a ONE value represents a compression mode. In the preferred embodiment of the invention, the codeword corresponding to a STRING as referred to in the Recommendations is stored in REG4 register 724. The codeword corresponding to the last entry within the dictionary is stored within REG5 register 725. The execution of the processing is performed by the program instructions stored in memory 400 of FIG. 1. The implementation of the Character Process procedure will now be described with reference to FIG. 4. The initiation of the procedure starts with step 1. Then, step 2, processor 500 reads memory 400 at the address which is defined by the contents REG4 register 724 (used to store the codeword of the string). The contents of the memory is then stored in the bloc 705-708 of registers. 705-708. Then, step 3, a test is performed in order to determine whether the string has a SON or not. This is achieved by testing the second field (ie the SON field) currently stored in S12A register 706 is equal to `1`. In this case, the process proceeds to step 4 where a comparison is performed between the SON field being considered and the received character. If the SON field appears to be different from the received character, the process proceeds to step 5 where another test is performed in order to determine whether the string has a BROTHER or not. This is achieved by the checking of the contents of B12A register by means of the COMPARE instruction and the COMPREG register 718. If the string appears to have a BROTHER, then state machine 600 checks whether this BROTHER is the receive character, step 6. In the reverse case, the process proceeds to step 7 where the existence of another brother (of the received string) is checked. In the preferred embodiment of the invention, this is achieved by Iooping back to step 5 again. If the tests of step 4 or that of test 6 lead to a positive result, meaning that the string associated with the received character forms a string which is already stored within the dictionary, the process proceeds to step 8. In this step, a test is performed in order to determine whether the latter string (formed by the combination of the former string with the received character) is the last string created within the dictionary. If the answer is yes, then the processor 500 goes to step 9 where an additional test is performed for determining whether the mode is either transparent or compressed. This is achieved by reading the memory at the address `0` and test the value of the BROTHER field of that location. This test is also performed when the tests performed in steps 3 and 5 lead to a negative result. If the result of the test of step 9 appears to be positive, then a CHECK CODEWORD SIZE routine is initiated, step 10. This procedure is referred to in the CCITT recommendations, illustrated in diagram c of the Appendix I and will not be discussed more for clarity's sake. It should be noticed that a call to this procedure is easily achieved with the invention by means of the SWAP instruction associated with the SWAP register. This provides a very fast way of executing a call operation since the contents of both SWAP and PCREG registers 713 and 715 can be instantaneously exchanged. At the completion of the CHECK CODEWORD SIZE routine, the process proceeds to step 11 where the codeword is transmitted to the FLOW.sub.-- CONTROL.sub.-- 2.sub.-- OUT circuit 200 by means of DATA.sub.-- OUT register 726. Then, an ADD.sub.-- STRING+CHARACTER.sub.-- TO.sub.-- DICTIONARY procedure is initiated in step 12 which allows the addition of the string and the character being received into the dictionary, as discussed in the CCITT V42bis recommendations. This latter procedure is particularly illustrated in diagram I of the Appendix I of the Recommendations. Step 12 is also reached when the test performed in step 9 revealed the existence of a transparent mode. After the completion of step 12, a test is performed, similar to that of step 9, in order to determine the actual mode, step 13. When in transparent mode, a step 14 results in the sending of the received character to the FLOW.sub.-- CONTROL.sub.-- 2.sub.-- OUT circuit 200. After step 15, and also when the test of step 13 revealed that the mode was not transparent, an ESCAPE CHARACTER procedure which is illustrated in diagram g of the CCITT V42bis recommendations and discussed in the latter. When the test performed in step 8 revealed that the string and the received character is not the last string being created within the dictionary, the process proceeds to step 16 where the received character is added in the string variable in order to update the latter. Below is listed an illustrative set of instructions for the implementation of the above described flow chart (see Table 1). Table 2 also illustrates the storage of the example of dictionary into the memory.
TABLE 1
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LABEL INSTRUCTION COMMENTS
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PROCESS CHARACTER:
MOVE ADDA,REG4 ;Load in ADDA string codeword
MOVE EXTERNAL READ.sub.-- MEM.sub.-- TO A ;Read dictionnary
entry
MOVE EXTERNAL READ.sub.-- DATA ;Read character received
ILOAD COMPREG,0 ; Load compreg with value 0
COMPARE EQUAL S12A ; Compare S12A to 0
IJUMP POSSIBLE.sub.-- SON
IJUMP STRING+CHAR.sub.-- NOT.sub.-- FOUND
POSSIBLE.sub.-- SON:
MOVE ADDA,S12A
MOVE EXTERNAL READ.sub.-- MEM.sub.-- TO.sub.-- A ;Read Son
COMPARE EQUAL DATAIN ; Compare son to character
IJUMP BROTHER?
IJUMP STRING+CHAR.sub.-- FOUND
BROTHER: ILOAD COMPREG,0
COMPARE EQUAL,B12A ;Search for Brother
IJUMP A.sub.-- BROTHER.sub.-- FOUND
IJUMP STRING+CHAR.sub.-- NOT.sub.-- FOUND
A.sub.-- BROTHER.sub.-- FOUND:
MOVE ADDA,B12A
MOVE EXTERNAL,READ.sub.-- MEM.sub.-- TO.sub.-- A
MOVE COMPREG,DATA A
COMPARE EQUAL,DATAIN ;Compare brother to character
IJUMP BROTHER?
IJUMP STRING+CHAR.sub.-- FOUND
STRING+CHAR.sub.-- FOUND:
MOVE COMPREG,REG5
COMPARE EQUAL,ADDA
IJUMP SAME.sub.-- AS.sub.-- LAST.sub.-- ENTRY
MOV REG5,ADDA
IJUMP MODE?
SAME.sub.-- AS.sub.-- LAST.sub.-- ENTRY:
ILOAD ADDB,0
MOVE EXTERNAL READ.sub.-- MEM.sub.-- TO.sub.-- B
ILOAD COMPREG,0
COMPARE EQUAL,B12B
IJUMP ADD.sub.-- STRING+CHAR.sub.-- TO.sub.-- DICTIO
ILOAD SWAP,ADD1 ; ADD1 is address of task check
; check.sub.-- codeword.sub.-- size minus 1
;The program will execute the programme check.sub.-- codeword.sub.--
size
;which will end with a swap instruction which will return to
;the following of the current program.
MOVE DATA.sub.-- OUT,REG4
MOVE EXTERNAL.sub.-- WRITE.sub.-- CODEWORD ; Send codeword
ADD.sub.-- STRING+CHAR.sub.-- TO.sub.-- DICTIO: ILOAD SWAP,ADD2 ; ADD2 is
address of task
; add.sub.-- string.sub.-- +.sub.-- character.sub.--
.
; to.sub.-- dictionnary minus 1
;The programm will execute the corresponding programm
;which will end with a swap instruction which will return to
;the following of the current programm.
MOVE' ADREG,DATAIN
ILOAD REG6,3
ADD REG6
MOVE REG4,REGR ; String=unmatched character
MODE?: ILOAD ADDB,0
MOVE EXTERNAL,READ.sub.-- MEM.sub.-- TO.sub.-- B
ILOAD COMPREG,0
MOVE DATA.sub.-- IN,DATA.sub.-- OUT
COMPARE EQUAL,B12B
MOVE EXTERNAL.sub.-- WRITE.sub.-- CODEWORD
ILOAD SWAP,ADD3 ; ADD3 is address of task
; Escape.sub.-- character.sub.-- procedure minus
1
;The programm will execute the corresponding programm
;which will end with a swap instruction which will return to
;the end of this programm
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