Digital scale

Abstract

The invention relates to a scale system which employs a microcomputer forming an integral part of the analog to digital conversion means in which the microcomputer controls the sequence of operations for performing the conversion, accumulates and stores digital data derived during the conversion of the analog signal and combines and processes that data to provide the digital output data resulting from the conversion, all in addition to performing other scale functions. The invention relates to an improved multicapacity weighing and computing digital scale having a triple slope analog-to-digital conversion means. The analog weight signal is integrated for a time interval which is fixed for a given scale capacity range which would generate substantially the same integrator output level in response to a full capacity weight signal for the selected scale capacity as would be generated by a full capacity weight for all other scale capacities. In accordance with the invention, the time interval during which the first reference DC source is integrated is extended beyond the detection of the crossover of the integrator output with its reference level. The invention also provides an improved weight filtering arrangement which enables the full advantage of the improved converter to be obtained. The invention further provides for the tracking of the net zero indication by modification of the stored tare weight data by a predetermined amount to decrease the absolute value of the net weight in response to the net weight being within a preselected weight range.

Claims

What is claimed is:

1. In a digital scale an analog to digital converter means comprising in combination an integrator means having an input and an output, means for applying an analog input signal to the integrator input to drive the integrator output from a datum level to a level dependent upon the magnitude of the analog input signal, switch means for applying a reference signal to the integrator input, program controlled means interconnected with the integrator output and with the switch means, the program controlled means having a counting and timing program loop of instructions of fixed duration for counting the excursions around the loop during the time required for the reference signal to drive the integrator output back to a predetermined level near the datum level.

2. In a digital scale an analog to digital converter means in accordance with claim 1 wherein the program controlled means includes program means to continue the operation of the integrator means in response to the reference signal for an additional time interval after the integrator output is driven across the datum level.

3. In a digital scale an analog to digital converter means in accordance with claim 1 where in the means for applying an analog input signal to the integrator input includes counting means for counting predetermined intervals of time and the program controlled means includes program loops to control the counting means to control the time the analog input signal is applied to the input of the integrator.

4. In a digital scale an analog to digital converter means in accordance with claim 3 wherein the program controlled means includes storage means to store data for different scale capacities to condition the counting means to count different amounts for different scale capacities whereby the input analog signal is applied to the input of the integrator for different times for different scale capacities.

5. In a digital scale an analog to digital converter means comprising in combination an integrator having an input and an output, switch means for applying an analog input signal to the integrator input to drive the integrator output from a datum level to a level dependent upon the magnitude of the analog input signal, program controlled means interconnected with the integrator output and with the switch means, the program controlled means having a counting and timing program loop of instructions to control the time of operation of the switch means.

6. In a digital scale an analog to digital converter means in accordance with claim 5 wherein the program controlled means includes counting means controlled by the counting and timing program loop, storage means to store data for different scale capacities, and means controlled by the stored data for different scale capacities to set the counting means to count to different numbers for the different scale capacities.

7. In a digital scale an analog to digital converter means in accordance with claim 5 wherein the program controlled means includes counting means controlled by the counting program loop to count excursions around the loop, storage means to store data for different scale capacities, and means to condition the counting means to cause the integrator output to reach substantially the same level at full load for the different scale capacities.

8. In a digital scale a triple slope analog to digital converter means comprising in combination integrating means having an input and an output, means for applying an analog signal representing a weight on the scale to the input of the integrating means to drive the output of the integrating means from a datum level to a level controlled by the magnitude of the input analog signal, first switch means to apply a first reference signal to the input of the integrating means to drive the output of the integrating means toward the datum level at a first predetermined rate, second switch means to apply a second reference signal to the input of the integrating means to drive the output of the integrating means toward the datum level at a second predetermined rate, program controlled means interconnected with the first and second switch means and the output of the integrating means, the program controlled means including counting means for counting predetermined time intervals during the application of the first reference signal to the input of the integrating means during which interals the output of the integrating means changes by an amount representing a plurality of weight increments, the program controlled means also including counting means to count the predetermined time intervals during the application of the second reference signal to the input of the integrating means during which intervals the output of the integrator changes by an amount representing a different number of weight increments and arithmetic means for combining the counted number of intervals to obtain a digital representation of total weight increments.

9. In a digital scale, a triple slope analog to digital converter means comprising in combination, integrating means having an input and an output, first switch means for applying an analog signal to the input of the integrating means, second switch means for applying a first reference signal to the input of the integrating means, third switch means for applying a second reference signal to the input of the integrating means, program controlled means interconnected with the integrating output and with the first, second, and third switch means, the program controlled means including timing means to control the time of application of the input signals to the input of the integrating means for deriving a digital representation of the magnitude of the input analog signal.

10. In a digital scale in accordance with claim 9 wherein the program controlled means includes storage means for storing data for different scale capacities, means responsive to the stored data for the respective scale capacities to control the time of application of the input analog signal to the input of the integration means to produce substantially the same digital representation of a full load for each of the respective scale capacities, and arithmetic means to convert the digital representation of the magnitude of the input signal to respective weight indications for the respective scale capacities.

11. In a digital scale a triple slope analog to digital converter means in accordance with claim 9 wherein the output of the integrating means is driven from a datum level to a level representing the weight on the scale in response to the application of the analog input signal and is driven back to the datum level in response to the application of the first reference signal, and wherein the first reference signal is applied to the input of the integrating means for a further predetermined interval of time.

12. In a digital scale a triple slope analog to digital converter in accordance with claim 11 wherein the output of the integrating means is driven back to the datum level in response to the application of the second reference signal to the input of the integrating means.

13. In a digital scale a triple slope analog to digital converter means in accordance with claim 11 wherein the program controlled means includes means for preventing change in the output of the integrating means during the further interval of time from affecting the output digital representation of the weight on the scale.

14. In a digital scale in accordance with claim 9 comprising in combination means for correcting each digital representation of the magnitude of the analog input including means for comparing each digital representation with a previously corrected digital representation, means responsive to the difference being within a predetermined range to augument a fraction of the difference toward the last representation and means for combining the result with the last digital representation to obtain the corrected digital representation.

15. An analog to digital converter comprising, in combination, integrator means having an input and an output, first switch means for applying an analog signal to the input of the integrator means to drive the output of the integrator means from a datum level to a level representing the amplitude of the analog signal, second switch means for applying a reference signal to the integrator means to drive the output of the integrator means back to a level near the datum level, a computer interconnected with the output of the integrator means and with the first and second switch means, a program delay loop for controlling the computer, and counting means for counting excursions around the program delay loop to control one of the switch means.

16. An analog to digital converter comprising, in combination, integrating means having an input and an output, means for applying an analog signal to the input of the integrating means to drive the output of the integrating means from a datum level to a level representing the amplitude of the analog signal, first switch means for applying a first reference signal to the input of the integrating means to drive the output of the integrating means toward the datum level at a first predetermined rate, second switch means for applying a second reference signal to the input of the integrating means to drive the output of the integrating means toward the datum level at a second predetermined rate, program controlled means interconnected with the output of the integrating means and interconnected with the first switch means and with the second switch means for actuating the first switch means until the output of the integrator is driven back to a level near the datum level and for thereafter actuating the second switch means to drive the output of the integrator back to substantially the datum level, the program controlled means including a program loop for controlling the program controlled means for a predetermined interval of time, counting means for counting excursions around the program loop during the actuation of the first switch means and during the actuation of the second switch means, and combining means for deriving a digital representation of the amplitude of the input analog signal from the numbers of excursions around the program loop.

17. An analog to digital converter in accordance with claim 16 comprising, in combination, means for maintaining the first switch means actuated for an additional time interval after the output of the integrator crosses the datum level.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention concerns weight measuring apparatus. More particularly, the invention is concerned with a weighing scale system having an improved analog-to-digital conversion means including a microcomputer which forms an integral part thereof and to the automatic tracking of the net zero indication of such an apparatus.

2. Description of the Prior Art

Weighing and computing scales must meet several stringent requirements for performance and cost. The scales must be accurate enough to satisfy public weights and measures authorities, yet be available at a reasonably affordable price and perform their operations within a period of time which is convenient for sales transactions.

One of the important factors in digital scales upon which cost, accuracy and operation time depends, is the conversion of the unknown analog weight signal corresponding to an article weight to digital data representative of the article weight.

In the past, digital weighing and computing scales have typically performed the analog-to-digital conversion with a separate distinct and independently controlled analog-to-digital converter circuit which may provide its digital output to a data processing means. Typical examples are Williams, Jr. et al, U.S. Pat. No. 3,709,309 and Loshbough et al., U.S. Pat. No. 3,962,569. This prior art circuitry conventionally uses the dual slope method of analog-to-digital conversion, which method is illustrated in Gilbert, U.S. Pat. No. 3,051,939 and Ammann, U.S. Pat. No. 3,316,547. Triple slope analog-to-digital converters are shown in U.S. Pat. Nos. 3,577,140 Aasnacs; 3,582,947 Harrison; 3,678,506 Wheable; and Re 28706 Dorey. Reference is also made to U.S. Pat. No. 3,937,287 granted to E. G. Pryor and R. C. Loshbough on Feb. 10, 1976 relating to data filtering. The exemplary embodiment of the invention described herein describes features shown in U.S. Pat. Nos. 3,962,569 Loshbough et al; 3,962,570 Loshbough et al; 3,986,012, Loshbough et al; 4,004,139, Hall et al; and application Ser. No. 729,911, Hall et al now U.S. Pat. No. 4,159,521.

Prior art weight measuring apparatus has generally required circuitry separate from the data processing means for performing the integrating, counting, and control functions normally associated with an integrating type analog-to-digital conversion. Attendant with the requirement for separate circuitry is its cost and the relative inflexibility due to the limited number of functions performed by hardwired circuitry.

SUMMARY OF THE INVENTION

There is, therefore, a need for a weighting scale having a relatively simple design which is capable of more effectively utilizing the data processing means to reduce the number of components required to implement the analog-to-digital conversion and thereby reduce the cost of the weighing scale and allow the analog-to-digital conversion to avail itself of the flexibility afforded by the data processing means.

The present invention achieves the foregoing needs by providing a weighing scale system which employs a microcomputer data processing means which is integral to an analog-to-digital conversion and which is used for controlling the sequence of operations and computing the required data for the scale system. The requirement for separate control and counting circuitry associated solely with the analog-to-digital conversion is thereby eliminated, with the additional advantage of allowing the analog-to-digital conversion to be modified via a modification of the instructions of the microcomputer.

In a conventional triple slope analog-to-digital conversion, an analog signal is applied through a switching circuit to an integrator circuit for a first fixed time interval in order to drive its output from an initial level to a level which is proportional to the amplitude of the analog signal. Then a second integrating interval is begun in which a clock-driven digital timing counter begins counting time intervals and simultaneously a first reference DC source is applied through the switching circuit to the integrator to drive its output past a reference level. This level is detected by a threshold detector circuit. In accordance with the present invention, the second time interval is extended an additional time interval beyond the crossover of the reference level. Then during the third integrating interval, the elapse of time is counted. The slower rate permits the crossover to be more precisely detected. Upon detection of such crossover by the threshold detector, the counting of the elapsed time is halted.

In the prior art a separate single digital counter is used to count the clock pulses to accumulate a count of elapsed time for both the second and third integrating intervals. Its most significant digits are used to accumulate the elapsed time count during the second interval and its least significant digits are used to accumulate the elapsed time count during the third interval.

A unique feature of the present invention is that the control of the switching circuit is performed by a microcomputer and the output of the threshold detector is applied directly to the microcomputer so that all counting and arithmetic operations are performed by the microcomputer.

The analog to digital conversion system also affects other characteristics of a weighing and computing scale. For example, an improved digital input weight filtering arrangement is provided which permits the improved accuracy to be obtained by reducing the filter delay and at the same time reducing the effects of vibration or jitter.

In order for a weighing scale to be able to provide a choice of full scale capacities, it is necessary that the weight signal or data be modified in either its analog form or its digital form in a manner which is dependent upon the particular scale capacity and units of weight which are selected.

The weight can be detected according to a single one of several possible scale capacities and weight units and then multiplied by an appropriate conversion factor when another scale capacity is selected. This, however, requires that a computer of such a weighing scale have a more complex sequence of operations because for each selected scale capacity it must deal with substantially different numbers in performing all of its various checks and control functions.

Alternatively, the analog weight signal may be amplified by an amplification factor which is unique for each scale capacity. This selective modification of the analog gain has the disadvantage that it requires the use of either adjustable or multiple circuit elements, such as resistors, in the analog circuitry, one of which must be manually switched into the circuit for each selected amplification factor corresponding to each selected scale capacity. The use of such alternatively selectable circuit elements requires a substantial additional expense and creates problems in calibration.

These problems can be reduced by causing the full capacity analog weight signal for each scale capacity to produce the same digital number at the output of the analog-to-digital converter. This also permits a single span control to set the full capacity output for all selectable scale capacities. For example, in the exemplary embodiment of the present invention, a full scale weight for each scale capacity will produce a digital output of 30,000 net effective weight increments which are termed raw weight increments. The number of raw weight increments is then multiplied by a factor, depending upon the scale capacity to obtain the proper weight units.

It is a unique feature of the present invention that it provides substantially the same digital data with a full capacity weight for all selected scale capacities without requiring multiple circuit elements and without requiring modification of the analog circuit gain. This unique aspect of the present invention is provided by the microcomputer implementation of the analog-to-digital conversion.

Another unique feature of the present invention relates to the computing and displaying of a net weight. The prior art includes weighing and computing scales upon which a food container or other tare weight may be placed, weighed and have the tare weight entered into memory. This stored tare weight is available for later subtraction from the gross weight of the filled container to compute and display the net weight of the contents.

Whenever such a tare weight container is placed on the platter of a scale operating in such a net mode, the digital display should indicate a zero weight. However, drift and hysteresis effects may cause the digital data representing the subsequent measurement of the weight of the container to be different from the previously measured weight data which was stored as the tare weight. Consequently, a subtraction of the earlier stored tare weight from the currently measured weight may cause an erroneous non-zero numer to be displayed.

It is a unique feature of the present invention that such drift or wandering in the digital tare weight data is automatically tracked and the stored tare weight is automatically updated so that an accurate net zero indication is maintained.

The objects and features of the invention will be apparent from the specification and claims when considered in connection with the accompanying drawings illustrating the exemplary embodiment of the invention.

The means, apparatus, and structure, by which the above novel improvements, in accordance with the present invention, are achieved in the exemplary embodiment described herein, comprises various registers, counters, timers, flags, storage spaces, together with specific routines and routine loops for the control of the respective apparatus or means by the central controlled unit. In addition, numerous switches, lamps and display devices cooperate with the central control unit and the various storage spaces, counters, timers, etc., which apparatus comprises input and output means for the system.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the apparatus of the exemplary embodiment of the invention.

FIG. 2 is a diagram illustrating the layout and relative interrelationship of the circuit diagrams of FIGS. 3 through 8 and is shown on the same sheet as FIG. 10.

FIGS. 3 through 8 show the detailed circuitry of an exemplary embodiment of the invention.

FIGS. 9 through 11 are block diagrams of the integrated circuits forming the central processor, memory and general purpose keyboard and display interface devices used in combination with the circuitry of the exemplary embodiment of the invention.

FIG. 12 is a diagram illustrating the operation of the exemplary embodiment of the invention.

FIG. 13 is a random access memory assignment table illustrating the assignments for the memory of the exemplary embodiment of the invention.

FIGS. 14A through 14Z are flow diagrams illustrating the operation of the preferred embodiment of the invention (FIG. numbers 14Q and 14U are not used for clarity).

In describing the preferred embodiment of the invention illustrated in the drawings, specific terminology will be resorted to for the sake of clarity. However, it is not intended to be limited to the specific terms so selected, and it is to be understood that each specific term includes all technical equivalents which operate in a similar manner to accomplish a similar purpose. For example, the term connection is not necessarily limited to direct connection but also includes connection through other circuit elements.

GENERAL DESCRIPTION

The exemplary embodiment of the invention is illustrated in the block diagram of FIG. 1. A load cell 40 mechanically supports a platter 12 and is supplied with electrical energy by a power source 42. The load cell applies an analog weight signal through a preamplifier 44 and filter 46 to a switching circuit 50. The analog weight signal has an amplitude which is dependent upon the weight supported by the load cell 40.

The switching circuit 50 is also connected to the power supply so that not only the analog signal but also two reference DC sources can be sequentially applied to the integrator 51 during the performance of a triple slope A/D conversion. The output of the integrator is amplified by an amplifier 52 and applied to a threshold detector so that the crossover of the integrator output with its reference output level is detected by the threshold detector 53. The output of the amplifier is also connected to the switching means 50 for use in resetting the integrator 51. The output of the threshold detector 53 is applied to a microcomputer 54 which is also connected to the switching circuit 50 for controlling its switching functions.

The microcomputer 54 is connected to a printer 28 and through latch decoder and driver circuitry 56 to indicator lamp displays 26. Operational mode selector switches 22 are also connected to data input terminals of the microcomputer 54.

The microcomputer is further connected to a general purpose keyboard and display interface 58 for receiving data from a keyboard 20 and transmitting data through a decoder/driver 60 to digit displays 24. The "PREPACK ON/OFF" switch 16 and the "Z" key 17 are individually connected to discrete inputs to the microcomputer 54.

In this exemplary embodiment, the analog-to-digital conversion is performed by the combination of the switching circuit 50, the reference DC sources derived from the power source 42, the integrator 51, the threshold detector 53 and the microcomputer 54. The amplifier 52 is provided to amplify the integrator output so that the threshold detector will more accurately determine when the integrator output crosses the threshold voltage.

The microcomputer 54 includes storage registers in which the elapsed time counts, which are derived from a microcomputer program or instruction loop, are accumulated. It also includes stored data for each scale capacity. The microcomputer 54 includes a central processor, associated memory and stored data for controlling the switching circuit 50 to appropriately apply the inputs to the integrator 51 in the proper sequence and at the proper time, for interrogating the output of the threshold detector 53, and for arithmetically processing the accumulated elapsed time intervals or counts.

FIG. 12 illustrates, in simplified form, the signal relationships which are most significant in describing the invention. The vertical axes represent amplitudes which are not drawn to scale in order that the principles of operation may be more clearly illustrated. The horizontal axis represents time.

The top most graph 12A depicts the computer interrogation and counting cycles and in the exemplary embodiment have a 65 microsecond period. These are not drawn to scale because several thousand such cycles would be needed. Each cycle represents the length of time required for the microcomputer to loop through its interrogation and indexing sequence of operations.

Below that is a graph 12B illustrating in a solid line the output of the integrator 51 and also illustrating, with broken lines, portions of alternative outputs from the integrator 51.

Finally, the lowest graph 12C illustrates the output state of the threshold detector 53. Its threshold level is set to correspond to the initial level V.sub.0 at the output of the integrator 51 and its output is high when the output of the integrator is negative and is low when the output of the integrator is positive.

Referring to FIGS. 1 and 12, at time T.sub.0 the microcomputer 54 switches the switching circuit 50 to apply the analog signal, which was derived from the load cell, to the input of the integrator 51. This analog signal continues to be applied and is integrated for the entire time interval T.sub.1. This input causes the output of the integrator to be driven from its initial level V.sub.0 along slope S.sub.1 to level V.sub.1. The magnitude of V.sub.1 -V.sub.0 is directly proportional function of the amplitude of the analog signal and is also a function of its integration time T.sub.1.

The time interval T.sub.1 is a different but fixed and constant time for each different scale capacity and is controlled by the microcomputer 54 and is obtained by reading permanently stored timing data from the computer memory, loading it into suitable registers and sequentially setting the registers in accordance with selected timing loop instructions.

One unique feature of the present invention is that this first integrating interval T.sub.1, during which the analog signal is integrated, is different for each scale capacity and therefore different data is stored in memory and loaded into the time delay registers for each scale capacity.

A particular T.sub.1 time is chosen for each scale capacity so that whatever scale capacity is selected, a full scale weight on the platter for that scale capacity will always drive the integrator output to substantially the same level. Assume for example that the above described integration along integrator output slope S.sub.1 represents a 20 pound weight on the platter 12 with a 30 pound scale capacity selected, then a 30 pound weight on the platter 12 would integrate along slope S.sub.B to arrive at V.sub.MAX at the time T.sub.1A after time interval T.sub.1. If, for example, a 15 kg scale capacity were then selected, a shorter analog signal integrating the time would be provided by the microcomputer 54 so that a 15 kg weight on the scale platter would drive the integrator output along the slope S.sub.C to reach V.sub.MAX at a time T.sub.1B. In the examplary embodiment, the following analog signal time intervals are used:

6 kg.times.2 g-239.660 milliseconds

15 kg.times.5 g-95.790 milliseconds

30 lb.times.0.01 lb-105.625 milliseconds

At time T.sub.1A which is the end of the first integrating time interval T.sub.1, the microcomputer 54 switches the switching circuit 50 to begin the second integrating time interval T.sub.2 by applying a first reference DC source I.sub.1 to the input of the integrator 51. This first reference DC source I.sub.1 is then integrated to drive the integrator output level, which represents the sum of the integral obtained during T.sub.1 and the integral being performed during T.sub.2, along slope S.sub.2 back towards and past the initial integrator output level V.sub.0.

After initiating this second integrating interval T.sub.2, the microcomputer begins periodically interrogating the output of the threshold detector 53 looking for the transition which indicates the crossover of the integrator output level with its initial level V.sub.0.

Each time the microcomputer interrogates the output of the threshold detector 53 and finds that crossover has not occurred, it increments a memory register referred to as the T.sub.2 register or T.sub.2 counter which is assigned to accumulate such interrogation counts. Each such interrogation and counting cycle or instruction loop requires the identical time to perform which in the exemplary embodiment, is 65 m sec.

Eventually, at a time labelled T.sub.2A in FIG. 12B, the output of the integrator 51 crosses over its initial level V.sub.0 causing the output of the threshold detector to switch from a high state to a low state. This transition may occur anywhere within an interrogation and indexing cycle or the end or beginning of such a cycle. However, because of the digital ambiguity the microcomputer 54 will not detect this transition until it interrogates the output of the threshold detector 53 at time T.sub.2B.

When the switching of the output of the threshold detector 53 is detected at T.sub.2B by the microcomputer 54, no more interrogation and indexing cycle counts are accumulated in the memory register. Therefore, the digital count accumulated in the first memory register at time T.sub.2B represents the sum of the amplitude (V.sub.1 -V.sub.0) plus any overshoot V.sub.2 -V.sub.0 of slope S.sub.2, beyond level V.sub.0.

On occasion, the coincidence of the integrator output with the threshold level V.sub.0 will occur relatively near the end of a counting cycle. The possibility then exists that circuit switching, which occurs at the end of the computer interrogating cycles, may cause transients which might cause erroneous operation. For example, if the crossover occurs just before an interrogation of the output of the threshold detector 53 by the microcomputer 54 so that very little overshoot occurs, then the output level of the integrator will be close to the level V.sub.0. If the next integrating interval T.sub.3 were then begun, a computer clock pulse may cause the threshold detector 53 to switch states prematurely.

A unique feature of the present invention is that these crosstalk problems can be eliminated by providing an extra delay at the end of the T.sub.2 interval after the microcomputer 54 has detected the V.sub.0 crossover. Conveniently, this delay interval, labelled T.sub.2C, can be made equal to one interrogation cycle and will cause the integrator output to be driven further along S.sub.2 from V.sub.2 and V.sub.3. However, the count accumulating memory is not incremented so that no count is added to the memory register for that extra cycle.

After delay time T.sub.2C, the computer 54 switches the switching circuit 50 to apply a second reference DC source I.sub.2 to the integrator 51. This second reference DC source I.sub.2 is substantially less than the first reference DC source I.sub.1 which was integrated during interval T.sub.2 because it is desired to integrate at a reduced slope S.sub.2 in order to obtain more precisely the time of the coincidence of the integrator output with its initial level V.sub.0. In the exemplary embodiment of the invention, the reference source which is integrated during the T.sub.2 interval is 32 times greater than the reference source which is integrated during the T.sub.3 interval. Therefore, the magnitude of the slope S.sub.2 of the integrator output during interval T.sub.2 is 32 times greater than the magnitude of the slope S.sub.3 during interval T.sub.3.

Upon the beginning of interval T.sub.3, the microcomputer 54 again goes through interrogating and counting cycles just as it did during interval T.sub.2. However, during interval T.sub.3, the interrogating and counting cycles are counted by incrementing a memory register referred to as the T.sub.3 counter or T.sub.3 register. Then, as during interval T.sub.2, counts continue to be accumulated in the second memory register until the first interrogation of the threshold detector 53 by the computer 54 which occurs after coincidence of the integrator output with the threshold level V.sub.0. When the computer detects the resultant output level change of the threshold detector 53 at time T.sub.4, the T.sub.3 integrating interval and the count accumulation is stopped by the microcomputer 54.

At time T.sub.4, the count accumulated in the second register during interval T.sub.3, is directly proportional to and represents the difference between the integrator output level V.sub.3 at T.sub.2C which is at the beginning of interval T.sub.3 and the integrator output level at T.sub.4 at the end of interval T.sub.3. For computational purposes, the integrator output level at the end of T.sub.3 is assumed to be V.sub.0. Since this is a digital ambiguity within one of the counting cycles for the integration along the lesser slope S.sub.3, it will be apparent from the following discussion that the error is less than one part in 30,000 at full scale capacity in the exemplary embodiment.

Nonetheless the time T.sub.4, when the microcomputer detects the crossover, there will again be some overshoot past the initial level V.sub.0 if the crossover occurs between periodic interrogations of the output of the threshold detector 53.

In order to remove the affect of this overshoot and accurately reset the integrator precisely to the identical V.sub.0 prior to each integration, the microcomputer 54 switches the switching circuit 50 to effectively connect the integrator output to its input. This negative feedback drives the integrator output to V.sub.0 following T.sub.4 by effectively discharging the capacitor of the integrator 51. This is desirable because the current may drift prior to the next integrating cycle and because the overshoot and the end of the interval T.sub.3 may produce an error in the time of crossover during the T.sub.2 interval in which the integration is done along the steeper slope S.sub.2.

The integration functions of the triple slope A/D conversion are completed with the accumulation in each of two memory registers of the digital count data taken along slopes S.sub.2 and S.sub.3. The microcomputer must now take this data and derive a digital number which is proportional to V.sub.1 -V.sub.0 and which therefore is proportional to the amplitude of the analog input signal which was integrated during time interval T.sub.1.

The counts in the T.sub.2 register are proportional to V.sub.1 -V.sub.2. The counts accumulated in the T.sub.3 register are proportional to V.sub.3 -V.sub.0. However, these counts were derived from the integration of two different reference DC sources of substantially different amplitudes. Therefore each T.sub.2 count represents a different and greater quantity of integrator output amplitude and thus a greater weight increment than is represented by each T.sub.3 count. In the exemplary embodiment, the first reference DC source I.sub.1 is 32 times greater than the second reference DC source I.sub.2 and therefore each T.sub.2 count represents 32 times as much amplitude (32 raw weight increments) as does each T.sub.3 count.

In order to equalize the value of each count in the T.sub.2 and T.sub.3 counters, the microcomputer 54 first multiplies the T.sub.2 count by the ratio of I.sub.1 /I.sub.2 which in the exemplary embodiment is 32. There upon the result represents the raw weight increments.

By way of example, 600 interrogating and counting cycle counts may have been accumulated in the T.sub.2 register in driving the integrator output from V.sub.1 to V.sub.2 and 45 interrogating and counting cycle counts may have been accumulated in the T.sub.3 counter in driving the integrator output from V.sub.3 to V.sub.0 during interval T.sub.3. Consequently, in accordance with the invention, the microcomputer will multiply 600 by 32 to obtain a product of 19,200 raw weight increments represented by V.sub.1 -V.sub.2.

The microcomputer then processes the T.sub.3 count to convert it from a number representing V.sub.3 -V.sub.0 to a number representing V.sub.2 -V.sub.0. This is done by subtracting from the T.sub.3 count a number of counts representing V.sub.3 -V.sub.2. Since the integration along slope S.sub.2 from V.sub.2 to V.sub.3 required one interrogating and counting cycle during time T.sub.2, that interval T.sub.2C represents the same amplitude as is represented by a number of T.sub.3 counts which is equal to the ratio of the first reference DC source I.sub.1 to the second constant DC source I.sub.2. Consequently, the microscomputer subtracts that ratio I.sub.1 /I.sub.2 from the accumulated T.sub.3 count.

In the above example for the exemplary embodiment, the number 32 is the ratio which is subtracted from the T.sub.3 count of 45 yield a difference of 13 counts. These 13 counts represent 13 raw weight increments represented by V.sub.2 -V.sub.0.

Therefore, the microcomputer can now arithmetically derive the number of raw weight increments represented by V.sub.1 -V.sub.0 by subtracting this difference of T.sub.3 counts which represents V.sub.2 -V.sub.0 from 32 times the number of T.sub.2 counts. In the example, the microcomputer subtracts 13 from 19,200 to yield 19,187 raw weight increments.

This digital number is proportional to the amplitude of the analog weight signal which was integrated during T.sub.1. In the exemplary embodiment this digital represents weight increments which are referred to as raw weight increments herein.

Each weight indication is then filtered by an improved digital filter. Each weight, when obtained, is subtracted from the filtered weight and the difference divided by two. A one is then added or subtracted from the result to make the result approach the last weight and the last weight corrected by the final result.

This digital number of raw weight units is multiplied by the computer at a later time by the computer by a factor, depending upon the scale capacity to obtain the weight in the proper units for display.

The present invention maintains an accurate zero indication when the scale is not operating in the net mode and also maintains an accurate net zero indication in addition by updating the data stored in a tare weight register.

Tare weight data may be entered into a tare memory register by either of two methods. The digits of a tare weight may be keyed in through the keyboard 20 and this is referred to as a keyboard tare. The tare weight data may also be entered into memory by placing an empty container or other tare weight on the platter and depressing the "T" key. This is referred to as manual tare and causes the scale to read the tare weight and store it in the tare memory.

After a tare weight is properly entered by either of these operations, the computing and weighing scale displays the net weight, which is the difference between the weight of an object on the platter and the weight data stored in the tare register. Consequently, an object weighing the same as the tare weight, for example, the same empty container, should cause a zero net weight to be displayed. A lessor weight on the platter will generate the display of a negative weight.

Unfortunately, creep, hysteresis effects and drift may cause an object on the platter to generate slightly different tare weight data at different times. Similar difficulties have been observed in the maintenance of a gross zero indication as described in Loshbough et al, U.S. Pat. No. 3,986,012. In that situation, a separate auto zero register is used to store a correction factor for automatically correcting the gross zero indication. However, it has been discovered that the same auto zero register cannot be used for net zero tracking because whenever the scale reverts from a net mode of operation back to its gross mode, the auto zero register would still contain net zero tracking data and be erroneous for gross auto zero correction purposes.

The invention involves the periodic updating of the tare weight data to track such wander in order to maintain the display of a zero net weight under the conditions for which a zero net weight should be displayed and in order to use the most recently detected and most accurate tare weight data as a reference which is subtracted from total gross weight to compute net weight.

Each time the microcomputer 54 computes a net weight, it examines that weight data to determine whether the tare weight data should be modified. If the net weight is found to be exactly zero, then no drift has occurred and no tracking is necessary. Since a zero indication already exists, the microcomputer skips the remaining net zero tracking sequence of operations.

However, if the computed net weight is not exactly zero, it is then examined to determine whether it is close enough to a net weight of zero that its departure from zero can be attributed to creep, drift or hysteresis effects rather than to a change in the weight placed on the platter.

This decision, whether the net zero tracking should actually be performed, is made by determining whether the net weight is within a preselected, narrow, weight range or band centered about a net weight indication of zero. Therefore if the computed but non-zero net weight is outside this range, the remainder of the net zero tracking sequence of operations is skipped. However, if it is within the range, net zero tracking is performed by modifying the previously stored tare weight data to compensate for the shift or wander of the net zero.

Data representing the preselected range within which net zero tracking is performed is permanently stored in the memory of the microcomputer 54. In the exemplary embodiment of the invention this range is a predetermined number of increments which represent different weights for each scale capacity so the net zero tracking sequence of operations is done with data which has already been multiplied by a scale conversion factor to represent output increments of weight rather than units of raw weight increments.

For example, in the exemplary embodiment, for the following scale capacities, the net weight must be within the following ranges in order for the tare weight data to be modified to track the net zero:

    ______________________________________
    Scale Capacity     Range
    ______________________________________
     6kg .times. 0.002kg
                       .+-. 0.0008kg
    15kg .times. 0.005Kg
                       .+-.00.0002kg
    30 lb .times. 0.01 lb
                       .+-.00.004 lb
    ______________________________________