Utility consumption monitoring and control system

Abstract

The present invention is a digital and analog system for generating an energy log for instant recall and display. The system is permanently programmed in read-only memory with the task of scanning sensor inputs, performing consumption calculations, updating the non-volatile memory, responding to external commands, and monitoring peripheral performance. The stored information is available for real-time query of individual sensor data or as a composite hard copy report on a month-to-date or month-end basis. The apparatus accepts inputs from both analog and digital sensors whose outputs produce information related to data such as current consumption, water consumption, or fuel consumption and provides an optional interface for the control of these functions based on pre-programmed upper/lower limits. Based on the various inputs, data is stored in specified memory locations and consumption rates and costs are computed based on sensor calibration factors and energy cost factors stored in non-volatile memory at the time of calibration. The system is programmed to detect invalid data and failed sensor inputs in addition to automatically calibrating.

Claims

What is claimed is:

1. A system for individually monitoring utility resource consumption in a multi-occupant dwelling, said system comprising:

a plurality of utility receiving means for providing utility resources to occupants of the multi-occupant dwelling;

a plurality of sensors operably coupled to said utility receiving means, each said sensor producing a signal indicative of measured utility consumption;

processor means for observing, recording, and calculating the cost of utility consumption; and

interface means for individually and selectively receiving said utility consumption signals, said utility consumption signals including at least two signals employing different communications schemes, said interface means also for providing a digital signal corresponding to a selected one of said utility consumption signals for use by said processor means, said interface means operably interconnecting said processor means with each said sensor;

said processor means including means for self calibrating said measured utility consumption according to dynamically calculated gain and offset parameters stored in said processor means for each one of said sensors.

2. The system of claim 1 wherein said processor means includes non-volatile memory for storing said gain and offset parameters.

3. The system of claim 1 wherein said processor means includes memory and programming stored in said memory, said programming providing for multi-tasking, and one of said tasks including receiving said digital signal from said interface means and recording cost of utility consumption values calculated from said digital signal.

4. The system of claim 1 further including a real time clock connected to said processor means, said real time clock producing a timing signal used in said calculation of cost of utility consumption.

5. The system of claim 1 wherein said calibration means includes means for producing at least two reference utility consumption signals, each said reference signal having a predetermined mutually exclusive value, whereby said processor means calculates said gain and offset parameters according to said digital signals which are provided in response to said reference signals.

6. The system of claim 1 further including data input means for receiving commands, and data display means for displaying cost of utility consumption, said data input means and said data display means operably coupled to said processor means.

7. The system of claim 6 wherein said processor means includes memory and programming stored in said memory, said programming providing for multi-tasking, and one of said tasks including receiving a command from said data input means and displaying cost of utility consumption values on said display means in accordance with said command.

8. A system for individually monitoring utility resource consumption in a multi-occupant dwelling, said system comprising:

a plurality of utility receiving means for providing resources to occupants of the multi-occupant dwelling;

a plurality of sensors operably coupled to said utility receiving means, each said sensor producing a signal indicative of measured utility consumption;

processor means for observing, recording, and calculating cost of utility consumption; and

interface means for receiving said utility consumption signal and providing a digital signal for use by said processor means, said interface means operably connected to each said sensor and said processor means;

said interface means including means for selectively activating at least two reference signals and providing digital signals corresponding to said reference signals for use by said processor means to calculate gain and offset parameters stored in said processor means for each one of said sensors, each said reference signal having a predetermined mutually exclusive value;

said processor means including memory and programming stored in said memory, said programming providing for multi-tasking, and one of said tasks including receiving said digital signal from said interface means and recording cost of utility consumption values calculated from said digital signal.

9. The system of claim 8 wherein said processor means includes non-volatile memory for storing said gain and offset parameters.

10. The system of claim 8 further including data input means for receiving commands, and data display means for displaying cost of utility consumption, said data input means and said data display means operably coupled to said processor means.

11. The system of claim 10 wherein one of said tasks of said multi-tasking programming includes receiving a command from said data input means and displaying cost of utility consumption values on said display means in accordance with said command.

12. A system for individually monitoring utility resource consumption in a multi-occupant dwelling, said system comprising:

a plurality of utility receiving means for providing desired resources to occupants of the multi-occupant dwelling;

a plurality of first sensors operably coupled to said utility receiving means, each said first sensor producing a first signal indicative of measured utility consumption;

a plurality of second sensors operably coupled to said utility receiving means, each said second sensor producing a second signal indicative of measured utility consumption, said second signal employing a communication scheme which is distinguishable from said first signal;

processor means for observing, recording, and calculating cost of utility consumption; and

interface means for receiving said first and second signal and providing a digital signal for said processor means, said interface means operably connected to each said sensor and said processor means;

said interface means including means for selecting one of said first sensors and said second sensors according to said processor means to thereby provide said digital signal.

13. The system of claim 12 wherein said first signal has a signal characteristic including one of the group consisting of voltage varying, frequency varying, amplitude sensitive varying, and large period varying characteristics, and said second signal has a signal characteristic including another of the group consisting of voltage varying, frequency varying, amplitude sensitive varying, and large period varying characteristics.

14. The system of claim 12 further comprising a communication bus operably connecting said processor means and said interface means, said communication bus including a plurality of bus lines, and said processor means including a multiplexing means for activating said selecting means, said multiplexing means in communication with a portion of said bus lines and sending an activation signal to one of said sensors according to said selecting means.

15. The system of claim 12 wherein said processor means includes memory and programming stored in said memory, said programming including periodically checking each said sensor for possible alarm conditions.

16. The system of claim 12 wherein said interface means includes an analog-to-digital signal converter and a schmitt trigger digital-to-digital signal converter.

17. The system of claim 12 further comprising an address bus including a plurality of address lines, said processor means including memory for storing programming and data, wherein a first subset of said address lines are operably connected to said memory for addressing memory locations, and a second subset of said address lines are operably connected to said interface means for selecting one of said first and second sensors.

18. The system of claim 17 further comprising a data bus comprised of a subset of said address lines, said data bus and said second subset being mutually exclusive.

19. The system of claim 12 wherein said interface means includes a switching means for activating an analog self-test control line which provides a known signal whereby said processor means can compare a digital signal output from said known signal with digital signal output of one of said first and second sensor groups.

20. The system of claim 19 wherein said switching means also can switch said analog self-test line on and off to provide a known frequency signal whereby said processor means can compare a digital signal output from said known frequency signal with a digital signal output of one of said first and second sensor groups.

Description

BACKGROUND OF THE INVENTION

The present invention relates to systems for monitoring utility consumption, such as electricity, gas, and water. More specifically, the field of the invention is that of utility monitoring systems for multi-occupant dwellings such as apartments or small businesses.

Many multi-occupant dwellings (i.e. large apartment complexes) and small businesses have been constructed with central metering systems for metering utility consumption by occupants. In this environment, individual occupant consumption can not be determined and thus the incentive, on the part of the occupant, to conserve utility based resources is minimal. The result may well be increased consumption of resources by some individuals which thereby provides a financial inequality to those other individuals prone to conserve.

Conventional central metering systems include a microprocessor which monitors utility consumption and outputs various usage and billing information. These prior art systems provide a basis for allocating costs and locating potential problems. The microprocessor exactly calculates the utility usage; however, these calculations can be no more accurate than the external metering from which the usage data is derived. Thus, problems exist with such conventional systems.

One problem with conventional systems is that no provision is made for the changing characteristics of the metering output over time, e.g., the slowing of a flow meter due to aging. Another problem is that conventional systems are designed for use with specific metering equipment. This limits the available replacement parts for repair of the metering equipment, as well as increases the difficulty of retrofitting a dwelling with such a system.

What is needed is a central metering system which adapts to the changing conditions of the metering equipment.

Also needed is a central metering system which can be used with a variety of metering equipment.

SUMMARY OF THE INVENTION

The present invention is a digital and analog apparatus comprising a microcomputer including a microprocessor having an interrupt capability with associated read-only memory, non-volatile random access memory, real-time clock, analog-to-digital converter (A/D), anti-tamper circuitry, watch-dog counter, data, address, and control buses. In addition, the microcomputer contains circuitry for detection of failed sensors or unauthorized penetration of the apparatus. The software in the read-only memory provides for a multi-level secure user validation, on-site self-calibration of sensors, storage of utility cost and consumption data, detection of out-of-tolerance conditions, continuous self-test of the apparatus, printer, alarm, and display control in an automated non-attended environment.

Low cost utilities are no longer available. Businesses and individuals are seeking ways to conserve natural resources provided by utility companies. Unless users can monitor utility consumption on a demand basis, the tendency is to accept the consumption rates rather than to implement measures to control or minimize utilization. The system allows for central monitoring of utility consumption thus allowing for real-time correction of excessive or non-existent utility consumption. For example, if excessive natural gas consumption existed in a specific location, measures could be immediately taken to determine if the condition were due to a failed sensor or blatant misuse of resources. Should recorded consumption be non-existent when environment conditions would indicate consumption, then an investigation could be performed to determine if sensor failure had occurred or a risk existed to the property relative to frozen pipes, etc. The system recalls utility consumption on a daily or monthly basis with the ability to monitor, detect, alarm, or control on the existence of out-of-tolerance conditions. Because of the real-time clock, out-of-tolerance problems can be hard-copied and time-stamped without on-site intervention and hourly trend data can be provided automatically for recording or plotting peak utility consumption data.

The purpose of the present invention is to provide a desk-top, wall mounted, or panel mounted utility consumption monitoring system for the recording and control of utility consumption of individual dwellings in a multi-occupant environment. The system continuously monitors and logs the individual occupant consumption of electricity (power), natural gas, hot water heat (by differential temperature measurement), and domestic water; and it is further adaptable to a variety of other types of measurement. The system provides both consumption and cost data providing the owner with a means to proportion utility costs on a preprogrammed or radiometric basis. To provide an equitable distribution of costs, the apparatus provides alarm indications relative to its physical penetration, attempted variable/data modification, sensor failure/disconnect, or out-of-limits consumption on a per metered area basis. To provide a more accurate measurement, the system calibrates on-site and performs self-tests to facilitate interfacing with parametrically differing sensor interfaces even within a specific sensor group.

A keypad allows a user to query input and to program the system parameters. A multi-digit display is provided with the keypad for real-time retrieval of data stored in memory. The keypad and display are under the control of the microprocessor via interface control circuitry which is interfaced to the microprocessor address and data bus.

Programmable digital I/O controllers interface with the microprocessor thereby reading the digital inputs and controlling the digital outputs. Analog inputs are controlled through a Field Effect Transistor (FET) switch array matrix which is routed directly to an analog-to-digital (A/D) converter or through a 60 Hz band-pass filter/RMS to DC converter to the A/D converter. Analog inputs are also optionally routed to a Frequency to Voltage (F/V) converter and then on to the A/D converter providing flexibility to interface with a variety of sensors to accommodate possible changes in the economic climate and technological sensor advances.

The real-time clock provides both time-stamping data, power failed data, and data update control for maximum system performance and maximum memory life. The software in ROM supports both a polled and interrupt driven system for sensor recording. The microprocessor software is multi-tasking which allows the sensor interfaces to continue independently of any keypad inquiries, hard-copy output activity, or alarm activation. Thus, under the control of one task, the microprocessor dedicates itself to purely processing sensor inputs, data recording, and output control as applicable; and under the control of the second task, the microprocessor dedicates itself to peripheral response related to operator keypad intervention or alarm servicing.

The system is capable of not only the real-time reading, computation, and update of consumption data, but is also capable of calibrating sensors and compensating for component offsets by storing variables and constants in non-volatile memory. This avoids the problem of calibration during the manufacturing and the specialized calibration equipment needed during on-site installation processing. Because of its programmable outputs and flexible input configurations, full performance and functionality validation can occur at the manufacturing facility or on-site without the need for specialized test equipment. Additionally, because of the socketed non-volatile memory, apparatus change-out can occur without the specified need for full re-calibration by simply changing out the non-volatile memory or retrieving the contents of the memory for reprogramming of a replacement unit as appropriate.

One object of the present invention is to provide a central metering system which adapts to the changing conditions of the metering equipment.

Another object is to provide a central metering system which can be used with a variety of metering equipment.

BRIEF DESCRIPTION OF THE DRAWINGS

The above mentioned and other features and objects of this invention, and the manner of attaining them, will become more apparent and the invention itself will be better understood by reference to the following description of embodiments of the invention taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a perspective view of a cabinet having a keypad and display for enclosing the remaining portions of the apparatus of the present invention.

FIG. 2 is a perspective view of a panel installation having a keypad, display, and the remaining portions of the apparatus of the present invention.

FIG. 3 is block diagram of the microprocessor and the associated peripherals.

FIG. 4 is a schematic diagram depicting the interface of the analog inputs.

FIG. 5 is a schematic diagram depicting the interface of the digital inputs.

FIG. 6 is a schematic diagram depicting the interface of microprocessor to the peripherals.

FIGS. 7-16 are flow chart diagrams of the operation of the present invention.

Corresponding reference characters indicate corresponding parts throughout the several views. The exemplification set out herein illustrates one preferred embodiment of the invention, in one form, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to FIG. 1, the present invention includes cabinet 10 having on which display board 11 and keypad 12 are mounted. Keypad 12 has a plurality of touch operated keys including numerical keys (0 through 9) and special function keys. Additionally, alarm 13 and power switch 14 are located on cabinet 10. Keypad 12 serves as a simple multiple key entry device which permits data retrieval and entry by the use of the CAL, PRT, DISP, PRGM, #and * keys in conjunction with other numeric input keys. Display board 11, being an alphanumeric display, permits the display of both numeric and a full alpha character set as visual feedback to the operator using keypad 12. Specialized attributes of display board 11 may serve as a traditional data separators or may serve as system integrity indicators to permit rapid validation that the apparatus and interfaces are functioning normally, for example by use of an inverse or blinking display capability.

Referring now to FIG. 2, display board 11 and keypad 12, with the alarm 13, power switch 14, and the main microprocessor/peripheral circuitry 16, are mounted in panel enclosure 15, which is typically an electrical panel. The functionality discussed with respect to FIG. 1 is similar to that of FIG. 2, but the packaging of the apparatus differs.

Referring to FIG. 3, the microcomputer of the present invention comprises a microprocessor 92 combined with associated peripheral support. The interfacing peripherals include program memory 93 comprising an EPROM type device, static CMOS RAM 94, EEPROM 95 for non-volatile data retention and storage without needing battery backup, real time clock 96 for measurement timing and time of day reference, programmable peripheral interface 99 which controls matrixed keypad 100, general I/O-printer interface 101, and a display module 102 for real-time display of data. Microprocessor 92 interfaces with A/D converter 105 whose inputs are from voltage reference 109 and analog sensors, specifically sensor groups 111, 112, 113, and 114 under the control of analog control logic 103. The output of sensor groups 111, 112, 113, and 114 is fed either directly to the 8 to 1 analog multiplexer 104, or through a differential amplifier 110 for differential temperature measurement, or through frequency to voltage converter 108 for flow rate data, or through a RMS to DC converter 107 for amplitude sensitive measurements such as the voltage representation of current flow. Additionally, digital information is input through digital interface 90 for measuring frequency oriented digital sensors. Additional interfaces include anti-tamper and alarm interface 91, memory mapped I/O control logic 97, and watchdog counter/under-voltage detector 98. The analog circuitry is self calibrating and self-testing as a result of self-test and calibrate logic 106. FIG. 3 represents the major interfaces to and from microprocessor 92 which is the master controller of the system. The microprocessor can interface with other similar circuitry for expanded functionality or sensor inputs via an expansion interface 115. This is implemented by a high speed data interface for use in a master/slave arrangement.

Referring to FIG. 4, the analog interface includes four major sensor inputs. Two inputs comprise high temperature and low temperature signals which are combined to produce a differential temperature input. The other two inputs are gas consumption and power consumption (current measurement). Each input type includes 24 analog input lines, which is the maximum number of input lines in the exemplary embodiment of the present invention. To monitor more than 24 inputs, multiple sensor groups may be used and may be interconnected as slave units to a unit designated as a master unit. Alternately, sensor groups having a larger input set can be designed within the spirit and scope of the present invention.

In the exemplary embodiment, a group of 24 inputs is referred to hereafter as a SENSOR GROUP comprising the input lines and three 1 of 8 Field Effect Transistor (FET) analog switches: 30, 31, and 32; 33, 34, and 35; 36, 37, and 38; & 39, 40, and 41; which are controlled and configured with any one of twenty-four (24) inputs capable of being selected. This provides the functionality of a 24 to 1 analog multiplexer. The control of the analog multiplexing function is digitally realized by the settings of bits A, B, C, originating from eight bit latch 57 under the control of microprocessor 92. EN1, EN2, and EN3 are produced by outputs from 8 bit latch 57 via 2 to 4 decoder 56 and select which of the three SENSOR GROUPs will be active; and A, B, and C select which of the eight inputs of the selected SENSOR GROUP will be active. This arrangement allows for five bits (the two input into decoder 56 and lines A, B, and C which are directly coupled to the internal logic of the FET switches) to address any of the 24 inputs of a selected SENSOR GROUP.

SENSOR GROUPs are connected in parallel providing for simultaneous active outputs from each SENSOR GROUP. The inputs of each SENSOR GROUP are conditioned and transformed in various ways, as described below, and applied to the input of 1 of 8 FET switch 58 which is under the control of the high order three bits of 8 bit latch 57 (lines CA, CB, and CC). The circuitry of FIG. 4 provides the functionality of a digitally controlled analog multiplexer.

The SENSOR GROUP providing the inputs to 1 of 8 FET switches 30, 31, and 32 provides an interface with external power consumption sensing circuitry (not shown). The power consumption sensing circuitry senses a voltage representation of current which allows the mathematical determination of power consumption. The SENSOR GROUP 33, 34, and 35 provides an external interface to the natural gas flow interface (not shown) which can be in the form of flow sensing circuitry which produces a frequency or analog voltage signal. The SENSOR GROUPs 39, 40, and 41; and 36, 37, and 38 provide an external interface to a differential temperature sensor interface 110. The invention provides an interface adapted to receive and process inputs having different communication schemes such as voltage variation, frequency variation, current variation, etc.

Each of the SENSOR GROUPs is low pass filtered to reduce high frequency noise. The low-pass filter comprises a 20 DB/decade filter which includes the on-resistance of the FET switch (approximately 1000 Ohms) in conjunction with a filter capacitor, on the output of the FET switch, to ground 42, 43, 44, and 45. This filter becomes necessary when driving into the non-inverting amplifiers 46, 47, 48, and 49 which provide a high impedance load to the FET switches to minimize the DC losses associated with FET on-resistance. This non-inverting amplifier design provides a high impedance input to a SENSOR GROUP and a low impedance output to the inputs of 1 to 8 source selector FET switch 58 or as a low impedance source to drive to intermediate circuitry (described below).

Intermediate circuitry between one of the SENSOR GROUPs and FET switch 58 includes differential amplifier 53, which provides a single output to the 1 of 8 source selector FET switch 58 indicating the differential temperature being measured. Also, the output of non-inverting amplifier 47 provides a low impedance source for time varying signal which is capacitively coupled to frequency to voltage converter 52, which provides an analog voltage to the 1 of 8 source selector FET switch 58. Power monitoring circuitry includes a non-inverting amplifier 46 for providing a low impedance drive for time varying signals to 60 Hz low pass filter 50 which is connected to a true RMS to DC converter 51 whose output is connected to the 1 of 8 source selector FET switch 58. The following circuits facilitate adaptation to a variety of different possible sensor types which may provide differing external interfaces: 60 HZ low-pass filter 50, RMS to DC converter 51, non-inverting amplifier for natural gas consumption 47, frequency to voltage converter 52, differential temperature amplifier 53, low side temperature sensor 48, high side temperature sensor 49, and calibration standard 54 and 55 voltage reference; and they are all connected as inputs to the 1 of 8 source selector FET switch 58.

The inputs to 1 of 8 source selector FET switch 58 are controlled by the three high order bit settings of 8 bit latch 57 which permits the CA, CB, and CC inputs to select any one of the eight inputs and route the input to voltage follower amplifier 59 for interface as the analog input to Analog-to-digital (A/D) converter 105 under the control of microprocessor 92.

Self-test and self calibration functionality is provided by quad FET switch 61 whose input is the voltage reference produced by voltage follower 55 with the actual quad FET switch control originating from analog self-test control line 60 which is under the control of microprocessor 92. The outputs of quad FET switch 61 are connected to each SENSOR GROUP and provide a calibration reference voltage for all circuits. By this arrangement, a two point (zero voltage and reference voltage) self calibration means is provided for negating gain and offsetting variations in the active circuitry by determining, calculating, and storing gain and offset parameters. Analog self-test control line 60 can also be pulsed at a known rate to provide calibration information to microprocessor 92 related to inaccuracies in the frequency to voltage converter 52, RMS to DC converter 51, and 60 Hz low pass filter 50 for storage and self calibration purposes. In addition, quad FET switch 61 can be used for self-test by the external shorting of each of a SENSOR GROUP's 24 inputs together and verifying proper sensor group functionality and parametric parameters.

Referring to FIG. 5, the digital interface of the system includes three octal buffers 63, 64, and 65 for interfacing with a digital type frequency source. The digital type frequency source might represent a flow rate indicator such as might be found on an incoming water line or may represent a switch closure associated with a thermostat type output. Octal buffers 63, 64, and 65 are schmitt trigger devices providing natural noise immunity and accommodating slow rise and fall times as a result of their dual threshold characteristics. This provides a noise free digital interface to the control circuitry shown in FIG. 6. The outputs of octal buffers 63, 64, and 65 are connected in parallel and serve as the inputs to 8 to 1 multiplexer 66 with octal transceiver 80 interfacing with microprocessor 92 as shown in FIG. 6 and the selection of the output controlled by control or signal lines DC, DD, and DE 68. Octal buffers 63, 64, and 65 have outputs which are tri-state, thus allowing each to be separately selected by 2 to 4 decoder 67 with control lines 68 originating from microprocessor 92. The combination of control lines 68 in conjunction with 2 to 4 decoder 67 and 8 to 1 multiplexer 66 provides a combined functionality of a 24 to 1 digital multiplexer.

Referring to FIG. 6, microprocessor 78 is an 8 bit self contained microprocessor with 16 bits of address space and on-board RAM and optional on-board PROM/ROM. The microprocessor 78 includes a digital interface 89 coupled to the digital interface logic of FIG. 5. Additionally, the analog control interface includes the functionality of an analog self-test control via the octal buffer 77 and analog-to-digital converter 87. The input to analog-to-digital converter 87 originates from the analog interface section as shown in FIG. 4. Also, voltage reference 86 is an input to analog-to-digital converter 87. Microprocessor 78 also provides a digital output control interface via programmable peripheral controller 82 and octal buffers 84 and 83. This digital output control is general purpose in nature and can be used for system control, loopback self-test, and/or printer interface/control. Programmable peripheral controller 82 also provides an interface to 3 to 8 decoder 85 whose output serves as a row or column interface to a matrixed keypad. The return from the keypad is directly input to programmable peripheral controller 82 as indicated in the four input lines directly below and associated with the 3 to 8 decoder. This configuration supports up to a 4 X 8 matrixed, 32 key keypad.

Further interfaces for the microprocessor 78 are included as software in program memory 70 which is a PROM/ROM type device which may contain up to 64K bytes of program memory and is used in situations where the use of on-board ROM/PROM contained within the microprocessor 78 is undesirable from a cost or performance standpoint. Electrically erasable programmable read only memory (EEPROM) 71 and 8K.times.8 of Complementary Metal-Oxide-Semiconductor (CMOS) Random Access Memory (RAM) 72 serve as permanent non-volatile memory and local scratchpad memory, respectively. The EEPROM 71 stores the various calibration data associated with the analog channels plus specific gain and offset constants necessary for proper apparatus functionality. Because EEPROM 71 has a finite write cycle life to any specific memory location, the 8K.times.8 CMOS RAM 72 is coupled to battery backup power 74 to permit high speed calculation and extensive data storage to be made in RAM 72 and then stored at a later time into EEPROM 71.

Real time clock 73 is coupled to battery backup 74 and serves as a time-of-day clock for display purposes and memory storage purposes and provides a means to determine the appropriate storage interval for EEPROM 71. In the exemplary embodiment, real time clock 73 is crystal controlled and can be altered by microprocessor 78.

Microprocessor 78 interfaces with display module 88 for purposes of displaying time-of-day, memory data associated with selective or multiple input sensor data, alarm conditions, and self-test (health check) status. Display module 88 may, under some conditions, act as the keypad input source instead of using programmable peripheral interface 82 and 3 to 8 decoder 85 for this purpose. Determination of which input source is preferable depends on component availability, cost, and output interface requirements.

Under-voltage sensor/watchdog timer 79 guards against improper microprocessor initialization, under-voltage shutdown, and internal microprocessor malfunction during operational periods. Under-voltage sensor/watchdog timer 79 assures that proper microprocessor operation is maintained while protecting other peripheral devices and external interface circuitry from improper microprocessor I/O interface.

The various peripherals are controlled using a memory mapped I/O design including a 3 to 8 decoder 76 which controls the selection of individual peripherals. Additionally, octal buffer 77 provides alarm control and anti-tamper control using a dedicated port interface of microprocessor 78.

RAM 72 and real-time clock 73 are coupled to battery backup power 74 with main power being supplied by an external power source. If the external power source is disrupted, the on-board battery of battery backup 74 will take control and retain the memory of RAM 72 and real time clock 73. The loss of power can be tolerated for up to 1000 hours with no risk of data loss in the CMOS RAM and real time clock. The voltage inputs required for proper active circuitry functionality are +5 V (for most operations) and .+-.5 V (for analog circuitry operations).

The operation of the hardware is exclusively controlled by the tasks or programs stored in PROM/ROM 70. The individual instructions and tasks will vary depending on the microprocessor selected and the specific peripherals integrated with the microprocessor. Generally, any eight bit microprocessor with a multi-task and interrupt capability is suitable for purposes of the present invention. The following hardware is considered suitable for implementation of this invention.

    ______________________________________
    INTEGRATED  PREFERRED
    CIRCUIT TYPE
                EMBODIMENT
    ______________________________________
    Microprocessor
                Intel Corporation
                8031 8 bit self contained, 40 pin
                DIP
    PROM        Intel Corporation
                P27256 32Kx8, 28 pin DIP
    EEPROM      XICOR Corp.
                X2864H 8Kx8, 28 pin DIP
    RAM         SAMSUNG Electronics
                KM6865LP 8Kx8, 28 pin DIP
    A/D Converter
                National Semiconductor
                ADC0802/ADC0803/ADC804, 20 pin DIP
    Programmable
                Intel Corporation
    Peripheral Interface
                8255A-5, 40 pin DIP
    8 to 1 Analog Mux
                Harris Corporation
    with input  HI-508A, 16 pin DIP
    protection
    Frequency to
                National Semiconductor
    Voltage Converter
                LM2907/2917, 14 pin DIP
    RMS to DC   Maxim Integrated Products
    Converter   AD536A/AD636, 14 pin DIP
    Watchdog counter &
                Maxim Integrated Products
    under voltage
                MAX690, 8 pin DIP
    sensor
    Display module
                Philips Corporation
                LTN211, 2 rows .times. 16 characters/row
    ______________________________________

• Inventors
  Shaffer, Robert; Thorpe, Thomas W.;
• Assignee
  Sleuth Inc. (Fort Wayne, IN)
• Published
  Oct-6-1992
• Current US Classes:
  324/103R
  705/412
• Application #
  594354
• International Classes
  G06F 015/20
• Field of Search
  324/103 364/464.01 364/464.04 364/465 364/483
• Examiner
  Lall; Parshotam S.
• Agent
  Baker & Daniels
• US Patent References:
  4002890
  4080568
  4120031
  4261037
  4291376
  4473797
  4489220
  4504831
  4575801
  4577977
  4591988
  4639876
  4675828
  4707852
  4803632
  4804957
  4862493
  4990893
  5079715