Utility usage

Computer controlled energy monitoring system

4568934

Abstract

Apparatus for monitoring and displaying energy consumption which comprises at least one communications channel, at least one group of remote stations each comprising a plurality of information channels and connected to a respective communication channel, and a central station connected to the communication channels and capable of addressing the information channels at the remote stations. The central station addresses an energy consumption sensor connected to an information channel at a remote station, and receives energy consumption data from the sensor, computes an actual energy consumption, and sends a signal representative of the computed energy consumption to a display device connected to an information channel of a remote station to display the same.


Claims

What is claimed is:

1. An apparatus for monitoring and displaying energy consumption comprising:

at least one communications channel;

at least one group of remote stations connected to a respective communications channel, each remote station comprising a plurality of information channels and addressable means for selectively connecting an addressed one of said plurality of information channels to said respective communications channel;

at least one energy consumption sensor connected to a respective information channel of a remote station;

at least one display device connected to a respective information channel of a remote station; and

a central station connected to each communications channel and comprising means for selectively addressing the information channels at said remote stations, means for receiving the output of said sensor during the period the information channel connected thereto is addressed and connected to a respective communications channel, means responsive to the output of said sensor for computing energy consumption data, and means for sending a signal representative of said energy consumption data to said display device during the period the information channel connected to said display device is addressed and connected to a respective communications channel, said display device displaying said energy consumption data.

2. An apparatus as in claim 1 wherein said sensor measures the flow of current through an electrical path and said energy consumption data represents electrical energy consumption.

3. An apparatus as in claim 1 or 2 wherein said means for computing computes as said energy consumption data a present rate of energy consumption in the form of a number of energy measurements units per a predetermined time period.

4. An apparatus as in claim 1 or 2 wherein said means for computing computes as said energy consumption data a present rate of energy consumption in the form of cost per a predetermined time period.

5. An apparatus as in claim 1 or 2 wherein said means for computing computes as said energy consumption data a total amount of energy consumed to date as a number of energy measurement units for a predetermined time period.

6. An apparatus as in claim 1 or 2 wherein said means for computing computes as said energy consumption data a total energy cost to date for a predetermined time period.

7. An apparatus as in claim 1 or 2 wherein said means for computing computes a total present energy consumption as sensed by said at least one sensor and further computes, as said energy consumption data, a percentage of a predetermined peak demand energy consumption constant corresponding to said total present energy consumption.

8. An apparatus as in claim 7 wherein a plurality of energy consumption sensors are respectively connected to information channels at said remote stations and said means for computing computes a total present energy consumption as sensed by said plurality of sensors.

9. An apparatus as in claim 1 wherein said means for sending sends a said signal in the form of tones which are modulated with digital data and said display device comprises:

a tone detector connected to a respective information channel;

means connected to the output of said tone detector for generating a sequence of digital data signals which vary in accordance with the modulation of the tones applied to said tone detector;

means connected to the output of said generating means for composing a display message from said sequence of digital data; and

means for displaying said display message.

10. An apparatus as in claim 9 wherein said tones are pulse-width modulated and said generating means comprises a pulse-width discriminator.

11. An apparatus as in claim 1 further comprising an information signal sending device connected to a respective information channel of a remote station, said information signal sending device generating at least one information signal on the information channel connected thereto;

means at said central station for receiving an information signal from said sending device during the period the information channel connected to said sending device is addressed and connected to a respective communications channel; and

means at said central station responsive to the receipt of said information signal for sending said signal representative of said energy consumption data to said display device during the period the information channel connected to said display device is addressed and connected to a respective communications channel.

12. An apparatus as in claim 11 wherein said information signal sending device comprises means for selectively sending one of a plurality of different information signals to said central station and said central station comprises means responsive to a received one of said plurality of information signals for selectively sending one of a plurality of data signals, each representative of a different type of energy consumption data, to said display device.

13. An apparatus as in claim 11 wherein a said sensor, a said display device and a said information signal sending device are connected to respective information channels of the same remote station.

14. An apparatus as in claim 12 wherein said information signal sending device comprises a switching device for selectively connecting different resistors to a respective information channel so that said plurality of information signals are formed as a plurality of different resistance values.

15. An apparatus as in claim 9 further comprising power supply means located at each remote station and connected to a said communications channel for converting electrical energy present in tones appearing on said communications channel to operating power for said display device.

16. An apparatus as in claim 1 further comprising a plurality of energy consumption sensors respectively connected to information channels at said remote stations and means at said central station for computing the total energy consumption sensed by said plurality of sensors, means for comparing said total energy consumption with a limit value, and means for sending a first indicator signal to said display device when said total energy consumption exceeds said limit value, said display device displaying said first indicator signal.

17. An apparatus as in claim 16 wherein said central station further comprises means for sending a second indicator signal to said display device when said total energy consumption is greater than a predetermined value below said limit value, said display device displaying said second indicator signal.

18. An apparatus as in claim 1 further comprising:

a pair of signal lines connected to said sensor;

means for taking a first open circuit voltage measurement V.sub.1 across said signal lines;

means for connecting a series connected resistance R.sub.0 and voltage source V.sub.2, each of a predetermined value, across said signal lines after said first measurement;

means for taking a second closed circuit voltage measurement V.sub.3 across said signal lines while said resistor R.sub.0 and voltage source V.sub.2 are connected thereacross; and

means for calculating a value representing the impedance of said sensor from the values R.sub.0, V.sub.1, V.sub.2, and V.sub.3.


Description

BACKGROUND AND SUMMARY OF THE INVENTION

The present invention relates to a centralized data communications system in which a plurality of groups of remote stations communicate with a central station over a respective plurality of communications channels each of which is shared by all the remote stations of a group. In a preferred arrangement of the system, data communicated from the remote stations to the central station is representative of sensed current in an electrical path which is used, together with data representing the voltage on the electrical path, by the central station to indicate energy consumption for information and billing purposes.

Various types of centralized data communications systems have been proposed in which a plurality of remote stations are addressed by a central station over one or more communications channels for the purposes of receiving data from or transmitting data to the remote stations. Generally speaking, the type of addressing which is employed is quite complex requiring sophisticated apparatus at both the central and remote stations. The complexity of this apparatus naturally decreases its reliability and increases its cost, limiting widespread use of centralized data communications systems.

Accordingly, one object of the present invention is to provide a relatively simple, reliable and low-cost data communications system in which a central station tone addresses a plurality of remote stations, each containing a plurality of information channels which may send data to or receive data from the central station. Each remote station contains apparatus therein for counting the number of tones on a communications channel connecting it to the central station and connecting one of the information channels to the communications channel only when the number of counted tones falls within a numerical range of tones assigned thereto. In addition, each remote station contains apparatus for sequentially connecting the information channels to the communications channel as tones within the predetermined numerical range assigned the remote station are counted. This type of addressing provides a centralized data communications system which is both simple and reliable, while considerably reducing its cost. The simplicity of construction of the remote stations also allows them to be constructed as low-cost modules which may be powered solely by the addressing tones.

An additional object of the invention is the provision of a centralized data communications system which is flexible and versatile, and which can be easily adapted to accurately take various output measurements from various types of sensors which may be connected to information channels at the remote stations.

An additional object of the invention is the provision of a centralized data communications system having a high degree of measurement accuracy which is achieved by calibrating the output of a remote station sensor. This is accomplished by first receiving and storing at a central station output calibration data from the sensor when measuring a parameter under known conditions. This calibration data is subtracted from output data of the sensor when measuring a parameter under unknown conditions, thus providing data that has been normalized to the known conditions.

An additional object of the invention is the provision of an automatic digital gain control circuit which is used at the central station of a centralized data communications system to adjust the level of an incoming signal to be within a predetermined measurement range of the central station equipment.

An additional object of the invention is the provision of a simple and low cost remote station module which is connected to a central station and used to monitor energy consumption or other parameters, which module contains unique circuitry for decoding and responding to tones emitted by the central station during addressing.

An additional object of the invention is the provision of a centralized data communications system which, with low cost sensors, is capable of measuring temperature, fluid flow, power and BTU consumption at a remote station with a high degree of accuracy.

An additional object of the invention is the provision of a centralized data communications system capable of controlling operations of an addressed remote station by sending tone control signals thereto.

The present invention also relates to a system for monitoring of energy consumption in an electrical path at a remote station. At present, there are many electrical installations such as in commercial buildings, apartments, condominiums, etc. where a single utility meter is provided at an electrical service entrance. With this arrangement, individual energy consumption in the apartments or other units of the building cannot be individually monitored or billed. This tends to promote waste as the occupants of the apartments have no individual control over total energy consumption and consequently little or no economic incentive to conserve energy.

Accordingly, an additional object of the invention is the provision of an energy management system which can be installed in a new or existing building not having individual unit metering to monitor and provide an indication of the individual energy consumption in each unit. Monitoring of the energy consumption enables the provision of an internal billing system for the building in which energy consumed by each unit can be individually metered and billed. In the system of the invention each unit contains at least one remote station communicating with a computer controlled central station over a communications channel. Each remote station includes at least one information channel which is connected to a current sensor which monitors the current passing through an input electrical path providing electrical service to the unit. The central station computer receives data from the current sensor representing current consumption and data representing voltage in the electrical path and calculates power, storing and processing it to provide a periodic indication of energy consumption which may be used for information or billing purposes. Thus, even though a building may not have individual electrical metering of each of the units, the system of the invention provides this function.

An additional object of the invention is to provide a unique power calculation circuit for calculating power existing in an electrical path from current in the path and a voltage derived from the voltage present on the path.

An additional object of the invention is the provision of a centralized data communications system for monitoring energy consumption at a remote station which provides a visual display at one or more monitored locations of the energy being consumed thereat.

An additional object of the invention is the provision of a centralized data communications system for monitoring energy consumption at a remote station and providing a visual display at the remote station of energy consumption in one of a number of different user selectable formats.

An additional object of the invention is the provision of an apparatus which is capable of reliably determining the impedance of an energy or other sensor connected therewith.

An additional object of the invention is the provision of a centralized communications system for monitoring energy consumption at a remote station which is capable of determining a fault or tampering condition of an energy sensor located at the remote station by monitoring the impedance of the sensor.

These and many other objects, features and advantages of the invention will become evident from the following detailed description which is presented in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the data communications system of the invention;

FIG. 2 is a schematic diagram of the remote stations illustrated in FIG. 1;

FIGS. 3 and 4, taken together, form a schematic diagram of one of the section switches illustrated in FIG. 1;

FIGS. 5, 6A and 6B, taken together, form a schematic diagram of the controller interface illustrated in FIG. 1;

FIG. 7 is a schematic diagram of the master controller illustrated in FIG. 1;

FIGS. 8A and 8B, taken together, form a schematic diagram of the A/D converter illustrated in FIG. 1;

FIG. 9 is an overall system flowchart for the operation of the computer illustrated in FIG. 1;

FIG. 10 is a flowchart of the initialization program illustrated in FIG. 9;

FIGS. 11 and 12 are flowcharts of the master timer interrupt program illustrated in FIG. 9;

FIG. 13 is a flowchart showing the essential steps of the data collecting and processing programs illustrated in FIG. 9;

FIG. 14 is a flowchart of a sensor interrupt program;

FIG. 15 is a flowchart of the program of FIG. 13 as specifically configured to gather and process data for a resistance measurement;

FIGS. 16A and 16B taken together form a flowchart of the program of FIG. 13 as specifically configured to gather and process data for a precision resistance change measurement;

FIG. 17 is a flowchart of the FIG. 13 program as specifically configured to gather and process data for a DC voltage measurement;

FIGS. 18A, 18B, 18C and 18D together form a flowchart of the FIG. 13 program as specifically configured to gather and process data for an AC power measurement;

FIG. 19 is a flowchart of a program for processing of gathered calibration data;

FIG. 20 is a flowchart of a program for processing gathered AC power measurement data;

FIG. 21 is a flowchart of a program for processing gathered air temperature data;

FIG. 22 is a flowchart of a program for processing gathered fire condition data;

FIG. 23 is a flowchart of a program for processing gathered fluid flow data;

FIG. 24 is a flowchart of a program for processing gathered BTU data;

FIGS. 25A . . . 25M together form a flowchart of the OIP program illustrated in FIG. 9;

FIG. 26 illustrates a current sensor which may be used with the invention;

FIG. 27 illustrates an air flow sensing system which may be used with the invention;

FIGS. 28A and 28B illustrate a fluid flow sensing system which may be used with the invention;

FIG. 29 illustrates a BTU sensing system which may be used with the invention;

FIG. 30 is a schematic diagram of a display apparatus which may be connected to a remote station illustrated in FIGS. 1 and 2;

FIG. 31 is a flow chart of a program which may be used to operate the digital display apparatus illustrated in FIG. 30;

FIGS. 32 and 33 are flow charts of a program for calculation of a percentage of demand limit parameter which may be displayed by the display apparatus illustrated in FIG. 30;

FIG. 34 is a flow chart of a program for calculation of a cost of energy consumption parameter which may be displayed by the display apparatus illustrated in FIG. 30;

FIG. 35 is a flow chart of a program for calculation of an energy consumption in kilowatt hours parameter which may be displayed by the display apparatus illustrated in FIG. 30;

FIG. 36 is a flow chart of a program for calculation of a cost of energy rate parameter which may be displayed by the display apparatus illustrated in FIG. 30;

FIG. 37 is a flow chart of a program for calculation of an energy consumption rate parameter which may be displayed by the display apparatus illustrated in FIG. 30;

FIG. 38 is a flow chart of a program for sending data from a central station to the display apparatus illustrated in FIG. 30;

FIG. 39 is a flow chart of a portion of the program illustrated in FIG. 38;

FIG. 40 is a flow chart of another portion of the program illustrated in FIG. 38;

FIG. 41 is a flow chart of a program illustrating the time of execution of the program illustrated in FIG. 32;

FIG. 42 is a timing diagram illustrating tone data transmissions from a central station to the display apparatus of FIG. 30;

FIGS. 43 and 44 are circuit diagrams illustrating a technique for measuring sensor impedance; and,

FIGS. 45A and 45B are a flow chart of a program for calculating and processing sensor impedance data.

DETAILED DESCRIPTION OF THE INVENTION

The remote station addressing technique and associated apparatus of the invention have applicability to any type of data gathering and/or distribution system wherein a central station communicates with a plurality of remote stations. Accordingly, this aspect of the invention will be described first. After this, a more detailed description of the data gathering and/or distribution system of the invention in a specific energy management system for monitoring energy consumption and other parameters at a remote station will be provided.

The overall data gathering and/or distribution system of the invention is illustrated in FIG. 1 which shows a central computer system 23 which communicates with a plurality of modular remote stations 11 through a master controller 19, a controller interface 15, an A-D converter 21 and a plurality of section switches 17. The computer system 23 is a conventional commercially available system. One which has been found to be particularly suitable for use with the invention is known as the North Star Horizon. It includes a central processing unit (CPU) 27, a random access memory (RAM) 29 for temporarily storing programs and data, a disc controller 31, a floppy disc system 33 for permanently storing programs and data, an interface 35 for communicating with an externally connected video input output terminal 37, and a bus structure 25 to which the CPU 27, RAM 29 disc controller 31, and interface 35 are connected. The bus 25 is known in the industry as an S-100 bus having 100 communication lines respectively connected to a like number of terminal pins. Some of the communications lines are dedicated to signals for communicating among the various devices contained within the computer system 23, while others are provided for allowing the computer system 23 to communicate with external devices connected thereto.

Master controller 19 working in conjunction with controller interface 15 provides the necessary signals between computer system 23 and section switches 17 which enables the computer system (more particularly CPU 27) to address and take data from or provide data to a selected one of the information channels 10, e.g. wire pairs, located at the remote stations 11. Data is acquired from or sent to the remote stations 11 by means of the section switches 17 which are connected to the remote stations via a system bus 13 and communication channels, e.g. wire pairs, 12.

Each section switch 17 contains two identical portions which connect with respective communications channels and up to 16 separate remote stations can be attached to each communications channel. If 16 remote stations are connected to each communications channel and 16 section switches are provided, each handling two communications channels, a total of 512 (16.times.16.times.2) remote stations can be handled by the system. If each remote station in turn has 16 information channels thereat, the computer system 23 can then address any one of 8,192 information channels (256 information channels for each communications channel).

The information channels 10 may have various sensors S or operative devices D connected thereto, the outputs or inputs of which are directly connected to the computer system 23 through the section switches 17 and A/D converter 21 when the information channel 10 corresponding thereto is addressed by the computer system 23. Data coming from the information channels via the remote stations 11 is converted to digital data by analog to digital converter 21 prior to entering computer system 23 which stores the digitized data.

Addressing of the remote stations 11 and the information channels 10 thereat is accomplished by sequentialy sending tone bursts down a communications channel 12 to which a group of remote stations is connected. The tone bursts are received by each of the remote stations of the group simultaneously, but each station is only enabled by a preassigned numerical range of tone bursts (an address). Upon receipt of the sequentail tone bursts in its preassigned numerical range, a remote station sequentially connects each of its information channels 10 to the communications channel. For example, a first remote station may only respond to the first 16 tone bursts transmitted to it to sequentially connect, upon each occurrence of a tone burst, a respective information channel 10 to the communications channel. Other tone bursts outside the assigned numerical range which are received by that remote station do not cause connection of any of its information channels 10 to the communications channel. The next remote station of the group may be responsive, for example, to the next sequence of 16 tone bursts, the third remote station responsive to the next 16 tone bursts, etc.

Thus, for any given communications channel interconnecting a section switch 17 with a group of remote stations, each of the remote stations of the group can be addressed by cycling through a predetermined number of tone bursts. If 16 remote stations each containing 16 information channels are connected to each communications channel, a total of 256 tone bursts will serve to address and sequentially connect each of the information channels to the communications channel. By repeating the sequence of 256 tone bursts, the remote stations and information channels thereat can be continually addressed by computer system 23. Moreover, the sequential addressing tone bursts can be sent simultaneously over all the communications channels so that every tone burst sent will cause 32 addressed information channels to be connected to the central station over 32 communications channels. A more detailed description of the component parts of the FIG. 2 system now follows.

REMOTE STATIONS

A better understanding of the addressing of the remote stations 11 can be seen with reference to FIG. 2 which shows the remote station apparatus. Terminals LG and L1 respectively represent the connection points of the remote station to the communications channel which leads to a section switch 17. For the purpose of further discussion, it will be assumed the information channels 10 and communications channel 12 are wire pairs, but other types of communications links can also be employed. The section switch itself will be described in more detail below.

The information channels 10 comprise a plurality of terminal pairs across which various sensors S or operative devices D can be connected. For purposes of illustration, a sensor 47 and operative device 48 have been shown as being respectively connected to the second and sixth information channels of the remote station illustrated. Each of the information channels 10 can be tone burst addressed in sequence and when addressed are connected by analog switches 41 and 43 to an output line 57 which is in turn connected through resistor 59 and fuse 61 to terminal L1. The terminal LG is a ground terminal at the remote station.

Terminal L1 is also connected through fuse 61, a capacitor 79, and a resistor 81 to a tuned circuit 83 which reacts to the frequency of the tone bursts on the line L1. Each time a tone burst of the proper frequency, e.g. 100 KHz, occurs, the output of tuned circuit 83 applies a signal to the input of one shot multivibrator 87 which responds by outputting a clock pulse to the clock input of counter 89.

Counter 89 is a 1 of 16 counter which supplies data output signals corresponding to the instantaneous value counted. These output signals occur on lines 51 which are connected to analog switches 41 and 43, and control which information channel 10 is connected to output line 57. An additional data line from counter 89 is provided to the inputs of NAND gates 99 and 104. The output of NAND gate 99 is connected to the input of NAND gate 103. NAND gates 103 and 104 are respectively connected to inhibit inputs of analog switches 41 and 43 and accordingly serve as "enabling" gates controlling whether switches 41 and 43 are operative or not. When operative, switches 41 and 43 connect one of the information channels 10, as determined by the data inputs thereto from counter 89, to the output line 57.

Gates 103 and 104 will remain off as long as there is no output signal from NAND gate 101. The latter gate is connected to the output of a comparison counter 97 which receives as inputs the output of a programmable address device 90 and the carry output of counter 89. As counter 89 cycles through its 16 count positions, it generates a carry output signal each time it completes a counting cycle. Comparison counter 97 counts the carry outputs, and when the counted number of carry outputs equals the count value set by programmable address device 90, it provides an output signal to gate 101 causing gates 103 and 104 to enable analog switches 41 and 43. The programmable address device 90 determines the address of the remote station, or stated otherwise, the numerical tone burst range (number of tone bursts) to which the remote station responds. Thus, each group of 16 tone bursts appearing on line L1 will be directed to a particular remote station. By changing the programmable address in device 90 by a digital value of "one" for each successive remote station, each group of 16 tones appearing on line L1 will address a different remote station by the output of the respective comparison counter 97. In addition, each tone burst in the tone burst group will address the information channels 10 at an addressed remote station by the data output of counter 89.

Each remote station also includes a timing circuit including capacitor 91, resistor 93 and a diode 95 in parallel with resistor 93. This timing circuit responds to a tone burst appearing on line L1 for a predetermined time duration longer than the time duration of the tone bursts which are used to address the information channels. The purpose of this timing circuit is to recognize a reset tone burst placed on the communications channel by the central station and to produce a reset signal to comparison counter 97, counter 89 and one shot multivibrator 87. The central station sends this reset tone burst just prior to sending another complete addressing sequence of tone bursts, e.g. 256 tone bursts. This ensures that all remote stations will be reset prior to the occurrence of the next (first) addressing tone burst of the next tone burst sequence on the line. Since the addressing tone bursts are of much shorter duration than the reset tone burst, the timing circuit will not respond to them and thus counters 89 and 97 are free to perform their counting functions in response only to the addressing tone bursts.

Each remote station is self-powered and includes a power supply circuit 63 which consists of a pair of oppositely polled diodes 67 and 69 connected to the opposite ends of a pair of series connected capacitors 71 and 73. The opposite ends of the series connected capacitors in turn are connected across a series pair of Zener diodes 75 and 77 with the connection point between the capacitors 71 and 73 and Zener diodes 75 and 77 being connected together and to ground. A pair of terminals T1 and T2 are connected to opposite ends of the Zener diodes and provide operative power to switches 41 and 43, all of the gates, one shot multivibrator 87, counter 89, comparison counter 97 and programmable address device 90. Power supply circuit 63 derives operative power from the tone bursts which are supplied on line L1 from the central station and in this manner, a separate remote station power supply is not required.

FIG. 2 also illustrates the information channel switching portion of each remote station by a numeral 39. In some instances, for example where the outputs of two or more sensors are to be simultaneously connected to the central station over respective communications channels, a plurality of switching portions 39 at a remote station are connected in parallel. Thus, a remote station can have one or more switching portions 39 connected to the outputs of counter 89 and gates 103 and 104, as illustrated in FIG. 2. Each additional switching portion 39 would have its own information channels 10, input and output terminals corresponding to LG and L1, but all may derive their operative power from a common power supply circuit 63.

Two switching devices 39 could be used, for example, to simultaneously connect a current sensor connected to one device 39 and a voltage sensor connected to the other to the central station so that instantaneous power could be calculated (VXI).

Because of the relative simplicity of the circuit used and the self-contained power supply, the remote stations may be constructed as low cost modular units of identical construction, the only difference between units being in the address assigned thereto by the programming of address device 90.

A calibration resistor 49 is also shown connected to the first information channel 10. By periodically checking this fixed resistance value when the first information channel is connected to the central station, the central station can ensure that there has been no significant change in the condition of a communications channel. In other words, resistor 39 is used as a calibration standard to diagnose faulty line conditions.

As noted, a group of remote stations 11 may be commonly connected to a single wire pair forming a communications channel to the central station. Thus, the terminals LG and L1 for a plurality of remote stations may be connected in parallel to the communications channel which goes to a section switch 17. Moreover, a plurality of communications channels, each having a group of remote stations connected to it, may be used. To further illustrate the connection of the communications channels to the section switches, reference will be made to FIGS. 3 and 4 which show in detail the construction of each section switch 17. However, before further describing the structures of the section switch 17, as well as the remaining portions of the system, it is necessary to understand some of the bus line labeling and nomenclature which will be used.

BUS STRUCTURE

FIGS. 3 to 8 show various circuits connected to terminal areas designated as follows: ##STR1## where N is a number. These designations throughout the drawings refer to pin terminals. When appearing on the drawings for the master controller 19 (FIG. 7) and the analog to digital converter 21 (FIGS. 8A and 8B) they identify pin terminals on the S-100 bus 25. When appearing on the drawings for the controller interface 15 (FIGS. 5, 6A and 6B) and the section switches 17 (FIGS. 3 and 4) they identify terminals on system bus 13.

To further facilitate description of the application, a brief description of the pin terminals used on both the S-100 bus 25 and the system bus 13 follows:

    ______________________________________
    S-100 Bus
    Addressing and Data Signals
    CPU 27 Pin     Data Output
                              Pin    Data Input
                                             Pin
    Address
           Desig-  Lines From Desig- Line To Desig-
    Lines  nation  CPU 27     nation CPU 27  nation
    ______________________________________
    A.0.   79      D0.0.      36     DI.0.   95
    A1     80      D01        35     DI1     94
    A2     81      D02        88     DI2     41
    A3     31      D03        89     DI3     42
    A4     30      D04        38     DI4     91
    A5     29      D05        39     DI5     92
    A6     82      D06        40     DI6     93
    A7     83      D07        90     DI7     43
    ______________________________________
    Control Signals
    Control
           Pin          Control Signal
    Signal Designation  Description
    ______________________________________
     ##STR2##
            77           Timing signal generated by CPU
                        during output operation
                        indicating valid data is on
                        S-100 bus
    SINP   46           Signal applied to S-100 bus by
                        CPU during a data input
                        operation
    SOUT   45           Signal applied to S-100 bus by
                        CPU during a data output
                        operation
    PDBIN  78           Signal provided by CPU
                        indicating its reading of data
                        from S-100 bus
    PRDY   72           Signal placing CPU in wait
                        state; generated by devices
                        external to CPU 23
     ##STR3##
           73           Interrupt request line
                        requesting interrupt of CPU
    V16    10           Highest Priority interrupt
                        (master interrupt) to CPU
    V15     9           Next highest Priority interrupt
                        (sensor interrupt) to CPU
    V14     8           Lowest Priority interrupt
                        (sampling interrupt) to CPU
    CLK    24           System clock 4 MHz
    PSYNC  76           Synchroizing signal generated
                        by CPU during input/output
                        cycles
     ##STR4##
            99           System reset signal
                        synchronized to CPU clock
    ______________________________________


System Bus 13

The system bus 13 may also be a 100 pin bus, but the signals on the various pin terminals are different from those on the S-100 bus. For system bus 13, the pin designations and corresponding signals are as follows:

    ______________________________________
    Addressing and Data Signals
    Data Output
             Pin     Data Input
                               Pin    CPU 27 Pin
    Lines From
             Desig-  Lines To  Desig- Address
                                             Desig-
    CPU 27   nation  CPU 27    nation Lines  nation
    ______________________________________
    D0.0.    38      DI.0.     95     A.0.   79
    D01      35      DI1       94     A1     80
    D02      88      DI2       41     A2     81
    D03      89      DI3       42     A3     31
    D04      38      DI4       91
    D05      39      DI5       92
    D06      40      DI6       93
    D07      90      DI7       43
    ______________________________________


The system data bus 13 also includes pin terminals for the output lines of one or more analog to digital converters. These output lines, AD.0. . . . AD9, are connected to the pins of system bus 13 as follows:

    ______________________________________
    Analog to Digital Converter Outputs
                          Pin Designations
    ______________________________________
    AD.0.                 74
    AD1                   75
    AD2                   76
    AD3                   82
    AD4                   83
    AD5                   84
    AD6                   85
    AD7                   86
    AD8                   87
    AD9                   37
    ______________________________________


The 32 incoming wire pairs from the remote stations 11 may be grouped into four groups of 8 incoming lines each as follows: S.0.L.0. . . . S7L.0.; S.0.L1 . . . S7L1; S8L.0. . . . S15L.0.; and S8L1 . . . S15L1. These incoming lines are respectively assigned to the pins of bus 13 as follows:

    ______________________________________
    Incoming Lines from Remote Stations
                          Pin Designation
    ______________________________________
    S.0.L.0.               3
    S1L.0.                 5
    S2L.0.                 8
    S3L.0.                10
    S4L.0.                13
    S5L.0.                15
    S6L.0.                18
    S7L.0.                20
    S.0.L1                 4
    S1L1                   6
    S2L1                   9
    S3L1                  11
    S4L1                  14
    S5L1                  16
    S6L1                  19
    S7L1                  21
    S8L.0.                53
    S9L.0.                55
     S10L.0.              58
     S11L.0.              60
     S12L.0.              63
     S13L.0.              65
     S14L.0.              68
     S15L.0.              70
    S8L1                  54
    S9L1                  56
     S10L1                59
     S11L1                61
     S12L1                64
     S13L1                66
     S14L1                69
     S15L1                71
    ______________________________________


Bus 13 also contains varius control signal lines containing signals generated by various portions of the system as follows:

    ______________________________________
    Control Signals
                Pin Designation
                            Descrition of Signal
    ______________________________________
    SS          23          CPU signal to clock
                            automatic digital gain
                            control through
                            various gain values
    V Test      24          Supplies a test
                            voltage to various
                            portions of the system
                            for testing purposes
    15 Khz      25          A clocking signal
                            used by portions of
                            the system.
    SSPCL       26          A reset signal
                            used to reset the
                            automatic digital gain
                            control system
    IFI0        28          Decoded address from
                            the CPU used to
                            designate a controller
                            interface input/output
                            operation
     ##STR5##   30          Control signal sent
                            by CPU to control
                            on/off operation of
                            A to D converter on
                            section switch
    LINESEL     32          Decoded address from
                            CPU which conditions
                            section switches for
                            line assignment
    CFGSCL      44          Control signal sent by
                            CPU to condition the
                            section switches to
                            configure them to
                            operate on a split or
                            nonsplit bus
                            configuration
     ##STR6##   45          Decoded address from
                            CPU which conditions
                            secton switches for
                            input/output operation
     ##STR7##   46          Control signal sent
                            by CPU to activate
                            offset voltage compen-
                            sation in multiplying
                            circuit of section
     ##STR8##   47          Control signal sent by
                            CPU to enable
                            automatc digital gain
                            control circuit
    500 Khz     48          Another; clocking sig-
                            nal used by Portions
                            of the system
    Tone Signal 49          A gated tone signal
                            used for addressing
                            and control of remote
                            stations
     ##STR9##   77          Same as PWR on
                            S-100 bus
    PDBIN       78          Same PDBIN on
                            S100 bus
     ##STR10##  Control signal sent
                            by CPU to condition
                            section switches
                            for AC measurements
    ______________________________________


SECTION SWITCH

Each section switch includes two identical switching and signal processing portions shown in FIG. 4, which are respectively connected to different communications channels (input lines). The two identical section switch portions in turn share a common addressing and control signal generating portion, illustrated in FIG. 3.

Since FIG. 4 represents two identical section switch circuits, the unparenthesized line labels (numbers) are for one of the two circuits, and those in parenthesis are for the other circuit.

Each section switch portion (FIG. 4) is connected to 16 of the 32 incoming lines with the other identical portion being connected to the remaining 16 incoming lines. Since each section switch portion (FIG. 4) only services one of the 16 lines connected thereto, a pair of analog selection switches 143 and 145 is used to connect one of the 16 incoming lines to the remainder of the section switch circuit. The selecting data inputs to analog switches 143 and 145 are taken from lines 737, 739, 741 and 743 which are taken from the output of a latch 131 in FIG. 3. The data inputs to latch 131 originate from CPU 27 data output lines and are applied to the S-100 bus 25 and are also connected to system bus 13 pins 90, 40, 39, 38, 89, 88, 35 and 36 by the controller interface 15 as described in more detail below.

Half of the output data lines (737, 739, 741, 743) of latch 131 are coupled in parallel to analog switches 143 and 145 of one section switch portion. The other data output lines 729, 731, 733 and 735 are applied to the analog switches of the other section switch portion. Line 737 which is coupled to the enable input of switch 143 is also coupled through an inverter 147 to the enable input of switch 145. Line 737 serves to select one of the two switches 143 and 145 for operation, while the remaining three data input lines 739, 741 and 743 serve to connect one of the input lines to respective switches 143 and 145 to respective output lines 151 and 153.

During system initialization, CPU 27 assigns a section switch portion to one of the incoming lines connected thereto by addressing and supplying data to latch 131. Once initialization is completed, the section switch remains connected to the incoming line to which it was assigned.

Inverter 147 can be disabled by a control signal CFGSEL applied to line 751, in a manner described further below, so that the signal applied to line 737 will enable both analog switches 143 and 145 at the same time. In certain applications, it is desirable that each section switch portion illustrated in FIG. 4 be capable of communicating with two lines simultaneously. For example, if one incoming line was coupled to a voltage sensor and the other to a current sensor at a remote station, a section switch portion could simultaneously process current and voltage information to calculate the power being monitored at a remote station. This so-called "split-bus" configuration, is set by the CPU which addresses a latch 371 in the controller interface supplying thereto a signal CFGSEL which is applied to the section switches by a pin 44 of system bus 13. Each section switch receives the signal CFGSEL from pin 44 (FIG. 3) and applies it to line 751 to control switch 149. When it is desired to have a "split-bus" configuration, the CFGSEL signal instructs switch 149 to open while for a normal bus configuration the switch 149 remains closed. Signal CFGSEL also controls operation of inverter of 147 so that when a split-bus configuration is desired both switches 143 and 145 are simultaneously enabled to pass one of the incoming lines respectively connected thereto to the respective output lines 151 and 153.

The output line 151 of analog switch 143 is connected to an input signal path 150 which is connected to one of the switch terminals of analog switch 175. The output line 153 of analog switch 145 is connected to input signal line 155 directly and through switch 241 to input signal line 243.

When a sensor which is connected to a section switch via an information channel and an incoming line outputs a DC voltage which is to be measured by the system, it is applied to line 155 which is connected as one of the input terminals to switch 199. When switch 199 is in the position illustrated in FIG. 4 this DC voltage from the sensor is passed through buffer amplifier 197 to an output line 781 (J.0.) which is one of thirty two input lines to the A/D converter 21 illustrated in FIG. 1. Switch 199 is controlled by a signal ACMEN signal applied to line 753 which controls whether an AC measurement or DC measurement is to be performed. The signal ACMEN is applied to the section switches via a system bus pin 97 which receives it from a latch 373 in the controller interface which is addressed and sent data by CPU 27 in a manner more fully described below. When the signal ACMEN has an opposite polarity than that which places switch 199 in a position illustrated in FIG. 4, the output line 195 of this switch is connected to input 191 which in turn is connected to the output of an AC power measurement circuit which is also more fully described below.

Since the output from various sensors connected to the information channels of the remote stations may differ widely in terms of the type of output generated, i.e. a changing resistance of a changing voltage, as well as in the level of the output signal, the section switches incorporate a voltage offset compensation circuit for adding to the sensor output a predetermined DC voltage level which serves to normalize the sensor output voltages to be within a predetermined voltage range, or to convert a resistance sensor output to a voltage signal. The voltage offset compensation is provided by an analog switch 161 and jumper selectable reference voltage bus 159. Analog switch 161 contains a plurality of inputs 163, 165, 167, 169, 171 and 173 which can be jumper connected through respective resistors to one of four reference voltage lines provided at bus 159. For example, the four lines illustrated may respectively receive voltages of 0, 2.5, 5 and 10 volts.

Two additional inputs to analog switch 161 are from line 761 which receives a tone burst signal from the controller interface 15 and from pin 24 which receives a test voltage as described below. Thus, the output of analog switch 161 can be any one of the reference voltages to which lines 163 . . . 173 are connected, the test voltage, or the tone on line 761. The tone burst is used for addressing the information channels at the remote stations, and can also be used to control an operative device connected to an addressed information channel. The addressing and control tone bursts are at different frequencies and the manner of generating different frequency tones will be described below with reference to the controller interface 15.

The output 152 of analog switch 161 is selectively connected to one of the inputs by means of signals applied to control lines 719, 721, 723 and 727 (725 for the other section switch portion). The latter signal is an enable signal while the first three signals cause selection of one of the input lines to switch 161 to be connected to output line 152. The signals on lines 719, 721, 723 and 727 originate from latch 119 of the section switches (FIG. 3) which is coupled to the data output lines of CPU 27 through the system bus 13 and the S-100 bus 25. CPU 27 addresses latch 119 and sends to it data enabling switch 161 and instructing it to connect a predetermined one of its inputs to its output. Assuming for the moment that the output of switch 161 is one of the reference voltages contained on the input lines, this reference voltage is supplied to input path 155 (through an associated resistor) which is receiving the output (voltage or resistance) from a sensor. If the sensor output is a changing resistance, the reference voltage will be divided between the resistance of the sensor and resistance associated with the selected reference voltage to supply a D.C. voltage on line 155 which varies with a change in sensor resistance. The voltage on line 155 is supplied to line 193 of switch 199 and through amplifier 197 to line 781 (J.0.) which, as noted, is applied as one of thirty-two inputs to the A/D converter 21 (FIG. 1).

A principle feature of the system of the invention is its ability to monitor power consumed in an electrical path located at a remote station. For this purpose, a current sensing transducer (sensor) is coupled to an information channel at a remote station and its output is multiplied by a signal representing a voltage on the monitored electrical path to produce a signal representing power consumed. To perform the power calculation, each section switch portion illustrated in FIG. 4 includes AC measurement structures. Included are a power calculation circuit identified by dotted block 183 in FIG. 4 which performs actual power calculations and an automatic digital gain control circuit identified by dotted block 245 in FIG. 4, which is used to ensure that the calculated power value falls within a predetermined digitizing range of A/D converter 21 (FIG. 1).

For AC measurements, switch 199 is switched by the signal ACMEN from CPU 27 to a position where output line 195 is connected to input line 191. Input line 191 is connected to the output of amplifier 189 which receives at its input the output of amplifier 187, which in turn receives at its input the output of an analog-to-digital multiplier 185. Multiplier 185 and amplifiers 187 and 189 form a so-called "four quadrant multiplier". Multiplier 185 calculates power consumption by multiplying a digital representation of a voltage by an analog representation of current in a monitored electrical path. The current signal originates from a current sensor having a voltage output which changes with sensed current and is applied to the input terminal 154 of switch 241, the output 243 of which is connected to an amplifier 217. The output of amplifier 217 is connected to the input of a programmable voltage divider 215 having an output connected to the input of an amplifier 213. The output of amplifier 213 is connected to the input of an amplifier 211, the output of which passes to amplifier 209 through a capacitor 205. The output of amplifier 209, which is a voltage representative of sensed current, is applied to an analog input of analog/digital multiplier 185. A digitized voltage input is also applied, via a plurality of digital input lines, to multiplier 185.

The digital voltage input to multiplier 185 is received from a tracking analog to digital converter 181 which receives as an input signal the output of an amplifier 179 which receives on its input line 177 a voltage which represents the voltage on the electrical path at the remote station which is being monitored. This voltage can be obtained from a number of sources and for this reason an analog switch 175 is provided for selectively connecting one of four inputs thereto to its output which is connected to input line 177 of amplifier 179. The input voltage to converter 181 can be taken from pins 33 or 34 of the system bus 13 or from line 150 which is connected to output 151 of switch 143. As described earlier, the computer can configure switches 143 and 145 so that they are both simultaneously enabled allowing each of output lines 151 and 153 to be connected to a respective section switch input line. In this "split bus" configuration switch 149 is also activated to uncouple the outputs of lines 151 and 153 so that the output on line 151 is connected as an input to switch 175. This allows a remote station voltage sensor connected to one of the section switch input lines to be used as the voltage input to the tracking analog to digital converter 181, while one of the input lines to switch 145 supplies the output of a current sensor at the remote station.

As an alternative manner for generating a voltage representative of that at the electrical path being monitored, the electrical service entrance to a building can be tapped for a voltage which represents the voltage at the monitored electrical path. System bus 13 pins 33 and 34 which are inputs to switch 175 provide a voltage which is taken from the service entrance. A more detailed description of how these voltages are applied to pins 33 and 34 follows in the detailed description of the controller interface.

Switch 175 connects one of the inputs thereto to line 177 under control of signals MODESEL and VSSEL applied to lines 715 (713 for the other half of the section switch) and 717. These signals originate at latch 119 (FIG. 3) and are supplied thereto by CPU 27 which addresses the latch. The CPU thus determines which of the voltage inputs to switch 175 is used by the tracking A to D converter 181. Switch 175 also has an additional voltage input which is received from pin 24 of the system bus 13. This is a test voltage pin which can also be selected under control of the CPU by the MODESEL and VSSEL signals for testing purposes.

Before reaching the analog input of multiplier 185, the sensor current output passes through an automatic digital gain control circuit 245. This circuit ensures that the multiplied output of the four quadrant multiplier remains within the digitizing range of analog to digital converter 21. It automatically decreases the level of signal applied as an analog input to multiplier 185 until the output of multiplier 185 is within a predetermined signal range set by a window comparator.

Gain control circuit 245 receives as an input on line 231 the output of the four quandrant multiplier and supplies this output to a window comparison circuit 225 consisting of a pair of comparison amplifiers 233 and 235. Window comparator 225 determines if the output of the multiplier is within a predetermined range. It if is not, an output signal is applied through inverter 229 to gate 227 as an enable signal allowing gate 227 to pass 15 KHz clocking signal on line 749 to the clock terminal of counter 221. These clocking signals originate in the controller interface. As a result, the counter counts clock pulses occurring at a 15 KHz rate whenever the signal at the output of the four quadrant multiplier exceeds a predetermined signal level range. Counter 221 also receives as an alternate clock input a signal SS on line 755 which is received from pin 23 of system bus 13 (FIG. 3). This signal originates from a latch 371 provided in the controller interface which is addressed and sent data by CPU 27 as described further below.

A reset terminal is also provided on counter 221 which is connected to line 759 which receives the control signal SSPCL from system bus 13 pin 26. This signal originates at a one shot multivibrator 383 (FIG. 6A) provided in the controller interface. Reset signal SSPCL is generated by the one-shot multivibrator at the leading edge of a control signal SSP supplied to a latch 373 in the controller interface by CPU 27. Signal SSP is also supplied as an enabling signal to gate 227.

The digital output of counter 221 is sent to a decoder 219 which supplies a digital representation of the counter 221 contents to a programmable voltage divider 215. Programmable voltage divider 215 and amplifier 213 together determine the gain applied by the automatic gain control circuit 245 to an applied intput signal. The multiplying factors of amplifiers 213 and 211 are such that the maximum gain of automatic gain control circuit 245 is 32. However, this gain factor is reduced by the programmable voltage divider 215 so that the output signal from amplifier 211 may have a gain of 32 or gains of 16, 8, 4, 2, 1, 0.5, or 0.25 as determined by the output of decoder 219. Programmable voltage divider 215 can be formed by a multiplying analog to digital converter similar to that used as multiplier 185.

The SSPCL reset signal applied to counter 221 on line 759 is received from one shot multivibrator 383 in the controller interface as described earlier. The one shot multivibrator 383 supplies a pulse to reset the automatic gain control circuit 245 to maximum gain when CPU 27 instructs the setting of the automatic gain control circuit 245 via the SSP signal applied to line 757, and to one shot multivibrator 383.

As noted, the automatic digital gain control circuit 245 is rendered operative by the SSP signal applied to line 757 which enables gate 227 and thus counter 221 to begin counting clock pulses applied to line 749. Whenever window comparator 225 detects a voltage outside a suitable range of the analog to digital converter 21, gate 227 is enabled to pass the clock pulses to the clock input of counter 221. Accordingly, counter 221 steps through its counting states to progressively decrease the gain factor applied to the signal on line 243 until window comparator 225 provides an output signal indicating that the output of the four quadrant multiplier is within a suitable conversion range. When this occurs, the output of the window comparator passes through inverter 229 and disables gate 227. This stops the supply of clocking signals to counter 221 which remains in its last counting state which decoder 219 applies to the programmable voltage divider 215 leaving it in a particular voltage dividing state.

As counter 221 cycles through its counting states, decoder 219 may eventually instruct programmable voltage divider 215 to divide by its highest dividing value. This is detected by inverter 223 which operates to inhibit gate 227 from providing any further clock pulses to counter 221. Thus, when the programmable voltage divider is cycled through to its highest dividing value, counter 221 is inhibited so that no further changes occur and the programmable voltage divider remains set in its highest dividing (lowest gain) position.

An alternate clock input CLK2 also provided on counter 221 which is connected to line 755 which receives the control signal SS from system bus 13 pin 23 as described previously. This signal, composed of a series of pulses, is sent by the latch 371 under the control of CPU 27 to set the counter 221 to a previously determined state which sets the automatic digital gain control circuit 245 to a desired gain setting rather than allowing the automatic setting of the gain as described previously. This would normally only be done for test purposes.

CPU 27 receives the output data value from counter 221 via lines 707, 709 and 711 (701, 703 and 705 for the other half of the section switch). This data is furnished through buffer 133 (FIG. 3) to the system data bus 13 which in turn furnishes it to the S-100 data bus as inputs to the CPU 27. In this manner, the CPU 27 receives data representing the amount of attenuation applied to the output signal of amplifier 217. This attenuation value is used by the CPU 27 when it determines actual power consumed at a remote location, since the digitized value of current multiplied by voltage provided by the four quadrant multiplier will have been reduced by a factor corresponding to the output of counter 221.

An undesirable by-product of the current sensor signal path through the automatic gain control circuit 245 and into multiplying A/D converter 185 is a DC offset voltage produced by the various amplifiers in the chain. To compensate for these offset voltages, capacitors 205 and 203 are respectively provided in the outputs of amplifier 211 and 189. Prior to the occurrence of an AC power measurement, these capacitors are allowed to charge to the inherent offset voltages by connecting the output side of each to ground while at the same time grounding the AC path input 243 through switch 241 using control input 747 more fully described below. The outputs of capacitors 205 and 203 are grounded by respective switches 207 and 201 which are activated by CPU 27 prior to an AC measurement being taken. After capacitors 205 and 203 are charged to the DC offset voltages, their connection to ground is removed by CPU 27 opening switches 207 and 201 so that the accumulated charge on capacitors 205 and 203 acts inversely to cancel the offset voltage. Operation of switches 207 and 201 is controlled by the CPU 27 which sends a signal ACGRD to the section switches from system bus 13 pin 46 (FIG. 3). This signal is furnished to latch 373 (FIG. 6A) in the controller interface by CPU 27 just prior to an AC measurement operation. This signal closes switches 207 and 201 for a period sufficient to charge capacitors 205 and 203 to the offset voltage, after which it is removed by CPU 27. A delayed version of ACGRD, i.e. DELACGRD, is generated by a delay circuit 137 provided in the section switches (FIG. 3) on line 747 which is supplied to switch 241. DELACGRD controls switch 241 to connect amplifier 217 input signal line 243 to line 154 a predetermined period of time after capacitors 205 and 203 are released from ground by ACGRD. Accordingly, a sensor output signal is applied to the input of the automatic gain control circuit 245 only after capacitors 205 and 203 have been charged to the DC offset voltages.

FIG. 4 also shows that the input to the multiplying A to D converter 185 may come from system bus 13 pins 30, 37, 87, 86, 85, 84, 83, 82, 76, 75 and 74. These pins are connected to another tracking analog to digital converter provided in the controller interface 15 which can be used if a tracking A to D converter 181 is not provided in the section switches. The tracking A to D converter 181, when provided in the section switches in the manner illustrated in FIG. 4, is enabled by a signal applied to pin 30 of the system bus 13 which receives a signal SSADOFF sent by CPU 27 to latch 371 in the controller interface.

FIG. 3 illustrates the common section switch portion which supplies control signals to the two section switch circuits illustrated in FIG. 4.

The bottom of FIG. 3 shows various signal lines which are applied to FIG. 4 to control the configuration of the section switch portions. Line 761 contains a gated tone which is supplied to switch 161 (FIG. 4). The tone originates in the controller interface which contains circuitry controlled by CPU 27 for setting both the frequency and on/off period of the tone. The tone is supplied to pin 49 of the system bus. The tone is taken from pin 49 and amplified by amplifier 141. The remaining control signals on lines 745, 747, 749, 751, 753, 755, 757 and 759 and their origination have been described above and will not be repeated.

As noted, each section switch is addressed by the CPU 27 which supplies data thereto and takes data therefrom. Data is received from the section switches through buffer 133 (FIG. 3) over lines 701, 703, 705, 707, 709, and 711 which represent the contents of the counters 221 contained in the two section switch portions (FIG. 4). The output of buffer 133 is supplied to pins 43, 93, 92, 91, 42, 41, 94, and 95 of the system bus 13. From there they are applied through buffer 325 of the controller interface (FIG. 5), buffer 627 of the master controller (FIG. 7) and the S-100 bus to the data input lines to CPU 27. Buffer 133 is enabled by NAND gate 121 which receives a section switch board select input from address decoder 113. Address decoder 113 is connected through buffers 111 to the address lines of pins 31, 81, 80 and 79 of the system bus 13 which are in turn connected to the address lines of the S-100 bus through lines 821 of the controller interface (FIG. 6A) and master controller (FIG. 7). Address decoder 113 receives addressing signals from CPU 27 and, when a particular section switch is addressed, supplies a board select signal to gate 121. Gate 121 also receives as enabling inputs thereto the output of buffer 127 which is connected to system bus 13 pin 45. The controller interface supplies a signal SSIO to pin 45 (FIG. 5) which is received from inverter 776 of the master controller (FIG. 7). The signal SSIO appears whenever any one of the 16 section switch latches 119 or buffers 133 is being addressed by CPU 27 and is used to condition the section switches for an input/output operation. Gate 121 also receives as an enabling input thereto a signal PDBIN on pin 78 of system bus 13. This signal is supplied to pin 78 by the controller interface which receives its inverted form from the master controller (FIG. 7), which in turn receives the signal PDBIN from pin 78 of the S-100 bus. The PDBIN signal is supplied by CPU 27 when it is reading data from the S-100 data input terminals. Thus, gate 121 is energized by a signal (BOARD SELECT) indicating it is being addressed, a signal requesting a section switch input/output operation (SSIO), and a signal controlling the inputting of data to CPU 27 (PDBIN).When all three signals are present, buffer 133 is enabled to pass the signals on lines 701, 703, 705, 707, 709 and 711 to their respective system bus 13 pin terminals.

Latches 119 and 131 which respectively supply various control signals to the section switch portion illustrated in FIG. 4 are respectively enabled by the outputs of inverters 117 and 125. Inverter 117 receives the output of NAND gate 115. NAND gate 115 in turn receives enabling signals from the board select line from address decoder 113, the SSIO signal from pin 45 and a signal PWR from inverter 129 which receives the signal PWR from pin 77. The signal PWR at pin 77 is received from the controller interface, which in turn receives it from the S-100 bus pin 77 through the master controller. The PWR signal is a timing signal generated by CPU 27 indicating that data is on the S-100 bus for reception by a remote device.

NAND gate 115 responds to the presence of the three input signals to enable latch 119 to receive and latch data from the CPU 27.

NAND gate 123 enables latch 131 which also receives data from the CPU 27, supplying this to the section switch portion illustrated in FIG. 4. NAND gate 123 receives the board select output from address decoder 113, the PWR signal from inverter 129 and a line select (LINESEL) signal from pin 32 of the system bus 13. The LINESEL signal is applied to pin 32 by the controller interface (FIG. 5) which receives its inverted form from the master controller (FIG. 7) as a decoded address signal for 16 decoded addresses. Each of the 16 addresses corresponds to one of the 16 section switches. Each section switch NAND gate 123 receives enabling inputs from the line select signal PWR and Board Select signals such that one of the section switches will have the output of its NAND gate 123 enabled. This signal via inverter 125 enables latch 131 on the selected section switch 17, thus allowing the line assignment for that section switch to be transferred from system bus lines 90, 40, 39, 89, 88, 35 and 36 to latch 131. Thus, NAND gate 123 enables latch 131 to receive line selecting data from the CPU 27 which operates switches 143 and 145 (FIG. 4).

CONTROLLER INTERFACE

Referring to FIGS. 5 and 6, the controller interface 15 (FIG. 1) will now be described. As evident from the discussion of the section switches 17 above, the controller interface supplies to system bus 13 many of the control signals which the section switches use to configure them for a particular function, either receiving sensor outputs or supplying tone control signals to an addressed information channel 10 which is temporarily connected through a comunications channel to a respective section switch portion (FIG. 4). The controller interface also generates the addressing tones which are sent to the remote stations to connect an information channel to a respective communications channel.

Referring first to FIG. 6, the controller interface includes an address decoder 359 which is connected to address line A.0., A1, A2 and A3. These address lines, as well as signal line PWR collectively identified by numeral 821 in FIG. 6, are output lines from the master controller 19 as is signal line 825 containing IFIO. The address decoder 359, when enabled by the output of NAND gate 367, decodes four different addresses for respective latches 369, 371, 373 and 375. NAND gate 367 is enabled by the presence of the signal PWR which is applied to one input thereof via buffer 361 and NAND gate 365 and by the signal IFIO which is applied through buffer 363 to its other input. These signals which come from the master controller (FIG. 7), are supplied by CPU 27 whenever the controller interface is to perform an input/output operation.

Latch 369 receives as data inputs signals from data lines 823 via buffer 387 which originate in the master controller (FIG. 7). These in turn are connected to respective data output lines of the S-100 bus to which the CPU 27 sends output data. Accordingly, latch 369 latches data from the CPU 27 whenever addressed, as determined by address decoder 359. Latch 369 provides output data F.0. . . . F4, collectively indicated as lines 817, which are used to program a desired tone frequency into a programmable tone generator 313 (FIG. 5).

Latch 371 is likewise addressed by the CPU 27 sending an address corresponding thereto which is decoded by address decoder 359 and which supplies an enable signal causing latch 371 to receive data provided by CPU 27 on its data output lines. The output data of latch 371 includes the signal SSADOFF which turns the analog to digital converters 181 on the section switches on or off. This signal is applied to pin 30 of system bus 13 which is in turn connected to the section switches as described earlier. Latch 371 also applies signals SS and CFGSEL to respective pins 23 and 44 of the system bus 13 which are also used by the section switches in the manner described earlier.

Another output signal CIFADOFF appears on an output data line of latch 371. This signal is used to enable the buffer amplifiers collectively identified as 379 in FIG. 6 to gate the output of a tracking analog to digital converter 377 to the pins 37, 87, 86, 85, 84, 83, 82, 76, 75 and 74 of the system bus 13. As described earlier, tracking analog to digital converter 377 is used to provide the digital representation of a voltage at a monitored electrical path if a like tracking analog to digital converter 181 is not provided on the section switch portions (FIG. 4). When converter 377 is used, the digital data input to the A/D multiplier 185 is taken from pins 37, 87, 86, 85, 84, 83, 82, 76 75 and 74, as described earlier with reference to FIG. 4.

Another output signal from latch 371 is ADTEST which is used to control two additional gated buffer amplifiers in buffer 379 and the output buffers in latch 375 to allow signals AD.0. through AD9, respectively taken from other output lines AD.0., AD1 of latch 371 and all the output lines AD2 . . . AD9 of latch 375, to pass to the system bus 13 AD.0. through AD9 lines (pins 74, 75, 76, 82, 83, 84, 85, 86, 87 and 37). When ADTEST is present, signals AD.0. through AD9, which form a test work, are applied to respective pins of the system bus 13 and these signals are used by the A/D multiplier 185 of the section switches to generate a corresponding output which is digitized by A/D converter 21 and checked by the CPU 27 for accuracy.

Latch 375 is also enabled by a signal provided as an output of address decoder 359. When it is addressed by CPU 27, data applied on data lines 823 is stored by latch 375. When the signal ADTEST is enabled by latch 371 the contents of latch 375 along with bits AD.0. and AD1 are passed to the respective pins 37, 87, 86, 85, 84, 83, 82, 76, 75 and 74 of the system bus 13, as described in the preceding paragraph. The purpose of latch 375 is to store the eight most significant bits A2 through A9 of the test word to be applied by ADTEST to the input of the A/D multiplier 185 to test its operation and accurracy.

Latch 373 is also addressed by an output of address decoder 359. When addressed by CPU 27, it latches data on lines signals ACMEN, ACGRD and SSP which are respectively supplied to pins 97, 46, and 47 of the system bus 13. These signals are used by the section switches in the manner described earlier. Latch 373 also supplies output signals PH.0. and PH1 which are applied to 1 of 8 analog switch 337 (FIG. 5), the operation of which is described below.

Latch 373 also applies on respective output lines the signals TV.0., TV1 and TV2 which are applied in common to the data selection inputs of 1 of 8 analog switches 347 and 349 (FIG. 6B). These analog switches serve to provide a selected test voltage of a selected polarity to pin 24 (FIG. 6A) which is connected to one input of 1 of 4 analog switch 175 and one input of analog switch 161 of each of the section switches (FIG. 4) for testing and calibration purposes.

A precision reference voltage generator 351 (FIG. 6B) is provided which supplies output voltages V7, V8 and V9 to six of the eight input lines to switch 347. The other two input lines to switch 347 are respectively connected to a 60 hz line voltage input on line 813 and ground. The output line of switch 347 is connected to amplifier 355, the output of which is connected in common to four of the input lines of switch 349. The output of amplifier 355 also passed through inverting amplifier 357 and the inverted signal is connected to the 4 remaining input lines of switch 349. A selected one of the switches of analog switches 347 and 349 is closed in response to the data selection signals TV.0., TV1 and TV2 applied thereto, to provide at the output of switch 349 a precision voltage (one of V7, V8, V9, -V7, -V8, -V9 or a 60 hz reference signal, or a ground signal), the signal level and polarity of which is determined by data signals TV.0., TV1 and TV2. An additional reference voltage is taken directly from the reference voltage generator 351 by amplifier 353. This is applied to the tracking analog to digital converter 377 and is used as a reference level by the converter in performing its converting operation. The input voltage which is digitized by the tracking A/D converter 377 is applied on an input line 804 thereto and this voltage is received from the output of a buffer amplifier 333 (FIG. 5) of the controller interface.

The output of analog switch 349 (FIG. 6B) is applied to buffer amplifier 381 (FIG. 6A) and from there to pin 24 of the system bus 13. The voltage on pin 24 is used as an input to analog switch 175 of the section switches (FIG. 4) which may be used as an input to tracking analog to digital converter 181 for testing purposes.

The precision voltage at the output of buffer amplifier 381 is also applied to line 824 which is an input line to analog switch 337 (FIG. 5) which will be described below.

The SSP output of latch 373 (FIG. 6A) is also applied to a one shot multivibrator 383 which produces a pulse signal of a predetermined duration which appears at the output of inverter 385 as the signal SSPCL. This signal is applied to pin 26 of system bus 13 which is applied to line 759 of the section switch to reset counter 221. FIG. 6A also illustrates the coupling of data lines 823 from the master controller through buffer 387 to the pins 90, 40, 39, 38, 89, 88, 35 and 36 of the system bus 13. This signal path serves to couple the CPU data output lines from the S-100 bus to the CPU data output pins of the system bus 13.

The controller interface also includes circuitry for deriving a voltage signal representative of the voltage in a monitored electrical path at a remote station from the electrical service entrance of a building. Signal lines 801 collectively represent signal lines connected to two three-phase electrical service inputs to a building. These signal lines are coupled to the service entrance by transformers (not shown) which step the high voltage entering the building down to a low voltage level. The lines A1-N, B1-N, and C1-N represent three wires connected to the neutral wire of one of the two three-phase power distribution lines, while the signal lines A1-.0., B1-.0., and C1-.0. respectively represent the three-phases of the first power line. The second set of power distribution lines are designated as A2-N, B2-N, and C2-N for three wires connected to the neutral wire and A2-.0., B2-.0. and C2-.0. for the three phases of the second power line. The power lines, collectively illustrated as 801, are connected to a voltage dividing network 339 and the lines A1-.0., B1-.0., C1-.0., A2-.0., B2-.0., and C2-.0. are respectively coupled to different inputs of analog selection switch 337. Another input to selection switch 337 is the test voltage input on line 824 which is taken from the output of buffer amplifier 381 (FIG. 6A).

Analog switch 337 contains two switching sections operating in parallel which are responsive to data signals applied to lines 807 and 809 to selectively connect one applied input signal to an associated buffer amplifier (333 or 335) respectively connected to the outputs of the two sections of switch 337. The data applied to lines 807 and 809 are the signals PH.0. and PH1 which appear on the output of latch 373. By addressing latch 373 and applying the appropriate signals PH.0. and PH1 thereto CPU 27 configures one half of switch 337 to pass one of the signals on input lines 824, A1-.0., B1-.0., or C1-.0. to the input of buffer amplifier 333. The output of buffer amplifier 333 is applied to pin 33 of system bus 13 and to line 804 which is applied as an input to tracking A to D converter 377 (FIG. 6A). Likewise, in response to PH.0. and PH1 the other half of switch 337 couples one of the outputs from lines A1-N, A2-.0., B2-.0., or C2-.0. to the input of buffer amplifier 335, the output of which is connected to pin 34 of the system bus 13. The voltages of pins 33 and 34 appear as inputs to analog switch 175 of the section switches (FIG. 4) as described earlier. The voltage applied by buffer amplifiers 333 and 335 to pins 33 and 34 respectively can be used by the tracking analog to digital converter 337 in the controller interface (333 only) or by the tracking analog to digital converters 181 in the section switches (333 or 335) to provide a digital signal representative of the voltage on a monitored electrical path which can be used as the inputs to multiplier 185 for calculating power consumption.

FIG. 5 also illustrates an oscillator 301, the output of which is connected to the inputs of frequency dividers 303 and 305. Frequency divider 303 provides an output signal of, e.g. 500 KHz, to pin 48 of the system bus 13 to which the clocking input of the tracking A/D converters 181 of the section switches are connected (FIG. 4). The 500 KHz output of frequency divider 303 is also applied to signal line 822 which is used as a clocking signal for tracking analog to digital converter 377 (FIG. 6A). Frequency divider 305 provides an output signal of, e.g. 15 KHz, to pin 25 of the system bus. The 15 KHz output signal of frequency divider 305 is used as a clocking input to a counter 317. When counter 317 is enabled by a signal applied to the enable input thereof, it continually counts and the counted output appears on output lines 805 as an input to one of eight analog switch 319. As counter 317 continues to count, individual switches of analog switch 319, which have respective inputs connected to the lines A1-.0., B1-.0., C1-.0., A2-.0. , B2-.0. and C2-.0., will be successively closed. The output line 321 from switch 319 is applied via diode 345 to the input of a comparator 315 consisting of a comparison amplifier 343. Comparison amplifier 343 provides an output whenever an input voltage is applied thereto which exceeds a predetermined reference voltage. The purpose of switch 319, counter 317, and comparator 315 is to provide an automatic adaptive control loop which will continue to step switch 319 until a voltage is found on one of the power lines A1-.0., B1-.0., C1-.0., A2-.0., B2-.0. or C2-.0.. When a voltage is found, it is sensed by comparison amplifier 343 which changes state and removes the enable input on counter 317, stopping the counter from counting further clock pulses received from frequency divider 305. This causes analog switch 319 to remain in its last state effectively locking the switch closed on one of the power lines which has a voltage thereon. The output line 321 from analog switch 319 is applied as an input signal to a phase lock loop (PLL) frequency multiplier 307, the output of which (f.sub.out) is thirty-two (32) times the input frequency (f.sub. in). The output of multiplier 307 appears on line 310 which runs to the master controller (FIG. 7). This signal is used as a sampling interrrupt signal VI4 in a manner more fully described below.

The output of frequency divider 305 is also applied to pin 25 of system bus 13 which connects to NAND gate 227 of the section switch portions (FIGS. 3, 4) as described previously.

The controller interface also includes a programmable frequency divider 313 (FIG. 5) which receives as an input an output of oscillator 301. The frequency of oscillator 301 is divided by a value programmed into the frequency divider 313 on data lines 817. These data lines receive data from latch 369 (FIG. 6A) which is addressed by the CPU 27 to apply data to the latch representative of a desired tone frequency which is to be sent from the section switches to the remote station lines connected thereto. One tone frequency, e.g. 100 Khz, is used for addressing the information channels 10 at the remote stations, while other tone frequencies can be used to control an operative device connected to an addressed information channel 10 at a remote station. The output of programmable frequency divider 313 is applied to an active filter 311, the output of which is coupled to a buffer amplifier 309, the output of which is connected to pin 49. As discussed earlier, the section switches are connected to pin 49 (FIG. 3) via amplifier 141 to supply a tone on input line 761 of one of eight analog switch 161, which when appropriately configured by CPU 27, supplies the tone to a remote station communications channel which is connected to a respective section switch.

FIG. 5 also illustrates a set of buffer amplifiers, 325, which are provided in the controller interface to couple data on pins 43, 93, 92, 91, 42, 41, 94 and 95 of the system bus 13 to data lines 833 which run to the master controller (FIG. 7) and from there to the CPU 27 data input pins of the S-100 bus.

FIG. 5 also illustrates lines 827, 829 and 831 which respectively receive the signals LINESEL, PDBIN and SSIO from the master controller (FIG. 7). These signals are coupled through respective buffer amplifiers 327, 329 and 331 to pins 32, 78 and 45 of the system bus 13 and are received and used by the section switches as described earlier with reference to FIG. 3.

A line 811, also originating in the master controller, supplies a tone enable signal (TONEN) which is inverted by inverter 323 and applied as an ENABLE input to programmable frequency divider 313. Accordingly, the frequency emitted by programmable frequency divider 313 is controlled by data on the input lines 817 and the on/off state of the programmable divider is controlled by the TONEN signal on line 811 from the master controller.

MASTER CONTROLLER

The system master controller 19 (FIG. 1) is illustrated in greater detail in FIG. 7. One of the principal functions of the master controller 19 is to provide the CPU 27 with three separate interrupt signals which are used by CPU 27 to execute various interrupt programs for acquiring and processing data from remote station sensors.

The master controller includes an oscillator 675 having an output signal which is connected to the input of a frequency divider 677. The output of frequency divider 677 is connected to a frequency divider 683 the output of which provides a master interrupt timing signal MT0 on line 784. The output of frequency divider 677 is also coupled to the input of a programmable counter illustrated as having two separate programmable counting sections 679 and 681. The programmable counter sections are each configured to load an eight bit data signal which corresponds to a count value which must be reached before an output signal is provided on line 783 from the programmable counter. The two counter sections 679 and 681 are separately loaded in two successive eight bit bytes of a data signal applied to lines 781 by CPU 27 through buffer 685 which is connected to the CPU data output pins 36, 35, 88, 89, 38, 39, 40 and 90 of the S-100 bus. Data signals from CPU 27 program the counter sections 679 and 681 to set the time period (number of clock signals counted) which must transpire before an output signal is placed on line 783. The counter sections 679 and 681 are respectively loaded by load signals FTP and CTP provided on lines 785 and 781. These signals are generated as separately decoded addresses by address decoder 793 which is connected to address lines A.0., A1 and A2 of the S-100 bus (pins 79, 80 and 81). Signals FTP and CTP are applied to counter sections 679 and 681 after passing through respective buffer amplifiers 798 and 796. When CPU 27 programs the two sections 679 and 681 of the programmable counter, it successively outputs the signals FTP and CTP by providing appropriate address signals to address decoder 792, along with the data which is to be loaded into the counter sections 679 and 681 (applied to lines 781) by the FTP and CTP load signals.

The output of the programmable counter (PTO) on line 783 is a programmable time duration interrupt control signal, the purpose of which will become more evident in the discussion of the interrupt programs executed by CPU 27.

The programmable counter is enabled by PTEN, a data signal applied by CPU 27 to latch 601 via the S-100 bus data output lines through buffer 685. The signal PTEN is used to gate the programmable counter on so that after expiration of the time period set therein, the signal PTO will be generated. Other signals supplied to latch 601 by the CPU 27 are TONEN, PTIR, MTPS, MTIR and VI4EN, the purpose of these signals will be described below.

The tone enable signal (TONEN) from latch 601 is supplied as an output on a line 811 which connects with the controller interface (FIG. 5) and provides the on/off control signal to the enable input of programmable frequency divider 313 as described above.

The MTPS signal is an enable signal which is applied by the CPU (through latch 601) to frequency divider 683 to on/off control its operation.

The remaining three signals at latch 601, PTIR, MTIR and VI4EN control the application of three separate interrupt signals to the CPU interrupt lines as more fully described below.

Address decoder 786 is connected to the A4, A5, A6 and A7 address lines respectively connected to pins 30, 29, 82 and 83 of the S-100 bus. Address decoder 786 serves to decode four groups of sixteen addresses. For purposes of simplifying description, the address decoder is illustrated as having decoded output lines of 3X, 4X, 5X, and 6X (hex notation). The X represents one of sixteen possible hexidecimal numbers (.0. . . . F) so, for example, the address decoder provides an output on line 3X when it decodes any one of the hex decimal addresses 3.0. . . . 3F.

The 3X output is supplied as an input to negative input AND gate 774 which receives at another input thereto the output of NOR gate 790. Gate 774 is thus enabled whenever an address 3X is decoded and a SINP or SOUT signal is detected at respective S-100 bus pins 46 and 45. As described earlier, SINP and SOUT are signals supplied from the CPU 27 to the S-100 bus when it is getting ready to input data (SINP) or output data (SOUT) so that associated devices connected to the S-100 bus can suitably ready themselves for the input or output operations. When gate 774 is enabled, it supplies a signal to inverter 776, the output of which is supplied to negative input OR gate 782 as one enabling input thereof. The output of inverter 776 is also applied to a buffer amplifier to generate the the signal SSIO on line 831. This signal is applied to the controller interface (FIG. 5) which in turn supplies it to pin 45 of the system bus 13 as previously described.

The 5X decode output of address decoder 786 is applied as one input to a negative input AND gate 772, the other input of which is connected to the output of NOR gate 790. When enabled by the concurrent presence of the two input signals, gate 772 provides a signal LINESEL which passes through inverter 653 and appears on line 827 as LINESEL. This signal is applied to the controller interface (FIG. 5) which in turn supplies it to pin 32 of the system bus 13 and from there to the section switches as described earlier.

The decoded 6X output from address decoder 786 is supplied as one input to negative input AND gate 770, the other input of which receives the output of NOR gate 790. When enabled by the concurrent presence of the 6X decode addresses and a SINP or SOUT signal from CPU 27, gate 770 supplies, through buffer 651, a signal IFIO to line 825 which leads to the controller interface (FIG. 6A) as previously described.

The respective outputs of gates 770, 772 and 774 are also applied through respective inverters 778, 780 and 776 as inputs to negative input OR gate 782. The output of gate 782 enables, through NAND gate 792, a wait state generator 784 which supplies a wait signal to an output PRDY line connected to pin 72 of the S-100 bus. When a wait signal is supplied to pin 72, the CPU stops operating. The wait state generator 784 is a counter which counts through a predetermined counting period upon being enabled. It receives a clock input of, for example, 4 MHz which is available at pin 24 of the S-100 bus. To ensure that timing begins at an appropriate point in the instruction execution cycle of the CPU 27, a PSYNC signal applied to pin 76 of the S-100 bus by the CPU 27 is also applied as an enabling input to NAND gate 792. The PSYNC signal synchronizes enablement of the wait state generator with the CPU instruction processing.

As noted, address decoder 793 receives address signals from the address lines A.0., A1 and A2. It also receives an enable signal PWR through inverter 770 which receives the signal PWR from pin 77 of the S-100 bus. The signal PWR is generated by CPU 27 during an output operation indicating that valid data is on the S-100 CPU data output pins. Address decoder 793 also has two negative enable inputs, one of which is connected to the 4X decoded output from address decoder 786 and the other of which is connected to the output of NAND gate 768 which in turn receives at one input the output of NOR gate 790 through inverter 788. The net result of the enable signals and address signals applied to address decoder 793 is that it decodes addresses corresponding to the signals FTP and CTP and the enable signal for latch 601 (applied through inverter 794) from the CPU 27.

The master controller also provides three separate interrupt signals MTI, PTI and VI4 to respective pins 10, 9 and 8 of the S-100 data bus. These pins are in turn connected to three interrupt lines of CPU 27. The CPU processes applied interrupts in an order or priority with the MTI interrupt being of highest priority and the VI4 interrupt being of lowest priority. Each interrupt has one or more respective interrupt programs associated therewith which CPU 27 executes upon being interrupted. These programs will be described in detail below.

The three interrupt signals generated by the system are a master interrrupt MTI applied to pin 10 of the S-100 bus (FIG. 7), a programmable interrupt PTI applied to pin 9 of the S-100 bus, and a sampling interrupt VI4 phase locked to an AC power line and applied to pin 8 of the S-100 bus. The latter interrupt is generated by the phase lock loop (PLL) frequency multiplier 307 of the controller interface (FIG. 5) and is supplied as a signal VI4 on line 310 to the master controller. The programmable interrupt PTI is provided on pin 9 upon the appearance of the output signal PTO from programmable counter section 679 on line 783. The master interrupt MTI is provided on pin 10 upon the appearance of the MTO signal emitted by frequency divider 683 on line 784.

The three interrupt control signals VI4, PTO and MTO are each connected to respective identical latching and reset circuits in the master controller. For the purpose of simplifying description, only the latching and reset circuit which generates signal PTI will be described in detail. The PTO control signal on line 783 is applied to a clock input of a flip-flop 603 the output of which enables buffer amplifiers 607 and 609 to apply a ground condition to respective pins 73 and 9 of the S-100 bus. Amplifiers 607 and 609 respectively generate output signals PINT and PTI. The PINT signal which is applied to pin 73 of the S-100 bus goes "low" to indicate to the CPU 27 that an interrupt has occurred. The CPU 27 then examines its interrupt lines respectively connected to pins 10, 9 and 8 of the S-100 bus to determine which interrupt(s) is occurring. The CPU then processes the interrupt program for the highest priority interrupt then occurring.

After the interrupt PTI occurs, flip-flop 603 must be reset before the occurrence of the next interrupt, otherwise it will not be detected. For this purpose, flip-flop 603 is reset by a signal PTIR which is provided on an output line of latch 601. CPU 27 supplies the signal PTIR to the latch 601 to reset flip-flop 603 during processing of the interrupt program(s) associated with the PTI interrupt. The master interrupt control signal MTO on line 784 likewise clocks flip-flop 605 which is reset by a signal MTIR also received from the output of latch 601. In like manner, the interrupt control signal VI4 received on line 310 clocks flip-flop 617 which is reset by the signal VI4EN supplied by latch 601. Whenever any of the interrupt outputs to respective pins 10, 9 or 8 is generated, the associated interrupt request signal PINT is also generated to notify CPU 27 that an interrupt signal is present.

FIG. 7 also shows a buffer 627 which is used to output data to the data input pins 43, 93, 92, 91, 42, 41, 94 and 95 of the S-100 bus which are connected to the data input lines of CPU 27. The buffer is enabled by the output of negative input AND gate 623. One input to gate 623 is taken from the output of inverter 625 which has an input connected to pin 78 of the S-100 bus. This pin has a signal PDBIN applied thereto by CPU 27. As described earlier, this signal is supplied when CPU 27 desires to read input data. The other input to gate 623 is taken from the output of inverter 776. Thus, whenever address decoder 786 decodes a 3X address and CPU 27 supplies a SINP signal to NOR gate 790 (enabling negative input AND gate 774) and the signal PDBIN to negative input AND gate 623, the latter is enabled to enable buffer 627 and allow data to pass to the input pins of the S-100 data bus.

A/D CONVERTER

FIGS. 8A and 8B show the details of the analog to digital converter 21. This device receives each of the output lines from the section switches J.0. . . . J31. These output lines contain an analog signal representing a sensor output, an AC power calculation signal or a test signal. The analog signals on the section switch output lines are digitized by A/D converter 21 and are then supplied to the data input lines of the S-100 bus for input to the CPU 27.

The A/D converter 21 includes an address decoder 501 (FIG. 8A) which is connected to the address lines A0, A1, . . . A7 of the S-100 bus. Address decoder 501 has three output lines 903, 905 and 907. Output line 907 contains a signal when any one of 32 different addresses, corresponding one each to the section switch FIG. 4 portions, are received from the CPU 27. This line is an address line for energizing the A/D converter 21. Output lines 903 and 905 of address decoder 501 are two specific addresses which supply signals to negative input AND gates 515 and 517 respectively. These gates respectively enable latches 509 and 513 which receive data from the CPU through buffer 507 connected to the data output pins 90, 40, 39, 38, 89, 88, 35 and 36 of the S-100 bus. Additional input enable signals to gates 515 and 517 arrive from the output of inverter 519 which has an input connected to the output of negative input AND gate 521. The two inputs to gate 521 come respectively from pin 77 of the S-100 bus and NOR gate 523 having its inputs respectively connected to pins 45 and 46 of the S-100 bus. NOR gate 523 determines whether the CPU 27 has supplied either of the signals SOUT or SINP to the S-100 bus, respectively indicating that output data will be supplied or that it will accept input data. When gate 523 detects either of these signals and the signal PWR is applied to pin 77 by CPU 27 when it is ready to do an output operation, gate 521 will be enabled and either of gates 515 and 517 will thus be enabled depending on which is addressed by the CPU 27 via the signal on lines 903 and 905 of address decoder 501.

Latch 513 receives previously stored offset data from the CPU 27 via buffer 507 which is representative of calibration voltages obtained from the various sensors which are connected to the information channels at the remote stations during a calibration procedure. This digitized offset data is supplied to the input of D/A converter 511. The calibration voltages are obtained by sequentially scanning the sensors when they are under known load conditions and they are stored by the CPU 27 for summation with actual sensor output signals which are to be digitized. The output of latch 513 represents, in digital form, the upper eight bits of the digitized offset values. The lower two bits come from latch 509 and are latched therein together with the control signals GAIN 4X, SIGN, SUMINV, 11 BIT, TWO'S COMP and GATE EN, all of which are supplied by CPU 27. The control signals configure A/D converter 21 to different operative states as described below.

Digital to analog converter 511 has a control input which selects the polarity (positive or negative) of the analog output. The polarity of the offset is set by the SIGN control signal at the output of latch 509.

The analog offset voltage output of D/A converter 511 is fed to a summing amplifier 512 which receives at its other input the output of 1 of 32 line select switch 503. This device is similar to previously described analog selection switches. A particular switch is closed to pass one of the input lines to the output line 901 in accordance with the addressing data signal applied thereto. The selecting of an appropriate input line is accomplished by connecting the data select input 505 of the line select switch 503 to the address bus lines A.0. . . . A4 of the S-100 bus. The line inputs to the line select switch 503 are the respective lines J.0. . . . J31 exiting from the section switches. Two lines exit each section switch, one for each of the FIG. 4 portions. These lines represent the 32 wire pairs which are respectively connected to 32 groups of remote stations.

Summing amplifier 512 sums the calibration offset voltages applied by D/A converter 511 with the output from the section switches which are selectively connected to line 901. Summing amplifier 512 has a switchable gain. In normal operation it has a gain factor of one, but it can be switched by a control signal GAIN-4X applied from the output of latch 509 to a gain factor of 4. The output of summing amplifier 512 is applied to switchable polarity, unity gain amplifier 514. The polarity of the output of amplifier 514 is set by the control signal SUMINV. The output of amplifier 514 appears at line 914 which is an input line to A/D converter 553 (FIG. 8B). The output of A/D converter 553 is supplied via gated buffers 563, 565 and 567 to data input pins 43, 93, 92, 91, 42, 41, 94 and 95 of the S-100 bus and are thus fed to CPU 27.

Buffers 563, 565 and 567 are used to gate the 11 bit output lines of A/D converter 553 to the 8 bit input data lines of CPU 27. Various outputs of the A to D converter 553 are transmitted to the CPU 27 data input lines by operating buffers 563, 565 and 567 at different times under control of a decoder 551 and a flip-flop 548 (FIG. 8B). Decoder 551 decodes the control signal 11 BIT to activate either its "0" or "1" output lines depending on the level of 11 BIT. When decoder 551 applies a signal to its "0" output line, gate 563 is enabled. Decoder 551, in turn, is enabled by the output of inverter 539. When enabled, buffer 563 applies the 8 most significant bits (MSBS) of the output of A/D converter 553 to pins 43, 93, 92, 91, 42, 41, 94 and 95.

Flip flop 548 has its two outputs (Q, Q) respectively connected to the enable inputs of buffers 565 and 567 through gated buffer amplifiers 550. The gating signal for amplifiers 550 originates at the "1" output line of decoder 551. When decoder 551 enables amplifiers 550 either buffer 565 or 567 will be enabled depending on the state of flip flop 548. By toggling flip flop 548 buffers 565 and 567 can be sequentially enabled.

Buffer 565 has five upper inputs connected to the output of a gate 557 through inverter 568 and the next input to the MSB or MSB output of converter 553 as described below. The last two bits of buffer 565 go to bits 9 and 8 of A/D converter 553. Buffer 567 has its 8 inputs connected to the 8 least significant bits of A/D converter 553. As can be seen, by appropriately controlling decoder 551 with the control signal 11 BIT and operating flip flop 548 with the outputs of gates 531 and 533 (respectively applied to the S and CL inputs) various output bits of the A/D converter 553 can be gated under control of CPU 27 to its data inputs.

The uppermost data input line of buffer 563 is connected to the most significant bit MSB and inverted most significant bit MSB output lines of A/D converter 553 through negative input OR gate 561, and NAND gates 557 and 559. The purpose of these gates and inverter 555 is to allow the upper data line of buffer 563 and buffer 565 to receive either the MSB or MSB outputs of A/D converter 553. This is under control of the TWO'S COMP control signal at the output of latch 509.

The A/D converter 21 also includes various gating circuits which are used to control operation of the A/D converter 553 as well as to enable decoder 551 and operate flip flop 548. Negative input AND gate 529 receives the output of NOR gate 523 and the output of an inverter 527 connected through the buffer 525 to the pin 78 of the S-100 bus which contains the PDBIN signal. Accordingly, when the CPU 27 outputs either an SOUT or an SINP signal and a PDBIN signal, gate 529 is enabled. The output of gate 529 is supplied to the input of NAND gate 531 which has at its other input the output signal on line 903 which is an address decoded by address decoder 501. When the address signal and output of gate 529 are present, gate 531 is enabled to supply a signal to one input of negative input OR gate 537 which receives at its other input the output of NAND gate 533. The inputs of NAND gate 533 are respectively connected to the output of gate 529 and line 907 which is one of the address select line for the A/D converter 21. Accordingly, when the A/D converter 21 is addressed to make line 907 true and the CPU supplies the signals PDBIN and either of SOUT or SINP, NAND gate 533 is enabled. When either of gates 531 or 533 are enabled, negative input OR gate 537 supplies an output signal which is inverted by inverter 539. The output of inverter 539 is passed to the decoder 551 enabling it to supply its decoded output to the "0" or "1" output line. The output of gates 531 and 533 also control the state of flip flop 548 and in turn the enablement of buffers 565 and 567.

The output of NAND gate 533 is also connected through inverter 535 to one input of NAND gate 541 which receives as its other input the PSYNC signal on pin 76 of the S-100 bus through buffer 525. When enabled by the concurrent presence of the two input signals thereto, NAND gate 541 supplies an enable signal to wait state generator 545. Wait state generator 545 is similar to the wait state generator on the master controller. When enabled, it counts a predetermined number of clock pulses before emitting an output signal. The purpose of wait state generator 545 is to allow data to settle on the incoming section switch lines before A/D converter 553 is instructed to perform a conversion operation. The output signal from wait state generator 545 is supplied to a convert input terminal of the A/D converter 553 and this starts the A/D conversion operation.

The output of NAND gate 541 which enables the wait state generator is also applied as a clear (CL,) input to flip-flop 575. The output of flip-flop 575 passes through NOR gate 573 and activates buffer 569 to pull the line connected to pin 72 of the S-100 bus "low". This supplies a PRDY signal to the CPU 27 placing it in a wait state. After the wait state counter counts to its predetermined value (approximately a two microsecond delay), the A/D converter 553 is instructed to being conversion. At this time the status line STA of A/D converter 553 goes high and remains high during the conversion process. This signal passes through NOR gate 573 and keeps buffer amplifier 569 enabled to continue application of the PRDY signal to pin 72 of the S-100 bus. After conversion is completed (approximately two micro-seconds), A/D converter 553 removes the high signal from the status line and also supplies a clock reset signal to flip-flop 575 so that NOR gate 573 is now disabled and removes the control signal from buffer amplifier 569 thereby removing the wait signal from PRDY pin 72. A set input (line 526) to flip-flop 575 is supplied through buffer 525 from the POC line connected to pin 99 of the S-100 bus. This signal is a reset signal which is applied to pin 99 whenever the system is reset and merely resets flip-flop 575 whenever a main system reset occurs.

A negative input OR gate 571 is also provided which receives the GATE EN signal from latch 509 and the output of gate 573. It supplies an enabling signal to line select switch 503 on line 911 whenever GATE EN is present or when gate 573 is supplying a wait state control signal to gated buffer amplifier 569.

SENSORS

The system as described above has the capability of measuring a sensor output as a resistance, a precision resistance change, a voltage, or a current. The sensor outputs are read and digitized under control of CPU 27 during the time that the addressed information channels are connected to the central station over one of the 32 line pairs connecting the central station with the various groups of remote stations. The outputs of the sensors can represent sensed temperature, fluid flow, BTU consumption, etc. virtually without restriction.

Several representative sensors which can be used in the invention and the parameters which they measure will now be described.

For the purpose of measuring current in an electrical path at a remote station, a current measuring transducer as shown in FIG. 26 may be employed. It comprises a precision wound toroidal current transformer 210 having a precision resistor 208 mounted adjacent to the transformer. The precision resistor 208 is connected in parallel with the secondary output of the transformer and with a pair of back-to-back Zener diodes 204 and 206. A resistor 202 is also connected in series with the coil, precision resistor and Zener diodes and the entire assembly is then connected across the terminals of an information channel 10 at a remote station. Since the precision resistor 208 is a fixed part of the assembly, the output of the circuit illustrated in FIG. 2 is a voltage, not a current, as with a standard current transformer. The main advantage of having a voltage output for the current sensor is that the length of wire between the transducer and an actual measuring device is not critical, as is the case with a typical current transformer.

The series resistor 202 at the current transducer output is used to provide a high output impedance which makes it easy to detect tampering with the current transducer. For example, if various resistive or reactive electrical components are connected across the output of the current transducer, the resultant impedance change caused can be easily detected. Tampering can thus be detected by periodically operating CPU 27 to check the impedance of the current transducer against a known reference impedance value for the transducer stored during initial calibration of the system. The purpose of Zener diodes 204 and 206 is to protect precision resistor 208 and the remote station 11 to which the transducer is connected from very high current surges in line 212 which try to induce very high voltages across resistor 208.

The present invention can also be used to economically measure temperature, fluid flow and heat flow at a multiplicity of locations. This is done by using a combination of resistance and precision resistance change measurements in conjunction with various temperature and flow sensors which have been developed to supply resistance and precision resistance outputs to the information channels 10.

Temperature is measured using a thermistor or other temperature sensitive device which is connected to an information channel 10 at a remote station. CPU 27 operates the A/D converter 21, controller interface 15 and section switches 17 to acquire and store the temperature sensor output as digital data.

Air flow is determined by measuring the temperature difference between a first conventional temperature sensor e.g. a thermistor, provided in an air stream and a second temperature sensor provided in the air stream at a location downstream of the first. FIG. 27 illustrates an air flow sensing system using a thermistor 214 and a thermistor 218, the latter being thermally bonded to a fixed resistor 216 by a thermally conductive epoxy 224, as the first and second temperature sensors. Resistor 216 is connected across a voltage source 222. Also illustrated is a conventional humidity detector 220. The temperature difference between thermistor 218 and thermistor 214 (each of which changes resistance with temperatures changes) determines the air flow since for any given air handling system a curve of air flow rate versus temperature differences can be experimentally derived. Although these curves vary somewhat with absolute air temperature and humidity, it is possible to construct families of curves for air flow rate versus temperature difference which are entered into CPU 27 and used as look up tables for determining an air flow knowing the absolute air temperature and the humidity.

Humidity is measured by humidity detector 220 which provides an output resistance which changes with air humidity level. Since any one of several conventional devices can be used as humidity detector 220 a detailed description of this device is not provided.

The purpose of fixed resistor 216 and associated voltage source 222 is to provide a heated surface in contact with thermistor 218 which is maintained approximately 20.degree. to 30.degree. C. above the air temperature under full flow conditions. Experimentation has shown that the most accurate results are achieved when the heat dissipating area of the downstream sensor comprised of resistor 216, thermistor 218 and epoxy housing 224 is small and of consistent size and symmetrical shape to minimize the effects of orientation of the sensor in the flow stream which is being measured. The best configuration for the air flow sensor has been found to be a resistor and thermistor encapsulated in an oval shaped housing made of a highly thermally conductive and low electrically conductive epoxy 224. The oval shape makes it possible to string the flow sensor across an air flow duct perpendicular to the air flow with a minimum of air disturbance and without concern for its rotational position.

Heat transferred in BTU's by air handling heat exchangers can be determined by using the invention with sensors which measure the input air temperature to an air heat exchanger (e.g. sensor 214, FIG. 27), the output air temperature from the exchanger, the air flow rate (e.g. sensors 214 and 224, FIG. 27) and the humidity (sensor 220). For each combination of these parameters, a unique BTU value will exist. Thus, CPU 27 can read the values of these parameters from sensors connected at the remote station and calculate the corresponding BTU value.

Water (or other liquid) flow is measured by the system of the invention in much the same manner as air flow. In this case, however, humidity variations are not a consideration. To measure water flow, a thermistor/resistor sensor, similar to that for the air flow, has been devised which is housed in a tiny metal can. This flow sensor is illustrated in FIGS. 28A and 28B. The sensor 226 comprises a chip resistor 234 which is connected to a voltage source 238 for providing a constant temperature adjacent a thermistor 236 which is mounted by means of highly thermally conductive epoxy 232 in thermal contact with resistor 234. The entire assembly then is encased in a metal can 230 which is provided in a housing 228. The metal can is then inserted into a hole in a pipe 242 which defines a water flow path. A saddle T or other type of fixation device which will allow penetration of the metal can into the water stream without causing a leak in the pipe is used.

An additional thermistor 244 is mounted upstream of sensor 226. Sensors 244 and 226 operate essentially on the same principal as the two sensors of FIG. 27 which measure air flow. For any given water flow path, a set of curves can be experimentally obtained representing a temperature difference between the sensors which corresponds to a particular flow rate. Thus, a set of curves can be experimentally obtained and stored by CPU 27 relating the water flow rate to a difference in temperature sensed by sensors 244 and 226. The cylindrical shape of the metal can makes it possible to place the flow sensor in a pipe perpendicular to the water flow without having to worry about its rotational position. Once the temperature difference is determined, CPU 27 can then calculate a water flow rate.

For BTU measurements of liquid flow heat exchanger, the sensors 244 and 226 can be used on the input line to a heat exchanging device 231 (FIG. 29). The output line of the heat exchanging device can also be connected to another temperature sensor 245 identical to sensor 244. By measuring the input and output liquid temperatures with sensors 244 and 245 and the liquid flow rate with sensors 244 and 226 as described above, the amount of thermal energy emitted (or collected) by heat exchanger 231 can be determined.

The characteristics of the air and fluid flow sensors ilustrated can be varied by changing the materials, component values, heater power, mechanical configuration and physical size. Consistency from one sensor to another is achieved when all these parameters are maintained constant. However, even if there are variations from one sensor to another, the data processing and storage capabilities of the CPU 27 can obtain consistency between sensors as it can store known flow calibration readings for each sensor so that actual sensor readings can be balanced out using the calibration data. Thus, inexpensive sensors can be used while still achieving a high degree of measurement accuracy.

CPU OPERATION

Sensor data gathering and processing for the system is handled under interrupt control of the CPU 27. Further processing of the sensor data into more meaningful information for the display of gathered and processed data is handled by an operator interactive sequential program (OIP) which runs continuously, except when interrupted by the various system interrupts.

The system uses three interrupts to control the operation of CPU 27. These have been briefly described above with reference to the system hardware. The highest priority interrupt MTI is generated under control of the master timer signal MTO which is the output of divider 683 in the master controller. MTO is a pulse signal generated, for example, at the rate of 512 pulses per hour (one every 7.03125 seconds).

The next highest priority interrupt PTI is generated under control of the output (PTO) of the system's programmable timer formed by programmable counter sections 679 and 681 in the master controller. This interrupt is the system's most active interrupt and the time between the occurrence of PTO is programmed by the CPU 27 during execution of a program. For purposes of subsequent description the PTI interrupt will be referred to as the sensor interrupt.

The lowest priority interrupt VI4 for the system is generated by the phase lock loop (PLL) multiplier 307 on the controller interface. The output of the phase lock loop frequency multiplier is 32 equally spaced pulses for each cycle of an applied 60 Hz input signal; that is, a pulse rate of 1920 Hz. These interrupts are used by CPU 27 to gather and process data for AC power measurements.

The overall program executed by CPU 27 is illustrated in FIG. 9. It begins at step 401 where the CPU 27 initializes the system hardware. The initialization program executed at step 401 is shown in FIG. 10 and described in detail below. The overall program next proceeds to step 403 which contains the operator interactive program (OIP) which is illustrated in greater detail in FIGS. 25A . . . 25M and also described in more detail below. During initial system installation and at periodic times thereafter, it is desirable to calibrate the system by taking measurements under known conditions of the outputs of various sensors which are connected to the information channels 10 at the remote stations. Accordingly, step 405 determines whether a calibration routine is desired. If so, the program proceeds to step 415 where the CPU 27 obtains and stores initial calibration data from the sensors under control of the sensor interrupt. This data is that which is supplied by CPU 27 to D/A converter 511 through latches 509 and 513. If no further sensor interrupts occur or when it completes processing a sensor interrupt, CPU 27 returns to the operator interactive program (OIP). Since the data gathering programs executed during system calibration (step 415) are the same as those executed during normal system operation (described below) to obtain sensor data, a separate discussion of the calibration data gathering programs will not be provided.

Assuming that calibration is not desired, the CPU proceeds to start the master interrupt timer in step 407. In this step, the CPU 27 removes the MTIR reset signal from latch 601 which allows flip flop 605 to be responsive to the MTO output of the master interrupt timer to provide the signal MTI at the output of buffer 613 (pin 10). CPU 27 also supplies signal MTPS to latch 601 which enables frequency divider 683.

In the next step 409, CPU 27 begins collecting and processing sensor output data under control of the sensor interrupt (PTI) appearing at pin 9 of the S-100 bus. Whenever sensor interrupts are not being processed or when the sensor interrupts stop, the CPU returns to the operator interactive program (OIP) in step 411.

Whenever the high priority master interrupt occurs (signal MTI on pin 10 of the S-100 bus), the CPU executes a master timer interrupt program which, among other things, sends a reset tone pulse to all the remote stations on the 32 communications lines and begins again collecting and processing sensor data by returning to step 409.

It should be appreciated that the flowchart of FIG. 9 is a macro flowchart and that many individual programs or program steps occur at each operational block illustrated. A more complete description of CPU 27 operation follows.

The operational steps performed by CPU 27 when executing step 401 of FIG. 9 are shown in greater detail in the flowchart of FIG. 10.

When the system hardware is initially activated, it must be initialized, that is preset, to a particular installation environment. The section switches must be instructed as to which input lines they will handle, the tracking analog to digital converter in the section switches must be fed voltage from one of the available voltage sources, etc. This is what is accomplished by the initialization program.

In the first step 419 of the initialization program, the CPU supplies the section switch line selector latch 131 with data relating to which incoming line each section switch portion (FIG. 4) will handle, whether in a "split bus" or non-"split bus" configuration. Table I illustrates the line selecting bit value assignments of latch 131 for a "split bus" configuration, while Table II illustrates the bit value assignments for a non-"split bus" configuration.

                                      TABLE 1
    __________________________________________________________________________
    Latch 131
            1st 8 Input Lines
                            2nd 8 Input Lines
    Latch Outputs
            0 1 2 3 4 5 6 7 8 9 10
                                  11
                                    12
                                      13
                                        14
                                          15
    __________________________________________________________________________
    L1 A3   1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    L1 A2   0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
    L1 A1   0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
    L1 A.0. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
    L0 A3   1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    L0 A2   0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
    L0 A1   0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
    L0 A.0. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
    __________________________________________________________________________


TABLE II __________________________________________________________________________ Latch 131 16 Input Lines Latch Outputs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 __________________________________________________________________________ L1 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 L1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 L1 A1 0 0 1