Computing scale system

Abstract

Disclosed is a computing scale system utilizing an integrated circuit microcomputer for computing the value of a product being weighed and for controlling the operation of a label printer associated therewith. The microcomputer operates with 4-bit words, and there is provided a multiplexing network for multiplexing weight, price, and status information into the microcomputer. Weight readings are made by a bank of photosensors, which read the position of a chart moveable in response to weight on the scale platter. Means are provided for performing a parity check on the data read by the weight photocells, and the data so read is converted from Gray code to BCD code by a table lookup routine. The scale system may print labels having weight and computed value, zero weight and fixed value, or weight and fixed value. The scale has both selectable price and weight dead zone capability with adjustable range. There is a motion detection routine employing a variable settling time.

Claims

What is claimed is:

1. A scale system comprising:

a platter which moves in accordance with the weight of a commodity placed thereon,

a chart connected to said platter for movement together therewith, said chart having a series of weight indicating tracks provided with weight indicating areas arranged for weight indication and a parity indicating track provided with parity indicating areas arranged for indicating parity for corresponding weight indicating areas on said weight indicating tracks,

a series of photocells, including weight detecting photocells and a parity detecting photocell, observing said areas in said tracks and providing a corresponding series of weight indicating signals and a parity indicating signal,

transition detecting means for generating a transition signal indicating a positioning of said chart such that one of the photocells observing a weight indicating track is observing an edge of one of said weight indicating areas,

display means for presenting a visual representation of said weight indicating signals,

parity checking means for checking said weight indicating signals against said parity indicating signal and inhibiting the operation of said display means whenever a parity error is detected,

parity check suppressing means for interrupting inhibiting control of said display means by said parity checking means whenever said (threshold) transition signal is generated (.), and

function control means connected with said transition detecting means, display means and parity checking means for sequentially enabling events in the operating cycle of said scale system.

2. A scale system according to claim 1 further comprising a second parity indicating photocell positioned for viewing said parity indicating track and generating a second parity indicating signal which indicates opposite parity from the first aforesaid parity indicating signal.

3. A scale system according to claim 2 wherein said threshold detecting means includes a lengthwise addition to the weight (indicating) verifying graduated areas on said parity indicating track and means for generating said threshold signal whenever said parity indicating photocells each sense lengthwise addition areas and thereby have a common output.

4. A scale system according to claim 3 wherein said lengthwise additions are extensions of said chart parity indicating areas so that said common output is caused by observation of a parity indicating area by one of said photocells and observation of one of said extensions by the other of said photocells.

5. A scale system according to claim 4 wherein said extended length parity indicating areas and said weight indicating areas are translucent areas in said chart.

6. A scale system according to claim 1 wherein said transition detecting means comprises a threshold indicating track having translucent areas arranged thereon for indication of a positioning of said chart at a transition point between weight readings, means for directing light through said translucent areas, and a threshold indicating photocell for detection of said light.

7. A weighing scale system comprising:

a platter which moves in accordance with the weight of a commodity placed thereon,

a chart connected to said platter for movement therewith, said chart having a series of weight indicating tracks provided with weight indicating graduations and a parity indicating track with parity indicating graduations arranged for parity verification of the corresponding weight indicating graduations and for identification of weight transition points therein;

signal generating means for generating electrical weight indicating signals, a parity indicating signal, and a transition signal from said chart graduations,

parity checking means for checking said weight indicating signals against said parity indicating signal and inhibiting the operation of said scale system whenever a parity error is detected,

parity check suppressing means for suppressing the inhibiting function of said parity checking means whenever said transition signal indicates chart positioning near a weight transition point, and

function control means connected with said signal generating means, and parity checking means for sequentially enabling events in the operating cycle of said weighing scale system.

8. A scale system according to claim 7 wherein said parity track graduations are of greater length than the corresponding weight indicating track graduations and overlap portions of the adjacent weight graduations for controlling generation of said transition signal by said signal generating means.

9. A scale system according to claim 8 wherein said signal generating means includes two transducer elements located along the same parity indicating track.

10. A scale system comprising:

a platter which moves in accordance with the weight of a commodity placed thereon,

a chart connected to said platter for movement together therewith, said chart having a series of weight indicating tracks, a parity indicating track, and a transition indicating track, all of said tracks comprising alternate opaque and translucent areas, the areas on said weight indicating tracks being arranged to indicate commodity weight, the areas on said parity checking track being arranged to indicate parity for corresponding areas on the weight indicating tracks, and the areas on the transition indicating track also being arranged to indicate opaque to translucent transition regions between the areas on the weight indicating tracks,

a light source directed against said chart,

a series of photocells for detecting light passing through the translucent areas in said tracks,

means connected to said photocells for generating a digital representation of said commodity weight and parity as indicated by said tracks and detected by said photocells,

parity checking means for checking the parity of said digital weight representation against the indication of said parity indicating track as detected by said photocells,

error indicating means connected to said parity checking means for indicating detection of a parity error,

parity check suppressing means for inhibiting the operation of said parity checking means when said photocells detect a transition indication by said transition indicating track, and

function control means connected with said parity checking means for sequentially enabling parity checking and predetermined other events in the operating cycle of said scale system.

11. A scale according to claim 10 wherein said parity checking track further comprises areas to indicate opaque/translucent transition regions between the areas on the weight indicating tracks, and said parity check suppressing means comprises means for inhibiting operation of said parity checking means only when said photocells produce output signals indicative of light passage through both said threshold indicating track and said parity indicating track.

12. A scale according to claim 11 wherein said transition indicating track further comprises areas to indicate parity for an alignment of areas on said weight indicating tracks, said parity being opposite the parity indicated by said parity indicating track, and said parity checking means comprises means to check the parity of said digital weight representation against the indication of said threshold indicating track and means to signal an error in said parity check to said error indicating means.

13. In a computing scale system which generates a series of weight indications, improved scale motion monitoring apparatus comprising:

comparing means for comparing a current weight indication with a next preceding weight indication and generating a positive difference indication when said current weight indication exceeds said next preceding weight indication and a negative difference indication when said next preceding weight indication exceeds said current weight indication,

counting means for counting said negative and positive difference indications, a negative difference indication resetting the positive count and a positive difference indication resetting the negative count,

motion indicating means for generating a first motion indication when said counting means reaches a predetermined first count of either negative or positive indications and subsequent motion indications whenever said counting means thereafter reaches a predetermined second count of negative or positive indications,

count adjusting means for causing said second count to be lower in number than said first count,

timing means for indicating elapsed time since generation of a motion indication by said motion indicating means,

reset means for resetting said timing means and said counting means whenever said motion indicating means generates a motion indicating signal, and

motion cessation indicating means for indicating a motionless scale condition when said first motion indication has been generated and said timing means has thereafter indicated a predetermined elapsed time.

14. In the system of claim 13 wherein said counting means comprises a positive difference counting register and a negative difference counting register.

15. In the system of claim 13 wherein said timing means comprises a timing counter, means for incrementing said timing counter each time said comparing means successfully compares a current weight indication with a next preceding weight indication, and a waiting counter for controlling the time between said comparisons of weight indications.

16. In the system of claim 15 further including means also incrementing said timing counter in response to a current weight indication which neither compares with the preceding weight indication nor generates a motion indication.

17. In the system of claim 15 wherein said timing means further comprises manually operable selection means for adjusting the number of counts made by said waiting counter and thereby controlling the time lapse between a motion indication and a indication of a motionless scale condition.

18. A computing scale system comprising:

a scale providing an output signal indicative of the weight of an article placed thereon,

means for communicating a price per unit weight of said article to said scale,

means for multiplying said weight by said price per unit weight to obtain a total value,

means for indicating said total value,

means defining a weight dead zone in said scale and inhibiting said indication of total value when said output signal indicates a weight within said weight dead zone,

manually operable selection means for adjusting the size of said weight dead zone and

function control means for sequentially enabling events in the operating cycle of said scale system.

19. The scale system of claim 18 wherein said means defining a weight dead zone also inhibits said means for multiplying when said output signal indicates a weight within said weight dead zone.

20. In a computing scale of the type having a deflectable platter for weighing articles, transducer means providing signals indicative of platter deflection, function control means for determining an operating cycle, computation means for calculating weight-related information from the transducer signals and motion detecting means inhibiting the computation means until the platter and transducer have reached a stable position, the improvement comprising:

means for altering the motion sensitivity of said motion detector appratus between a first sensitivity condition for determining cessation of motion while the scale is settling out from a moving condition and a second lesser sensitive condition for determing the commencement of motion while the scale is in a substantially motionless condition.

21. Motion detecting apparatus for a weight scale comprising:

means for periodically generating electrical signals indicative of scale loading;

first counting means responsive to value increase of said electrical signals over a preceding signal without an intervening smaller signal;

second counting means responsive to value decrease at said electrical signals from a preceding signal without an intervening larger signal;

means for excluding from said first and second counting means electrical signals equal in value to preceding electrical signals

function control means for controlling said motion detecting apparatus; and

motion signal generating means responsive to attaining a predetermined count in said first or second counting means.

22. The apparatus of claim 21 further including second counting means for counting to a second predetermined number the occurrence of said first or second motion signals said first predetermined number of times.

23. Scale apparatus for generating verified weight signals comprising:

a multiple track encoder member positionable in a plurality of weight indicating positions in response to scale platter weight, coded indications in said tracks identifying each possible position of said encoder member;

means parity verifying the code indications in said tracks according to a predetermined convention;

means identifying instances wherein said parity verification and said code indications may be inconsistent; and

function control means for sequentially enabling the operating cycle of said scale apparatus.

24. The apparatus of claim 23 wherein said means identifying inconsistent instances includes a parity data track with exaggerated code indications each extending beyond the corresponding weight indicating track code indication to encoder track regions predictably free of data transitions.

25. Scale apparatus for generating substantiated weight signals comprising:

a multiple track encoder member positionable in a plurality of weight indicating positions in response to scale platter weight, coded indications in said tracks identifying each possible encoder member position;

verifying means including a parity data track for substantiating the code indications read from the weight indication tracks in accordance with a predetermined convention;

means including a predetermined parity data track code at a predetermined weight location on said encoder member for testing the operation of said verifying means; and

function control means connected with said verifying means and said means for testing for sequentially enabling events in the operating cycle of said scale system.

26. The apparatus of claim 25 wherein said predetermined parity data track code is located at the zero weight indicating position of said encoder member.

27. The apparatus of claim 25 wherein said predetermined parity data track code comprises the absence of parity information.

28. The apparatus of claim 25 further including means inhibiting the operation of said verifying means while said encoder member is remote from said predetermined weight location.

29. The apparatus of claim 25 including two parity data tracks one each for odd and even parity verification, and wherein both of said parity data tracks are omitted at chart positions adjacent zero weight indication.

30. The apparatus of claim 29 wherein each of said parity data tracks includes exaggerated code indications each extending beyond the corresponding weight indicating track code indication to overlap each other and wherein the operation of said verifying means is inhibited in response to encoder positions containing said overlapped parity track indications.

31. Weighing apparatus comprising the combination of:

a weight receiving scale platter;

a multiple track weight encoding member coupled with said platter and movable in response to the weight of articles placed thereon, graduations along said multiple tracks identifying each possible weight value stopping positions thereof;

transducer means adjacent said encoding member for generating electrical signals representing the graduations proximate said transducer means in each weight value position;

means parity verifying the correctness of said electrical signals;

means responsive to said electrical signals for generating a motion signal indicative of mechanical movement of said encoding member, and

function control means connected with said means for parity verifying and said means for generating a motion signal and sequentially enabling events in the operating cycle of said weighing apparatus.

32. The combination of claim 31 wherein said encoding member is an optical encoder with light and dark graduations along said tracks, said encoder being illuminated by a light source and wherein said transducer means includes photo-electric cells.

33. The combination of claim 31 wherein said means parity verifying the correctness of said electrical signals includes an additional track of graduations on said encoding member, the graduations in said additional track being encoded to parity verify each set of plural track graduations along said plural tracks.

34. The combination of claim 31 wherein said motion signal generating means includes means for testing said electrical signals in accordance with two different criteria.

35. The combination of claim 31 wherein said motion signal generating means includes motion testing with two different degrees of motion sensitivity.

36. A method for operating a weighing scale of the type having a platter movable chart with corresponding weight indicating, parity indicating, and weight transition points indicating, graduations comprising the steps of:

generating electrical weight indicating, parity indicating and transition point indicating signals from said chart graduations;

checking said weight indicating signal against said parity indicating signal and inhibiting the operation of said scale whenever a parity error is detected; and

suppressing said inhibiting step whenever said transition signal indicates chart positioning near a weight transition point.

37. The method of claim 36 further including the step of testing said checking step with predetermined parity graduations located at a predetermined weight position on said chart.

38. A method for detecting motion in a computing scale comprising the steps of:

generating a sequence of scale deflection signals;

examining a plurality of said deflection signals for representations of rapid deflection change in accordance with a predetermined fast movement criteria, a first motion signal being generated thereby;

testing a plurality of said deflection signals for sample-to-sample differences according to a predetermined difference criteria, a second motion signal being generated thereby;

combining said first and second motion signals in accordance with a predetermined convention to generate a no-motion indicating signal; and

inhibiting weight related computation in the scale until said no-motion signal is received.

39. The method of claim 38 wherein said predetermined convention comprises the absence of both said first and second motion signals for a time interval.

40. The method of claim 38 wherein said predetermined fast movement criteria includes sensing the high frequency signal components in said periodic sequence of scale deflection signals, fast scale movement producing signals of high frequency component.

41. The method of claim 38 wherein said testing of deflection signals includes comparing the number of deflection signals indicating weight difference with a first predetermined number when the scale has previously been determined to be in motion and with a second predetermined number when the scale has previously been determined to be not in motion.

42. The method of claim 41 wherein said first predetermined number is smaller than said second predetermined number, the scale being more sensitive to continuing motion after motion is once detected.

43. The method of claim 41 further including selecting between said first and second predetermined numbers in said testing step in accordance with information developed from said examining step.

44. The method of claim 38 wherein said predetermined difference criteria includes accommodation for modifications introduced in said deflection signals by signal multiplexing.

45. The method of claim 38 further including inhibiting weight related computation in said scale until after one of said first and second motion signals has appeared and both motion signals have disappeared.

46. The method of claim 38 further including performing the generation of said first and second motion signals at time intervals correlated with the settle-out rate of the weighing scale.

47. The method of claim 38 wherein said predetermined convention for combining said first and second motion signals includes the disappearance of said first motion signal.

Description

BACKGROUND OF THE INVENTION

This invention relates to computing the scale sytems of the general type disclosed in Allen et al. in U.S. Pat. No. 3,557,353. Such computing scale systems have a scale, a label printer, and a computer fabricated from discrete components. Such scale systems are widely used in the food merchandising trade and may be used in combination with indexing and label application systems as shown in Treiber U.S. Pat. No. 3,732,966 or with automatic wrapping machines as disclosed in Treiber U.S. Pat. No. 3,429,098 or Treiber et al. U.S. Pat. No. 3,585,784.

Such prior art computing scale systems are flexible and versatile in their operation, but these scales are ordinarily constructed for a specific type of application. If it is desired to convert the scale from one application to another it is often times necessary to modify the configuration of the computer. There are now available integrated circuit microcomputers which may be easily programmed to do a large number of tasks, and it has become desirable to further increase the capabilities of the above mentioned prior art scale systems by usage of such computers. It has now been found that significantly improved operation as well as added versatility and new operating modes may be achieved by such a combination as hereinafter described.

SUMMARY OF THE INVENTION

This invention improves the operation of a scale system of the type shown in Allen et al. U.S. Pat. No. 3,557,353 by utilizing therewith a readily available integrated circuit microcomputer, which may be programmed by loading bit patterns as appropriate into a read only memory. The microcomputer operates on 4-bit data words, and there is provided a multiplexing network for multiplexing data into the computer.

In accordance with one feature of the invention weight data is read from a scale chart by a bank of photocells or photosensors, and means are provided for checking the parity of the data read by the photocells. When the scale is in a position of transition between weight readings, photocell parity checking is suppressed to avoid generation of parity errors by photocell threshold phenomena.

The weight data which is read from the scale chart is in a Gray code format, and this Gray code is converted to a BCD code by a table lookup routine. The Gray coded weight information is used as a table address for a first BCD weight indication, and the Gray code address is thereafter modified by a fixed number of address locations. Following this a second table entry is made to obtain a second BCD coded weight, which should be the nines complement of the first obtained weight. The system checks both the address of the information obtained from the lookup table and also checks the code conversion process by adding the digits of the two sets of BCD codes and checking for a predetermined sum.

Also in accordance with this invention there are provided a series of switch means for controlling the operation of the microcomputer. The microcomputer is so configured that actuation of some of the switch means adjusts the size of the weight dead zone. Other of the switch means control a value rounding routine and still others select multiplication factors for adapting the scale to metric system use.

The scale system checks for scale motion by looking for simultaneous outputs from the two preselected photocells and also by a routine which looks for a predetermined number of successive weight changes in the same direction. When the predetermined number of weight changes in the same direction are detected, then a timing routine is entered. Switch means are provided for controlling the length of time spent in the timing routine. If a scale motion indication is generated during this time, then a new entry is made into the timing routine.

A motion status word is set by the first sensing of scale motion, which may be indicated by three successive weight changes in the same direction. Thereafter two successive weight changes in the same direction are sufficient for maintaining motion status and causing reentry into the timing routine.

Provision is also made in the scale system for printing product weight and a predetermined fixed product value on labels for use on products which are sold by count. This printing of variable weight and fixed value is accomplished as part of a "by-count" operating mode, in which it is possible also to print labels with zero weight and a predetermined fixed value. The zero weight is read into the printer output control register while a product is sitting on the scale and actually indicating some finite weight.

It is therefore an object of this invention to increase the performance and versatility of prior art computing scale systems.

It is another object of this invention to provide means for checking the parity of output signals from weight reading photocells.

Another object of this invention is to provide improved means for detecting scale motion.

Still another object of this invention is to provide improved means for converting a Gray coded weight reading into a BCD format.

Other and further objects and advantages of the invention will be apparent from the following description, the accompanying drawings, and the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial drawing of a computing scale system;

FIGS. 2A through 2E are an electrical schematic diagram of microcomputer circuitry used with the described embodiment of the invention;

FIGS. 3A through 3C are an electrical schematic diagram of multiplexing and interface circuitry for use with the circuitry of FIGS. 2A through 2E;

FIG. 4 is an electrical schematic diagram of scanner circuitry;

FIGS. 5A and 5B are an electrical schematic diagram of printer circuitry;

FIGS. 6A through 6E are an electrical schematic diagram of circuitry for interfacing the printer circuitry of FIGS. 5A and 5B with the microcomputer circuitry of FIGS. 2A through 2E;

FIGS. 7A and 7B are an electrical schematic diagram of further circuitry for interfacing the printer circuitry of FIGS. 5A and 5B with the microcomputer circuitry of FIGS. 2A through 2E;

FIG. 8 is an electrical schematic diagram of still further interface circuitry required for operation of the described embodiment;

FIG. 9 is a schematic diagram of a portion of a scale chart;

FIG. 10 is a general system block diagram for the described embodiment;

FIGS. 11A through 11F are a program flow chart for an executive routine performed by the microcomputer;

FIGS. 12A and 12B are a flow chart for a motion detecting subroutine performed by the microcomputer;

FIG. 13 illustrates the layout of FIGS. 2A through 2E;

FIG. 14 is a flow chart for a subroutine for controlling address data outputs;

FIGS. 15A through 15E are a flow chart for a printer control subroutine;

FIG. 16 illustrates the layout of FIGS. 3A through 3C;

FIG. 17 illustrates the layout of FIGS. 5A and 5B;

FIG. 18 illustrates the layout of FIGS. 6A through 6E;

FIG. 19 illustrates the layout of FIGS. 7A and 7B;

FIG. 20 is a flow chart of a subroutine for controlling clock data outputs;

FIG. 21 is a flow chart for a subroutine for determination of rounding status:

FIGS. 22A through 22C are a flow chart for a value rounding subroutine;

FIG. 23 is a flow chart for a weight dead zone subroutine;

FIGS. 24A and 24B are a flow chart for a data comparison subroutine;

FIGS. 25A through 25D are a flow chart for a price switch reading subroutine; and

FIGS. 26A through 26D are a flow chart for a parity checking subroutine.

DESCRIPTION OF THE PREFERRED EMBODIMENT

A computing scale system operating in accordance with this invention may be incorporated within apparatus as illustrated generally by FIG. 1. The major system elements as illustrated therein are a scale 20, having a platter 21, a computer 25, and a register printer or labeler 30. Scale 20 may have a weight reading window 22, a tare adjusting knob 23 and a tare light 24. The register printer comprises three knobs 31, 32 and 33 for indication of a price per unit weight of an article being weighed, and a label or ticket ejector mechanism 35, which may be of a type described in detail in Allen, et al, U.S. Pat. No. 2,948,466.

Register printer 30 may have on its front panel a manual start switch 72, a repeat switch 71, a reset switch 70 and a power turn on switch 74. Below these switches there may be located an indicator light 61 for indicating that a change in price may be needed, an indicator light 62 for indication of a low paper supply, an error indicating light 60, and a power on indicating light 64. Provision may also be made for insertion of a commodity key 37 in the side of register printer 30.

The functions of the above mentioned controls and the operation of register printer 30 are all described in detail in Allen et al., U.S. Pat. No. 3,557,353. Also described in Allen et al., '353, and in references therein mentioned, are the operation of the scale 20 and a photoelectric scale reading system incorporated within the scale housing. The operation of the tare adjustment knob 23 and tare light 24 is described in detail in Allen, et al., U.S. Pat. No. 3,786,881.

The apparatus as shown in FIG. 1 may be supplemented with additional control switches and indicator lights, the functions of which will become apparent in the further description of the preferred embodiment. Also, as hereinafter described, the computing scale system may be used in combination with package indexing and label application apparatus as described in Treiber, U.S. Pat. No. 3,732,966, and also with an automatic labeling machine as described in Treiber, U.S. Pat. No. 3,429,098 or in Treiber, et al., U.S. Pat. No. 3,585,784. The operating sequence of the present scale is controlled by a programmed microprocessor; steps in the program of the microprocessor cause commencing and termination of scale events such as weight reading, motion detecting and printing commencement in ordered sequence. In a discrete component or hard-wired scale embodiment, this ordered sequence control may, of course, be supplied by a series connected group of flip-flops or other sequencing circuits rather than a computer program.

A generalized block diagram for the system is shown in FIG. 10. The blocks shown in that figure represent the scale 20, the labeler 30, a set of multiplexers 40, a read only memory (ROM) 50, a central processing unit (CPU) 230, and a random access memory (RAM) 231. Memories 50 and 231 and CPU 230 are part of a 4-bit parallel microcomputer set, as described in detail below. A series of instructions for system operation, including instructions for necessary computation and data handling, are stored at predetermined storage locations in ROM 50. CPU 230 utilizes line 46 for addressing the various storage locations within memory 50 in numerical sequence, or other sequence as called for by codes stored within ROM 50, and ROM 50 responds to such addresses by sending back along line 47 a series of instruction codes stored at the addressed locations. CPU 230 performs the operations called for by the codes received from ROM 50, and utilizes RAM 231 for temporary storage.

All data representing labeler status from line 42, price per unit weight from line 43, and commodity weight from line 41, are transmitted through multiplexers 40 and along line 48 through an input port associated with ROM 50 for transmission to CPU 230. Operation of multiplexers 40 is under the control of data received on line 54 from line 49. Line 49 carries addressing data transmitted by CPU 230 through an output port associated with RAM 231. The output port from RAM 231 also addresses the price per unit weight switches within labeler 30, as indicated by the line 53, and addresses the print wheel solenoids within labeler 30, as indicated by the line 52. This same output port further supplies address information via line 51 for addressing a set of photosensors within scale 20 to provide an indication of product weight. Reading of data from labeler 30 and scale 20 to multiplexers 40 is under the control of strobe signals generated by CPU 230 and trasnmitted, as illustrated by line 45, through a pair of output ports associated with ROM 50.

Detailed electrical schematic diagrams for the system housed within the units illustrated in FIG. 1 are presented in FIGS. 2 through 8, each of which FIGS. is broken up into several parts for preparation of the drawings. Some portions of these schematics are illustrated here primarily for completeness of the disclosure. For instance, FIGS. 5A through 5B illustrate the control switches 70, 71 and 72, and the indicator lights 60, 61, 62 and 64. The output lines from the price per unit weight switches are lines 520 through 529, which provide pricing information to other circuitry as indicated in FIGS. 6A through 6D. FIGS. 5A and 5B also illustrate an ejector switch 540, a repeat switch 541, cam switch 543, a solenoid switch 544, a commodity change switch 545, a pair of price changing switches 546 and 547, and the ejector motor winding 560. Cam switch 543 is opened once with each cycle of the printer, and price change switches 546 and 547 are ganged together for cooperative switching whenever any of the price change knobs 31 through 33 are manually moved. The commodity change switches 545 and 590 are operated by removal of commodity key 37. During removal of commodity key 37 or movement of one of the price change knobs 31 through 33 an error signal is generated on line 507.

A pair of switches 561 and 562 are ganged together for cooperative switching. As described below, scale units which are designed for use in metric measuring countries utilized certain special computer routines. In order to accommodate the special metric operation switch 561 is closed and switch 562 is open. For operation in the United States the scale is delivered with switch 561 open and switch 562 closed. As a practical matter the setting of switches 561 and 562 is a factory operation, and the two switches may be omitted and replaced by a jumper wire at one location or the other.

Within register printer 30 are motors for driving a set of print wheels and for ejecting labels, the operation of which is described in Allen et al., U.S. Pat. No. 3,557,353. The print wheels are positioned by a set of primary segment gears loosely mounted on a rocker shaft (not illustrated). The primary segment gears are stopped in correct printing position by energizing or firing solenoids 551 through 558, one solenoid halting each segment gear. The solenoids in turn are fired by input signals on lines 701 through 708. Other control lines associated with the circuitry of FIGS. 5A and 5B are output lines 502 through 508 and input lines 601 through 606. A relay 501 for activating the print wheel drive motor (not shown) is operated by line 606. When the rocker shaft reaches its home position, a switch 544 is opened to provide a "home position" signal on line 503. Also during rotation of the rocker shaft, a cam switch 543 is operated to cause an output on line 530 for transmission to the system computer via multiplexer 626 (FIG. 6B). The signal indicates that the printer has completed a predetermined portion of its operating cycle.

The remainder of the circuitry, which is shown in FIGS. 2 through 4 and 6 through 7, makes extensive use of integrated circuits, which are commercially available. Table I below lists the integrated circuit types, the operating characteristics of which are readily available from the manufacturer. All of the circuit types with the prefix letters SN are manufactured by Texas Instruments Incorporated of Dallas, Texas. The remaining circuits are manufactured by Intel Corporation of Santa Clara, Calif. The Intel components, all of which appear in FIGS. 2A through 2E, are part of a 4-bit parallel microcomputer set marketed by Intel Corporation under the trademark MCS-4. For a description of such a microcomputer reference may be made to Hoff et al., U.S. Pat. No. 3,821,715. Procedures for using the microcomputer are set forth in a users manual, dated March 1974, REV. 5, published by Intel Corporation. This users manual sets forth timing diagrams, descriptions of computer modules, overall microcomputer operation, and detailed programming instructions. Table II below sets forth the Intel instruction set, as provided by the manufacturer, together with a description of the operations associated with the instructions.

MICROCOMPUTER CIRCUITRY

FIGS. 2A through 2E illustrate the connections for the microcomputer components. Integrated circuit 230 is the central processing unit. Circuit 230 communicates via data bus lines 270 through 273 with a RAM circuit 231, and a pair of interface circuits 232 and 233. The interface circuits 232 and 233 provide respectively a ROM address register and data multiplexing; these chips are respectively Intel 4008 and 4009 devices described in the intel users manual. RAM circuit 231 is used for temporary storage and for output of multiplexer control signals as hereinafter described. The multiplexer control signals are output from RAM 231 via four inverting amplifiers 260 through 263. In accordance with terminology used within the above mentioned users manual for the microcomputer's set, RAM 231 is termed RAM 0, and the inverting amplifiers 260 through 263 serve as a RAM 0 output port. Accordingly the output from inverting amplifier 260 is designed RAM 0, bit 0. Similarly the output signals from inverting amplifiers 261, 262 and 263 and RAM 0, bit 1, RAM 0, bit 2, and RAM 0, bit 3. The RAM bits are sent to appropriate control locations via lines 200 through 203, 204 through 207, and 214 through 217. As further described in the above mentioned users manual, RAM 231 comprises four registers, each having a main memory of sixteen 4-bit words and four 4-bit status characters.

CPU 230 has a command output line 274 which tells IC 233 how to interpret the data bus content at any given time. This command controls the operation of ROM input and output ports as described below. Central processing unit 230 also outputs a RAM control signal on line 275 and a sync signal on line 276. Central processing unit 230 has provision for controlling three additional RAMs, which are not used in the described embodiment of this invention.

Integrated circuit 232 interfaces the CPU to six ROM circuits 234 through 239. CPU 230 transmits ROM addresses at appropriate times to IC 232 via lines 270 through 273. These addresses are latched at the output lines 224 through 226 and 280 through 287. Lines 224 through 226 carry a 3-bit ROM address code, which is decoded by NOR gate 227 and a decoder 241. Lines 280 through 287 carry an 8-bit program address, which is sent to all of ROMs 234 through 239. ROM circuits 234 through 239 are of the programmable variety, and they contain at each address location an 8-bit binary code which is an instruction in the computer program as hereinafter described. Decoder 241 addresses ROMs 234 through 239 via address lines 1200 through 1205. Line 1200 addresses ROM 234, which for programming purposes, is termed ROM 0. Line 1200 is also connected to an AND gate 1225, which enables a buffer circuit 240. Buffer circuit 240 serves as a ROM 0 input port.

ROM circuits 235 through 239 are termed ROM 1 through ROM 5 respectively. The ROM select signals on lines 1201 and 1202 for ROM 1 and ROM 2 (i. e., circuits 235 and 236) are also applied to registers 242 and 243, which serve as output ports for ROM 1 and ROM 2 respectively. Eight-bit control codes as read out from the ROM circuits are provided via lines 290 through 297 (bit 0 through bit 7 respectively), to integrated circuit 233. IC 233 serves as an interface between the ROM units and the central processing unit. The 8-bit codes read out from ROM are transferred from circuit 233 to central processing unit 230, four bits at a time, via data bus lines 270 through 273. Circuit 233 also has four input/output lines 1210 through 1213 for transferring 4-bit codes from CPU 230 to ROM output ports 242 and 243 and for transferring 4-bit data inputs from ROM input port 240 to CPU 230.

In accordance with the convention established by the above mentioned users manual, the 4-data bits transferred from buffer 240 to lines 1210 through 1213 are termed ROM 0, bit 0 through ROM 0, bit 3. In another embodiment, integrated circuits type 1702A, which are used for the ROM units, could be replaced by integrated circuits type 4001, in which case ROM 0 would be provided with an integral data input port, while ROM 1 and ROM 2 would be provided with integral data output ports. ROM circuit types 4001 are not alterable or reprogrammable. Usuage of the 4001 circuits would eliminate the requirement for IC circuits 232, 233, 240, 242 and 243. For such an arrangement, AND gates 1220 through 1223 could also be eliminated.

As illustrated in FIGS. 2A through 2E, CPU 230 receives all data from the associated computing scale system, four bits at a time, from lines 310 through 313, which lines originate on FIG. 3. Output signals from the microcomputer are transmitted via inverting amplifiers 260 through 263 and ROM output ports 242 and 243, as above stated. Register 242 is able to provide four outputs term ROM 1, bit 0 through ROM 1, bit 3. However, as used in the described embodiment, only ROM 1, bit 3 is employed, and this bit is transmitted out via line 223. Similarly, register 243 is able to provide four outputs termed ROM 2, bit 0 through ROM 2, bit 3, but only bits 0, 1 and 2 are employed. These three bits are transmitted out to appropriate locations via lines 210 through 212 respectively. It will be seen that output data for registers 242 and 243 are transmitted to both of said registers via lines 1210 through 1213 from IC 233 and that a select signal on one of lines 1201 or 1202 from decoder 241 selects the appropriate one of registers 242 and 243 for output of the data. Registers 242 and 243 are cleared by a reset signal on line 802 from FIG. 8. Likewise a reset signal on line 801 from FIG. 8 resets RAM 231 and CPU 230. Sync signals for use by the interconnecting interface circuits are provided by lines 251 through 253.

For test purposes a test signal may be provided to central processing unit 230 via line 1214 from an external test unit. There is also provided a socket 249, which is interconnected with central processing unit 230 for monitoring the operation thereof. A two phase clock is provided by the circuitry of FIG. 2A.

DATA MULTIPLEXING

The above mentioned input signals designated ROM 0, bit 0 through ROM 0, bit 3, which appear on line 310 through 313, respectively, are provided by multiplexers 303 and 304 as illustrated in FIG. 3C. Multiplexers 303 and 304 are enabled to receive and multiplex a total of up to sixteen inputs. Four of the inputs for multiplexers 303 and 304 are received via lines 320 through 323 from multiplexers 301 and 302 of FIG. 3B. Multiplexers 301 and 302 in turn are enabled to receive and multiplex a total of up to sixteen inputs, so that the interconnection of multiplexers 301 and 302 with multiplexers 303 and 304 enables multiplexing into the microcomputer of up to twenty-eight inputs. Selection of the data to be multiplexed into the microcomputer is controlled by 4-bit control words output from RAM 231 via lines 200 through 203. Lines 200 and 201 control multiplexers 301 and 302, and lines 202 and 203 control multiplexers 303 and 304.

The operation of the multiplexers may be understood by referring to FIG. 3A, wherein are illustrated a set of photosensors A through P, which provide outputs representative of the weight of a commodity placed on platter 21 of scale 20. The output from these photocells is provided via a set of diodes 314 and four level converting circuits to four lines 330 through 333. The photocells are addressed by a code appearing on lines 630 through 633 to produce a 4-bit Gray code on lines 330 through 333. Operation of such photocells and generation of the Gray codes is discussed in detail in Allen et al., U.S. Pat. Nos. 3,439,760; 3,516,504; and 3,557,353. However, in the Allen patent there are no photocells corresponding to photocells O and P, which are used for parity checking operating as hereinafter described.

For reading a commodity weight, the microcomputer generates four successive codes, which after processing by the interface circuits, appear one at a time as photosensor selection signals on one of lines 630 through 633. This in turn causes production of four successive portions of the weight information (in Gray code) on lines 330 through 333. These four codes are read into the microcomputer memory, where they are converted from Gray code to BCD form, as hereinafter described, for use in computation of a product value.

In order to read the Gray code from lines 330 to 333 into the microcomputer memory, these lines must be briefly connected by multiplexers 301 and 302 to the lines 320 through 323 and then through multiplexers 303 and 304 to lines 310 through 313. This connection in the multiplexers is accomplished by generating the number 8 in binary form (1000) on RAM output lines 200 through 203, noting that line 203 carries RAM 0, bit 3 which is the "1". Generation of this 8 and other steps in the photocell reading are performed in the RDWT and READ portions of the programs shown in Table V. Thus by generating the number 8 in binary form four times, once for each of four groups of four photocells, and using inverting amplifiers 260 through 263 in FIG. 2D (which are connected to lines 200 through 203) the microcomputer reads in four 4-bit words of coded weight data. The first three words and the lower two bits of the fourth word represent the commodity weight in Gray code form. The upper two bits of the fourth word are output bits from photosensors O and P and are used for a weight reading parity check.

Prior to each generation of the number 8, an output is generated by RAM 231, which causes a HI output from one of inverting amplifiers 260 through 263. This output is connected via one of lines 214 through 217 to a latching circuit 645 shown in FIG. 6. At the appropriate strobe time latches in circuit 645 will be set. The latch outputs are decoded and will cause a HI output on one of lines 630 through 633. A HI output on line 630 selects photosensors A, B, C and D, and the output from these photosensors is read through multiplexers 301 to 304 into the microcomputer during the succeeding generation of the number 8 on lines 200 through 203. Similarly, a HI signal on line 631 selects photosensors E, F, G and H, while a HI on line 632 selects photosensors I, J, K and L, and a HI on line 633 selects photosensors M, N, O and P. thus to read four weight digits in Gray code into the CPU, the CPU generates the 4-bit word 0000 at the output of latches 645 to select the first group of photosensors, and then generates the word 1000 (8) to multiplex the photosensor data through multiplexer circuits 301, 302, 303 and 304 onto lines 310 through 313, which in turn pass through the tri state gates 240 onto lines 1210 through 1213, through the interface IC 233 and over data bus lines 270 through 273 to the central processing unit 230. The tri state gates 240 provide I/O or open output circuit conditions in order that lines 1210 through 1213 can function as both input and output ports to the interface IC 233. Thereafter the central processing unit causes generation of the RAM word 0010, followed again by 1000 to read the second word of weight information onto memory. The next two words of weight data are read similarly by generation respectively of RAM words 0100 and 1000, each followed by the RAM word 1000. Further explanation of the weight reading operation is set forth below in connection with the discussion of the computer program which is stored in ROM. In this preferred embodiment of the invention, weight information is collected into the central processor by electrically energizing successive four cell groups of the photosensors in response to a computer command. The energized condition is maintained until turned off through the use of a latch memory 645.

The photosensor information is collected in real time during the photosensor energized period by sending the proper commutation command from the central processor to the multiplexers. The commutation command in the arrangement sets up the multiplixer (i. e., addresses the multiplexer) to allow the input from the energized four photo sensors to enter a ROM input port. It is of course possible in the alternative to employ a latch or memory to retain the selected multiplexer address and thereby maintain the multiplexers in the correct commutating condition for a prolonged period while the selected photosensors are energized briefly by the central processor in real time. Selection between these two alternate photosensor energization arrangements is best made after considering other requirements of the scale system.

To aid in more fully understanding the signal commutating operation of multiplexers 301 through 304, there is set forth in Table III a truth table, which governs the operation of each of multiplexers 301 through 304. In general the presence of any of RAM words 0000 through 0010 on the RAM output port lines causes the reading into memory of labeler status bits appearing on lines 610 through 613. Other multiplexers, as illustrated in FIGS. 6A through 6E, also respond to RAM port words to determine the labeler status information to be presented on lines 610 through 613. RAM port words 0100 through 0111 cause reading into memory of selected digits of price per pound appearing on lines 620 through 623 as will be apparent by reference to FIGS. 6A through 6E. Table III also applied to multiplexers 626 through 629, which appear on FIGS. 6B through 6D. It will be noted that RAM port word 0111 causes reading of two bits of price dead zone information, which are multiplexed into lines 620 and 621.

RAM words 1001 through 1100 cause the reading into memory of control information which may be selected by setting of performance selection switches 341 through 352. While shown in FIG. 3B as being switches, the switches will ordinarily be located in an inaccessible location and will be set by factory or maintenance personnel. Accordingly switches 341 through 352 could be replaced by jumpers.

Switches 341 through 344 provide four bits of weight dead zone selection information to be used by the microcomputer as hereinafter described. Switches 345 and 346 provide two bits of rounding control information for use in rounding off the computation of the commodity value. Switch 347 is also a rounding control switch, and, when closed, instructs the microcomputer to employ a quarter round routine which is part of the computer program written for implementation of this invention.

Switches 348 and 349 respectively select five kg and ten kg routines within the computer program. These routines enable usage of the system for metric weight measurement, with maximum scale readings representing respectively either five kg or ten kg readings. In each case closure of the appropriate switch causes the microcomputer to select the proper conversion factor for converting a measured reading in pounds into metric units. In either case, where the scale is to be used for metric measurements, the spring, which is used for measurement in pounds, may be replaced by a spring of somewhat different stiffness, so that the multiplication factor introduced by the five kg or ten kg routine need accomplish only a part of the total required conversion. The five kg and ten kg routine, when selected, may also cause performance of special logic functions required by weights and measure practices in countries wherein metric standards are employed.

Switches 350 and 351 provide two bits of information for control of a waiting or time delay routine as described below. Finally, closure of switch 352 calls for a logic operation required by the microcomputer in order to cause printing of labels showing actual measured weight and a fixed commodity value. This is an option provided as a special case for labeling of commodities which are sold by count (i.e., fixed value for each package) rather than by weight.

PRINTER AND SCAN PULSE GENERATOR OPERATION

As discussed above, the printer has for each digit a pair of segment gears mounted on a rocker shaft, which rotates first in one direction and then in the other. During forward motion the rotational position of the rocker shaft is monitored by a photocell circuit, so that the computer can actuate or fire the solenoids 551 through 558 at appropriate times for stopping the primary segment gears while the secondary segment gears continue to a home position. Thereafter, during return rotation of the rocker shaft, the primary and secondary segment gears move together and set up the printing wheels for printing. The scanning network, which monitors rotation of the rocker shaft to inform the microcomputer regarding the position thereof, is illustrated in FIG. 4.

The FIG. 4 scanning network generates a pulse of uniform and predictable time duration in response to the print wheels of the printer-labeler moving through a possible printing position. As indicated in the portion of this specification which describes the printer-labeler subroutine, pulses generated by this printer scanner are used to tell the microcomputer when the print wheels have moved between printing positions. The circuit of FIG. 4 provides interface between two free-running portions of the scale system, the microcomputer clock and the printer mechanical elements.

In FIG. 4, the scanner which moves with the print wheels is identified with the number 403, the digits zero through eight on the scanner indicating light transmitting apertures in the scanner, while the photocell which responds to the scanner light pulses is shown at 402. Light falling on photocell 402 provides a positive going input to the threshold circuit 404. The circuit of FIG. 4 also includes a 4-bit counter 401, having clock, load parallel, enable parallel and data inputs and four output lines labeled QA-QD. The 4-bit counter 401 is connected to a four-input NOR gate 408 which has an enable line 415 that is always held in the enabled state; the gate 408 may be a type 7425 gate as listed in the component identifying table of this specification.

In response to an aperture of scanner 403 transmitting light to photocell 402, the circuit of FIG. 4 provides an output pulse on line 417 which is positive going and remains in the positive state while counter 401 counts 14 clock pulses as received from the central processor on line 251. This control of the signal on line 417 is achieved by commencing the counter 401 with the first clock pulse following change of the scanner input signal from threshold circuit 404 from the low or dark state to the high or light state and continuing the count in counter 401 until the appearance of a carry pulse on line 413 when the counter has reached a count of 15. This operation is achieved by using the gate 408 to decode the initial or zero state of counter 401; the condition of all zero inputs to the gate 408 providing a high output and thereby a low output from the inverter 410 to the load parallel control line of counter 401.

In the presence of the load parallel input, the first positive going information on the A input of the counter, i. e., the positive going pulse from the photocell 402, is accepted into the low order bit of the counter and results in changing the output state of gate 408, which in turn, removes the load parallel input from counter 401. After receiving the input signal on the input A terminal, the counter 401 steps through the states between zero and fifteen in response to central processor clock pulses received on line 251. The change in output state of the gate 408 from high to low in response to receipt of the first clock pulse on line 251 also provides a change in output state from low to high from the gate 411 thereby initiating the printer output pulse to the central processor in response to the first scanner pulse from the photocell 402.

The output of gate 411 on the line 417 remains in the high condition until the line 413 changes from the low to high state in response to the carry output of counter 401, this occurring after the required number of central processor clock pulses on line 251 have been counted. Once line 413 changes from low to high state to indicate the carry pulse, the line 414 changes from the high to the low state, thereby disabling the counter from further operation until the photocell 402 sees a dark condition and provides a low output on the line 406 to reset the counter and await the next arrival of light on photocell 402.

Thus integrated circuit 401 and its associated circuitry functions like a one-shot (mono-stable vibrator), producing pulses on line 417, for multiplexing into the computer through multiplexer 626 (FIG. 6B). The computer employs these pulses to time the firing control signals for the printer solenoids. In addition to the nine pulses provided by observation of scanner fan 403 by photocell 402, there is a home position pulse generated by the computer at the time it sends data to the printer for printing the number "9". For the embodiment herein described there are eight type wheels, which rotate together, each of which may be stopped at any of 10 positions for printing of the numbers 0 through 9 on the label.

As previously stated, the scanner pulses on line 417 provide an input to multiplexer 626, which is interpreted as a labeler status bit. Multiplexer 626 and multiplexer 629 multiplex all labeler status bits, and these bits appear as 4-bit binary words on lines 610 through 613, which are transmitted to multiplexers 303 and 304. Multiplexing of labeler status bits as well as price per pound switch output from lines 520-529, is controlled by 4-bit RAM output words on lines 214 through 217. These RAM output words are gated through AND gates 640 through 643 for application to the multiplexers.

The RAM words on lines 214 through 217 (RAM bit 0 through RAM bit 3 respectively) are also supplied through gates 640 through 643 to a quadruple D-type flip-flop 644 and to a 4-bit latch 645. The output from latch 645 is decoded by a BCD to decimal decoder 646, which has four output lines 630 through 633. These lines are used, as above described, to address the weight recording photocells of FIG. 3A. Three of the outputs are also applied via amplifiers to lines 601 through 603 for price per pound switch addressing. These three lines address the pennies, dimes, and dollars switches 31 through 33 as previously discussed in connection with the description of FIG. 5. For each address a response may be received back via one of lines 521 through 529 indicating one of the decimal numbers 1 through 9. For the system configuration used in the U.S., no response on any of the lines 521 through 529 represents the decimal number zero. For use in metric countries the number zero is represented by a response on line 520. These responses are applied to multiplexers 627 and 628 for multiplexing onto lines 620 through 624.

For reading of price per unit weight information a binary 0 (0000) on RAM output lines 214 through 217 latches up line 601 to check the pennies switch, and thereafter binary equivalents of the numbers 4, 5 and 6 appear in sequence on RAM output lines 214 through 217. The number 4 checks the decimal digits 1 through 3 (lines 521-524), the number 5 checks the decimal digits 5 through 8 (lines 525-528) and the number 6 checks the decimal digits 9 and 0 (lines 529 and 520). After the pennies digits have been checked and multiplexed back to the CPU, the addressing of the dimes is accomplished by generating a binary or RAM output lines 214-217. Thereafter the status of lines 520 through 529 is again checked, and finally a binary 2 is generated on the RAM output lines for addressing and checking of the dollars switch. In FIG. 6E a spare inverter is provided connected to line 633 for incorporating tens of dollars, etc., input. It will be appreciated, of course, that the pennies, dimes and dollars switches may represent three digits of price per unit weight information in any desired currency.

Multiplexer 628 has two inputs from switches 647 and 648 in addition to the above mentioned price per unit weight inputs. These two inputs are read into memory by generation of a binary 7 on the RAM output lines and indicate a price dead zone upper limit. For some applications it is desired to inhibit the system operation unless the indicated price per unit weight is greater than some preset minimum amount. Switches 647 and 648 may be set for reading into memory any of four different lower limits representing the numbers 0 to 3. A routine identified as MINP is used by the computer in connection with the minimum price check. The program listing as set forth in Table V presents a detailed description of the MINP routine.

Included within the bits of labeler status information multiplexed by multiplexers 626 and 629 are other bits relating to the status of additional equipment, which may be used in combination with the computing scale system. The input information for multiplexer 629 appears on lines 650, 651, 652, 712, 654, 504, 656 and 711, while input information for multiplexers 626 appears on lines 661, 657, 658, 659, 710, 625, 660, 661 and 709. Multiplexing control for multiplexers 626 and 629 is governed by signals appearing on lines 670 and 671 which are connected to terminals SA and SB respectively. These multiplexers operate in accordance with the truth table presented in Table III, and the multiplexed output at any time can be determined by noting that the input at terminal SA of both multiplexers corresponds to bit 0 of the RAM output words, while the control signal at terminal SB of both multiplexers corresponds to bit 1 of the RAM output words. In all cases for multiplexing of label status information through multiplexers 302 and 303, bits 2 and 3 of the RAM output words must both be 0 (these bits appear on lines 202 and 203 respectively for application to multiplexers 302 and 303).

Line 650, which is one of the input lines for multiplexers 629, indicates the presence of an indexing and label application system of the type described in Treiber U.S. Pat. No. 3,732,966. If such a system is being used, with the computing scale system, then line 650 will be grounded. Otherwise, a +5 volt signal will appear at line 650.

Line 651 is an output from latch 624 and indicates that the system is in its first cycle of operation. Line 652 is controlled by the signal on line 503 and indicates that the secondary segment gears, which control print wheel positioning, have reached the home position. Line 712 indicates the status of one of four solenoid check bits. The other three of these four solenoid check bits appear on lines 711, 710 and 709, the latter two lines being connected to provide inputs for multiplexer 626. These solenoid check bits indicate that solenoid drivers, which control the position of the print wheels, have been fired satisfactorily. The operation of these solenoid drivers and the generation of the solenoid check bits is described in detail below in connection with the description of FIGS. 7A and 7B.

Line 654, which provides another input to multiplexer 629, indicates the presence of an error signal on line 507. Such an error signal appears on line 507 if switches 546 and 547 have been operated by movement of any of the price per unit weight knobs 31 through 33, or if switch 545 has been operated by removal of commodity key 37.

Line 504 indicates operation of the repeat switch 71. Repeat switch 71 is manually operated whenever it is desirable to print another label exactly like the one previously printed. This can be done as long as the weight is left on the scale or removed from the scale while in the repeat mode. If the scale is unloaded and then loaded again with the same or a different weight, while in the repeat mode, the system will go into an error status.

Line 656 carries a computer start suppression signal. The signal on this line is controlled by the position of a switch 662. When the computing scale system is used in combination with an indexing and labeling system of the type described in Treiber '966, switch 662 will be closed by a cam during any period of time while a package is being moved. This in turn suppresses any computing cycle during package movement.

Line 657, which provides one of the inputs to multiplexer 626, provides a tare warning indication as generated at the Q1 output of latching circuit 624. The output signal at the Q1 terminal of the latching circuit 624 is set by movement of commodity key 37, which operates switch 590 (FIG. 5A), and which in turn is connected to line 508. The signal on line 508 is sensed at terminal IS.sub.1 of latching circuit 624. The output at terminal Q1 of latching circuit 624 is reset by an output on line 607 from tare circuit 663.

Tare circuit 663 is operated by touching of knob 23. Circuit 663 normally oscillates, but while knob 23 is being touched, the circuit stops oscillating, and line 607 goes from a normally non-conducting to a conducting condition, thereby grounding the base of transistor 664 to reset the Q1 output of latching circuit 624 and provide a HI tare indication for input to multiplexer 626. At the same time, transistor 698, which was previously conducting, ceases conducting to turn off the warning light 24. Line 658, which provides another input for multiplexer 626, provides a manual start indication, and this indication is controlled by the status on line 502. Line 502 normally carries a zero voltage and becomes negative when manual start switch 72 is operated. Operation of the manual start switch permits printing of a label, while the scale is within the weight dead zone. However, if either of switches 348 or 349 (FIG. 3B) is closed for indication of metric system operation, then operation of manual start switch 72 will not permit label printing anywhere within the weight dead zone except at zero weight, but switch 561 must be closed and switch 562 opened as previously discussed.

Input line 659 of multiplexer 626 is connected to line 417, which carries scanning pulses generated as discussed above in connection with FIG. 4. Input line 625 for multiplexer 626 is the output line from terminal Q3 of latch circuit 624. The status of this line indicates whether or not a printed label has been removed from ticket ejector mechanism 35. Normally, printed labels are supplied to ejector mechanism 35 with the adhesive side up. The labels are applied to packages by pushing the package against the label, and this in turn operates ejector switch 540. The ejector switch is normally closed and is opened during label application. This opening of the ejector switch resets the Q3 output of latching circuit 624. The Q3 output is set by operation of cam switch 543 (FIG. 5A), which is connected to line 530. Cam switch 543 is operated by a cam after the print wheels have been set up and before a label is printed.

Line 660 normally carries a +5 volts signal as an input to multiplexer 626, but the input is switched to ground by closure of a manually operated switch 665. Switch 665 may be physically located at any convenient place on register printer 30, computer 25, or scale 20. This switch is termed a "by-count" switch, and closure of this switch tells the computer to enter the "by-count" subroutine which is hereinafter discussed.

Line 661, which is connected to line 530, carries a cam switch status signal. As discussed above, line 530 is connected to a zero volts through switch 543 and operates as a set signal for output Q3 of latching circuit 624.

In addition to providing inputs to latching circuit 645, and controlling multiplexers 626 through 629, AND gates 640 through 643 also provide RAM output data to latching circuit 644. Outputs from latching circuit 644 cause generation of a printer start signal on line 606, pulses to trigger the ejector motor SCR on line 604 and an error light signal on line 605. Lines 604 through 606 are all connected to circuitry shown in FIGS. 5A and 5B. A clock signal for latching circuit 644 is provided by line 714, and a clear signal is provided by line 803. Line 803 also provides a clear signal for latching circuit 645, while clock signals for that latching circuit are provided by line 713. The signals 713 and 714 are developed in FIG. 7A from ROM output information.

Referring now to FIGS. 7A and 7B, it will be seen that there are eight Darlington amplifiers 731 through 738, which are connected to eight output lines 701 through 708 respectively. Operation of Darlington amplifiers 731 through 738 connects the respective lines 701-708 to ground thereby completing a circuit from the minus 24 volt source through respective labeler print wheel solenoids 551 through 558 (FIG. 5B). As previously discussed, the firing of these solenoids interrupts movement of associated primary segment gears to cause correct set up of the type wheels which print the labels.

Conduction of Darlington amplifiers 731 through 734 is controlled by latching circuit 722, and conduction of Darlington amplifiers 735 through 738 is controlled by latching circuit 721. Latching circuits 721 and 722 in turn are controlled by RAM output control words appearing on lines 204 through 207. As previously discussed in connection with FIG. 4, scanner output signals on line 417 are multiplexed into the computer memory to indicate the position of the rocker shaft, which causes forward rotational movement of primary segment gears associated with each of the print wheels.

In order to set up the print wheels, it is necessary to fire the solenoids 551 through 558 at appropriate times. After the computer has multiplied the commodity weight times the price per unit weight to obtain a commodity value or total value, it is stored for determining when each of solenoids 551 through 558 should be fired. At this point the printer is started by sending a printer start signal on line 606 (FIG. 6E). Immediately following printer start all solenoids for those print wheels which are to print the numeral 9 are fired. The first pulse on line 417 tells the computer that it is time to fire the control solenoids for all print wheels which are to print the number 8, and at this time the computer generates two RAM output words which will, through latches 721 and 722, cause conduction of the appropriate Darlington amplifiers and firing of the correct solenoids. The next pulse on line 417 similarly causes firing of the correct solenoids for setting of those printing wheels which are to print the number 7. This process continues through the number zero.

Clocking and clearing of latching circuits 721 and 722 is under the control of a demultiplexing circuit 720 and a reset signal appearing on line 804 from circuitry illustrated on FIG. 8. Demultiplexer 720 is strobed by a signal appearing on line 223, which is ROM 1, bit 3, as generated by the ROM 1 output port (IC 242 of FIG. 2E). Data signals and output line selecting signals for demultiplexer 720 are provided by lines 210 through 212, which respectively carry bits 0 through 2 of ROM 2 output words from IC 243. In addition to controlling the clocking and clearing of latching circuits 721 and 722, demultiplexer 720 provides output signals on lines 713 and 714, which are clocking signals for latching circuits 645 and 644 (FIG. 6E), respectively.

Whenever any of Darlington amplifiers 731 through 738 becomes conductive it causes a voltage drop across a corresponding one of resistors 741 through 748. This voltage drop when compared with a reference produces a data bit at an associated one of eight input terminals to multiplexer 723, and this data bit is used as a check bit to indicate that the associated one of solenoids 551 through 558 has been fired. The solenoid check bits multiplexed through multiplexer 723 appear as outputs on lines 709 through 712, which are multiplexed through multiplexers 626 and 629 and read into the computer and compared with print wheel solenoid data which was previously stored in the computer memory and sent to the print wheel solenoids, if the data does not compare an error results. This comparison is performed in PSCK subroutine in the output to printer portion of Table V. Selection of either the A inputs or the B inputs to multiplexer 723 is under the control of a signal appearing on line 609. A LO signal on line 609 selects the A inputs, while a HI selects the B inputs. Line 609 is tied to line 630, which is one of the latched RAM signal output lines from integrated circuit 646 of FIG. 6E.

MASTER RESET

As illustrated in FIG. 8, there is provided a circuit which provides master resetting of the entire scale system. This circuit includes a counter 805, which counts sync pulses generated on line 252 by the computer. This sync pulse is generated once every eight clock times by the CPU as described in the Intel manual. Counter 805 is cleared by a signal on line 505, which is generated by operation of the scale system reset switch 70 which is shown in FIG. 1. Whenever counter 805 is cleared and flip-flop 806 is set, reset signals are placed on lines 801-804. When the reset switch is released by the operator, counter 805 starts counting, and upon reaching full count turns off reset flip-flop 806. This in turn terminates counting by counter 805 and terminates the reset signals on line 801 through 804. The reset signal on line 801 is applied directly to the CPU, and the reset signal on line 802 is used for clearing integrated circuits 242 and 243, which serve as output ports for ROM 1 and ROM 2 respectively. The reset signal on line 803 is used as a reset for latching circuits 644 and 645, as above discussed, and the reset signal on line 804 is used for clearing integrated circuits 721.

During power up conditions line 505 is held in the low condition temporarily by the capacitor 899 in FIG. 8 which charges slowly through resistor 898 to clear counter 805 and set flip-flop 806, thus initiating the above described reset functions.

WEIGHT PARITY VERIFICATION

A portion of the scale chart, which is used by scale 20 is illustrated in FIG. 9. The illustrated portion of the chart covers the weight range from 00.26 through 00.32. In the United States this would be a reading of pounds, but in metric countries the digits would have a different significance. The chart consists of a series of tracks A through P, which have apertures cut therein as illustrated. Tracks A through N correspond to the tracks of the scale chart illustrated and described in Allen et al, U.S. Pat. No. 3,557,353. Track O and P are optional odd and even parity tracks respectively.

As described in the Allen patent this chart is used in combination with a light source and a series of photocells, the photocells being illustrated schematically in FIG. 3A by the letters A through P and diagrammatically in FIG. 9 by the reference numerals 901 through 916. In FIG. 9 it is to be understood that chart observation occurs along a slit line such as that indicated at 941, the chart being movable under the slit. The major portion of the FIG. 9 chart is opaque, but the apertures (represented by shaded areas 917) provide areas of translucency, which may be sensed by the photocells associated with tracks A-N for reading weight. As described in the Allen patent, the code represented by the illustrated tracks A through N is a Gray code of the binary-cyclic-biquinary type, and the apertures are cut in the chart to provide a transition at midpoints between the weight readings. Although not illustrated in FIG. 9, the E and G tracks have apertures extending below 0 and beyond 25.00 pounds to provide a signal when the balance position of the scale is below 0 or above its calibrated capacity. Aperture areas 918 and 919 provide even and odd parity checks for observation by photocells positioned at 916 and 915 respectively. Even parity indicating in this instance that the total number of observed bits including the parity bit is even.

In order to understand the operation of the O and P channels, Table IV has been constructed to give the readings of the photocells for weights ranging from 00.26 through 00.32. In each case a one or HI photocell output occurs when an aperture is in front of the associated photocell, while a zero occurs when an opaque area is in front of the photocell. The data of Table IV may be verified by comparison against FIG. 9. It will be seen that an aperture appears in the O track whenever the corresponding weight reading is represented by an even number of apertures. The aperture in the O track provides a total number of apertures which is odd for an odd parity check. Similarly an aperture appears in the P track, whenever an odd number of apertures appear at corresponding positions in the tracks A through N.

One of the major problems with reading and parity verifying a chart of the type described above is that it is impossible in practice to insure that the parity photocell and the weight reading photocell will consistently change output states at exactly the same chart position (i. e., cell resistance and chart line tolerances). If an attempt is made to check parity at a transition point weight reading, a parity error signal may be generated and cause an unwanted interruption of the computing cycle. That problem is circumvented in accordance with this invention by extending the parity apertures 918 and 919 slightly beyond their proper limits for parity checking, as indicated by the small shaded areas 920. As a result, whenever the scale comes to rest at a chart transition point between two weight readings, both parity photocells P and O will be lighted. In the preferred embodiment this condition exists over about 25 to 30 percent of the chart range, the extent of such overlapping provided being dependent on the attainable accuracy in positioning and sizing chart apertures in the chart manufacturing process. In an alternative embodiment the parity apertures 918 and 919 could be shortened, so that chart transition positioning would be represented by non-conduction or a LO output from both of photocells 915 and 916.

As discussed in more detail below, the system computer stores the reading of all photocells and checks the "O" and "P" readings, before making any parity checks. If a one is stored in memory for both the "O" and "P" channels, then the computer makes no parity check on the weight reading and proceeds to use the unverified data as read from channels "A" through "N" for computation of product value. On the other hand, a zero in memory for either of the "O" or "P" channels will cause execution of a parity checking routine and will produce an error condition if an improper parity check is made.

As described above, both of the parity checking tracks have apertures or translucent areas extending into the transition regions for the other tracks. It will be appreciated, however, that such an arrangement is not necessary. As an alternative arrangement there could be provided a single parity checking track having no transition region overlap and a transition indicating track having translucent areas only in the transition regions. For such an arrangement the computer would first check the output of the transsition indicating track and then proceed to perform a parity check on the reading from the parity checking track only if no transition condition is detected.

In still another embodiment there could be a transition indicating track and a single parity indicating track of the type illustrated in the preferred embodiment of FIG. 9. For this last arrangement the transition condition would be ascertained by observation of the reading from both tracks, while the reading from only the parity indicating track would be used for parity checking. Finally, the system could utilize a single parity track, such as track O and could observe this track with two photocells displaced from each other a distance representing an integral odd number of weight units. Such photocells might be termed O and P photocells and would provide output signals identical to the signals from photocells positioned as at 915 and 916 and viewing the O and P tracks illustrated in FIG. 9. Such an alternative arrangement is illustrated diagrammatically by the dotted circle 916a, which represents the position for a photocell to replace the photocell located at 916.

COMPUTER ARCHITECTURE AND PROGRAMMING

The computer program in Table V sets forth the sequential operations required for controlling the scale and labeler of the present invention. Table V gives from left to right: 12-bit ROM address locations, 8-bit instructions stored at the indicated ROM locations, mnemonic names for subroutines, mnemonic equivalents of the indicated 8-bit instruction words, and programmer's comments. The Table V program listing is assembled from a programmer's hand prepared listing using an assembly routine available from Intel Corporation, Santa Clara, California. In the Table V program listing the mnemonic instructions and 8-bit codes are in accordance with the instruction description contained in Table II. In using Table II it is to be noted that the RRR indications appearing in connection with the FIM, SRC, FIN, and JIN instructions refer to the address of one of eight index register pairs in the CPU. The RRRR indications appearing in connection with the INC, ISZ, ADD, SUC, LD, and XCH instruction refer to the address of one of sixteen index registers in the CPU. The sixteen index registers may be addressed as one of eight pairs using the RRR form of address or as one of sixteen registers using the RRRR form of address depending upon the instruction used.

In regard to the instructions relating to RAM status characters it will be noted that the RAM chip has four registers, each with twenty 4-bit characters subdivided into 16 main memory characters and four status characters. It should be further noted that as to the input/output and RAM instructions, the RAMs and ROMs operated on are those which have been selected by the last preceding SRC instruction. The register pair designated by the SRC instruction contains 8-bits, and the four highest ordered of these bits indicates the ROM Chip number, that is, the number of one of ROMs 234 through 239 in the present system. These ROMs are designated ROM 0 through ROM 5 respectively. The eight bits in the register pair incorporated into an SRC instruction also indicate a RAM and a main memory character within the RAM. The first two, or highest order, bits indicate the RAM number. (In the case of the present program there is only one RAM, designated RAM 0.) The next two bits indicate the register number within the RAM, and the last four bits indicate the number of the main memory character within the selected register.

A single SRC instruction may be used for both ROM and RAM designation. Since a ROM or RAM designation once made remains effective until the next SRC instruction is executed. Each ROM has memory capability for storing 256 8-bit instructions, so that six ROMs illustrated in FIG. 2C have a capacity for 1,536 instructions. The program in Table V uses fewer than this number of instructions, the entire Table V program being loaded in ROMs 234 through 238. Referring again to Table II, it will be seen that the JCN, FIM, JUN, JMS, and ISZ instructions are twoword instructions. Where such two-word instructions are loaded into memory, the program listing of Table V indicates the address of only the first of these two words.

For an understanding of the interaction between the computer and the system hardware components, it is helpful to refer to the OUTD and OUTC subroutines set forth commencing at memory location 733 on page 17 of Table V. The OUTD subroutine is used to outputting system control data such as multiplexer control signals (i.e. multiplexer addresses) print wheel set up pulses, photo sensor exciting signals and price switch selections through the RAM output port. The outputted address data appears as 4-bit codes at the output of inverting amplifiers 260 through 263 for transmission on lines 200 through 203, 204 through 207, and 214 through 217. The OUTD subroutine begins with the instruction SRC PO. This instruction causes RAM addressing in accordance with data previously loaded into register pair 0, most commonly by a FIM instruction. The data loaded into register pair 0 prior to execution of the OUTD subroutine always has the digits 00 stored in the two most significant digit locations (which are in register 0), so that a signal selecting RAM 0 (the only RAM used) will be generated by the CPU on line 275. For execution of the OUTD command, it makes no difference what data is stored in the two least significant locations within register 0 (i.e. bit positions 4 and 5 of the 8-bits within the register pair). However, the data stored in bit positions 0 through 3 are important, because this data is loaded into the accummulator by the instruction LD 1 and becomes the addressing data used by the hardware; this data is output from the RAM by the instruction WMP. After outputing this data the program executes the test instruction JCN T1 which merely stops the program if a test signal is present at line 1214 of FIG. 2D. Assuming that a test signal is not present, the program then branches back via the BBL instruction to the routine from which an exit had been made to OUTD.

The OUTC subroutine commencing at memory location 739 on page 17 of Table V executes a series of instructions, which cause generation of output signals from ROM port 1 (line 223) and ROM port 2 (lines 210 through 212). Prior to execution of the OUTC subroutine register pair 1 is loaded with the bits 0010 in register 2 for addressing ROM 2 (enabling integrated circuit 243), and other bits in bit positions 0, 1, and 2 of register 3 corresponding to the output desired on lines 210 through 212. This data in register 3 is loaded into the accumulator and thereafter written onto lines 210 through 212 by the instruction WRR in memory location 741. The data output on lines 210 through 212 is applied to demultiplexer 720, as above described, for use by the system hardware.

During the period of time that the OUTC output signals are present on lines 210 through 212, the FIM P1 24 instruction in memory location 742 in the OUTC subroutine also loads the binary word 00011000 into register pair 1. The subroutine then performs the instructions SRC, P1, LD 3, and WRR, which results in enabling of integrated circuit 242 and outputing of a HI signal on line 223 (which the computer views as being the output line for ROM I, bit 3). This signal on line 223 serves as a data strobe. This strobe is terminated by the instructions LDM O, and WRR. These latter two instructions load 0000 into the accumulator and write the 0 in bit 3 on line 223.

Data generated by the system hardware is loaded into the computer, as above described through integrated circuit 240 and lines 1210 through 1213. The data on lines 1210 through 1213 is read into the accumulator at appropriate times on the program by execution of the instruction RDR. Prior to execution of such an instruction, however, it is necessary to execute an SRC instruction, which will select ROM 0 thereby enabling IC 240 via line 1200 and NAND gate 1225.

EXECUTIVE ROUTINE

FIG. 11 in the drawing illustrates the steps in a normal scale weighing operation in flow diagram form. The FIG. 11 sequence may be regarded as the scale executive program, with the the steps illustrated being performed in each scale weighing operation and with several of the steps illustrated being performed as program subroutines which are described in subsequent figures of the drawings. The flow diagram of FIG. 11 describes an embodiment of the invention employing a programmed special purpose computer, i.e. an integrated circuit microprocessor. The steps of the FIG. 11 flow diagrams could of course be performed by wired dedicated electronic logic circuits in an alternate embodiment of the scale invention. In the present section, flow diagram steps are described both with respect to scale functions and with identification of the program instructions performing the indicated steps. In the description program steps are identified by memory locations, memory locations being the first 12-bit binary word in the left-hand column of the Table V program listing. Additional details regarding instruction addressing and memory location identification are contained in the Intel Users Manual referred to above. Since memory locations are identified by decimal digit numbering in the following description, conversions between binary bits and corresponding decimal digit numbers are indicated for a portion of the instructions on each page of Table V.

Referring now to FIG. 11, and the program listing of Table V, the scale operation commences with loading a time delay constant of 252 into register pair 7 for subsequent use in a wait operation, this being followed by the outputting of multiplexer control information, i.e. multiplexer addressing, which will connect the ROM dataport with the printer/labeler sensing switch indicating the printing mechanism to be in the home starting position. The printer home position switch status is tested in the decision block 1102, FIG. 11A, this test being the instruction JCN at memory location 009 of the Table V program. If the printer is found not to be in the home position, the scale goes into an error condition employing the subroutine at memory location 158 on page 4, Table V. If the printer home position status test is satisfied, the program jumps to the waste time (time delay) subroutine at memory location 752, page 18 of Table V.

Following the time dealy, a test is made as indicated in the block 1104 of FIG. 11 to determine if the home position test has been performed a sufficient number of times, this test being performed by the ISZ instruction at memory location 013. The repeated testing of printer home position is incorporated into the program to assure that the computer power supplies and the photocell exciting lamp have reached steady operating condition following power turnon. If the decision in block 1104 indicates the time for reaching steady state conditions has not elapsed, the preceding program steps are repeated as indicated by the path 1106. Once the decision in block 1104 is satisfied, the program proceeds to the program home position which is identified with the circle 1108 in FIG. 11 and the notation at memory location 015 in the Table V program listing.

Upon leaving the program home position the system interrogates four mechanical switches, the "first-cycle" indicating switch, the "repeat" switch 71, the "manual start" switch 72 and the "by-count" switch. The "manual start" and "repeat" switches are located on the labeler control panel as shown at 72 and 71 in FIG. 1. The reading of these control switches is accomplished by sending out the appropriate multiplexer addresses, reading the resulting switch data into the accumulator and transferring the read-in data to storage in the RAM as indicated by block 1109 following program home and by the series of Table V program steps ending with the instruction WRO in memory location 020. Testing of the "manual start" switch status signal is performed by the JCN instruction in memory location 030 on page 1 of Table V, this test being indicated by the block 1110 in the FIG. 11 block diagram. The OUTA subroutine on page 17 of Table V is used to actually set up the appropriate multiplexer addresses.

The "manual start" status bit is interrogated immediately after the memory storage operation by the two RAL instructions and the JCN instruction at memory locations 021-023. If the test of block 1110 indicates the "manual start" status bit was set, there follows a series of steps which modify the required number of trips through the motion detect subroutine needed to establish a no-motion condition, it being desirable for the system to accept a manual start command without requiring a prolonged closure of the "manual start" switch by the operator while the motion criteria is satisfied. By adding eight to the "trips through" counter as indicated by the block between blocks 1110 and 1112 in FIG. 11 the normally required sixteen trips through the motion detect sequence without detecting motion is decreased to a lower number enabling a rapid determination of manual start no-motion. As indicated by the steps surrounding the block 1112, if the addition of eight to the "trips through" counter produces a carry, the program proceeds to the junction 1114; the program also arriving at junction 1114 where the "manual start" switch status was not set or following the writing of the "trips through" counter sum back into the trips through counter in the block 1113 in the event no carry resulted.

The manual start switch 72 on the labeler control panel in FIG. 1 is provided primarily for use during servicing of the scale system; in addition, this switch may be employed to initiate the printing of a label while the scale is in the weight-dead zone or printing a second label relating to a package which remains on the scale without intervening scale motion. Since most such uses of the manual start switch 72 occur after the scale has become motionless, it is feasible to relax the rather rigorous requirement imposed in the motion detect subroutine for the termination of motion when the scale is operating on a manual start command. This relaxation of the motion cessation requirement allows the manual start switch 72 to be read in real-time while the manual start switch is manually closed as opposed to requiring the use of a flip-flop or memory element to remember the manual start switch closure until needed by the computer program. With the relaxed, no-motion criteria, the computer program interrogates the manual start switch 72 with sufficient frequency to capture a manual start command while the operator holds the switch closed.

Following the junction 1114 the scale prepares for a waiting period wherein the waste time routine at memory location 752 on page 18 of Table V will be employed. This second waste time sequence assures that the program steps prior to motion detect consume sufficient time for the motion detect weight samples to be compatible with the scale mechanical movement as is explained in the specification topic relating to motion detection. The JMS instruction at memory location 062 will provide entry into the waste time routine for this use. The steps immediately following junction 1114 up to the block 1115 in FIG. 11 are concerned with the waste time routine. The instructions performing waste time housekeeping steps are located between memory location 031 and 046 on pages 1 and 2 of Table V.

Commencing at block 1115 in FIG. 11 is a series of instructions which interrogate the printer home position switch to determine if a label has been printed and starting of the label ejector motor is required, use of the ejector motor being necessary if the printer has left the home position. Turning off or maintaining the ejector motor in the off position is appropriate if the printer has not departed home position. In the Table V program the home position steps commencing with block 1115 and ending at block 1118 are performed by the instructions in memory location 047 through 061 on page 2 of Table V.

Following the ejector motor sequence, the waste time subroutine previously prepared for is executed as indicated at block 1118 with instruction JMS WAST at memory location 062 and 063 of Table V providing access to the waste time subroutine. This particular waste time interval is also described in the portion of the present specification titled motion detection and as indicated above serves to make the program repetition cycle and the scale mechanical response time compatible.

The motion detect subroutine follows the waste time sequence indicated at 1118 in FIG. 11. The motion detect sequence is represented by the blocks 1120 and 1122 in FIG. 11 and is accessed by the JMS MOTN instruction at memory location 064 and 065 on page 2 of Table V. This command provides a jump of program control to memory location 292 on page 7 of Table V. The steps in the MOTN subroutine commencing at memory location 292 are described under the specification title "motion detection" herein. Testing of the "trips through" counter as indicated in the block 1122 of FIG. 11 is performed by the instruction JCN NZA at memory location 067 in Table V.

Upon satisfying the no-motion criteria of the motion detection subroutine, the program performs the series of instructions in memory locations 069 through 080 which determine if the label printed in a previous trip through the program has been removed from the label delivery chute, it being desirable that the scale operation and the printing of a second label be inhibited until the first label has been removed in order that confusion between labels be avoided.

As indicated at the block 1124 in FIG. 11, if the previous label remains on the label delivery chute, the program branches back to junction B following the decision block 1110 and repeats continuously the steps between this point and the block 1124 until the previous label taken test is satisfied. The steps in this repeated loop make use of the shortened "Manual Start" motion cessation criteria described above in order that repetition of the "previous label taken" test occur at a desirable rate.

When the present scale system is connected to automatic package weighing and label preparing equipment of the type disclosed in Treiber U.S. Pat. No. 3,732,966 wherein packages are conveyed to a scale weighing platform, weighed and appropriately labeled, it is found desirable to condition the start of a weighing and label preparing cycle upon the mechanical movement which places a package on the scale platform rather than depend on the scale detecting a cessation of platter motion as is usually done to start a weighing and label printing cycle. If commencing of a weighing cycle is based exclusively upon motion cessation, it is found, in the instance of two similar packages of small weight, that the scale may appear to come to rest prematurely while a portion of a second package is yet on the package transporting conveyor since little scale travel is needed to change between the first and second package indicating positions. This would, of course, produce an erroneous weight reading and an incorrect label.

By locating a cycle sensing switch in the package transporting equipment in a location responsive to the completion of an operating cycle and interrogating the status of this switch with the computer program, weighing and labeling errors of this type are eliminated. In the present weighing system the name "computer start suppress" is used to identify the switch and program steps which prevent the premature start of a weighing and label preparing cycle before the transported package is fully on the weighing platform.

In FIG. 11, the block 1126 indicates the program steps associated with the computer start suppress sequence, this sequence involving the instructions at memory location 084 - 087 on page 2 of Table V. If the package transport and weighing equipment is found not to have completed an operating cycle by the decision indicated at block 1126, the program loops again to the junction "B" immediately following decision block 1110 which was described above in connection with the previous label taken test. Where the scale system of the present invention is used in the stand-alone mode without package transport weighing and labeling equipment, a wired connection is employed to indicate proper positioning of the transport mechanism.

Following the computer start suppress decision are tests for sale by count and label repeat switches as indicated by the blocks 1128 and 1130 in FIG. 11 and as performed by instructions at memory location 091 - 098 on page 3 of Table V. When operated in the sale by count mode, the system supplies a total value quantity from a combination of the price per pound entry knobs and weight on the scale platter. In a similar manner, when the label repeat control switch is actuated by the operator, the system supplies labels having identical numerical values for use in th prepackage mode of operation. The label repeat subroutine is contained at memory location 119 on page 3 of the Table V program listing, as indicated in the second line of the JCN instruction at memory location 098.

Following the label repeat status test in block 1130 another test is performed to determine if the manual start switch was found closed in the block 1109-1110 sequence, this second manual start test being indicated by the block 1132; and performed by the JCN Cl THRE instruction in memory location 100 -101 on page 3 of Table V; if this test indicated manual start switch closure the program jumps to the junction E preceding block 1140 in FIG. 11, it being desired that computation start and a label be produced in response to a manual start command even through one or more of the tests indicated between blocks 1132 and 1140 is not satisfied.

If the manual start switch has not been closed, the program compares the weight value obtained during the motion detect subroutine with lower and upper limit weight values as indicated by the weight dead zone and scale range test of blocks 1134 and 1136 and the instructions commencing at memory location 108 on page 3 of Table V. If the stored weight value is either within the weight dead zone or in excess of the scale range, the program proceeds to the junction F resetting the motion status flag and returning to program home position so that the scale remains locked in a loop which includes one of blocks 1134 or 1136 repeating the steps in this loop indefinitely until an acceptable weight value is provided; printing of a weight and price label being inhibited so long as this loop-locked condition continues.

As indicated by the motion detect status text of block 1138 the scale of the present invention must go through a period of motion followed by a period of no-motion before computation can occur. If the motion status word has not been set by the motion detect subroutine, the test indicated at block 1138 will also provide indefinite looping of the program through the junction F back through the program home position.

In the Table V program listing, the steps indicated by blocks 1132 through 1138 are performed by the instructions at memory location 100 - 118 on page 3, these steps involving use of several subroutines accessed by JCN and JMF instructions, the subroutine addresses being indicated by the latter bits of these instructions as described in the Intel Users Manual.

Between memory location and 119 and 167 in Table V are located a plurality of subroutines including the repeat switch subroutine, the check tare subroutine and the error routine. Each of these subroutines is addressed by a jump instruction from another part of the computer program. Value computation commences with the JMS instruction in memory location 167 and the block 1150 in FIG. 11. The computation indicated in block 1152 is preceded by tests which determine that a tare entry has been made, i.e., that the touch-tare knob 23 has been touched, that the printer is not in an error condition, that the weight is within the scale range, parity test of the weight chart reading is satisfied, the weight is outside the weight dead zone and the scale has not been identified as a metric scale as indicated by the blocks 1140 - 1150. The first three of these tests leads to the error subroutine and scale disabling if not satisfied. If the weight is within the weight dead zone in the block 1146 test, a subsequent test is performed as indicated in the block 1148 to examine the manual start switch status, a scale computation cycle being permissible for weight values within the weight dead zone in a manually start cycle. Weight values within the weight dead zone result in indefinite program looping through the block 1148 when the manual start switch has not been depressed. The weight dead zone and manual start tests are performed by the instructions in memory location 182 - 195 on page 5 of Table V.

Upon satisfying either the weight dead zone or manual start test of block 1146 and 1148, tests for the scale being a five kilogram or ten kilogram metric scale are performed by the series of instructions in memory locations 196 - 205 on page 5 of Table V. These instructions also involve the metric multiplier subroutine at memory location 1280 on page 26 of Table V.

Following the steps relating to a metric scale as indicated in block 1150 of FIG. 11, the unit price indicating switches, i.e., the price per pound switches in an American embodiment of the invention, are read into memory as indicated by the block 1151 in FIG. 11, and performed by the instruction in memory location 205 and 206 and the subroutine in memory location 804 on page 19 of Table V. The unit price switches are shown at 31, 32 and 33 in FIG. 1 and FIG 5B of the drawings.

The computation of total value, i.e., the multiplication of weight times a quantity read from the unit price switches as indicated in block 1152 of FIG. 11, is performed by the instructions in memory location 206 - 213 on page 5 of Table V, the JMS MPLY instruction providing a jump to the multiply subroutine at memory location 601 on page 14 of Table V.

Mathematical accuracy of the total value multiplication is verified by dividing the total value quantity resulting from the block 1152 multiplication by the unit price quantity and ascertaining that the resulting quotient equals the original weight value, this division is indicated by the block 1158 with the comparison of quotient and weight values being indicated at block 1160. This division is preceded by the test indicated in block 1154 which excludes the verified division step in the event the unit price switches are set to zero value, division by zero being impermissible and causing the computer to hang up in an indefinite loop if not excluded. If the decision indicated at block 1154 finds the unit price switches were in fact set to zero value, the program proceeds to the rounding routine as indicated by the path 1159.

In the Table V program, the FIM instruction at memory location 215 - 217 are used to access the unit price information for non-zero value checking while the DIVO subroutine in memory location 219 - 222 actually performs the zero test and the instructions between memory location 222 and 234 increment the zero test through the digits of the word being tested. The CKPR portion of these instructions provides duplication of the data to be tested in memory location, i.e., RAM word 8-15 is a second original computed data will be lost by the division sequence indicated in block 1158.

The division of block 1158 performed by the instructions in memory location 235 - 242 including the division subroutine at memory location 644 on page 15 of Table V which is accessed by the JMS instruction in memory location 241. The comparison of block 1160 is performed by the instructions in memory location 234 - 259, a portion of which are located on the second of the system ROM chips, ROM I. Comparison failures from the block 1160 provide a jump to a central error receiving point on ROM I, memory location 290, from which point a JUN instruction having two-word jump address capability provides return to the previously used error subroutine at memory location 158 on ROM O as shown on page 4 of Table V. Memory addressing between ROM chips involves address bits located in the four highest bit positions of the address word as indicated in the Intel Users Manual.

Once the total value computation has been mathematically verified, the total value quantity can be rounded in accordance with the currency practice of the locale in which the scale is being used. In the United States, for example, it is desired that the total value be rounded to have two digits, i.e., dimes and cents, on the right of the decimal point with the cents digit being increased by one number from its computed value in response to numbers having a value larger than four occupying the 1/10 cent decimal position. In the present invention, the total value rounding desired is selected by a group of switches or jumpers, which are interrogated by the instructions commencing at memory location 419 on page 10 of Table V. The actual rounding operation is initiated by the instruction at memory location 430 together with the round subroutine commencing at memory location 695 on page 16 of Table V; reading of the round select status and the rounding operation is indicated by the blocks preceding block 164 in FIG. 11.

In some currencies, it is desirable that the last digit of the total value be either a zero or a five, th half-penny or five-tenths coin being denoted by this numeral five; for such currency, the scale of the present invention is provided with quarter rounding capability which can be activated during scale installation as needed. The JUN instruction at memory location 436 provided a jump to memory location 705 on page 16 of Table V where the quarter-round subroutine is located, the quarter-round subroutine including both a check of quarter-round selection switch status and performance of the quarter-rounding operation. The quarter-round subroutine is a second level subroutine activated by an instruction in the round subroutine.

Following the rounding, the total value quantity is loaded into the memory location used by the input/output subroutines and tested for its being an excessively large value as indicated in the block 1166. The total value remains in this memory location until utilized by the output to printer subroutine. Once the value overflow test of block 1166 and the output to printer subroutine has been performed, the scale weighing cycle is complete and the scale remains dormant until activated by platform motion or manual start command for a new weighing cycle. The output to printer subroutine described elsewhere in the specification and is accessed by the JUN instruction in memory location 288; the subroutine commences with the instruction in memory location 888 on page 20 of Table V.

MOTION DETECTION

The sequence of operations which determine whether the scale is in motion or at rest was indicated by the blocks 1120 and 1122 in FIG. 11 and in the specification topic describing the executive routine. A flow diagram which describes the motion detect subroutine in greater detail is shown in FIG. 12 of the drawings. The FIG. 12 diagram also repeats selected portions of the FIG. 11 executive suroutine which are relevant to an understanding of motion detect subroutine operations.

Access to the motion detect subroutine is provided by the JMS instruction in memory location 064 on page 2 of Table V; this instruction providing a program jump to the MOTN subroutine which commences at memory location 292 on page 7 of Table V.

The MOTN motion subroutine commences with bringing a new weight reading from the scale photocells into the computer memory. This is indicated by the block 1202 in FIG. 12 and accomplished by the RDWT subroutine on page 9 of Table V with the new weight reading being stored in RAM words 32-35, photosensor output bits DCBA being located in word 32, bits HGFE in word 33, bits LKJI in word 34 and bits PONM in word 35. The weight reading being at this time in Gray code form.

An overall view of the FIG. 12 flow diagram indicates that each new weight reading is tested for motion in two different fashions. One of these tests, which is shown in the steps 1204, 1228, 1230 etc. aligned along the right hand edge of FIG. 12, involves a dynamic motion test of the type described in U.S. Pat. No. 3,516,504. The other motion test which is shown in the steps 1206, 1208 etc. aligned along the left hand edge of FIG. 12 involves a comparison of successive weight readings. The condition of motion can be determined by either of these sequences of steps.

The new weight reading in RAM words 32-35 is first examined by a dynamic motion test which involves the subroutine MOTX commencing at memory location 294 on page 7 of the Table V program and is indicated by the "A and C both light"decision block 1204 in FIG. 12. If photosensors A and C are found by the MOTX routine, to have each provided a binary one output signal a motion condition is indicated since as explained in the above patent the A and C tracks of the scale chart actually contain no simultaneous translucent areas. The presence of simultaneous A and C signals therefore indicates that alternating light and dark areas in each of these tracks is being integrated by the slow responding photosensor elements to provide quasi ON signals which are interpreted as ON signals by the threshold circuitry.

Once the A and C test has determined that the scale is in motion a series of housekeeping steps is performed by the program. These steps include setting a motion status memory flag as indicated at 1228 in FIG. 12 and performed by the MOTC subroutine on page 8 of Table V, the motion status character being located at status character 1 of register 2 in the RAM. The housekeeping steps also include resetting the time counter located at status character 3 of register 2, the negative motion counter at status character 2, register 2 and the positive motion counter at status character 0, register 2 all performed by the MOTZ routine at page 8 of Table V and indicated at 1230 - 1234 in FIG. 12. The function of each of these counters is explained below. Information regarding the RAM organization including the status character identification is provided in the previously mentioned Intel Users Manual.

Upon resetting the above counters, the program proceeds to the MOTA subroutine indicated by the block 1236 and commencing at memory location 323 on page 8 of Table V; in the MOTA sequence the new weight reading is transferred from RAM location 40 to location 36 a step which has the effect of updating the previous weight storage at RAM location 36. Following updating of the previous weight storage, the time counter located at status character 3 of register 2 is incremented as shown at block 1238 in FIG. 12 and a test made to determine if the program has traversed the motion detect sequence a sufficient number of times to have the scale mechanism physically settle out, that is the number of trips through the motion detect routine without detecting motion is compared with the number of trips known to consume the time required for scale settle out. This test is performed by the RD 3 and JCN instructions at memory locations 66-68 at page 2 of the Table V program listing and indicated by the block 1240 in FIG. 12. Failure to satisfy this test results in a return to Program Home at 1108 in FIG. 11, this return being indicated by the line 1201 in the motion detect flow diagram of FIG. 12. Actually the system does not perform the Read Weight sequence of block 1202 immediately upon return via the path 1201 but instead proceeds through the steps 1109-1118 in the executive routine before once again reaching the block 1202 Read Weight sequence; that is, a part of block 1120 in FIG. 11 is performed prior to block 1202.

Returning now to the A and C photosensor decision operation at 1204 in FIG. 12 and the Table V program, if the MOTX routine finds that at least one of the photosensors A and C is not illuminated the program proceeds into the more sensitive successive comparison of weight reading motion test shown at 1206 etc. along the left hand edge of FIG. 12. The weight comparison motion test commences with the transfer of Gray Code weight readings to RAM location 40-43, the address used for performing code change operations, the actual transfer being performed by the MNAC routine at memory location 307 on page 7 of Table V followed by the converting of Gray code weight readings to binary coded decimal form as indicated by the block 1208 and performed by the CDCH routine on page 10 of Table V. The code changed weight reading is placed back in RAM word 40-43.

Following code change, the current weight reading located in RAM word 40-43 is compared with the previous weight reading located in RAM word 36-39 by the COMP routine on page 13 of Table V, a comparison between these two weight readings indicating the lack of motion and causing the program to jump along the path 1211 to the transfer weight, increment time counter, and time counter examine sequence of steps 1236, 1238 in the MOTA routine described above in connection with the A and C photosensor test.

If the comparison of current weight reading in RAM word 40-43 with the previous weight reading in RAM word 36-39 finds a difference in these two weight readings, a series of such different readings is examined sequentially to determine if the movement is oscillating in nature or sufficiently small to yet consider the scale being in a no-motion condition. This examination being performed by the MOTT, MNEG and MOTU routines located on page 8 of Table V and indicated along the left hand edge of FIG. 12 at 1212, 1218 and 1222 respectively. The MOTT routine determines which the weight readings 40 or 36 is larger and places a bit indicating the larger reading in a positive or negative motion counter, a positive motion bit causing the previous negative motion count to be reset and a negative motion bit causing any previous motion count to be reset. It is significant to note that the incremented counter, the positive motion counter for example, is incremented by one count regardless of how much difference is found between the current and previous weight readings, that is, the detection of motion is based upon the concept that several successive weight reading comparisons each indicate a weight change in the same direction and not upon the concept that a single comparison shows a great difference in weight reading. In this respect, the scale of the present invention practices the teachings of the patent of Robert M. Rogers, U.S. Pat. No. 3,921,736 assigned to the assignee of the present invention.

According to this criteria for determining motion, the count in the appropriate motion counter, for example the positive motion counter, will be incremented during each of several successive trips through the MOTT routine and the state of being in motion indicated if this corner attains a predetermined count.

The MOTU routine on page 8 of Table V performs the examination of positive and negative motion counters and indicates the motion or no-motion condition according to one criteria if the scale was previously known to be in motion and according to another criteria if the scale was known to be previously at rest. In the MOTU routine the motion status word from status character 1 of register 2 is added to the contents of the motion counter being examined, i.e. the positive motion counter or the negative motion counter. The motion status word being a one if the scale was previously known to be in motion or a zero if the scale was previously at rest. To the sum of the motion counter and the status word is added a constant 13 which is selected in order that a count of 2 in the motion counter can provide an overflow count of 16 and thereby generate a carry bit which is easily sensed with the available Intel instruction family. Thus, if the scale was previously known to be in motion two successive weight readings each differing in the same direction will be sufficient to produce a motion indicating signal from the MOTU routine. If the scale was not previously in motion, i.e. if the motion status word is a zero, then three successively larger or three sucessively smaller weight readings are required to produce a motion indication from the MOTU routine.

In a weighing situation in FIG. 12 motion detection system could be expected to operate in the following manner. As a result of charge movement following placing an article on the scale platform, the system will make several trips through the right hand portion of FIG. 12 with the A and C photosensor test indicating rapid and dynamic movement of the scale. Each trip through this sequence causes the motion status character to be set and a new weight reading to be placed in RAM location 36 and the time counter left containing a count of one.

When the scale chart ultimately approaches the condition of balance and begins to slow its movement, a point is reached where the A and C photosensor test no longer indicates motion and the program then makes successive trips through the weight comparison test shown at the left hand edge of FIG. 12. During these initial passes through the weight test each weight reading will differ from the previous reading so that the positive motion counter will be successively incremented at block 1216 and a carry produced when the constant 13 is added to the motion counter contents. At some time, however, the scale chart will slow and ultimately come to rest either at the correct weight reading or in an overshoot position, so that the COMP routine comparison of block 1210 on page 13 in Table V, will indicate coincidence between previous and current weight readings. Actual weight reading coincidence will cause the program to jump to the MOTA routine along the path 1211 and cause the time counter at status character 3 of register 2 to be incremented to a new count. A count of 16 or zero in the time counter has been selected for termination of the motion detect operation. This is detected by sensing the counter contents being 0000 during the 16th count. In the preferred embodiment of the scale, a count of 16 cycles without motion in the time counter has been found to provide satisfactory assurance that the scale has come to rest without imposing an objectionable delay prior to commencing scale operations; obviously counting to some other number to give a different delay time could be selected. Since each trip through the motion detect sequence involves the delay imposed by the waste time sequence 1118 in FIG. 11 executive routine preceding the MOTN routine in FIG. 12, it is impossible for the time counter to obtain a count of 16 and initiate a computation cycle as a result of a brief pause of the scale chart in an overshoot condition.

Following the previously described upward direction overshoot motion of the scale chart, the chart may move backwards toward the true weight indication and possibly may again overshoot in the negative direction. The negative and positive motion counters of the MNEG and MOTT routines respond to any possible combination of upward, downward or oscillatory movement of the scale chart; depending upon the speed and duration of a particular movement of this response may include sufficient incrementing of a motion counter to generate a motion indicating carry in the MOTU routine. In view of the time delay of the block 1118 waste time routine, however, an oscillatory or overshoot movement of the chart will not be sufficient to increment the time counter through 15 counts and provide a computation start decision. Following the possible succession of negative and positive overshooting movements each successively smaller than the preceding movement as a result of damping apparatus in the scale, the chart eventually will come to rest on a weight reading. With the chart in this position, the condition of no-motion will be indicated either by failure of the positive or negative motion counter to attain a count providing a motion indicating carry bit in the MOTU routine or by coincidence being found in the COMP routine at 1210 in FIG. 12. When one of these conditions occurs the program jumps to the MOTA routine at 1236 via one of the paths 1211 or 1227 and increments the time counter at 1238 through one of the 15 counts required to initiate a computation cycle.

Once the motion status word at status character 1 of register 2 has been set in the motion detect sequence shown in FIG. 12, it remains set until late in the scale operating